Unified Coverage Report :: Module :: prim_generic_clock_inv

Module : prim_generic_clock_inv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_inv_0/rtl/prim_generic_clock_inv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_clk_spi.gen_generic.u_impl_generic

---

Module Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_clk_spi

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_scan.i_dft_tck_mux	85.19	100.00	55.56				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.