Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_generic_flop
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_tpm_csb_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_tpm_csb_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spid_csb_sync.u_count_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spid_csb_sync.u_count_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_sys_csb_syncd.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_sys_csb_syncd.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_read_pipe_stg1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_read_pipe_stg2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_read_en_pipe_stg1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_read_en_pipe_stg2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spid_status.u_sck2csb_status.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spid_addr_4b.u_spi2sys_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spid_addr_4b.u_spi2sys_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_passthrough.u_read_half_cycle.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_passthrough.u_read_pipe_stg1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_passthrough.u_read_pipe_stg2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spi_tpm.u_wrfifo_busy_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spi_tpm.u_wrfifo_busy_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_1.gen_generic.u_impl_generic 100.00 100.00 100.00
tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_2.gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_csb_sync.u_count_sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_csb_sync.u_count_sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sys_csb_syncd.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sys_csb_syncd.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_read_pipe_stg1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_read_pipe_stg1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_read_pipe_stg2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_read_pipe_stg2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_read_en_pipe_stg1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_read_en_pipe_stg1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_read_en_pipe_stg2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_read_en_pipe_stg2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_status.u_sck2csb_status.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sck2csb_status


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_passthrough.u_read_half_cycle.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_read_half_cycle


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_passthrough.u_read_pipe_stg1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_read_pipe_stg1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_passthrough.u_read_pipe_stg2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_read_pipe_stg2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_wrfifo_busy_sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_wrfifo_busy_sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_1.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_1


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_2.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_sync_2


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_flop
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Module : prim_generic_flop
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T5

Line Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T4,T5

Line Coverage for Instance : tb.dut.u_spid_csb_sync.u_count_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spid_csb_sync.u_count_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_csb_sync.u_count_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spid_csb_sync.u_count_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_sys_csb_syncd.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_sys_csb_syncd.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_sys_csb_syncd.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_sys_csb_syncd.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_sys_tpm_csb_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_sys_tpm_csb_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_read_pipe_stg1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_read_pipe_stg1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5

Line Coverage for Instance : tb.dut.u_read_pipe_stg2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_read_pipe_stg2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5

Line Coverage for Instance : tb.dut.u_read_en_pipe_stg1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_read_en_pipe_stg1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5

Line Coverage for Instance : tb.dut.u_read_en_pipe_stg2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_read_en_pipe_stg2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5

Line Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_status.u_sck2csb_status.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spid_status.u_sck2csb_status.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T4

Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_passthrough.u_read_half_cycle.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_passthrough.u_read_half_cycle.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5

Line Coverage for Instance : tb.dut.u_passthrough.u_read_pipe_stg1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_passthrough.u_read_pipe_stg1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5

Line Coverage for Instance : tb.dut.u_passthrough.u_read_pipe_stg2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_passthrough.u_read_pipe_stg2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T5

Line Coverage for Instance : tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_busy_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_busy_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_busy_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_busy_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo_ready.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T6

Line Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spi_tpm.u_rdfifo_ready.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T5,T6

Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_1.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL33100.00
ALWAYS1833100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
18 1 1
19 1 1
21 1 1


Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.u_sync_2.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 18 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv' or '../src/lowrisc_prim_generic_flop_0/rtl/prim_generic_flop.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 18 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%