Module Definition
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Module Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_spi_in_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_spi_out_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_clk_csb_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_csb_rst_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_tpm_csb_rst_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
64.81 100.00 44.44 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
g_scan_mux.u_scan_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
85.19 100.00 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
gen_scan.i_dft_tck_mux


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Module : prim_generic_clock_mux2
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Module : prim_generic_clock_mux2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 1146654441 1146644469 0 0
selKnown1 381988954 381987400 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 1146654441 1146644469 0 0
T1 40243 40238 0 0
T2 119323 119318 0 0
T3 4014 4008 0 0
T4 35 29 0 0
T5 2977936 2977929 0 0
T6 1093 1087 0 0
T7 2248688 2248681 0 0
T8 543591 543586 0 0
T9 956513 956506 0 0
T10 59080 59075 0 0
T11 146684 438749 0 0
T12 24 47 0 0
T14 930 928 0 0
T15 284 282 0 0
T16 60 58 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 381987400 0 0
T1 13408 13407 0 0
T2 39758 39757 0 0
T3 1325 1324 0 0
T5 992277 992276 0 0
T6 360 359 0 0
T7 749009 749008 0 0
T8 181176 181175 0 0
T9 318604 318603 0 0
T10 19687 19686 0 0
T11 145674 145674 0 0

Line Coverage for Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_clk_spi_in_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 381988954 381987400 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 381987400 0 0
T1 13408 13407 0 0
T2 39758 39757 0 0
T3 1325 1324 0 0
T5 992277 992276 0 0
T6 360 359 0 0
T7 749009 749008 0 0
T8 181176 181175 0 0
T9 318604 318603 0 0
T10 19687 19686 0 0
T11 145674 145674 0 0

Line Coverage for Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_clk_spi_out_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 381990775 381988923 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 381990775 381988923 0 0
T1 13409 13408 0 0
T2 39759 39758 0 0
T3 1326 1325 0 0
T4 1 0 0 0
T5 992278 992277 0 0
T6 361 360 0 0
T7 749010 749009 0 0
T8 181177 181176 0 0
T9 318605 318604 0 0
T10 19688 19687 0 0
T11 0 145674 0 0

Line Coverage for Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T4
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T4
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_clk_csb_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 147729 145877 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 147729 145877 0 0
T1 9 8 0 0
T2 24 23 0 0
T3 1 0 0 0
T4 9 8 0 0
T5 498 497 0 0
T6 1 0 0 0
T7 653 652 0 0
T8 31 30 0 0
T9 157 156 0 0
T10 9 8 0 0
T11 0 720 0 0
T12 0 24 0 0

Line Coverage for Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T4
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T4

Assert Coverage for Instance : tb.dut.u_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 145877 144595 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 145877 144595 0 0
T1 8 7 0 0
T2 23 22 0 0
T4 8 7 0 0
T5 497 496 0 0
T7 652 651 0 0
T8 30 29 0 0
T9 156 155 0 0
T10 8 7 0 0
T11 720 719 0 0
T12 24 23 0 0

Line Coverage for Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T4,T5

Assert Coverage for Instance : tb.dut.u_tpm_csb_rst_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 195166 194376 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 195166 194376 0 0
T3 18 17 0 0
T4 8 7 0 0
T5 54 53 0 0
T6 5 4 0 0
T7 177 176 0 0
T9 193 192 0 0
T11 145 144 0 0
T14 465 464 0 0
T15 142 141 0 0
T16 30 29 0 0

Line Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9444.44
Logical9444.44
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT3,T4,T5
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01Not Covered
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T4,T5

Assert Coverage for Instance : tb.dut.u_tpm_csb_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 1 50.00 1 50.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 1 50.00 1 50.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 195165 194375 0 0
selKnown1 0 0 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 195165 194375 0 0
T3 18 17 0 0
T4 8 7 0 0
T5 54 53 0 0
T6 5 4 0 0
T7 177 176 0 0
T9 193 192 0 0
T11 145 144 0 0
T14 465 464 0 0
T15 142 141 0 0
T16 30 29 0 0

Line Coverage for Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL11100.00
CONT_ASSIGN1711100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' or '../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
17 1 1


Cond Coverage for Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalCoveredPercent
Conditions9555.56
Logical9555.56
Non-Logical00
Event00

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T2,T3

Assert Coverage for Instance : tb.dut.u_clk_spi.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
selKnown0 381990775 381988923 0 0
selKnown1 381988954 381987400 0 0


selKnown0
NameAttemptsReal SuccessesFailuresIncomplete
Total 381990775 381988923 0 0
T1 13409 13408 0 0
T2 39759 39758 0 0
T3 1326 1325 0 0
T4 1 0 0 0
T5 992278 992277 0 0
T6 361 360 0 0
T7 749010 749009 0 0
T8 181177 181176 0 0
T9 318605 318604 0 0
T10 19688 19687 0 0
T11 0 145674 0 0

selKnown1
NameAttemptsReal SuccessesFailuresIncomplete
Total 381988954 381987400 0 0
T1 13408 13407 0 0
T2 39758 39757 0 0
T3 1325 1324 0 0
T5 992277 992276 0 0
T6 360 359 0 0
T7 749009 749008 0 0
T8 181176 181175 0 0
T9 318604 318603 0 0
T10 19687 19686 0 0
T11 145674 145674 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%