Toggle Coverage for Module :
prim_onehot_check
| Total | Covered | Percent |
Totals |
5 |
5 |
100.00 |
Total Bits |
138 |
138 |
100.00 |
Total Bits 0->1 |
69 |
69 |
100.00 |
Total Bits 1->0 |
69 |
69 |
100.00 |
| | | |
Ports |
5 |
5 |
100.00 |
Port Bits |
138 |
138 |
100.00 |
Port Bits 0->1 |
69 |
69 |
100.00 |
Port Bits 1->0 |
69 |
69 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T28,T48,T49 |
Yes |
T1,T2,T3 |
INPUT |
oh_i[5:0] |
Yes |
Yes |
*T1,*T2,*T5 |
Yes |
T1,T2,T5 |
INPUT |
oh_i[6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[8:7] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
oh_i[9] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[14:10] |
Yes |
Yes |
T1,T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
oh_i[18:15] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[58:19] |
Yes |
Yes |
*T1,*T2,T5 |
Yes |
T1,T2,T5 |
INPUT |
oh_i[59] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[70:60] |
Yes |
Yes |
*T3,T5,*T6 |
Yes |
T3,T5,T6 |
INPUT |
oh_i[71] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
oh_i[72] |
Yes |
Yes |
T5,T7,T9 |
Yes |
T5,T7,T9 |
INPUT |
addr_i[6:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
en_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
err_o |
Yes |
Yes |
T57,T58,T59 |
Yes |
T57,T58,T59 |
OUTPUT |
*Tests covering at least one bit in the range