Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_205
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_205
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_205
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_206
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_206
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_206
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_207
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_207
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_207
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_208
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_208
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_208
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_209
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_209
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_209
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_210
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_210
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_210
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_211
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_211
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_211
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_212
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_212
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_212
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_213
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_213
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_213
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_214
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_214
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_214
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_215
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_215
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_215
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_216
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_216
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_216
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_217
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_217
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_217
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_218
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_218
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_218
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_219
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_219
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_219
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_220
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_220
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_220
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_221
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_221
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_221
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_222
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_222
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_222
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_223
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_223
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_6_filter_223
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_224
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_224
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_224
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_225
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_225
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_225
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_226
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_226
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_226
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_227
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_227
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_227
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_228
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_228
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_228
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_229
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_229
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_229
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_230
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_230
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_230
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |
Line Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_231
| Line No. | Total | Covered | Percent |
TOTAL | | 7 | 7 | 100.00 |
ALWAYS | 56 | 4 | 4 | 100.00 |
CONT_ASSIGN | 64 | 1 | 1 | 100.00 |
CONT_ASSIGN | 65 | 1 | 1 | 100.00 |
CONT_ASSIGN | 72 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
56 |
1 |
1 |
57 |
1 |
1 |
58 |
1 |
1 |
59 |
1 |
1 |
|
|
|
MISSING_ELSE |
64 |
1 |
1 |
65 |
1 |
1 |
72 |
1 |
1 |
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_231
| Total | Covered | Percent |
Conditions | 2 | 2 | 100.00 |
Logical | 2 | 2 | 100.00 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 64
EXPRESSION (wr_en ? wr_data : qs)
--1--
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T5 |
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_filter_7_filter_231
| Line No. | Total | Covered | Percent |
Branches |
|
5 |
5 |
100.00 |
TERNARY |
64 |
2 |
2 |
100.00 |
IF |
56 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_subreg.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 64 (wr_en) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T5 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 56 if ((!rst_ni))
-2-: 58 if (wr_en)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T5 |
0 |
0 |
Covered |
T1,T2,T3 |