Line Coverage for Module :
prim_slicer
| Line No. | Total | Covered | Percent |
TOTAL | | 2 | 2 | 100.00 |
CONT_ASSIGN | 25 | 1 | 1 | 100.00 |
CONT_ASSIGN | 27 | 1 | 1 | 100.00 |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_slicer.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
25 |
1 |
1 |
27 |
1 |
1 |
Assert Coverage for Module :
prim_slicer
Assertion Details
Name | Attempts | Real Successes | Failures | Incomplete |
ValidWidth_A |
1852 |
1852 |
0 |
0 |
ValidWidth_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
1852 |
1852 |
0 |
0 |
T1 |
1 |
1 |
0 |
0 |
T2 |
1 |
1 |
0 |
0 |
T3 |
1 |
1 |
0 |
0 |
T4 |
1 |
1 |
0 |
0 |
T5 |
1 |
1 |
0 |
0 |
T6 |
1 |
1 |
0 |
0 |
T7 |
1 |
1 |
0 |
0 |
T8 |
1 |
1 |
0 |
0 |
T9 |
1 |
1 |
0 |
0 |
T10 |
1 |
1 |
0 |
0 |