Module Definition
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Module : tlul_err_resp
SCORELINECONDTOGGLEFSMBRANCHASSERT
57.80 76.92 40.91 55.56

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_reg.u_socket.gen_err_resp.err_resp 57.80 76.92 40.91 55.56



Module Instance : tb.dut.u_reg.u_socket.gen_err_resp.err_resp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
57.80 76.92 40.91 55.56


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
71.05 87.76 40.91 55.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.25 100.00 93.33 95.65 100.00 u_socket


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_intg_gen 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : tlul_err_resp
Line No.TotalCoveredPercent
TOTAL262076.92
ALWAYS3414964.29
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5311100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5811100.00
CONT_ASSIGN5911100.00
ALWAYS645480.00
CONT_ASSIGN7511100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
34 1 1
35 1 1
36 1 1
37 1 1
38 1 1
39 1 1
40 1 1
41 0 1
42 0 1
43 0 1
44 0 1
45 0 1
46 1 1
47 1 1
==> MISSING_ELSE
51 1 1
52 1 1
53 1 1
55 1 1
58 1 1
59 1 1
64 1 1
65 1 1
66 1 1
67 0 1
69 1 1
75 1 1


Cond Coverage for Module : tlul_err_resp
TotalCoveredPercent
Conditions22940.91
Logical22940.91
Non-Logical00
Event00

 LINE       40
 EXPRESSION (tl_h_i.a_valid && tl_h_o_int.a_ready)
             -------1------    ---------2--------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       51
 EXPRESSION (((~err_rsp_pending)) & ( ~ (err_req_pending & ((~tl_h_i.d_ready))) ))
             ----------1---------   ----------------------2----------------------
-1--2-StatusTests
01Not Covered
10Not Covered
11CoveredT1,T2,T3

 LINE       51
 SUB-EXPRESSION (err_req_pending & ((~tl_h_i.d_ready)))
                 -------1-------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       52
 EXPRESSION (err_req_pending | err_rsp_pending)
             -------1-------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

 LINE       59
 EXPRESSION ((err_opcode == Get) ? AccessAckData : AccessAck)
             ---------1---------
-1-StatusTests
0Not Covered
1CoveredT1,T2,T3

 LINE       59
 SUB-EXPRESSION (err_opcode == Get)
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       66
 EXPRESSION ((err_req_pending || err_rsp_pending) && ((!tl_h_i.d_ready)))
             ------------------1-----------------    ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       66
 SUB-EXPRESSION (err_req_pending || err_rsp_pending)
                 -------1-------    -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10Not Covered

Branch Coverage for Module : tlul_err_resp
Line No.TotalCoveredPercent
Branches 9 5 55.56
TERNARY 59 2 1 50.00
IF 34 4 2 50.00
IF 64 3 2 66.67

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv' or '../src/lowrisc_tlul_socket_1n_0.1/rtl/tlul_err_resp.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 59 ((err_opcode == Get)) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Not Covered


LineNo. Expression -1-: 34 if ((!rst_ni)) -2-: 40 if ((tl_h_i.a_valid && tl_h_o_int.a_ready)) -3-: 46 if ((!err_rsp_pending))

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Not Covered
0 0 1 Covered T1,T2,T3
0 0 0 Not Covered


LineNo. Expression -1-: 64 if ((!rst_ni)) -2-: 66 if (((err_req_pending || err_rsp_pending) && (!tl_h_i.d_ready)))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%