Module Definition
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Module : prim_generic_flop_en
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic 100.00 100.00 100.00



Module Instance : tb.dut.u_spid_status.u_stage_to_commit.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_stage_to_commit


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_generic_flop_en
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2811100.00
ALWAYS3244100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
28 1 1
32 1 1
33 1 1
34 1 1
35 1 1
MISSING_ELSE


Branch Coverage for Module : prim_generic_flop_en
Line No.TotalCoveredPercent
Branches 3 3 100.00
IF 32 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv' or '../src/lowrisc_prim_generic_flop_en_0/rtl/prim_generic_flop_en.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 32 if ((!rst_ni)) -2-: 34 if (en)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T5
0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%