Unified Coverage Report :: Module :: tlul_sram_byte

Module : tlul_sram_byte

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tlul2sram_egress.u_sram_byte	100.00	100.00
tb.dut.u_tlul2sram_ingress.u_sram_byte	100.00	100.00

---

Module Instance : tb.dut.u_tlul2sram_egress.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.16	94.03	62.07			70.83	85.71	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_tlul2sram_ingress.u_sram_byte

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
88.09	94.03	75.00			83.33	100.00	u_tlul2sram_ingress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : tlul_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
320	1	1
321	1	1
322	1	1

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
320	1	1
321	1	1
322	1	1

Line Coverage for Instance : tb.dut.u_tlul2sram_ingress.u_sram_byte

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	320	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	322	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' or '../src/lowrisc_tlul_adapter_sram_0.1/rtl/tlul_sram_byte.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
320	1	1
321	1	1
322	1	1