| T1809 |
/workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3042807545 |
|
|
Mar 17 01:31:50 PM PDT 24 |
Mar 17 01:32:22 PM PDT 24 |
11591147930 ps |
| T1810 |
/workspace/coverage/default/47.spi_device_read_buffer_direct.1734703190 |
|
|
Mar 17 03:17:19 PM PDT 24 |
Mar 17 03:17:25 PM PDT 24 |
6831982654 ps |
| T1811 |
/workspace/coverage/default/14.spi_device_pass_cmd_filtering.2309906675 |
|
|
Mar 17 01:29:56 PM PDT 24 |
Mar 17 01:30:06 PM PDT 24 |
5933714365 ps |
| T1812 |
/workspace/coverage/default/15.spi_device_upload.2577247891 |
|
|
Mar 17 03:14:44 PM PDT 24 |
Mar 17 03:14:52 PM PDT 24 |
1044467318 ps |
| T1813 |
/workspace/coverage/default/5.spi_device_tpm_sts_read.3798702248 |
|
|
Mar 17 03:13:29 PM PDT 24 |
Mar 17 03:13:30 PM PDT 24 |
25871418 ps |
| T1814 |
/workspace/coverage/default/9.spi_device_pass_cmd_filtering.2216316609 |
|
|
Mar 17 01:29:28 PM PDT 24 |
Mar 17 01:29:31 PM PDT 24 |
351630475 ps |
| T1815 |
/workspace/coverage/default/32.spi_device_flash_mode.822797797 |
|
|
Mar 17 03:16:13 PM PDT 24 |
Mar 17 03:16:44 PM PDT 24 |
24958194624 ps |
| T1816 |
/workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.71116263 |
|
|
Mar 17 01:29:28 PM PDT 24 |
Mar 17 01:32:40 PM PDT 24 |
108439727437 ps |
| T1817 |
/workspace/coverage/default/44.spi_device_csb_read.3590450341 |
|
|
Mar 17 01:32:27 PM PDT 24 |
Mar 17 01:32:28 PM PDT 24 |
17156919 ps |
| T1818 |
/workspace/coverage/default/30.spi_device_stress_all.310365370 |
|
|
Mar 17 03:16:09 PM PDT 24 |
Mar 17 03:16:11 PM PDT 24 |
223320753 ps |
| T1819 |
/workspace/coverage/default/28.spi_device_tpm_read_hw_reg.33732872 |
|
|
Mar 17 03:15:52 PM PDT 24 |
Mar 17 03:16:10 PM PDT 24 |
5546789667 ps |
| T1820 |
/workspace/coverage/default/3.spi_device_csb_read.2116353899 |
|
|
Mar 17 01:28:50 PM PDT 24 |
Mar 17 01:28:51 PM PDT 24 |
53907666 ps |
| T1821 |
/workspace/coverage/default/33.spi_device_intercept.3672260461 |
|
|
Mar 17 03:16:16 PM PDT 24 |
Mar 17 03:16:26 PM PDT 24 |
6421854850 ps |
| T1822 |
/workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.665387945 |
|
|
Mar 17 01:32:35 PM PDT 24 |
Mar 17 01:33:57 PM PDT 24 |
7608114717 ps |
| T1823 |
/workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1152384122 |
|
|
Mar 17 03:17:18 PM PDT 24 |
Mar 17 03:19:54 PM PDT 24 |
36697219988 ps |
| T1824 |
/workspace/coverage/default/22.spi_device_intercept.3597117350 |
|
|
Mar 17 03:15:24 PM PDT 24 |
Mar 17 03:15:28 PM PDT 24 |
3254152294 ps |
| T1825 |
/workspace/coverage/default/21.spi_device_pass_cmd_filtering.1049450491 |
|
|
Mar 17 01:30:31 PM PDT 24 |
Mar 17 01:30:38 PM PDT 24 |
482116538 ps |
| T1826 |
/workspace/coverage/default/17.spi_device_tpm_all.92712270 |
|
|
Mar 17 01:30:13 PM PDT 24 |
Mar 17 01:30:58 PM PDT 24 |
12509607361 ps |
| T1827 |
/workspace/coverage/default/46.spi_device_flash_and_tpm.4010049646 |
|
|
Mar 17 01:32:37 PM PDT 24 |
Mar 17 01:34:46 PM PDT 24 |
64139239475 ps |
| T1828 |
/workspace/coverage/default/14.spi_device_tpm_rw.1164001718 |
|
|
Mar 17 01:29:55 PM PDT 24 |
Mar 17 01:29:58 PM PDT 24 |
118848132 ps |
| T1829 |
/workspace/coverage/default/47.spi_device_pass_addr_payload_swap.209404886 |
|
|
Mar 17 01:32:43 PM PDT 24 |
Mar 17 01:32:51 PM PDT 24 |
1016916405 ps |
| T1830 |
/workspace/coverage/default/3.spi_device_upload.2042076132 |
|
|
Mar 17 03:13:12 PM PDT 24 |
Mar 17 03:13:18 PM PDT 24 |
748380913 ps |
| T1831 |
/workspace/coverage/default/27.spi_device_tpm_sts_read.3982172124 |
|
|
Mar 17 03:15:46 PM PDT 24 |
Mar 17 03:15:48 PM PDT 24 |
99234989 ps |
| T1832 |
/workspace/coverage/default/31.spi_device_pass_cmd_filtering.804856668 |
|
|
Mar 17 03:16:12 PM PDT 24 |
Mar 17 03:16:24 PM PDT 24 |
2012688889 ps |
| T1833 |
/workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3694825056 |
|
|
Mar 17 03:15:56 PM PDT 24 |
Mar 17 03:15:58 PM PDT 24 |
1963813360 ps |
| T1834 |
/workspace/coverage/default/42.spi_device_csb_read.3605520537 |
|
|
Mar 17 01:32:12 PM PDT 24 |
Mar 17 01:32:13 PM PDT 24 |
15208113 ps |
| T1835 |
/workspace/coverage/default/23.spi_device_tpm_all.796177752 |
|
|
Mar 17 01:30:43 PM PDT 24 |
Mar 17 01:31:16 PM PDT 24 |
25334853956 ps |
| T1836 |
/workspace/coverage/default/21.spi_device_tpm_all.1751334007 |
|
|
Mar 17 03:15:16 PM PDT 24 |
Mar 17 03:15:38 PM PDT 24 |
1216194495 ps |
| T1837 |
/workspace/coverage/default/30.spi_device_flash_and_tpm.1174112006 |
|
|
Mar 17 01:31:24 PM PDT 24 |
Mar 17 01:31:46 PM PDT 24 |
7366850434 ps |
| T1838 |
/workspace/coverage/default/49.spi_device_upload.4090496089 |
|
|
Mar 17 01:32:48 PM PDT 24 |
Mar 17 01:32:56 PM PDT 24 |
553621161 ps |
| T1839 |
/workspace/coverage/default/7.spi_device_tpm_rw.4214642856 |
|
|
Mar 17 01:29:23 PM PDT 24 |
Mar 17 01:29:25 PM PDT 24 |
75403611 ps |
| T1840 |
/workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1123558039 |
|
|
Mar 17 01:32:05 PM PDT 24 |
Mar 17 01:32:10 PM PDT 24 |
1354685192 ps |
| T1841 |
/workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2513141471 |
|
|
Mar 17 01:31:28 PM PDT 24 |
Mar 17 01:31:33 PM PDT 24 |
978646211 ps |
| T1842 |
/workspace/coverage/default/13.spi_device_intercept.1607819885 |
|
|
Mar 17 03:14:39 PM PDT 24 |
Mar 17 03:14:44 PM PDT 24 |
2261905498 ps |
| T1843 |
/workspace/coverage/default/25.spi_device_flash_mode.2815302262 |
|
|
Mar 17 01:30:54 PM PDT 24 |
Mar 17 01:31:15 PM PDT 24 |
6460902887 ps |
| T1844 |
/workspace/coverage/default/7.spi_device_tpm_all.1524808308 |
|
|
Mar 17 01:29:21 PM PDT 24 |
Mar 17 01:29:59 PM PDT 24 |
2144149651 ps |
| T1845 |
/workspace/coverage/default/15.spi_device_alert_test.3189846477 |
|
|
Mar 17 03:14:47 PM PDT 24 |
Mar 17 03:14:49 PM PDT 24 |
23038550 ps |
| T1846 |
/workspace/coverage/default/1.spi_device_tpm_all.2035827408 |
|
|
Mar 17 01:28:29 PM PDT 24 |
Mar 17 01:29:20 PM PDT 24 |
79891234526 ps |
| T1847 |
/workspace/coverage/default/2.spi_device_mailbox.1975296784 |
|
|
Mar 17 03:13:07 PM PDT 24 |
Mar 17 03:13:14 PM PDT 24 |
6349284485 ps |
| T1848 |
/workspace/coverage/default/31.spi_device_pass_addr_payload_swap.751120970 |
|
|
Mar 17 03:16:12 PM PDT 24 |
Mar 17 03:16:17 PM PDT 24 |
1099646085 ps |
| T1849 |
/workspace/coverage/default/17.spi_device_cfg_cmd.174455597 |
|
|
Mar 17 01:30:12 PM PDT 24 |
Mar 17 01:30:17 PM PDT 24 |
3381491417 ps |
| T1850 |
/workspace/coverage/default/37.spi_device_stress_all.4065003981 |
|
|
Mar 17 03:16:38 PM PDT 24 |
Mar 17 03:16:40 PM PDT 24 |
232137802 ps |
| T1851 |
/workspace/coverage/default/1.spi_device_tpm_rw.2657693014 |
|
|
Mar 17 01:28:29 PM PDT 24 |
Mar 17 01:28:34 PM PDT 24 |
113124475 ps |
| T1852 |
/workspace/coverage/default/47.spi_device_csb_read.3836080991 |
|
|
Mar 17 01:32:33 PM PDT 24 |
Mar 17 01:32:34 PM PDT 24 |
31693427 ps |
| T1853 |
/workspace/coverage/default/19.spi_device_pass_addr_payload_swap.234832657 |
|
|
Mar 17 01:30:22 PM PDT 24 |
Mar 17 01:30:26 PM PDT 24 |
4012858383 ps |
| T1854 |
/workspace/coverage/default/5.spi_device_read_buffer_direct.49007587 |
|
|
Mar 17 01:29:09 PM PDT 24 |
Mar 17 01:29:13 PM PDT 24 |
392709966 ps |
| T1855 |
/workspace/coverage/default/34.spi_device_cfg_cmd.226156659 |
|
|
Mar 17 03:16:21 PM PDT 24 |
Mar 17 03:16:24 PM PDT 24 |
41533013 ps |
| T1856 |
/workspace/coverage/default/40.spi_device_tpm_rw.549439175 |
|
|
Mar 17 03:16:47 PM PDT 24 |
Mar 17 03:16:48 PM PDT 24 |
110000565 ps |
| T1857 |
/workspace/coverage/default/9.spi_device_read_buffer_direct.3929319666 |
|
|
Mar 17 03:14:05 PM PDT 24 |
Mar 17 03:14:11 PM PDT 24 |
1070694514 ps |
| T1858 |
/workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2149800065 |
|
|
Mar 17 01:30:57 PM PDT 24 |
Mar 17 01:31:08 PM PDT 24 |
6974945851 ps |
| T1859 |
/workspace/coverage/default/18.spi_device_flash_all.4060006274 |
|
|
Mar 17 01:30:21 PM PDT 24 |
Mar 17 01:31:12 PM PDT 24 |
5661302021 ps |
| T1860 |
/workspace/coverage/default/40.spi_device_tpm_all.407419888 |
|
|
Mar 17 01:32:06 PM PDT 24 |
Mar 17 01:32:46 PM PDT 24 |
7623235321 ps |
| T1861 |
/workspace/coverage/default/34.spi_device_stress_all.1698749852 |
|
|
Mar 17 01:31:42 PM PDT 24 |
Mar 17 01:31:43 PM PDT 24 |
297689241 ps |
| T1862 |
/workspace/coverage/default/31.spi_device_upload.2701949635 |
|
|
Mar 17 01:31:21 PM PDT 24 |
Mar 17 01:31:45 PM PDT 24 |
14704730199 ps |
| T1863 |
/workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3252186060 |
|
|
Mar 17 03:14:24 PM PDT 24 |
Mar 17 03:14:35 PM PDT 24 |
1788644735 ps |
| T1864 |
/workspace/coverage/default/30.spi_device_mailbox.1821129096 |
|
|
Mar 17 01:31:17 PM PDT 24 |
Mar 17 01:31:25 PM PDT 24 |
497686738 ps |
| T1865 |
/workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1368583923 |
|
|
Mar 17 01:30:28 PM PDT 24 |
Mar 17 01:30:32 PM PDT 24 |
1446934497 ps |
| T1866 |
/workspace/coverage/default/38.spi_device_alert_test.529113656 |
|
|
Mar 17 01:31:55 PM PDT 24 |
Mar 17 01:31:56 PM PDT 24 |
30507849 ps |
| T1867 |
/workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2023241841 |
|
|
Mar 17 03:13:59 PM PDT 24 |
Mar 17 03:14:06 PM PDT 24 |
1492257143 ps |
| T1868 |
/workspace/coverage/default/18.spi_device_tpm_sts_read.2701644056 |
|
|
Mar 17 01:30:19 PM PDT 24 |
Mar 17 01:30:20 PM PDT 24 |
49655234 ps |
| T1869 |
/workspace/coverage/default/10.spi_device_flash_mode.1605940773 |
|
|
Mar 17 01:29:39 PM PDT 24 |
Mar 17 01:29:55 PM PDT 24 |
787293929 ps |
| T1870 |
/workspace/coverage/default/21.spi_device_intercept.2499324861 |
|
|
Mar 17 01:30:32 PM PDT 24 |
Mar 17 01:30:36 PM PDT 24 |
110393925 ps |
| T1871 |
/workspace/coverage/default/29.spi_device_mailbox.1750647291 |
|
|
Mar 17 03:15:58 PM PDT 24 |
Mar 17 03:16:01 PM PDT 24 |
80727530 ps |
| T1872 |
/workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4078685442 |
|
|
Mar 17 03:16:08 PM PDT 24 |
Mar 17 03:21:18 PM PDT 24 |
80349942553 ps |
| T1873 |
/workspace/coverage/default/4.spi_device_mailbox.3142791300 |
|
|
Mar 17 03:13:27 PM PDT 24 |
Mar 17 03:13:41 PM PDT 24 |
547714054 ps |
| T1874 |
/workspace/coverage/default/29.spi_device_tpm_sts_read.184102666 |
|
|
Mar 17 03:15:55 PM PDT 24 |
Mar 17 03:15:56 PM PDT 24 |
90327965 ps |
| T1875 |
/workspace/coverage/default/20.spi_device_csb_read.3697729685 |
|
|
Mar 17 03:15:12 PM PDT 24 |
Mar 17 03:15:13 PM PDT 24 |
30571281 ps |
| T1876 |
/workspace/coverage/default/24.spi_device_tpm_all.3978841971 |
|
|
Mar 17 01:30:49 PM PDT 24 |
Mar 17 01:31:21 PM PDT 24 |
4324325725 ps |
| T1877 |
/workspace/coverage/default/19.spi_device_alert_test.647848820 |
|
|
Mar 17 03:15:13 PM PDT 24 |
Mar 17 03:15:14 PM PDT 24 |
54691292 ps |
| T1878 |
/workspace/coverage/default/7.spi_device_tpm_sts_read.213424395 |
|
|
Mar 17 03:13:44 PM PDT 24 |
Mar 17 03:13:45 PM PDT 24 |
21755694 ps |
| T1879 |
/workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1396185057 |
|
|
Mar 17 03:12:59 PM PDT 24 |
Mar 17 03:14:10 PM PDT 24 |
17957056472 ps |
| T66 |
/workspace/coverage/default/0.spi_device_sec_cm.3966824561 |
|
|
Mar 17 01:28:21 PM PDT 24 |
Mar 17 01:28:23 PM PDT 24 |
358891049 ps |
| T1880 |
/workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3205910496 |
|
|
Mar 17 01:28:23 PM PDT 24 |
Mar 17 01:33:07 PM PDT 24 |
49630065908 ps |
| T1881 |
/workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3459638591 |
|
|
Mar 17 01:31:45 PM PDT 24 |
Mar 17 01:31:50 PM PDT 24 |
1609018899 ps |
| T1882 |
/workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3572200802 |
|
|
Mar 17 01:30:12 PM PDT 24 |
Mar 17 01:30:14 PM PDT 24 |
455798661 ps |
| T1883 |
/workspace/coverage/default/7.spi_device_read_buffer_direct.1005365104 |
|
|
Mar 17 03:13:47 PM PDT 24 |
Mar 17 03:13:53 PM PDT 24 |
1443712577 ps |
| T1884 |
/workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2610944763 |
|
|
Mar 17 03:15:53 PM PDT 24 |
Mar 17 03:15:57 PM PDT 24 |
147814291 ps |
| T1885 |
/workspace/coverage/default/4.spi_device_flash_mode.569963981 |
|
|
Mar 17 03:13:27 PM PDT 24 |
Mar 17 03:14:20 PM PDT 24 |
9793275061 ps |
| T1886 |
/workspace/coverage/default/14.spi_device_flash_mode.1200064848 |
|
|
Mar 17 01:29:56 PM PDT 24 |
Mar 17 01:30:08 PM PDT 24 |
2456867594 ps |
| T1887 |
/workspace/coverage/default/29.spi_device_stress_all.3217570832 |
|
|
Mar 17 03:16:00 PM PDT 24 |
Mar 17 03:19:04 PM PDT 24 |
24010141166 ps |
| T1888 |
/workspace/coverage/default/14.spi_device_tpm_read_hw_reg.67208419 |
|
|
Mar 17 03:14:34 PM PDT 24 |
Mar 17 03:14:48 PM PDT 24 |
12635474992 ps |
| T1889 |
/workspace/coverage/default/17.spi_device_tpm_rw.853688188 |
|
|
Mar 17 01:30:16 PM PDT 24 |
Mar 17 01:30:17 PM PDT 24 |
74269702 ps |
| T1890 |
/workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1219652617 |
|
|
Mar 17 03:16:46 PM PDT 24 |
Mar 17 03:27:38 PM PDT 24 |
375972373001 ps |
| T1891 |
/workspace/coverage/default/18.spi_device_ram_cfg.3984198773 |
|
|
Mar 17 01:30:12 PM PDT 24 |
Mar 17 01:30:13 PM PDT 24 |
24299106 ps |
| T1892 |
/workspace/coverage/default/46.spi_device_tpm_read_hw_reg.229369155 |
|
|
Mar 17 01:32:44 PM PDT 24 |
Mar 17 01:32:54 PM PDT 24 |
2760611659 ps |
| T1893 |
/workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3848614254 |
|
|
Mar 17 03:13:29 PM PDT 24 |
Mar 17 03:13:43 PM PDT 24 |
8281164174 ps |
| T1894 |
/workspace/coverage/default/39.spi_device_flash_and_tpm.3012613623 |
|
|
Mar 17 01:32:01 PM PDT 24 |
Mar 17 01:32:37 PM PDT 24 |
32323392680 ps |
| T1895 |
/workspace/coverage/default/3.spi_device_read_buffer_direct.1773125731 |
|
|
Mar 17 01:28:58 PM PDT 24 |
Mar 17 01:29:03 PM PDT 24 |
960667934 ps |
| T1896 |
/workspace/coverage/default/42.spi_device_mailbox.817256130 |
|
|
Mar 17 03:16:56 PM PDT 24 |
Mar 17 03:17:13 PM PDT 24 |
2145819200 ps |
| T1897 |
/workspace/coverage/default/49.spi_device_mailbox.2643597709 |
|
|
Mar 17 03:17:30 PM PDT 24 |
Mar 17 03:17:37 PM PDT 24 |
881038983 ps |
| T1898 |
/workspace/coverage/default/13.spi_device_tpm_sts_read.133412668 |
|
|
Mar 17 01:29:50 PM PDT 24 |
Mar 17 01:29:51 PM PDT 24 |
122343160 ps |
| T1899 |
/workspace/coverage/default/29.spi_device_alert_test.1014777039 |
|
|
Mar 17 01:31:10 PM PDT 24 |
Mar 17 01:31:12 PM PDT 24 |
14820424 ps |
| T1900 |
/workspace/coverage/default/8.spi_device_mailbox.3252108199 |
|
|
Mar 17 01:29:28 PM PDT 24 |
Mar 17 01:29:47 PM PDT 24 |
5523231454 ps |
| T1901 |
/workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3151986033 |
|
|
Mar 17 03:14:44 PM PDT 24 |
Mar 17 03:16:27 PM PDT 24 |
4410589329 ps |
| T1902 |
/workspace/coverage/default/7.spi_device_tpm_all.825597560 |
|
|
Mar 17 03:13:46 PM PDT 24 |
Mar 17 03:14:17 PM PDT 24 |
19566124954 ps |
| T1903 |
/workspace/coverage/default/1.spi_device_ram_cfg.1904124243 |
|
|
Mar 17 01:28:30 PM PDT 24 |
Mar 17 01:28:30 PM PDT 24 |
31601586 ps |
| T1904 |
/workspace/coverage/default/35.spi_device_stress_all.4149388213 |
|
|
Mar 17 01:31:44 PM PDT 24 |
Mar 17 01:31:45 PM PDT 24 |
111707349 ps |
| T1905 |
/workspace/coverage/default/38.spi_device_pass_cmd_filtering.501694945 |
|
|
Mar 17 01:31:57 PM PDT 24 |
Mar 17 01:32:06 PM PDT 24 |
4121511970 ps |
| T1906 |
/workspace/coverage/default/9.spi_device_flash_all.3049688732 |
|
|
Mar 17 01:29:34 PM PDT 24 |
Mar 17 01:30:55 PM PDT 24 |
16012944618 ps |
| T1907 |
/workspace/coverage/default/9.spi_device_tpm_sts_read.3117579106 |
|
|
Mar 17 01:29:33 PM PDT 24 |
Mar 17 01:29:34 PM PDT 24 |
48026767 ps |
| T1908 |
/workspace/coverage/default/4.spi_device_tpm_all.2231902933 |
|
|
Mar 17 03:13:20 PM PDT 24 |
Mar 17 03:13:55 PM PDT 24 |
7167123350 ps |
| T1909 |
/workspace/coverage/default/30.spi_device_flash_mode.1447949232 |
|
|
Mar 17 03:16:04 PM PDT 24 |
Mar 17 03:16:34 PM PDT 24 |
18195417721 ps |
| T84 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1515479960 |
|
|
Mar 17 01:09:45 PM PDT 24 |
Mar 17 01:09:49 PM PDT 24 |
60912209 ps |
| T85 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1882447936 |
|
|
Mar 17 01:09:41 PM PDT 24 |
Mar 17 01:09:45 PM PDT 24 |
143197546 ps |
| T1910 |
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.2019517449 |
|
|
Mar 17 01:44:01 PM PDT 24 |
Mar 17 01:44:02 PM PDT 24 |
48549889 ps |
| T1911 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.3218517740 |
|
|
Mar 17 01:10:12 PM PDT 24 |
Mar 17 01:10:13 PM PDT 24 |
145287302 ps |
| T86 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.315506445 |
|
|
Mar 17 01:09:40 PM PDT 24 |
Mar 17 01:10:02 PM PDT 24 |
1912255114 ps |
| T87 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3881848767 |
|
|
Mar 17 01:43:45 PM PDT 24 |
Mar 17 01:43:48 PM PDT 24 |
150598437 ps |
| T1912 |
/workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.739922686 |
|
|
Mar 17 01:10:06 PM PDT 24 |
Mar 17 01:10:09 PM PDT 24 |
59126178 ps |
| T131 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1219176687 |
|
|
Mar 17 01:09:56 PM PDT 24 |
Mar 17 01:09:57 PM PDT 24 |
177990520 ps |
| T106 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3075543307 |
|
|
Mar 17 01:09:37 PM PDT 24 |
Mar 17 01:10:13 PM PDT 24 |
2171558565 ps |
| T103 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1894570648 |
|
|
Mar 17 01:10:07 PM PDT 24 |
Mar 17 01:10:11 PM PDT 24 |
169904110 ps |
| T1913 |
/workspace/coverage/cover_reg_top/49.spi_device_intr_test.560120761 |
|
|
Mar 17 01:10:12 PM PDT 24 |
Mar 17 01:10:13 PM PDT 24 |
32511014 ps |
| T90 |
/workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3829914321 |
|
|
Mar 17 01:10:06 PM PDT 24 |
Mar 17 01:10:09 PM PDT 24 |
130348814 ps |
| T1914 |
/workspace/coverage/cover_reg_top/28.spi_device_intr_test.1070515677 |
|
|
Mar 17 01:10:08 PM PDT 24 |
Mar 17 01:10:10 PM PDT 24 |
23887266 ps |
| T94 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2051197534 |
|
|
Mar 17 01:43:56 PM PDT 24 |
Mar 17 01:43:59 PM PDT 24 |
151963034 ps |
| T1915 |
/workspace/coverage/cover_reg_top/16.spi_device_intr_test.524861256 |
|
|
Mar 17 01:44:00 PM PDT 24 |
Mar 17 01:44:00 PM PDT 24 |
41564623 ps |
| T1916 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.1693361118 |
|
|
Mar 17 01:10:08 PM PDT 24 |
Mar 17 01:10:10 PM PDT 24 |
45624038 ps |
| T1917 |
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.393154490 |
|
|
Mar 17 01:10:07 PM PDT 24 |
Mar 17 01:10:09 PM PDT 24 |
13487141 ps |
| T88 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1129890802 |
|
|
Mar 17 01:10:05 PM PDT 24 |
Mar 17 01:10:25 PM PDT 24 |
314174982 ps |
| T95 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2832026327 |
|
|
Mar 17 01:09:40 PM PDT 24 |
Mar 17 01:09:43 PM PDT 24 |
246969327 ps |
| T89 |
/workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1046311655 |
|
|
Mar 17 01:43:49 PM PDT 24 |
Mar 17 01:43:58 PM PDT 24 |
1957876430 ps |
| T1918 |
/workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1524861167 |
|
|
Mar 17 01:09:57 PM PDT 24 |
Mar 17 01:10:01 PM PDT 24 |
476069410 ps |
| T1919 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.320203596 |
|
|
Mar 17 01:09:40 PM PDT 24 |
Mar 17 01:09:42 PM PDT 24 |
32457872 ps |
| T164 |
/workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1201920853 |
|
|
Mar 17 01:09:49 PM PDT 24 |
Mar 17 01:09:56 PM PDT 24 |
109737677 ps |
| T104 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3295709533 |
|
|
Mar 17 01:09:40 PM PDT 24 |
Mar 17 01:10:08 PM PDT 24 |
4412269673 ps |
| T1920 |
/workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1863383316 |
|
|
Mar 17 01:09:39 PM PDT 24 |
Mar 17 01:09:41 PM PDT 24 |
31574174 ps |
| T107 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1727725866 |
|
|
Mar 17 01:43:48 PM PDT 24 |
Mar 17 01:43:51 PM PDT 24 |
73847760 ps |
| T105 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1867438343 |
|
|
Mar 17 01:43:51 PM PDT 24 |
Mar 17 01:43:52 PM PDT 24 |
218637306 ps |
| T1921 |
/workspace/coverage/cover_reg_top/34.spi_device_intr_test.3571208623 |
|
|
Mar 17 01:44:03 PM PDT 24 |
Mar 17 01:44:03 PM PDT 24 |
13212124 ps |
| T132 |
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.657162555 |
|
|
Mar 17 01:09:58 PM PDT 24 |
Mar 17 01:10:01 PM PDT 24 |
80598520 ps |
| T98 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2279097981 |
|
|
Mar 17 01:09:41 PM PDT 24 |
Mar 17 01:09:46 PM PDT 24 |
54414750 ps |
| T1922 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.2274686469 |
|
|
Mar 17 01:43:59 PM PDT 24 |
Mar 17 01:44:00 PM PDT 24 |
37414374 ps |
| T108 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2976989343 |
|
|
Mar 17 01:43:45 PM PDT 24 |
Mar 17 01:43:48 PM PDT 24 |
67997247 ps |
| T133 |
/workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1721101047 |
|
|
Mar 17 01:43:57 PM PDT 24 |
Mar 17 01:44:00 PM PDT 24 |
496213077 ps |
| T1923 |
/workspace/coverage/cover_reg_top/30.spi_device_intr_test.340705842 |
|
|
Mar 17 01:44:02 PM PDT 24 |
Mar 17 01:44:03 PM PDT 24 |
11158481 ps |
| T1924 |
/workspace/coverage/cover_reg_top/23.spi_device_intr_test.3844219153 |
|
|
Mar 17 01:10:06 PM PDT 24 |
Mar 17 01:10:07 PM PDT 24 |
37570058 ps |
| T109 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2211094296 |
|
|
Mar 17 01:43:40 PM PDT 24 |
Mar 17 01:43:42 PM PDT 24 |
176241724 ps |
| T1925 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2111546253 |
|
|
Mar 17 01:44:03 PM PDT 24 |
Mar 17 01:44:05 PM PDT 24 |
99049431 ps |
| T96 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2405968942 |
|
|
Mar 17 01:09:56 PM PDT 24 |
Mar 17 01:10:00 PM PDT 24 |
637158771 ps |
| T1926 |
/workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4221884794 |
|
|
Mar 17 01:43:51 PM PDT 24 |
Mar 17 01:43:54 PM PDT 24 |
42709154 ps |
| T91 |
/workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3886394148 |
|
|
Mar 17 01:44:00 PM PDT 24 |
Mar 17 01:44:04 PM PDT 24 |
791616314 ps |
| T92 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_errors.705544710 |
|
|
Mar 17 01:43:57 PM PDT 24 |
Mar 17 01:44:01 PM PDT 24 |
382231372 ps |
| T1927 |
/workspace/coverage/cover_reg_top/46.spi_device_intr_test.3594497540 |
|
|
Mar 17 01:44:05 PM PDT 24 |
Mar 17 01:44:07 PM PDT 24 |
19959920 ps |
| T1928 |
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.2375337885 |
|
|
Mar 17 01:09:59 PM PDT 24 |
Mar 17 01:10:01 PM PDT 24 |
55309254 ps |
| T1929 |
/workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2066539784 |
|
|
Mar 17 01:43:49 PM PDT 24 |
Mar 17 01:43:52 PM PDT 24 |
41590243 ps |
| T1930 |
/workspace/coverage/cover_reg_top/37.spi_device_intr_test.1950545045 |
|
|
Mar 17 01:44:02 PM PDT 24 |
Mar 17 01:44:03 PM PDT 24 |
43629319 ps |
| T110 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.166745306 |
|
|
Mar 17 01:09:49 PM PDT 24 |
Mar 17 01:09:56 PM PDT 24 |
202841859 ps |
| T111 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2804593768 |
|
|
Mar 17 01:43:46 PM PDT 24 |
Mar 17 01:44:11 PM PDT 24 |
1163047474 ps |
| T157 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3136733428 |
|
|
Mar 17 01:10:07 PM PDT 24 |
Mar 17 01:10:14 PM PDT 24 |
448650230 ps |
| T1931 |
/workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.125642189 |
|
|
Mar 17 01:09:42 PM PDT 24 |
Mar 17 01:09:47 PM PDT 24 |
112820570 ps |
| T1932 |
/workspace/coverage/cover_reg_top/43.spi_device_intr_test.2857292292 |
|
|
Mar 17 01:44:02 PM PDT 24 |
Mar 17 01:44:03 PM PDT 24 |
14325489 ps |
| T165 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.557943191 |
|
|
Mar 17 01:09:57 PM PDT 24 |
Mar 17 01:10:06 PM PDT 24 |
104005418 ps |
| T1933 |
/workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1267988066 |
|
|
Mar 17 01:09:58 PM PDT 24 |
Mar 17 01:10:02 PM PDT 24 |
174339628 ps |
| T1934 |
/workspace/coverage/cover_reg_top/25.spi_device_intr_test.4089136325 |
|
|
Mar 17 01:10:07 PM PDT 24 |
Mar 17 01:10:09 PM PDT 24 |
21126730 ps |
| T1935 |
/workspace/coverage/cover_reg_top/45.spi_device_intr_test.2178054474 |
|
|
Mar 17 01:10:08 PM PDT 24 |
Mar 17 01:10:10 PM PDT 24 |
13586616 ps |
| T97 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.275412089 |
|
|
Mar 17 01:09:58 PM PDT 24 |
Mar 17 01:10:01 PM PDT 24 |
121199934 ps |
| T1936 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3839998168 |
|
|
Mar 17 01:10:12 PM PDT 24 |
Mar 17 01:10:16 PM PDT 24 |
212313840 ps |
| T1937 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.889650292 |
|
|
Mar 17 01:09:46 PM PDT 24 |
Mar 17 01:09:49 PM PDT 24 |
226169369 ps |
| T102 |
/workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1867549357 |
|
|
Mar 17 01:09:58 PM PDT 24 |
Mar 17 01:10:04 PM PDT 24 |
127389431 ps |
| T93 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3132629270 |
|
|
Mar 17 01:09:58 PM PDT 24 |
Mar 17 01:10:01 PM PDT 24 |
465211632 ps |
| T1938 |
/workspace/coverage/cover_reg_top/19.spi_device_intr_test.3816410363 |
|
|
Mar 17 01:44:05 PM PDT 24 |
Mar 17 01:44:05 PM PDT 24 |
17145234 ps |
| T1939 |
/workspace/coverage/cover_reg_top/3.spi_device_intr_test.4003713616 |
|
|
Mar 17 01:09:39 PM PDT 24 |
Mar 17 01:09:39 PM PDT 24 |
50642019 ps |
| T99 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_errors.274092820 |
|
|
Mar 17 01:44:06 PM PDT 24 |
Mar 17 01:44:09 PM PDT 24 |
217836574 ps |
| T1940 |
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.3014939636 |
|
|
Mar 17 01:10:09 PM PDT 24 |
Mar 17 01:10:10 PM PDT 24 |
19210746 ps |
| T1941 |
/workspace/coverage/cover_reg_top/2.spi_device_intr_test.1576164082 |
|
|
Mar 17 01:09:40 PM PDT 24 |
Mar 17 01:09:42 PM PDT 24 |
31158087 ps |
| T100 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2079589230 |
|
|
Mar 17 01:43:54 PM PDT 24 |
Mar 17 01:43:58 PM PDT 24 |
122893210 ps |
| T76 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1855560196 |
|
|
Mar 17 01:09:49 PM PDT 24 |
Mar 17 01:09:50 PM PDT 24 |
34394512 ps |
| T1942 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1806132182 |
|
|
Mar 17 01:43:46 PM PDT 24 |
Mar 17 01:43:49 PM PDT 24 |
169303073 ps |
| T1943 |
/workspace/coverage/cover_reg_top/24.spi_device_intr_test.3939960575 |
|
|
Mar 17 01:10:10 PM PDT 24 |
Mar 17 01:10:11 PM PDT 24 |
14339860 ps |
| T1944 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2024931642 |
|
|
Mar 17 01:43:40 PM PDT 24 |
Mar 17 01:43:53 PM PDT 24 |
762678395 ps |
| T1945 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.482774853 |
|
|
Mar 17 01:10:08 PM PDT 24 |
Mar 17 01:10:10 PM PDT 24 |
36610635 ps |
| T112 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1366417742 |
|
|
Mar 17 01:09:41 PM PDT 24 |
Mar 17 01:09:58 PM PDT 24 |
2539267498 ps |
| T1946 |
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.701159862 |
|
|
Mar 17 01:09:46 PM PDT 24 |
Mar 17 01:09:48 PM PDT 24 |
14366609 ps |
| T113 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4091375657 |
|
|
Mar 17 01:43:45 PM PDT 24 |
Mar 17 01:43:47 PM PDT 24 |
51616576 ps |
| T134 |
/workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1423196053 |
|
|
Mar 17 01:09:39 PM PDT 24 |
Mar 17 01:09:42 PM PDT 24 |
70889342 ps |
| T114 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1722755010 |
|
|
Mar 17 01:43:43 PM PDT 24 |
Mar 17 01:44:05 PM PDT 24 |
1829157347 ps |
| T115 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.314127814 |
|
|
Mar 17 01:43:44 PM PDT 24 |
Mar 17 01:43:53 PM PDT 24 |
1469198136 ps |
| T116 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2872091821 |
|
|
Mar 17 01:09:49 PM PDT 24 |
Mar 17 01:09:51 PM PDT 24 |
34533220 ps |
| T1947 |
/workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3938712746 |
|
|
Mar 17 01:43:55 PM PDT 24 |
Mar 17 01:43:59 PM PDT 24 |
176012074 ps |
| T1948 |
/workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3877613822 |
|
|
Mar 17 01:09:38 PM PDT 24 |
Mar 17 01:09:39 PM PDT 24 |
15897525 ps |
| T118 |
/workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2847392503 |
|
|
Mar 17 01:10:08 PM PDT 24 |
Mar 17 01:10:11 PM PDT 24 |
81135681 ps |
| T159 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2221003576 |
|
|
Mar 17 01:10:08 PM PDT 24 |
Mar 17 01:10:15 PM PDT 24 |
105739754 ps |
| T1949 |
/workspace/coverage/cover_reg_top/40.spi_device_intr_test.486457257 |
|
|
Mar 17 01:44:01 PM PDT 24 |
Mar 17 01:44:02 PM PDT 24 |
18550900 ps |
| T1950 |
/workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.811286224 |
|
|
Mar 17 01:10:10 PM PDT 24 |
Mar 17 01:10:14 PM PDT 24 |
53967473 ps |
| T1951 |
/workspace/coverage/cover_reg_top/6.spi_device_intr_test.2668890341 |
|
|
Mar 17 01:43:48 PM PDT 24 |
Mar 17 01:43:50 PM PDT 24 |
42775602 ps |
| T1952 |
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1309790700 |
|
|
Mar 17 01:10:07 PM PDT 24 |
Mar 17 01:10:12 PM PDT 24 |
231695809 ps |
| T1953 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1854985474 |
|
|
Mar 17 01:43:42 PM PDT 24 |
Mar 17 01:43:45 PM PDT 24 |
183415638 ps |
| T1954 |
/workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3423940167 |
|
|
Mar 17 01:43:45 PM PDT 24 |
Mar 17 01:43:46 PM PDT 24 |
152925808 ps |
| T135 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3847888451 |
|
|
Mar 17 01:43:49 PM PDT 24 |
Mar 17 01:43:51 PM PDT 24 |
750553747 ps |
| T1955 |
/workspace/coverage/cover_reg_top/33.spi_device_intr_test.2397983527 |
|
|
Mar 17 01:10:05 PM PDT 24 |
Mar 17 01:10:06 PM PDT 24 |
88996531 ps |
| T1956 |
/workspace/coverage/cover_reg_top/38.spi_device_intr_test.2941469524 |
|
|
Mar 17 01:44:02 PM PDT 24 |
Mar 17 01:44:03 PM PDT 24 |
15935343 ps |
| T1957 |
/workspace/coverage/cover_reg_top/35.spi_device_intr_test.1211058946 |
|
|
Mar 17 01:10:12 PM PDT 24 |
Mar 17 01:10:13 PM PDT 24 |
22802437 ps |
| T1958 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.420607039 |
|
|
Mar 17 01:10:07 PM PDT 24 |
Mar 17 01:10:10 PM PDT 24 |
53584308 ps |
| T150 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2784717604 |
|
|
Mar 17 01:44:03 PM PDT 24 |
Mar 17 01:44:28 PM PDT 24 |
4480470572 ps |
| T1959 |
/workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.265454512 |
|
|
Mar 17 01:43:51 PM PDT 24 |
Mar 17 01:43:55 PM PDT 24 |
110209764 ps |
| T1960 |
/workspace/coverage/cover_reg_top/17.spi_device_intr_test.2922400123 |
|
|
Mar 17 01:10:06 PM PDT 24 |
Mar 17 01:10:07 PM PDT 24 |
49449607 ps |
| T77 |
/workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2512651741 |
|
|
Mar 17 01:43:47 PM PDT 24 |
Mar 17 01:43:49 PM PDT 24 |
44895862 ps |
| T1961 |
/workspace/coverage/cover_reg_top/18.spi_device_intr_test.3003432929 |
|
|
Mar 17 01:43:58 PM PDT 24 |
Mar 17 01:43:59 PM PDT 24 |
21557085 ps |
| T117 |
/workspace/coverage/cover_reg_top/15.spi_device_csr_rw.632109795 |
|
|
Mar 17 01:10:10 PM PDT 24 |
Mar 17 01:10:12 PM PDT 24 |
32505169 ps |
| T160 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4086613498 |
|
|
Mar 17 01:09:46 PM PDT 24 |
Mar 17 01:10:03 PM PDT 24 |
660860551 ps |
| T158 |
/workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4248848599 |
|
|
Mar 17 01:43:48 PM PDT 24 |
Mar 17 01:44:11 PM PDT 24 |
2847726358 ps |
| T1962 |
/workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.110657635 |
|
|
Mar 17 01:43:51 PM PDT 24 |
Mar 17 01:43:53 PM PDT 24 |
28978412 ps |
| T1963 |
/workspace/coverage/cover_reg_top/39.spi_device_intr_test.722747915 |
|
|
Mar 17 01:44:05 PM PDT 24 |
Mar 17 01:44:05 PM PDT 24 |
20235594 ps |
| T166 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3132158747 |
|
|
Mar 17 01:09:57 PM PDT 24 |
Mar 17 01:10:13 PM PDT 24 |
618345650 ps |
| T1964 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2266876745 |
|
|
Mar 17 01:09:40 PM PDT 24 |
Mar 17 01:09:41 PM PDT 24 |
11422207 ps |
| T101 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_errors.992071511 |
|
|
Mar 17 01:09:40 PM PDT 24 |
Mar 17 01:09:44 PM PDT 24 |
142566768 ps |
| T1965 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4095184020 |
|
|
Mar 17 01:09:37 PM PDT 24 |
Mar 17 01:09:39 PM PDT 24 |
57124632 ps |
| T167 |
/workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2516585581 |
|
|
Mar 17 01:09:59 PM PDT 24 |
Mar 17 01:10:15 PM PDT 24 |
4488847049 ps |
| T1966 |
/workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.482119370 |
|
|
Mar 17 01:43:40 PM PDT 24 |
Mar 17 01:43:53 PM PDT 24 |
339686784 ps |
| T1967 |
/workspace/coverage/cover_reg_top/10.spi_device_intr_test.2749735996 |
|
|
Mar 17 01:09:56 PM PDT 24 |
Mar 17 01:09:58 PM PDT 24 |
22823686 ps |
| T1968 |
/workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3900663899 |
|
|
Mar 17 01:43:59 PM PDT 24 |
Mar 17 01:44:13 PM PDT 24 |
1158661781 ps |
| T1969 |
/workspace/coverage/cover_reg_top/22.spi_device_intr_test.296791651 |
|
|
Mar 17 01:44:01 PM PDT 24 |
Mar 17 01:44:02 PM PDT 24 |
12046657 ps |
| T1970 |
/workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1831462192 |
|
|
Mar 17 01:43:59 PM PDT 24 |
Mar 17 01:44:03 PM PDT 24 |
235330943 ps |
| T1971 |
/workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3526714005 |
|
|
Mar 17 01:44:03 PM PDT 24 |
Mar 17 01:44:05 PM PDT 24 |
314759651 ps |
| T78 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.757904357 |
|
|
Mar 17 01:43:43 PM PDT 24 |
Mar 17 01:43:44 PM PDT 24 |
219039592 ps |
| T1972 |
/workspace/coverage/cover_reg_top/13.spi_device_intr_test.3136511710 |
|
|
Mar 17 01:43:56 PM PDT 24 |
Mar 17 01:43:57 PM PDT 24 |
114927522 ps |
| T1973 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1337885752 |
|
|
Mar 17 01:09:37 PM PDT 24 |
Mar 17 01:09:40 PM PDT 24 |
1502132039 ps |
| T1974 |
/workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1700375021 |
|
|
Mar 17 01:09:49 PM PDT 24 |
Mar 17 01:09:52 PM PDT 24 |
367073395 ps |
| T1975 |
/workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1469682249 |
|
|
Mar 17 01:43:48 PM PDT 24 |
Mar 17 01:44:07 PM PDT 24 |
1168440286 ps |
| T1976 |
/workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1342168473 |
|
|
Mar 17 01:09:49 PM PDT 24 |
Mar 17 01:09:52 PM PDT 24 |
443852534 ps |
| T1977 |
/workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4122201082 |
|
|
Mar 17 01:10:07 PM PDT 24 |
Mar 17 01:10:25 PM PDT 24 |
1231350557 ps |
| T1978 |
/workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4111530539 |
|
|
Mar 17 01:09:44 PM PDT 24 |
Mar 17 01:09:49 PM PDT 24 |
295343862 ps |
| T1979 |
/workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3627608517 |
|
|
Mar 17 01:43:58 PM PDT 24 |
Mar 17 01:44:02 PM PDT 24 |
323703426 ps |
| T1980 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3895123592 |
|
|
Mar 17 01:09:42 PM PDT 24 |
Mar 17 01:10:10 PM PDT 24 |
3778752570 ps |
| T1981 |
/workspace/coverage/cover_reg_top/21.spi_device_intr_test.1747800800 |
|
|
Mar 17 01:44:02 PM PDT 24 |
Mar 17 01:44:03 PM PDT 24 |
91141497 ps |
| T1982 |
/workspace/coverage/cover_reg_top/41.spi_device_intr_test.421049319 |
|
|
Mar 17 01:10:09 PM PDT 24 |
Mar 17 01:10:10 PM PDT 24 |
22149772 ps |
| T1983 |
/workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1538856741 |
|
|
Mar 17 01:43:57 PM PDT 24 |
Mar 17 01:44:04 PM PDT 24 |
1285250937 ps |
| T1984 |
/workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4251491646 |
|
|
Mar 17 01:43:36 PM PDT 24 |
Mar 17 01:43:58 PM PDT 24 |
2051020022 ps |
| T1985 |
/workspace/coverage/cover_reg_top/11.spi_device_intr_test.1382829641 |
|
|
Mar 17 01:43:49 PM PDT 24 |
Mar 17 01:43:50 PM PDT 24 |
52970383 ps |
| T1986 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3146531906 |
|
|
Mar 17 01:10:00 PM PDT 24 |
Mar 17 01:10:02 PM PDT 24 |
88226113 ps |
| T1987 |
/workspace/coverage/cover_reg_top/20.spi_device_intr_test.475768965 |
|
|
Mar 17 01:44:03 PM PDT 24 |
Mar 17 01:44:04 PM PDT 24 |
24590176 ps |
| T1988 |
/workspace/coverage/cover_reg_top/4.spi_device_intr_test.1950507446 |
|
|
Mar 17 01:43:44 PM PDT 24 |
Mar 17 01:43:45 PM PDT 24 |
48560747 ps |
| T1989 |
/workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2413223488 |
|
|
Mar 17 01:43:51 PM PDT 24 |
Mar 17 01:43:55 PM PDT 24 |
1031677300 ps |
| T1990 |
/workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2028899604 |
|
|
Mar 17 01:43:53 PM PDT 24 |
Mar 17 01:43:57 PM PDT 24 |
55687647 ps |
| T1991 |
/workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3711544055 |
|
|
Mar 17 01:43:52 PM PDT 24 |
Mar 17 01:43:55 PM PDT 24 |
108912066 ps |
| T1992 |
/workspace/coverage/cover_reg_top/31.spi_device_intr_test.2969844622 |
|
|
Mar 17 01:44:04 PM PDT 24 |
Mar 17 01:44:05 PM PDT 24 |
175489510 ps |
| T79 |
/workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4128839849 |
|
|
Mar 17 01:09:40 PM PDT 24 |
Mar 17 01:09:42 PM PDT 24 |
33361653 ps |
| T1993 |
/workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3786237276 |
|
|
Mar 17 01:09:40 PM PDT 24 |
Mar 17 01:09:43 PM PDT 24 |
48511754 ps |
| T1994 |
/workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.251273789 |
|
|
Mar 17 01:43:44 PM PDT 24 |
Mar 17 01:43:46 PM PDT 24 |
74371912 ps |
| T1995 |
/workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1462861867 |
|
|
Mar 17 01:44:02 PM PDT 24 |
Mar 17 01:44:08 PM PDT 24 |
105443165 ps |
| T1996 |
/workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3713480554 |
|
|
Mar 17 01:43:42 PM PDT 24 |
Mar 17 01:43:51 PM PDT 24 |
309792063 ps |
| T1997 |
/workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1973569711 |
|
|
Mar 17 01:43:51 PM PDT 24 |
Mar 17 01:43:56 PM PDT 24 |
314808290 ps |
| T1998 |
/workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1954295259 |
|
|
Mar 17 01:43:59 PM PDT 24 |
Mar 17 01:44:02 PM PDT 24 |
435693414 ps |
| T1999 |
/workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.340604407 |
|
|
Mar 17 01:09:39 PM PDT 24 |
Mar 17 01:09:47 PM PDT 24 |
381698573 ps |
| T2000 |
/workspace/coverage/cover_reg_top/13.spi_device_csr_rw.487506811 |
|
|
Mar 17 01:10:00 PM PDT 24 |
Mar 17 01:10:02 PM PDT 24 |
28753967 ps |
| T2001 |
/workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2783023840 |
|
|
Mar 17 01:43:47 PM PDT 24 |
Mar 17 01:44:00 PM PDT 24 |
214030527 ps |
| T2002 |
/workspace/coverage/cover_reg_top/29.spi_device_intr_test.3457810045 |
|
|
Mar 17 01:44:03 PM PDT 24 |
Mar 17 01:44:04 PM PDT 24 |
14448809 ps |
| T161 |
/workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.113096993 |
|
|
Mar 17 01:43:45 PM PDT 24 |
Mar 17 01:44:04 PM PDT 24 |
581669625 ps |
| T2003 |
/workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2350186572 |
|
|
Mar 17 01:43:58 PM PDT 24 |
Mar 17 01:44:02 PM PDT 24 |
146509025 ps |