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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.98 98.38 94.42 98.61 89.36 97.09 95.75 98.22


Total test records in report: 2202
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T156 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2265712866 Mar 17 01:09:39 PM PDT 24 Mar 17 01:09:44 PM PDT 24 576825714 ps
T2004 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1627613993 Mar 17 01:43:50 PM PDT 24 Mar 17 01:43:55 PM PDT 24 65379981 ps
T2005 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1372190475 Mar 17 01:43:55 PM PDT 24 Mar 17 01:43:58 PM PDT 24 39054509 ps
T2006 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2463316170 Mar 17 01:43:49 PM PDT 24 Mar 17 01:43:50 PM PDT 24 12945343 ps
T162 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3159101596 Mar 17 01:43:59 PM PDT 24 Mar 17 01:44:23 PM PDT 24 2085185275 ps
T2007 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.828320906 Mar 17 01:43:48 PM PDT 24 Mar 17 01:43:51 PM PDT 24 207388133 ps
T2008 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.483301736 Mar 17 01:10:07 PM PDT 24 Mar 17 01:10:11 PM PDT 24 649171427 ps
T2009 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3727552195 Mar 17 01:09:44 PM PDT 24 Mar 17 01:09:52 PM PDT 24 258893289 ps
T2010 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3122711878 Mar 17 01:09:39 PM PDT 24 Mar 17 01:09:41 PM PDT 24 17775859 ps
T2011 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.562760329 Mar 17 01:10:05 PM PDT 24 Mar 17 01:10:10 PM PDT 24 50274342 ps
T2012 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.796675908 Mar 17 01:09:59 PM PDT 24 Mar 17 01:10:01 PM PDT 24 18811938 ps
T2013 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1557988390 Mar 17 01:44:04 PM PDT 24 Mar 17 01:44:04 PM PDT 24 57872065 ps
T2014 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3563802241 Mar 17 01:43:46 PM PDT 24 Mar 17 01:43:49 PM PDT 24 36752077 ps
T2015 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2812066754 Mar 17 01:10:08 PM PDT 24 Mar 17 01:10:11 PM PDT 24 34263435 ps
T2016 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2106220045 Mar 17 01:10:13 PM PDT 24 Mar 17 01:10:14 PM PDT 24 25353122 ps
T2017 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1921630947 Mar 17 01:43:44 PM PDT 24 Mar 17 01:43:45 PM PDT 24 129968521 ps
T2018 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.550172885 Mar 17 01:10:12 PM PDT 24 Mar 17 01:10:12 PM PDT 24 24777080 ps
T2019 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1101429650 Mar 17 01:09:45 PM PDT 24 Mar 17 01:09:47 PM PDT 24 634379310 ps
T2020 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1276144805 Mar 17 01:43:49 PM PDT 24 Mar 17 01:43:50 PM PDT 24 12709377 ps
T2021 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2219598673 Mar 17 01:43:48 PM PDT 24 Mar 17 01:43:51 PM PDT 24 39968022 ps
T2022 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2068938355 Mar 17 01:43:54 PM PDT 24 Mar 17 01:43:56 PM PDT 24 403324878 ps
T2023 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3543994628 Mar 17 01:09:56 PM PDT 24 Mar 17 01:09:58 PM PDT 24 21897631 ps
T2024 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.805575401 Mar 17 01:43:43 PM PDT 24 Mar 17 01:43:44 PM PDT 24 38423142 ps
T2025 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.162792709 Mar 17 01:10:10 PM PDT 24 Mar 17 01:10:11 PM PDT 24 67723904 ps
T2026 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3772460282 Mar 17 01:43:54 PM PDT 24 Mar 17 01:43:56 PM PDT 24 80033520 ps
T2027 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2678782936 Mar 17 01:09:38 PM PDT 24 Mar 17 01:09:39 PM PDT 24 26483928 ps
T2028 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2490280341 Mar 17 01:09:47 PM PDT 24 Mar 17 01:10:03 PM PDT 24 2553177090 ps
T2029 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1607095747 Mar 17 01:43:57 PM PDT 24 Mar 17 01:43:59 PM PDT 24 810489560 ps
T2030 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4083700699 Mar 17 01:10:09 PM PDT 24 Mar 17 01:10:11 PM PDT 24 236860076 ps
T2031 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1423411222 Mar 17 01:43:44 PM PDT 24 Mar 17 01:43:59 PM PDT 24 2015958417 ps
T2032 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2315889806 Mar 17 01:09:46 PM PDT 24 Mar 17 01:09:49 PM PDT 24 142483808 ps
T2033 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2418216531 Mar 17 01:10:07 PM PDT 24 Mar 17 01:10:12 PM PDT 24 150461099 ps
T2034 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.932114063 Mar 17 01:43:48 PM PDT 24 Mar 17 01:44:11 PM PDT 24 843733394 ps
T2035 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.413427082 Mar 17 01:09:58 PM PDT 24 Mar 17 01:10:17 PM PDT 24 671652706 ps
T2036 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1912117109 Mar 17 01:44:03 PM PDT 24 Mar 17 01:44:03 PM PDT 24 48715379 ps
T2037 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2099329221 Mar 17 01:43:38 PM PDT 24 Mar 17 01:43:42 PM PDT 24 43827111 ps
T2038 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1617431375 Mar 17 01:43:56 PM PDT 24 Mar 17 01:43:58 PM PDT 24 191394197 ps
T2039 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.561998987 Mar 17 01:09:58 PM PDT 24 Mar 17 01:10:05 PM PDT 24 240157462 ps
T2040 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2656947118 Mar 17 01:09:47 PM PDT 24 Mar 17 01:09:51 PM PDT 24 80203967 ps
T163 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1090000078 Mar 17 01:43:55 PM PDT 24 Mar 17 01:44:22 PM PDT 24 11856623128 ps
T2041 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.906980902 Mar 17 01:43:47 PM PDT 24 Mar 17 01:43:48 PM PDT 24 137813212 ps
T2042 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3656397059 Mar 17 01:44:07 PM PDT 24 Mar 17 01:44:08 PM PDT 24 20769817 ps
T2043 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4032376162 Mar 17 01:43:58 PM PDT 24 Mar 17 01:44:07 PM PDT 24 665261888 ps
T2044 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4248148249 Mar 17 01:43:47 PM PDT 24 Mar 17 01:43:50 PM PDT 24 25500035 ps
T2045 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2896314628 Mar 17 01:43:48 PM PDT 24 Mar 17 01:43:51 PM PDT 24 22434527 ps
T2046 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1870584522 Mar 17 01:10:10 PM PDT 24 Mar 17 01:10:11 PM PDT 24 48228305 ps
T2047 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.774412938 Mar 17 01:09:39 PM PDT 24 Mar 17 01:09:42 PM PDT 24 110668533 ps
T2048 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2252199270 Mar 17 01:10:07 PM PDT 24 Mar 17 01:10:09 PM PDT 24 21295856 ps
T2049 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.987223088 Mar 17 01:43:55 PM PDT 24 Mar 17 01:43:57 PM PDT 24 23000491 ps
T2050 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.179062787 Mar 17 01:44:07 PM PDT 24 Mar 17 01:44:08 PM PDT 24 47407007 ps
T2051 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1452737955 Mar 17 01:43:44 PM PDT 24 Mar 17 01:43:45 PM PDT 24 14260215 ps
T2052 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1600246053 Mar 17 01:10:10 PM PDT 24 Mar 17 01:10:11 PM PDT 24 12014898 ps
T2053 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2978112408 Mar 17 01:44:04 PM PDT 24 Mar 17 01:44:04 PM PDT 24 17744328 ps
T2054 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1189932296 Mar 17 01:10:00 PM PDT 24 Mar 17 01:10:07 PM PDT 24 224577208 ps
T2055 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1386247322 Mar 17 01:43:58 PM PDT 24 Mar 17 01:43:59 PM PDT 24 58186153 ps
T2056 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2991301191 Mar 17 01:10:00 PM PDT 24 Mar 17 01:10:04 PM PDT 24 769770636 ps
T2057 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.697408026 Mar 17 01:43:46 PM PDT 24 Mar 17 01:43:49 PM PDT 24 228154143 ps
T2058 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3353674053 Mar 17 01:44:02 PM PDT 24 Mar 17 01:44:03 PM PDT 24 42907268 ps
T2059 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.557737216 Mar 17 01:43:51 PM PDT 24 Mar 17 01:43:53 PM PDT 24 104418009 ps
T2060 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1289085707 Mar 17 01:44:02 PM PDT 24 Mar 17 01:44:03 PM PDT 24 20678028 ps
T2061 /workspace/coverage/cover_reg_top/47.spi_device_intr_test.457903449 Mar 17 01:44:03 PM PDT 24 Mar 17 01:44:04 PM PDT 24 18229429 ps
T2062 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2791076297 Mar 17 01:09:38 PM PDT 24 Mar 17 01:09:41 PM PDT 24 72419720 ps
T2063 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3782559881 Mar 17 01:10:07 PM PDT 24 Mar 17 01:10:08 PM PDT 24 59602988 ps
T2064 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2110515397 Mar 17 01:44:05 PM PDT 24 Mar 17 01:44:05 PM PDT 24 13758149 ps
T2065 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3653123941 Mar 17 01:10:09 PM PDT 24 Mar 17 01:10:31 PM PDT 24 2020000023 ps
T2066 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2817496491 Mar 17 01:09:56 PM PDT 24 Mar 17 01:10:01 PM PDT 24 202616749 ps
T2067 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3703622036 Mar 17 01:43:56 PM PDT 24 Mar 17 01:44:00 PM PDT 24 298107797 ps
T2068 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.888736680 Mar 17 01:09:57 PM PDT 24 Mar 17 01:09:59 PM PDT 24 36475175 ps
T2069 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1024520011 Mar 17 01:09:37 PM PDT 24 Mar 17 01:09:40 PM PDT 24 78675196 ps
T2070 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1547486733 Mar 17 01:43:55 PM PDT 24 Mar 17 01:43:58 PM PDT 24 141330108 ps
T2071 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1583483471 Mar 17 01:09:41 PM PDT 24 Mar 17 01:09:49 PM PDT 24 277714666 ps
T2072 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.456481139 Mar 17 01:43:44 PM PDT 24 Mar 17 01:43:45 PM PDT 24 31377855 ps
T2073 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.766311791 Mar 17 01:09:55 PM PDT 24 Mar 17 01:10:00 PM PDT 24 230441916 ps
T2074 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.178107521 Mar 17 01:10:08 PM PDT 24 Mar 17 01:10:10 PM PDT 24 38573353 ps
T2075 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.211438186 Mar 17 01:10:07 PM PDT 24 Mar 17 01:10:08 PM PDT 24 40615818 ps
T2076 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3703482529 Mar 17 01:10:09 PM PDT 24 Mar 17 01:10:14 PM PDT 24 124324137 ps
T2077 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3627963169 Mar 17 01:09:45 PM PDT 24 Mar 17 01:09:48 PM PDT 24 364484554 ps
T2078 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2741288605 Mar 17 01:09:40 PM PDT 24 Mar 17 01:09:44 PM PDT 24 216971706 ps
T2079 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.396807097 Mar 17 01:09:47 PM PDT 24 Mar 17 01:09:48 PM PDT 24 18541387 ps
T2080 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1845416691 Mar 17 01:09:51 PM PDT 24 Mar 17 01:10:08 PM PDT 24 1133969404 ps
T2081 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.290768342 Mar 17 01:09:57 PM PDT 24 Mar 17 01:10:00 PM PDT 24 41970863 ps
T2082 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.865111370 Mar 17 01:43:38 PM PDT 24 Mar 17 01:43:39 PM PDT 24 37154275 ps
T2083 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3432064355 Mar 17 01:43:46 PM PDT 24 Mar 17 01:44:26 PM PDT 24 2798085579 ps
T2084 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1720199666 Mar 17 01:43:47 PM PDT 24 Mar 17 01:43:47 PM PDT 24 22325303 ps
T2085 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.434647919 Mar 17 01:43:47 PM PDT 24 Mar 17 01:44:14 PM PDT 24 1568479969 ps
T2086 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2923386587 Mar 17 01:43:43 PM PDT 24 Mar 17 01:43:45 PM PDT 24 59149952 ps
T2087 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1388006502 Mar 17 01:09:41 PM PDT 24 Mar 17 01:09:43 PM PDT 24 40200363 ps
T2088 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2699368299 Mar 17 01:43:47 PM PDT 24 Mar 17 01:43:50 PM PDT 24 113963271 ps
T2089 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3879032698 Mar 17 01:09:57 PM PDT 24 Mar 17 01:09:59 PM PDT 24 182741605 ps
T2090 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4168495835 Mar 17 01:43:58 PM PDT 24 Mar 17 01:44:03 PM PDT 24 898413753 ps
T2091 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2957918374 Mar 17 01:43:54 PM PDT 24 Mar 17 01:43:55 PM PDT 24 43622905 ps
T2092 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1629798549 Mar 17 01:43:39 PM PDT 24 Mar 17 01:43:41 PM PDT 24 215787231 ps
T2093 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.75347419 Mar 17 01:43:46 PM PDT 24 Mar 17 01:43:47 PM PDT 24 33972912 ps
T2094 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.960320370 Mar 17 01:10:15 PM PDT 24 Mar 17 01:10:16 PM PDT 24 12637687 ps
T2095 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1101726960 Mar 17 01:10:08 PM PDT 24 Mar 17 01:10:10 PM PDT 24 99392055 ps
T2096 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3502750152 Mar 17 01:09:46 PM PDT 24 Mar 17 01:09:50 PM PDT 24 262402804 ps
T2097 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1823162464 Mar 17 01:43:49 PM PDT 24 Mar 17 01:43:50 PM PDT 24 16059057 ps
T2098 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1299598264 Mar 17 01:44:07 PM PDT 24 Mar 17 01:44:08 PM PDT 24 35297148 ps
T2099 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2071273190 Mar 17 01:43:58 PM PDT 24 Mar 17 01:44:01 PM PDT 24 411712061 ps
T2100 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4069738576 Mar 17 01:09:51 PM PDT 24 Mar 17 01:09:54 PM PDT 24 422182786 ps
T2101 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4108026081 Mar 17 01:43:57 PM PDT 24 Mar 17 01:44:00 PM PDT 24 232302332 ps
T2102 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3990699322 Mar 17 01:10:06 PM PDT 24 Mar 17 01:10:11 PM PDT 24 316407745 ps
T2103 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2676485837 Mar 17 01:09:38 PM PDT 24 Mar 17 01:09:40 PM PDT 24 57265157 ps
T2104 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3162281572 Mar 17 01:09:40 PM PDT 24 Mar 17 01:09:42 PM PDT 24 70177313 ps
T2105 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3944924958 Mar 17 01:09:37 PM PDT 24 Mar 17 01:09:38 PM PDT 24 89866091 ps
T2106 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1623336276 Mar 17 01:10:09 PM PDT 24 Mar 17 01:10:11 PM PDT 24 14491700 ps
T2107 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4058731357 Mar 17 01:10:07 PM PDT 24 Mar 17 01:10:09 PM PDT 24 12300772 ps
T2108 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2177523634 Mar 17 01:09:46 PM PDT 24 Mar 17 01:09:50 PM PDT 24 150438649 ps
T2109 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.839290428 Mar 17 01:10:09 PM PDT 24 Mar 17 01:10:11 PM PDT 24 18509545 ps
T2110 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2309279972 Mar 17 01:09:39 PM PDT 24 Mar 17 01:09:41 PM PDT 24 203873616 ps
T2111 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.796659749 Mar 17 01:09:56 PM PDT 24 Mar 17 01:09:57 PM PDT 24 162514973 ps
T2112 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2969898078 Mar 17 01:43:56 PM PDT 24 Mar 17 01:43:59 PM PDT 24 341481220 ps
T2113 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2001427244 Mar 17 01:10:08 PM PDT 24 Mar 17 01:10:10 PM PDT 24 12313190 ps
T2114 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.46612824 Mar 17 01:43:52 PM PDT 24 Mar 17 01:43:53 PM PDT 24 66244228 ps
T2115 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2804785751 Mar 17 01:43:58 PM PDT 24 Mar 17 01:44:02 PM PDT 24 66141621 ps
T2116 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.63888799 Mar 17 01:09:47 PM PDT 24 Mar 17 01:09:49 PM PDT 24 151966366 ps
T2117 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.693148325 Mar 17 01:43:53 PM PDT 24 Mar 17 01:43:55 PM PDT 24 49019638 ps
T2118 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2884440548 Mar 17 01:43:44 PM PDT 24 Mar 17 01:43:46 PM PDT 24 199432529 ps
T2119 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2983748646 Mar 17 01:10:08 PM PDT 24 Mar 17 01:10:10 PM PDT 24 16723115 ps
T2120 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1907067328 Mar 17 01:44:03 PM PDT 24 Mar 17 01:44:06 PM PDT 24 223986022 ps
T2121 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3957001461 Mar 17 01:43:48 PM PDT 24 Mar 17 01:43:50 PM PDT 24 77022019 ps
T2122 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3498950876 Mar 17 01:10:07 PM PDT 24 Mar 17 01:10:10 PM PDT 24 27048203 ps
T2123 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3796731439 Mar 17 01:09:46 PM PDT 24 Mar 17 01:09:47 PM PDT 24 14008530 ps
T2124 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1746715755 Mar 17 01:43:44 PM PDT 24 Mar 17 01:43:46 PM PDT 24 217869240 ps
T2125 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3795989850 Mar 17 01:44:06 PM PDT 24 Mar 17 01:44:07 PM PDT 24 48502744 ps
T2126 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3041723655 Mar 17 01:09:47 PM PDT 24 Mar 17 01:09:48 PM PDT 24 12329201 ps
T2127 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1140450951 Mar 17 01:43:55 PM PDT 24 Mar 17 01:44:15 PM PDT 24 943250656 ps
T2128 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.490262869 Mar 17 01:43:45 PM PDT 24 Mar 17 01:43:46 PM PDT 24 20400888 ps
T2129 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.374982774 Mar 17 01:44:00 PM PDT 24 Mar 17 01:44:23 PM PDT 24 3162970606 ps
T2130 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2440330033 Mar 17 01:10:08 PM PDT 24 Mar 17 01:10:09 PM PDT 24 16510349 ps
T2131 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2188208544 Mar 17 01:43:41 PM PDT 24 Mar 17 01:43:43 PM PDT 24 82050279 ps
T2132 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3795204609 Mar 17 01:43:48 PM PDT 24 Mar 17 01:44:02 PM PDT 24 631022677 ps
T2133 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4230522434 Mar 17 01:10:00 PM PDT 24 Mar 17 01:10:02 PM PDT 24 47637349 ps
T2134 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1458251887 Mar 17 01:43:57 PM PDT 24 Mar 17 01:44:24 PM PDT 24 3899394651 ps
T2135 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1039059970 Mar 17 01:43:55 PM PDT 24 Mar 17 01:43:57 PM PDT 24 150936483 ps
T2136 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1064052310 Mar 17 01:09:54 PM PDT 24 Mar 17 01:09:56 PM PDT 24 46481071 ps
T2137 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4034847162 Mar 17 01:43:49 PM PDT 24 Mar 17 01:44:03 PM PDT 24 803660654 ps
T2138 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3425967242 Mar 17 01:09:47 PM PDT 24 Mar 17 01:09:49 PM PDT 24 29331105 ps
T2139 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1940339309 Mar 17 01:43:51 PM PDT 24 Mar 17 01:43:54 PM PDT 24 27699429 ps
T2140 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3158874503 Mar 17 01:43:44 PM PDT 24 Mar 17 01:44:19 PM PDT 24 4353151333 ps
T2141 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2536375991 Mar 17 01:43:44 PM PDT 24 Mar 17 01:43:47 PM PDT 24 244089665 ps
T2142 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.270197071 Mar 17 01:43:51 PM PDT 24 Mar 17 01:43:55 PM PDT 24 198089467 ps
T2143 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2240298636 Mar 17 01:09:40 PM PDT 24 Mar 17 01:09:41 PM PDT 24 31728294 ps
T2144 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1406199823 Mar 17 01:43:50 PM PDT 24 Mar 17 01:43:53 PM PDT 24 600709759 ps
T2145 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1518479578 Mar 17 01:44:00 PM PDT 24 Mar 17 01:44:01 PM PDT 24 108884307 ps
T2146 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.433251091 Mar 17 01:10:12 PM PDT 24 Mar 17 01:10:13 PM PDT 24 12633676 ps
T2147 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3670226228 Mar 17 01:43:51 PM PDT 24 Mar 17 01:43:53 PM PDT 24 97282342 ps
T2148 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1955783424 Mar 17 01:10:07 PM PDT 24 Mar 17 01:10:10 PM PDT 24 18617036 ps
T2149 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4224272113 Mar 17 01:09:47 PM PDT 24 Mar 17 01:09:48 PM PDT 24 78672514 ps
T2150 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4069690251 Mar 17 01:43:43 PM PDT 24 Mar 17 01:43:44 PM PDT 24 22946530 ps
T2151 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1997930729 Mar 17 01:43:47 PM PDT 24 Mar 17 01:43:47 PM PDT 24 13420017 ps
T2152 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2913803417 Mar 17 01:09:45 PM PDT 24 Mar 17 01:10:05 PM PDT 24 1289537447 ps
T2153 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1355038718 Mar 17 01:44:02 PM PDT 24 Mar 17 01:44:03 PM PDT 24 43738982 ps
T2154 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3488756291 Mar 17 01:09:46 PM PDT 24 Mar 17 01:09:46 PM PDT 24 24411717 ps
T2155 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1383018785 Mar 17 01:43:43 PM PDT 24 Mar 17 01:43:44 PM PDT 24 125041349 ps
T2156 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.130648453 Mar 17 01:10:07 PM PDT 24 Mar 17 01:10:12 PM PDT 24 286225832 ps
T2157 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1439881773 Mar 17 01:09:38 PM PDT 24 Mar 17 01:09:42 PM PDT 24 61724695 ps
T2158 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.377270462 Mar 17 01:09:38 PM PDT 24 Mar 17 01:09:46 PM PDT 24 431365494 ps
T2159 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.241384214 Mar 17 01:09:39 PM PDT 24 Mar 17 01:09:52 PM PDT 24 219030147 ps
T2160 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1151517116 Mar 17 01:44:07 PM PDT 24 Mar 17 01:44:09 PM PDT 24 26318875 ps
T2161 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4195605501 Mar 17 01:44:01 PM PDT 24 Mar 17 01:44:02 PM PDT 24 16564066 ps
T2162 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2229929361 Mar 17 01:09:40 PM PDT 24 Mar 17 01:09:54 PM PDT 24 641908062 ps
T2163 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2826165375 Mar 17 01:09:40 PM PDT 24 Mar 17 01:09:52 PM PDT 24 2225025100 ps
T2164 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3035031998 Mar 17 01:43:40 PM PDT 24 Mar 17 01:43:43 PM PDT 24 146183445 ps
T2165 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.867730721 Mar 17 01:09:41 PM PDT 24 Mar 17 01:09:43 PM PDT 24 663681440 ps
T2166 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.887261364 Mar 17 01:43:57 PM PDT 24 Mar 17 01:43:59 PM PDT 24 417973840 ps
T2167 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1679206668 Mar 17 01:43:54 PM PDT 24 Mar 17 01:43:57 PM PDT 24 100556565 ps
T2168 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.376626305 Mar 17 01:44:02 PM PDT 24 Mar 17 01:44:03 PM PDT 24 33233653 ps
T2169 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3178759527 Mar 17 01:43:39 PM PDT 24 Mar 17 01:43:48 PM PDT 24 110104031 ps
T2170 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1463580502 Mar 17 01:09:56 PM PDT 24 Mar 17 01:09:59 PM PDT 24 48234955 ps
T2171 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.801762006 Mar 17 01:43:57 PM PDT 24 Mar 17 01:43:59 PM PDT 24 95008661 ps
T2172 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.220024322 Mar 17 01:09:57 PM PDT 24 Mar 17 01:10:00 PM PDT 24 22425651 ps
T2173 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3152658455 Mar 17 01:44:01 PM PDT 24 Mar 17 01:44:04 PM PDT 24 388355839 ps
T2174 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3696444995 Mar 17 01:43:45 PM PDT 24 Mar 17 01:43:48 PM PDT 24 528393626 ps
T2175 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3901220771 Mar 17 01:44:02 PM PDT 24 Mar 17 01:44:04 PM PDT 24 332870909 ps
T2176 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2107518629 Mar 17 01:44:01 PM PDT 24 Mar 17 01:44:02 PM PDT 24 48957623 ps
T2177 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4277719385 Mar 17 01:43:56 PM PDT 24 Mar 17 01:43:58 PM PDT 24 37948353 ps
T2178 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3887222148 Mar 17 01:43:49 PM PDT 24 Mar 17 01:43:54 PM PDT 24 171481555 ps
T2179 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4183411634 Mar 17 01:09:49 PM PDT 24 Mar 17 01:09:52 PM PDT 24 37948945 ps
T2180 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2075442259 Mar 17 01:43:45 PM PDT 24 Mar 17 01:43:47 PM PDT 24 109204108 ps
T2181 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4063367505 Mar 17 01:10:10 PM PDT 24 Mar 17 01:10:12 PM PDT 24 24782901 ps
T2182 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3204483154 Mar 17 01:10:07 PM PDT 24 Mar 17 01:10:08 PM PDT 24 27732664 ps
T2183 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.577806576 Mar 17 01:09:37 PM PDT 24 Mar 17 01:09:45 PM PDT 24 143770483 ps
T2184 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2905496633 Mar 17 01:09:58 PM PDT 24 Mar 17 01:10:03 PM PDT 24 41270278 ps
T2185 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1194708674 Mar 17 01:09:51 PM PDT 24 Mar 17 01:09:51 PM PDT 24 13908287 ps
T2186 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3920675683 Mar 17 01:09:50 PM PDT 24 Mar 17 01:09:55 PM PDT 24 56613968 ps
T2187 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.791862535 Mar 17 01:10:11 PM PDT 24 Mar 17 01:10:14 PM PDT 24 461925366 ps
T2188 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1035783438 Mar 17 01:43:56 PM PDT 24 Mar 17 01:43:58 PM PDT 24 87710498 ps
T2189 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4224227314 Mar 17 01:10:11 PM PDT 24 Mar 17 01:10:15 PM PDT 24 189679080 ps
T2190 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3126785150 Mar 17 01:43:58 PM PDT 24 Mar 17 01:43:58 PM PDT 24 24067948 ps
T2191 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3192951744 Mar 17 01:09:45 PM PDT 24 Mar 17 01:09:48 PM PDT 24 380312899 ps
T2192 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3175880677 Mar 17 01:43:52 PM PDT 24 Mar 17 01:43:52 PM PDT 24 40799322 ps
T2193 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3109789956 Mar 17 01:43:47 PM PDT 24 Mar 17 01:43:53 PM PDT 24 389429617 ps
T2194 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2959641548 Mar 17 01:44:03 PM PDT 24 Mar 17 01:44:04 PM PDT 24 21131018 ps
T2195 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3046889527 Mar 17 01:43:51 PM PDT 24 Mar 17 01:43:54 PM PDT 24 231708930 ps
T2196 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3338976547 Mar 17 01:43:46 PM PDT 24 Mar 17 01:43:49 PM PDT 24 58829280 ps
T2197 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1030874682 Mar 17 01:09:46 PM PDT 24 Mar 17 01:09:50 PM PDT 24 1399758461 ps
T2198 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3531205033 Mar 17 01:09:56 PM PDT 24 Mar 17 01:10:01 PM PDT 24 292810392 ps
T2199 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3173038554 Mar 17 01:09:47 PM PDT 24 Mar 17 01:09:49 PM PDT 24 31094813 ps
T2200 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4247192163 Mar 17 01:09:48 PM PDT 24 Mar 17 01:09:53 PM PDT 24 130525148 ps
T2201 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2463024867 Mar 17 01:09:41 PM PDT 24 Mar 17 01:09:43 PM PDT 24 170516460 ps
T2202 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1182981934 Mar 17 01:09:44 PM PDT 24 Mar 17 01:10:12 PM PDT 24 2470702564 ps

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1289543804
Short name T7
Test name
Test status
Simulation time 105535034002 ps
CPU time 166.68 seconds
Started Mar 17 03:13:18 PM PDT 24
Finished Mar 17 03:16:06 PM PDT 24
Peak memory 265460 kb
Host smart-ddc70c1e-3428-41d1-8908-c423b9f7c96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289543804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1289543804
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3087158292
Short name T11
Test name
Test status
Simulation time 6712198858 ps
CPU time 113.69 seconds
Started Mar 17 01:28:22 PM PDT 24
Finished Mar 17 01:30:16 PM PDT 24
Peak memory 263976 kb
Host smart-738e78e2-438c-49c6-9bb6-b334a5761e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087158292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3087158292
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.531518131
Short name T29
Test name
Test status
Simulation time 127598358025 ps
CPU time 262.67 seconds
Started Mar 17 01:30:12 PM PDT 24
Finished Mar 17 01:34:35 PM PDT 24
Peak memory 289456 kb
Host smart-1e5e6f07-7346-4d0c-8d63-882dbdbf2650
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531518131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.531518131
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.4071379516
Short name T152
Test name
Test status
Simulation time 29165195989 ps
CPU time 75.81 seconds
Started Mar 17 01:29:40 PM PDT 24
Finished Mar 17 01:30:56 PM PDT 24
Peak memory 259000 kb
Host smart-8d100dfe-03b8-408a-9604-9c2fc8d098be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071379516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.4071379516
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1882447936
Short name T85
Test name
Test status
Simulation time 143197546 ps
CPU time 3.51 seconds
Started Mar 17 01:09:41 PM PDT 24
Finished Mar 17 01:09:45 PM PDT 24
Peak memory 216504 kb
Host smart-485fc272-48c1-46a9-84db-06733ad545ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882447936 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.1882447936
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.2062001532
Short name T189
Test name
Test status
Simulation time 224347870564 ps
CPU time 519.54 seconds
Started Mar 17 01:31:01 PM PDT 24
Finished Mar 17 01:39:41 PM PDT 24
Peak memory 285332 kb
Host smart-ff0f4fd7-1776-49fc-b500-3e48a9be5cd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062001532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.2062001532
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.3643191636
Short name T594
Test name
Test status
Simulation time 33316864 ps
CPU time 0.73 seconds
Started Mar 17 03:14:09 PM PDT 24
Finished Mar 17 03:14:10 PM PDT 24
Peak memory 216032 kb
Host smart-0f9231cb-e541-4858-bf50-a53f7f1bb5bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643191636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.3643191636
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2733646251
Short name T30
Test name
Test status
Simulation time 320849739461 ps
CPU time 555.45 seconds
Started Mar 17 01:32:48 PM PDT 24
Finished Mar 17 01:42:04 PM PDT 24
Peak memory 249808 kb
Host smart-afdadf0f-9b9e-45dc-9d16-e0a7255c7b74
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733646251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2733646251
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1593888126
Short name T168
Test name
Test status
Simulation time 329192118459 ps
CPU time 710.25 seconds
Started Mar 17 01:32:22 PM PDT 24
Finished Mar 17 01:44:12 PM PDT 24
Peak memory 297936 kb
Host smart-1cb86ea0-9a82-407f-a801-b31d87337b56
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593888126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1593888126
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3492614409
Short name T48
Test name
Test status
Simulation time 91967590198 ps
CPU time 381.77 seconds
Started Mar 17 03:15:16 PM PDT 24
Finished Mar 17 03:21:38 PM PDT 24
Peak memory 267640 kb
Host smart-e07a9121-e9db-4628-86ea-0b8664eb020f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492614409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3492614409
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2515776992
Short name T324
Test name
Test status
Simulation time 39741187 ps
CPU time 0.75 seconds
Started Mar 17 01:28:29 PM PDT 24
Finished Mar 17 01:28:29 PM PDT 24
Peak memory 205096 kb
Host smart-f450020c-4899-4b08-91bd-0d6b2d85ce60
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515776992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
515776992
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.1083852633
Short name T33
Test name
Test status
Simulation time 1294196413 ps
CPU time 4.68 seconds
Started Mar 17 01:29:40 PM PDT 24
Finished Mar 17 01:29:45 PM PDT 24
Peak memory 222468 kb
Host smart-7fd7ff6b-c903-4a5b-9a9b-a59419fdad74
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1083852633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.1083852633
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4195495567
Short name T35
Test name
Test status
Simulation time 45360842768 ps
CPU time 152.54 seconds
Started Mar 17 03:15:58 PM PDT 24
Finished Mar 17 03:18:31 PM PDT 24
Peak memory 269112 kb
Host smart-388f84a0-f9cf-465e-a5f5-b530995339ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195495567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4195495567
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2003711871
Short name T65
Test name
Test status
Simulation time 1076102016 ps
CPU time 1.38 seconds
Started Mar 17 03:12:48 PM PDT 24
Finished Mar 17 03:12:51 PM PDT 24
Peak memory 234864 kb
Host smart-7b066008-6f77-4564-838c-d75070222bf8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003711871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2003711871
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2784717604
Short name T150
Test name
Test status
Simulation time 4480470572 ps
CPU time 25.28 seconds
Started Mar 17 01:44:03 PM PDT 24
Finished Mar 17 01:44:28 PM PDT 24
Peak memory 215272 kb
Host smart-f647dbec-0259-45ad-859d-cf83604e40b7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784717604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2784717604
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.1366417742
Short name T112
Test name
Test status
Simulation time 2539267498 ps
CPU time 16.23 seconds
Started Mar 17 01:09:41 PM PDT 24
Finished Mar 17 01:09:58 PM PDT 24
Peak memory 206908 kb
Host smart-c22011d7-de59-4e5d-9032-b4582b26a2bd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366417742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.1366417742
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3886394148
Short name T91
Test name
Test status
Simulation time 791616314 ps
CPU time 4.32 seconds
Started Mar 17 01:44:00 PM PDT 24
Finished Mar 17 01:44:04 PM PDT 24
Peak memory 215164 kb
Host smart-d31876ab-355d-4e0d-a5c0-d7ac55052cec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886394148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3886394148
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.816163210
Short name T36
Test name
Test status
Simulation time 32362724884 ps
CPU time 331.4 seconds
Started Mar 17 03:17:15 PM PDT 24
Finished Mar 17 03:22:47 PM PDT 24
Peak memory 275564 kb
Host smart-607ab09e-ac74-4099-905d-0573701964c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816163210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.816163210
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_mem_parity.459009249
Short name T735
Test name
Test status
Simulation time 403104449 ps
CPU time 1.09 seconds
Started Mar 17 01:28:18 PM PDT 24
Finished Mar 17 01:28:19 PM PDT 24
Peak memory 216480 kb
Host smart-31e619a6-25f0-44c2-b07c-2fafcdd77759
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459009249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
0.spi_device_mem_parity.459009249
Directory /workspace/0.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3419609456
Short name T23
Test name
Test status
Simulation time 17244372499 ps
CPU time 93.74 seconds
Started Mar 17 01:29:40 PM PDT 24
Finished Mar 17 01:31:14 PM PDT 24
Peak memory 233772 kb
Host smart-a908b92f-16b2-4d77-b838-97a771f7853a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419609456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3419609456
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2489716065
Short name T153
Test name
Test status
Simulation time 34863005474 ps
CPU time 207.59 seconds
Started Mar 17 03:14:21 PM PDT 24
Finished Mar 17 03:17:49 PM PDT 24
Peak memory 272280 kb
Host smart-5723a1d3-43a3-41ab-a02c-601f58e8bb65
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489716065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2489716065
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1354203651
Short name T41
Test name
Test status
Simulation time 46605028042 ps
CPU time 489.67 seconds
Started Mar 17 01:32:35 PM PDT 24
Finished Mar 17 01:40:44 PM PDT 24
Peak memory 297576 kb
Host smart-4519e2d2-44c0-41a8-b27f-83ac55f5925e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354203651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1354203651
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1849489111
Short name T14
Test name
Test status
Simulation time 5930435525 ps
CPU time 101.17 seconds
Started Mar 17 01:30:07 PM PDT 24
Finished Mar 17 01:31:49 PM PDT 24
Peak memory 253496 kb
Host smart-ba7bcb92-5e4f-41f7-b926-b80e391a379a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849489111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1849489111
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.312049569
Short name T278
Test name
Test status
Simulation time 7240588059 ps
CPU time 35.73 seconds
Started Mar 17 03:13:06 PM PDT 24
Finished Mar 17 03:13:42 PM PDT 24
Peak memory 241020 kb
Host smart-132064f5-b997-4db2-9cae-b63204761dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312049569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.312049569
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1587964421
Short name T215
Test name
Test status
Simulation time 80610322737 ps
CPU time 538.57 seconds
Started Mar 17 03:17:16 PM PDT 24
Finished Mar 17 03:26:15 PM PDT 24
Peak memory 273536 kb
Host smart-905d714f-5d1f-457c-8b34-ef91d8b45fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587964421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1587964421
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2079589230
Short name T100
Test name
Test status
Simulation time 122893210 ps
CPU time 4.33 seconds
Started Mar 17 01:43:54 PM PDT 24
Finished Mar 17 01:43:58 PM PDT 24
Peak memory 215276 kb
Host smart-692ecab7-d7b6-470d-986d-092b1e0dde80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079589230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2079589230
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3563014075
Short name T246
Test name
Test status
Simulation time 25073397017 ps
CPU time 94.27 seconds
Started Mar 17 03:15:41 PM PDT 24
Finished Mar 17 03:17:15 PM PDT 24
Peak memory 266544 kb
Host smart-b2c10699-2937-43d1-b338-d05d4cbff7ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563014075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3563014075
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1650683947
Short name T202
Test name
Test status
Simulation time 418032565667 ps
CPU time 770.85 seconds
Started Mar 17 01:31:44 PM PDT 24
Finished Mar 17 01:44:35 PM PDT 24
Peak memory 263684 kb
Host smart-d895883f-0d7d-481b-b2f3-c1bb35c95bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650683947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1650683947
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.2516699352
Short name T119
Test name
Test status
Simulation time 124141436052 ps
CPU time 222 seconds
Started Mar 17 01:31:57 PM PDT 24
Finished Mar 17 01:35:39 PM PDT 24
Peak memory 287580 kb
Host smart-8e6c575c-a891-4edd-8dd6-5ffa4daa5bd1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516699352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.2516699352
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2518346968
Short name T137
Test name
Test status
Simulation time 104017459195 ps
CPU time 246.39 seconds
Started Mar 17 01:28:50 PM PDT 24
Finished Mar 17 01:32:57 PM PDT 24
Peak memory 265084 kb
Host smart-04af9875-f59c-47b8-9404-0609bce17fcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2518346968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2518346968
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3808740018
Short name T239
Test name
Test status
Simulation time 14943196730 ps
CPU time 116.67 seconds
Started Mar 17 03:14:34 PM PDT 24
Finished Mar 17 03:16:31 PM PDT 24
Peak memory 251136 kb
Host smart-53b8b7ab-8169-40e0-81d6-13e98a5d06b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808740018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3808740018
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3398069193
Short name T277
Test name
Test status
Simulation time 1130932812 ps
CPU time 14.2 seconds
Started Mar 17 03:16:00 PM PDT 24
Finished Mar 17 03:16:14 PM PDT 24
Peak memory 235116 kb
Host smart-d199032a-b9fa-4660-8ee4-aec37733826d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3398069193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3398069193
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3159101596
Short name T162
Test name
Test status
Simulation time 2085185275 ps
CPU time 23.59 seconds
Started Mar 17 01:43:59 PM PDT 24
Finished Mar 17 01:44:23 PM PDT 24
Peak memory 215712 kb
Host smart-8868f893-3695-4b9c-b170-41f9b342246b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159101596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3159101596
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1987601856
Short name T276
Test name
Test status
Simulation time 46465638900 ps
CPU time 220.17 seconds
Started Mar 17 01:30:00 PM PDT 24
Finished Mar 17 01:33:41 PM PDT 24
Peak memory 264308 kb
Host smart-0a25bb25-f6a6-4257-8d59-1dfa893476de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987601856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1987601856
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.1244765544
Short name T265
Test name
Test status
Simulation time 828957289713 ps
CPU time 591.83 seconds
Started Mar 17 01:29:30 PM PDT 24
Finished Mar 17 01:39:23 PM PDT 24
Peak memory 272468 kb
Host smart-a3c63b7b-b947-4210-b962-da301a12452a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244765544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.1244765544
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1046311655
Short name T89
Test name
Test status
Simulation time 1957876430 ps
CPU time 8.56 seconds
Started Mar 17 01:43:49 PM PDT 24
Finished Mar 17 01:43:58 PM PDT 24
Peak memory 223092 kb
Host smart-3b8a364c-6da1-4613-b641-cbc62254d858
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046311655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1046311655
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2997439446
Short name T80
Test name
Test status
Simulation time 1959981873 ps
CPU time 16.31 seconds
Started Mar 17 03:12:50 PM PDT 24
Finished Mar 17 03:13:07 PM PDT 24
Peak memory 216140 kb
Host smart-33b49d1a-c231-410a-b0f6-d685f348d7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997439446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2997439446
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2265712866
Short name T156
Test name
Test status
Simulation time 576825714 ps
CPU time 3.95 seconds
Started Mar 17 01:09:39 PM PDT 24
Finished Mar 17 01:09:44 PM PDT 24
Peak memory 215236 kb
Host smart-c8ad0313-7146-4fe5-9667-46959c4c2611
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265712866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
265712866
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.3550317065
Short name T1650
Test name
Test status
Simulation time 147191111243 ps
CPU time 269.4 seconds
Started Mar 17 03:13:46 PM PDT 24
Finished Mar 17 03:18:16 PM PDT 24
Peak memory 263824 kb
Host smart-8b978f12-e7a8-4c8a-8f1b-d6a0c38c928a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550317065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.3550317065
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1196128
Short name T255
Test name
Test status
Simulation time 12723697991 ps
CPU time 58.73 seconds
Started Mar 17 03:12:55 PM PDT 24
Finished Mar 17 03:13:54 PM PDT 24
Peak memory 236172 kb
Host smart-7a1d51d7-a446-451f-b5bb-24bb54ad1aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1196128
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3563570877
Short name T204
Test name
Test status
Simulation time 6848515790 ps
CPU time 23.36 seconds
Started Mar 17 01:30:07 PM PDT 24
Finished Mar 17 01:30:31 PM PDT 24
Peak memory 232828 kb
Host smart-b19e4da5-7e87-409b-bfc3-cd316d85d431
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563570877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3563570877
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2382250704
Short name T272
Test name
Test status
Simulation time 30671399279 ps
CPU time 83.74 seconds
Started Mar 17 03:14:52 PM PDT 24
Finished Mar 17 03:16:16 PM PDT 24
Peak memory 249064 kb
Host smart-6ec43ebf-fe86-41b8-b077-9a62b1bff42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382250704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2382250704
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2507947840
Short name T170
Test name
Test status
Simulation time 762693560 ps
CPU time 3.91 seconds
Started Mar 17 01:30:01 PM PDT 24
Finished Mar 17 01:30:05 PM PDT 24
Peak memory 223960 kb
Host smart-5190f71c-ea15-48d1-b13d-469b9599c8ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507947840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2507947840
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1629798549
Short name T2092
Test name
Test status
Simulation time 215787231 ps
CPU time 1.4 seconds
Started Mar 17 01:43:39 PM PDT 24
Finished Mar 17 01:43:41 PM PDT 24
Peak memory 215976 kb
Host smart-9c900bec-b490-4840-b961-0683cc70b578
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629798549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1629798549
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2279097981
Short name T98
Test name
Test status
Simulation time 54414750 ps
CPU time 4.35 seconds
Started Mar 17 01:09:41 PM PDT 24
Finished Mar 17 01:09:46 PM PDT 24
Peak memory 217268 kb
Host smart-8b4ad0a8-8a43-4286-834c-89eebee5d448
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279097981 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2279097981
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3178759527
Short name T2169
Test name
Test status
Simulation time 110104031 ps
CPU time 8.07 seconds
Started Mar 17 01:43:39 PM PDT 24
Finished Mar 17 01:43:48 PM PDT 24
Peak memory 206840 kb
Host smart-e8e86c88-be63-4aeb-a4b3-157928a328b5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178759527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3178759527
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3075543307
Short name T106
Test name
Test status
Simulation time 2171558565 ps
CPU time 35.33 seconds
Started Mar 17 01:09:37 PM PDT 24
Finished Mar 17 01:10:13 PM PDT 24
Peak memory 206768 kb
Host smart-eb1952c9-1da2-4000-980b-d42a146f364a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075543307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.3075543307
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.482119370
Short name T1966
Test name
Test status
Simulation time 339686784 ps
CPU time 12.43 seconds
Started Mar 17 01:43:40 PM PDT 24
Finished Mar 17 01:43:53 PM PDT 24
Peak memory 206888 kb
Host smart-2269329a-6409-4ade-a732-e80dfe5e217b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482119370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.482119370
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1855560196
Short name T76
Test name
Test status
Simulation time 34394512 ps
CPU time 1.19 seconds
Started Mar 17 01:09:49 PM PDT 24
Finished Mar 17 01:09:50 PM PDT 24
Peak memory 206936 kb
Host smart-98178b42-5085-449e-8605-0674949bceda
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855560196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1855560196
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1854985474
Short name T1953
Test name
Test status
Simulation time 183415638 ps
CPU time 3.81 seconds
Started Mar 17 01:43:42 PM PDT 24
Finished Mar 17 01:43:45 PM PDT 24
Peak memory 216576 kb
Host smart-35796d2a-578e-4ac6-91c2-142973a9f199
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854985474 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1854985474
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1024520011
Short name T2069
Test name
Test status
Simulation time 78675196 ps
CPU time 2.2 seconds
Started Mar 17 01:09:37 PM PDT 24
Finished Mar 17 01:09:40 PM PDT 24
Peak memory 215012 kb
Host smart-61d6ffa7-d13b-48b3-9a55-010375bb01d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024520011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
024520011
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.2211094296
Short name T109
Test name
Test status
Simulation time 176241724 ps
CPU time 1.93 seconds
Started Mar 17 01:43:40 PM PDT 24
Finished Mar 17 01:43:42 PM PDT 24
Peak memory 215076 kb
Host smart-7c5e8f59-0f82-4c12-bf61-7dc1455caff8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211094296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2
211094296
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2678782936
Short name T2027
Test name
Test status
Simulation time 26483928 ps
CPU time 0.71 seconds
Started Mar 17 01:09:38 PM PDT 24
Finished Mar 17 01:09:39 PM PDT 24
Peak memory 203248 kb
Host smart-35ede2e5-76c6-4ebd-80af-c133a5fd1ae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678782936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
678782936
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.865111370
Short name T2082
Test name
Test status
Simulation time 37154275 ps
CPU time 0.74 seconds
Started Mar 17 01:43:38 PM PDT 24
Finished Mar 17 01:43:39 PM PDT 24
Peak memory 203248 kb
Host smart-215466b3-ddc1-477e-83ad-e2df3c65d975
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865111370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.865111370
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2075442259
Short name T2180
Test name
Test status
Simulation time 109204108 ps
CPU time 1.93 seconds
Started Mar 17 01:43:45 PM PDT 24
Finished Mar 17 01:43:47 PM PDT 24
Peak memory 215040 kb
Host smart-8018d17e-d837-4aa9-bc5f-62580bdfed20
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075442259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2075442259
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2791076297
Short name T2062
Test name
Test status
Simulation time 72419720 ps
CPU time 2.23 seconds
Started Mar 17 01:09:38 PM PDT 24
Finished Mar 17 01:09:41 PM PDT 24
Peak memory 215052 kb
Host smart-4d24a855-3226-4542-bdf9-7592683b443f
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791076297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2791076297
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1452737955
Short name T2051
Test name
Test status
Simulation time 14260215 ps
CPU time 0.69 seconds
Started Mar 17 01:43:44 PM PDT 24
Finished Mar 17 01:43:45 PM PDT 24
Peak memory 203216 kb
Host smart-93a9600b-bccc-40a9-8777-feeb88b5e3e4
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452737955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1452737955
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.1863383316
Short name T1920
Test name
Test status
Simulation time 31574174 ps
CPU time 0.65 seconds
Started Mar 17 01:09:39 PM PDT 24
Finished Mar 17 01:09:41 PM PDT 24
Peak memory 203180 kb
Host smart-6ad7ba87-ec71-425c-9f99-b2c0933b3202
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863383316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.1863383316
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1746715755
Short name T2124
Test name
Test status
Simulation time 217869240 ps
CPU time 1.78 seconds
Started Mar 17 01:43:44 PM PDT 24
Finished Mar 17 01:43:46 PM PDT 24
Peak memory 206764 kb
Host smart-768fab61-a9a3-4cce-b1b5-98044f9646b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746715755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1746715755
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.774412938
Short name T2047
Test name
Test status
Simulation time 110668533 ps
CPU time 3.07 seconds
Started Mar 17 01:09:39 PM PDT 24
Finished Mar 17 01:09:42 PM PDT 24
Peak memory 214996 kb
Host smart-23231ec2-0ec5-43a0-ad13-dd061a6082de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774412938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.774412938
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3035031998
Short name T2164
Test name
Test status
Simulation time 146183445 ps
CPU time 2.29 seconds
Started Mar 17 01:43:40 PM PDT 24
Finished Mar 17 01:43:43 PM PDT 24
Peak memory 215244 kb
Host smart-961e22f3-bf6f-41e7-97b2-83fea35a8f5c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035031998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
035031998
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.1583483471
Short name T2071
Test name
Test status
Simulation time 277714666 ps
CPU time 8.08 seconds
Started Mar 17 01:09:41 PM PDT 24
Finished Mar 17 01:09:49 PM PDT 24
Peak memory 215160 kb
Host smart-85205d29-8298-40ad-b12c-7efee44f5c51
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583483471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.1583483471
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.4251491646
Short name T1984
Test name
Test status
Simulation time 2051020022 ps
CPU time 21.69 seconds
Started Mar 17 01:43:36 PM PDT 24
Finished Mar 17 01:43:58 PM PDT 24
Peak memory 215360 kb
Host smart-76a8471a-625d-49d6-900d-ae6e0b335b0a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251491646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.4251491646
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.314127814
Short name T115
Test name
Test status
Simulation time 1469198136 ps
CPU time 8.64 seconds
Started Mar 17 01:43:44 PM PDT 24
Finished Mar 17 01:43:53 PM PDT 24
Peak memory 206864 kb
Host smart-4201667f-5127-41b6-9aed-7700610e396b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314127814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.314127814
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.340604407
Short name T1999
Test name
Test status
Simulation time 381698573 ps
CPU time 8.47 seconds
Started Mar 17 01:09:39 PM PDT 24
Finished Mar 17 01:09:47 PM PDT 24
Peak memory 206896 kb
Host smart-85f49ec9-a2f2-4be0-83a9-32a9ab4d91e5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340604407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.340604407
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3158874503
Short name T2140
Test name
Test status
Simulation time 4353151333 ps
CPU time 34.46 seconds
Started Mar 17 01:43:44 PM PDT 24
Finished Mar 17 01:44:19 PM PDT 24
Peak memory 206960 kb
Host smart-4a751887-4c01-4b4c-99b7-1333d94dc632
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158874503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3158874503
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3895123592
Short name T1980
Test name
Test status
Simulation time 3778752570 ps
CPU time 26.88 seconds
Started Mar 17 01:09:42 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 206860 kb
Host smart-01571a7d-6a8f-4d86-bbf0-870a31364c93
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895123592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3895123592
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2463024867
Short name T2201
Test name
Test status
Simulation time 170516460 ps
CPU time 1.52 seconds
Started Mar 17 01:09:41 PM PDT 24
Finished Mar 17 01:09:43 PM PDT 24
Peak memory 206872 kb
Host smart-f1240c8a-daa8-4669-8609-1804ffdf26b7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463024867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.2463024867
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.490262869
Short name T2128
Test name
Test status
Simulation time 20400888 ps
CPU time 1.22 seconds
Started Mar 17 01:43:45 PM PDT 24
Finished Mar 17 01:43:46 PM PDT 24
Peak memory 206864 kb
Host smart-112d947e-2291-49b7-b96b-8bf2b585be96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490262869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.490262869
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1806132182
Short name T1942
Test name
Test status
Simulation time 169303073 ps
CPU time 2.63 seconds
Started Mar 17 01:43:46 PM PDT 24
Finished Mar 17 01:43:49 PM PDT 24
Peak memory 216200 kb
Host smart-c805d6e2-2cb9-4661-a112-71e5e6849e86
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806132182 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.1806132182
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4095184020
Short name T1965
Test name
Test status
Simulation time 57124632 ps
CPU time 1.73 seconds
Started Mar 17 01:09:37 PM PDT 24
Finished Mar 17 01:09:39 PM PDT 24
Peak memory 214988 kb
Host smart-ee279101-3bf0-4238-a4e9-c80f4bee9c97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095184020 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.4095184020
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1337885752
Short name T1973
Test name
Test status
Simulation time 1502132039 ps
CPU time 2.62 seconds
Started Mar 17 01:09:37 PM PDT 24
Finished Mar 17 01:09:40 PM PDT 24
Peak memory 214992 kb
Host smart-059b963c-4c3d-4668-85af-f2afa0712116
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337885752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
337885752
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3563802241
Short name T2014
Test name
Test status
Simulation time 36752077 ps
CPU time 2.36 seconds
Started Mar 17 01:43:46 PM PDT 24
Finished Mar 17 01:43:49 PM PDT 24
Peak memory 215068 kb
Host smart-8844139d-7365-4daf-9bce-c18215f08ced
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563802241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
563802241
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3122711878
Short name T2010
Test name
Test status
Simulation time 17775859 ps
CPU time 0.81 seconds
Started Mar 17 01:09:39 PM PDT 24
Finished Mar 17 01:09:41 PM PDT 24
Peak memory 203220 kb
Host smart-9dd0f794-e367-41e5-9acc-18b0769d7ce4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122711878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
122711878
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.4069690251
Short name T2150
Test name
Test status
Simulation time 22946530 ps
CPU time 0.73 seconds
Started Mar 17 01:43:43 PM PDT 24
Finished Mar 17 01:43:44 PM PDT 24
Peak memory 203208 kb
Host smart-091b6050-0950-43a0-895a-e99c1002f758
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069690251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.4
069690251
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2309279972
Short name T2110
Test name
Test status
Simulation time 203873616 ps
CPU time 1.87 seconds
Started Mar 17 01:09:39 PM PDT 24
Finished Mar 17 01:09:41 PM PDT 24
Peak memory 215096 kb
Host smart-2a46d703-2d3e-4125-af21-9a79e322f733
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309279972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2309279972
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.906980902
Short name T2041
Test name
Test status
Simulation time 137813212 ps
CPU time 1.47 seconds
Started Mar 17 01:43:47 PM PDT 24
Finished Mar 17 01:43:48 PM PDT 24
Peak memory 215152 kb
Host smart-f4075a84-0a40-4612-8105-837e40f973ca
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906980902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.906980902
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.2240298636
Short name T2143
Test name
Test status
Simulation time 31728294 ps
CPU time 0.66 seconds
Started Mar 17 01:09:40 PM PDT 24
Finished Mar 17 01:09:41 PM PDT 24
Peak memory 203208 kb
Host smart-d8cd02b9-0de3-49d9-856d-09c66cb2af3c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240298636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.2240298636
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.805575401
Short name T2024
Test name
Test status
Simulation time 38423142 ps
CPU time 0.65 seconds
Started Mar 17 01:43:43 PM PDT 24
Finished Mar 17 01:43:44 PM PDT 24
Peak memory 203160 kb
Host smart-90b1459c-a0c0-488a-ba5c-459beafe96cf
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805575401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.805575401
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2536375991
Short name T2141
Test name
Test status
Simulation time 244089665 ps
CPU time 2.05 seconds
Started Mar 17 01:43:44 PM PDT 24
Finished Mar 17 01:43:47 PM PDT 24
Peak memory 215076 kb
Host smart-f83db80a-f60e-45fd-b17e-b62d1aa97b7d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536375991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2536375991
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3162281572
Short name T2104
Test name
Test status
Simulation time 70177313 ps
CPU time 1.87 seconds
Started Mar 17 01:09:40 PM PDT 24
Finished Mar 17 01:09:42 PM PDT 24
Peak memory 215012 kb
Host smart-127f2eee-485c-49f6-8536-c2ca01656b20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162281572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3162281572
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.2099329221
Short name T2037
Test name
Test status
Simulation time 43827111 ps
CPU time 3.3 seconds
Started Mar 17 01:43:38 PM PDT 24
Finished Mar 17 01:43:42 PM PDT 24
Peak memory 215116 kb
Host smart-adc2fe83-48cb-43f7-ba65-b0c79ca7f683
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099329221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.2
099329221
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4111530539
Short name T1978
Test name
Test status
Simulation time 295343862 ps
CPU time 4.62 seconds
Started Mar 17 01:09:44 PM PDT 24
Finished Mar 17 01:09:49 PM PDT 24
Peak memory 215280 kb
Host smart-5dd8b4b7-e096-4d4f-95cf-2196a792214d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111530539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
111530539
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2024931642
Short name T1944
Test name
Test status
Simulation time 762678395 ps
CPU time 12.79 seconds
Started Mar 17 01:43:40 PM PDT 24
Finished Mar 17 01:43:53 PM PDT 24
Peak memory 215972 kb
Host smart-17b6c28e-746b-4cbf-87d1-8121c7a997d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024931642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2024931642
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.315506445
Short name T86
Test name
Test status
Simulation time 1912255114 ps
CPU time 21.17 seconds
Started Mar 17 01:09:40 PM PDT 24
Finished Mar 17 01:10:02 PM PDT 24
Peak memory 215392 kb
Host smart-434b8aaf-0209-4eff-9747-65d639ce4667
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315506445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_
tl_intg_err.315506445
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2028899604
Short name T1990
Test name
Test status
Simulation time 55687647 ps
CPU time 3.56 seconds
Started Mar 17 01:43:53 PM PDT 24
Finished Mar 17 01:43:57 PM PDT 24
Peak memory 217196 kb
Host smart-d0aaf6c1-74a5-4cf7-b822-3376e230af0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028899604 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.2028899604
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.220024322
Short name T2172
Test name
Test status
Simulation time 22425651 ps
CPU time 1.61 seconds
Started Mar 17 01:09:57 PM PDT 24
Finished Mar 17 01:10:00 PM PDT 24
Peak memory 215048 kb
Host smart-09173a14-ad55-476f-aa52-4189188f7231
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=220024322 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.220024322
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.3146531906
Short name T1986
Test name
Test status
Simulation time 88226113 ps
CPU time 1.33 seconds
Started Mar 17 01:10:00 PM PDT 24
Finished Mar 17 01:10:02 PM PDT 24
Peak memory 206872 kb
Host smart-ea035dfc-d361-452c-990f-044d3524dfda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146531906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
3146531906
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.46612824
Short name T2114
Test name
Test status
Simulation time 66244228 ps
CPU time 1.25 seconds
Started Mar 17 01:43:52 PM PDT 24
Finished Mar 17 01:43:53 PM PDT 24
Peak memory 206848 kb
Host smart-747b944d-6621-4782-bce7-cb8d5b134c52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46612824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.46612824
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2749735996
Short name T1967
Test name
Test status
Simulation time 22823686 ps
CPU time 0.73 seconds
Started Mar 17 01:09:56 PM PDT 24
Finished Mar 17 01:09:58 PM PDT 24
Peak memory 203308 kb
Host smart-158fe328-39aa-498d-847f-d8a1fdad40bc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749735996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2749735996
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2957918374
Short name T2091
Test name
Test status
Simulation time 43622905 ps
CPU time 0.7 seconds
Started Mar 17 01:43:54 PM PDT 24
Finished Mar 17 01:43:55 PM PDT 24
Peak memory 203228 kb
Host smart-b11d8888-99f4-40ed-990e-5db67ee8e397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957918374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2957918374
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2991301191
Short name T2056
Test name
Test status
Simulation time 769770636 ps
CPU time 4.02 seconds
Started Mar 17 01:10:00 PM PDT 24
Finished Mar 17 01:10:04 PM PDT 24
Peak memory 214928 kb
Host smart-af7511c1-baa0-4a81-a45e-10206bcfeb92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991301191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.2991301191
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4221884794
Short name T1926
Test name
Test status
Simulation time 42709154 ps
CPU time 2.69 seconds
Started Mar 17 01:43:51 PM PDT 24
Finished Mar 17 01:43:54 PM PDT 24
Peak memory 215068 kb
Host smart-29aea90d-91da-4bb4-a095-23f451d2ea64
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221884794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4221884794
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1463580502
Short name T2170
Test name
Test status
Simulation time 48234955 ps
CPU time 1.4 seconds
Started Mar 17 01:09:56 PM PDT 24
Finished Mar 17 01:09:59 PM PDT 24
Peak memory 215056 kb
Host smart-67f8869a-c1a5-446f-b0f8-c6ffe37f46a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1463580502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1463580502
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.987223088
Short name T2049
Test name
Test status
Simulation time 23000491 ps
CPU time 1.53 seconds
Started Mar 17 01:43:55 PM PDT 24
Finished Mar 17 01:43:57 PM PDT 24
Peak memory 215196 kb
Host smart-5b589ec6-4151-40bc-9cbd-7435ffc63c78
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987223088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.987223088
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.1140450951
Short name T2127
Test name
Test status
Simulation time 943250656 ps
CPU time 19.25 seconds
Started Mar 17 01:43:55 PM PDT 24
Finished Mar 17 01:44:15 PM PDT 24
Peak memory 215492 kb
Host smart-f1cccc6b-65ab-4b3f-90f6-a3ae2196e347
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140450951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.1140450951
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2516585581
Short name T167
Test name
Test status
Simulation time 4488847049 ps
CPU time 14.64 seconds
Started Mar 17 01:09:59 PM PDT 24
Finished Mar 17 01:10:15 PM PDT 24
Peak memory 215204 kb
Host smart-9edbdf6d-1f3b-451d-a1e9-f96e2ef1be3d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516585581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2516585581
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1267988066
Short name T1933
Test name
Test status
Simulation time 174339628 ps
CPU time 2.71 seconds
Started Mar 17 01:09:58 PM PDT 24
Finished Mar 17 01:10:02 PM PDT 24
Peak memory 215308 kb
Host smart-85edbd84-7cbf-4ceb-8644-9f93680536f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267988066 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1267988066
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2068938355
Short name T2022
Test name
Test status
Simulation time 403324878 ps
CPU time 2.58 seconds
Started Mar 17 01:43:54 PM PDT 24
Finished Mar 17 01:43:56 PM PDT 24
Peak memory 215052 kb
Host smart-0f40dc9e-b54d-4d2c-a313-1922b799b8ff
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068938355 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2068938355
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.1372190475
Short name T2005
Test name
Test status
Simulation time 39054509 ps
CPU time 2.51 seconds
Started Mar 17 01:43:55 PM PDT 24
Finished Mar 17 01:43:58 PM PDT 24
Peak memory 215092 kb
Host smart-47e30735-7a56-4e0d-818a-d003c96e1450
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372190475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
1372190475
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.796659749
Short name T2111
Test name
Test status
Simulation time 162514973 ps
CPU time 1.29 seconds
Started Mar 17 01:09:56 PM PDT 24
Finished Mar 17 01:09:57 PM PDT 24
Peak memory 206688 kb
Host smart-76eaff1d-50fa-41fe-9825-e285ec56c44d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796659749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.796659749
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.1382829641
Short name T1985
Test name
Test status
Simulation time 52970383 ps
CPU time 0.74 seconds
Started Mar 17 01:43:49 PM PDT 24
Finished Mar 17 01:43:50 PM PDT 24
Peak memory 203252 kb
Host smart-a7ff86bd-83af-4005-a277-340c821ccc38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382829641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
1382829641
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.4230522434
Short name T2133
Test name
Test status
Simulation time 47637349 ps
CPU time 0.73 seconds
Started Mar 17 01:10:00 PM PDT 24
Finished Mar 17 01:10:02 PM PDT 24
Peak memory 203292 kb
Host smart-f3348bfc-6045-4140-b76e-8e5cd3af3f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230522434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
4230522434
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.110657635
Short name T1962
Test name
Test status
Simulation time 28978412 ps
CPU time 1.77 seconds
Started Mar 17 01:43:51 PM PDT 24
Finished Mar 17 01:43:53 PM PDT 24
Peak memory 214964 kb
Host smart-1e730ebd-3fc7-4743-b328-86155298908e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110657635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.110657635
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.657162555
Short name T132
Test name
Test status
Simulation time 80598520 ps
CPU time 1.96 seconds
Started Mar 17 01:09:58 PM PDT 24
Finished Mar 17 01:10:01 PM PDT 24
Peak memory 215120 kb
Host smart-5d02c1d8-8daa-4edd-820b-9cf08dee0f68
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657162555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.s
pi_device_same_csr_outstanding.657162555
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.1973569711
Short name T1997
Test name
Test status
Simulation time 314808290 ps
CPU time 4.2 seconds
Started Mar 17 01:43:51 PM PDT 24
Finished Mar 17 01:43:56 PM PDT 24
Peak memory 219116 kb
Host smart-ac8d8e40-3327-4b3c-b81a-9a2d8cdb5447
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973569711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
1973569711
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.2405968942
Short name T96
Test name
Test status
Simulation time 637158771 ps
CPU time 2.52 seconds
Started Mar 17 01:09:56 PM PDT 24
Finished Mar 17 01:10:00 PM PDT 24
Peak memory 215184 kb
Host smart-189fd59a-e68f-4661-baa9-9e5c63bca187
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405968942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
2405968942
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.3132158747
Short name T166
Test name
Test status
Simulation time 618345650 ps
CPU time 15.14 seconds
Started Mar 17 01:09:57 PM PDT 24
Finished Mar 17 01:10:13 PM PDT 24
Peak memory 215164 kb
Host smart-37df3e87-4e6c-4259-a0be-53ab88795dea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132158747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.3132158747
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.4034847162
Short name T2137
Test name
Test status
Simulation time 803660654 ps
CPU time 14.05 seconds
Started Mar 17 01:43:49 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 215592 kb
Host smart-f5a6180c-4a8d-4f83-98e0-475da6d3d1b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034847162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.4034847162
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1867549357
Short name T102
Test name
Test status
Simulation time 127389431 ps
CPU time 4.31 seconds
Started Mar 17 01:09:58 PM PDT 24
Finished Mar 17 01:10:04 PM PDT 24
Peak memory 216960 kb
Host smart-e62838b8-6abf-4f4a-baec-0c9bfdaa5ea8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867549357 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1867549357
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.3703622036
Short name T2067
Test name
Test status
Simulation time 298107797 ps
CPU time 3.33 seconds
Started Mar 17 01:43:56 PM PDT 24
Finished Mar 17 01:44:00 PM PDT 24
Peak memory 216812 kb
Host smart-4b918e00-016b-4033-9c08-f9cb84acd910
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703622036 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.3703622036
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1219176687
Short name T131
Test name
Test status
Simulation time 177990520 ps
CPU time 1.36 seconds
Started Mar 17 01:09:56 PM PDT 24
Finished Mar 17 01:09:57 PM PDT 24
Peak memory 206792 kb
Host smart-fe7145e0-2c58-40a7-8e5b-c1438bbf0f6d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219176687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1219176687
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.4277719385
Short name T2177
Test name
Test status
Simulation time 37948353 ps
CPU time 2.25 seconds
Started Mar 17 01:43:56 PM PDT 24
Finished Mar 17 01:43:58 PM PDT 24
Peak memory 206868 kb
Host smart-96c16fe6-e8b7-4657-875b-39afb0e9759a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277719385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
4277719385
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3126785150
Short name T2190
Test name
Test status
Simulation time 24067948 ps
CPU time 0.7 seconds
Started Mar 17 01:43:58 PM PDT 24
Finished Mar 17 01:43:58 PM PDT 24
Peak memory 203272 kb
Host smart-faa9befd-2e10-4312-9c19-5d4ecc6c68b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126785150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3126785150
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.888736680
Short name T2068
Test name
Test status
Simulation time 36475175 ps
CPU time 0.72 seconds
Started Mar 17 01:09:57 PM PDT 24
Finished Mar 17 01:09:59 PM PDT 24
Peak memory 203280 kb
Host smart-13e77029-9bcb-4f4c-8ea0-91526cb57025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888736680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.888736680
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.4168495835
Short name T2090
Test name
Test status
Simulation time 898413753 ps
CPU time 4.92 seconds
Started Mar 17 01:43:58 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 214928 kb
Host smart-b042a95c-88a9-48e7-aa4b-fde57dc67458
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168495835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.4168495835
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.766311791
Short name T2073
Test name
Test status
Simulation time 230441916 ps
CPU time 4.22 seconds
Started Mar 17 01:09:55 PM PDT 24
Finished Mar 17 01:10:00 PM PDT 24
Peak memory 215052 kb
Host smart-a445b9a6-d262-44dc-9d24-2d8fa6d24e9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766311791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.s
pi_device_same_csr_outstanding.766311791
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.275412089
Short name T97
Test name
Test status
Simulation time 121199934 ps
CPU time 1.9 seconds
Started Mar 17 01:09:58 PM PDT 24
Finished Mar 17 01:10:01 PM PDT 24
Peak memory 215176 kb
Host smart-fd209a59-2dbb-4c7c-9b22-a23085b49925
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275412089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.275412089
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.1538856741
Short name T1983
Test name
Test status
Simulation time 1285250937 ps
CPU time 7.14 seconds
Started Mar 17 01:43:57 PM PDT 24
Finished Mar 17 01:44:04 PM PDT 24
Peak memory 215564 kb
Host smart-5cf3efd1-86cd-4ee2-97f2-860d4145f3cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538856741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.1538856741
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.413427082
Short name T2035
Test name
Test status
Simulation time 671652706 ps
CPU time 16.51 seconds
Started Mar 17 01:09:58 PM PDT 24
Finished Mar 17 01:10:17 PM PDT 24
Peak memory 215012 kb
Host smart-4e94dcb0-5288-4010-91f4-7e87c7a55a88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413427082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.413427082
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2817496491
Short name T2066
Test name
Test status
Simulation time 202616749 ps
CPU time 3.61 seconds
Started Mar 17 01:09:56 PM PDT 24
Finished Mar 17 01:10:01 PM PDT 24
Peak memory 217036 kb
Host smart-be3a12b8-4a63-43d1-a6d2-ce97abb636cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817496491 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2817496491
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2969898078
Short name T2112
Test name
Test status
Simulation time 341481220 ps
CPU time 2.78 seconds
Started Mar 17 01:43:56 PM PDT 24
Finished Mar 17 01:43:59 PM PDT 24
Peak memory 216180 kb
Host smart-24619cce-89b7-4a6a-b0fd-e9d146dad6b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969898078 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2969898078
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3901220771
Short name T2175
Test name
Test status
Simulation time 332870909 ps
CPU time 2.45 seconds
Started Mar 17 01:44:02 PM PDT 24
Finished Mar 17 01:44:04 PM PDT 24
Peak memory 215100 kb
Host smart-5e3d743c-e7f2-41f7-a5cf-f3d759f9916c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3901220771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3901220771
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.487506811
Short name T2000
Test name
Test status
Simulation time 28753967 ps
CPU time 1.83 seconds
Started Mar 17 01:10:00 PM PDT 24
Finished Mar 17 01:10:02 PM PDT 24
Peak memory 214980 kb
Host smart-57cb0ee3-b2ef-421e-842f-7091c3d38b3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487506811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.487506811
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.2375337885
Short name T1928
Test name
Test status
Simulation time 55309254 ps
CPU time 0.75 seconds
Started Mar 17 01:09:59 PM PDT 24
Finished Mar 17 01:10:01 PM PDT 24
Peak memory 203340 kb
Host smart-53c8b13e-4989-474e-abe7-b11e89e50803
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2375337885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
2375337885
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3136511710
Short name T1972
Test name
Test status
Simulation time 114927522 ps
CPU time 0.74 seconds
Started Mar 17 01:43:56 PM PDT 24
Finished Mar 17 01:43:57 PM PDT 24
Peak memory 203308 kb
Host smart-2d6835c0-25cc-4a79-aebf-9bbe151e7229
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136511710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3136511710
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4108026081
Short name T2101
Test name
Test status
Simulation time 232302332 ps
CPU time 1.93 seconds
Started Mar 17 01:43:57 PM PDT 24
Finished Mar 17 01:44:00 PM PDT 24
Peak memory 215068 kb
Host smart-7525f843-fc86-492a-b631-1b716c770a7a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108026081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.4108026081
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.561998987
Short name T2039
Test name
Test status
Simulation time 240157462 ps
CPU time 5.27 seconds
Started Mar 17 01:09:58 PM PDT 24
Finished Mar 17 01:10:05 PM PDT 24
Peak memory 215144 kb
Host smart-567f26e8-514d-4919-ac51-0d0f65025e0f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561998987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.s
pi_device_same_csr_outstanding.561998987
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3132629270
Short name T93
Test name
Test status
Simulation time 465211632 ps
CPU time 3.03 seconds
Started Mar 17 01:09:58 PM PDT 24
Finished Mar 17 01:10:01 PM PDT 24
Peak memory 215144 kb
Host smart-0c5e5525-3a42-48ef-aae2-308c6fd9dde0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132629270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3132629270
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.3938712746
Short name T1947
Test name
Test status
Simulation time 176012074 ps
CPU time 3.5 seconds
Started Mar 17 01:43:55 PM PDT 24
Finished Mar 17 01:43:59 PM PDT 24
Peak memory 215172 kb
Host smart-c0a658bb-7a24-4455-9a8c-63dd07c88551
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938712746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
3938712746
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.4032376162
Short name T2043
Test name
Test status
Simulation time 665261888 ps
CPU time 8.2 seconds
Started Mar 17 01:43:58 PM PDT 24
Finished Mar 17 01:44:07 PM PDT 24
Peak memory 214980 kb
Host smart-21954d61-d272-43d6-89d6-760ddcf6b446
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032376162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.4032376162
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.557943191
Short name T165
Test name
Test status
Simulation time 104005418 ps
CPU time 7.31 seconds
Started Mar 17 01:09:57 PM PDT 24
Finished Mar 17 01:10:06 PM PDT 24
Peak memory 215112 kb
Host smart-ed318d70-a59f-477a-b11a-62afde100820
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557943191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.557943191
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1721101047
Short name T133
Test name
Test status
Simulation time 496213077 ps
CPU time 2.76 seconds
Started Mar 17 01:43:57 PM PDT 24
Finished Mar 17 01:44:00 PM PDT 24
Peak memory 216788 kb
Host smart-fa173a29-d191-4f02-aef9-b62b44e2261a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721101047 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1721101047
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1894570648
Short name T103
Test name
Test status
Simulation time 169904110 ps
CPU time 2.9 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:11 PM PDT 24
Peak memory 216712 kb
Host smart-4bca65d4-f241-4a1d-95a6-804311b52f1f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1894570648 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1894570648
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3543994628
Short name T2023
Test name
Test status
Simulation time 21897631 ps
CPU time 1.32 seconds
Started Mar 17 01:09:56 PM PDT 24
Finished Mar 17 01:09:58 PM PDT 24
Peak memory 206736 kb
Host smart-acf488a3-28be-4133-99f6-9ae8ac618636
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543994628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3543994628
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.887261364
Short name T2166
Test name
Test status
Simulation time 417973840 ps
CPU time 2.24 seconds
Started Mar 17 01:43:57 PM PDT 24
Finished Mar 17 01:43:59 PM PDT 24
Peak memory 207044 kb
Host smart-e194b423-b83a-46c0-a55e-7813bca7f42a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887261364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.887261364
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.1386247322
Short name T2055
Test name
Test status
Simulation time 58186153 ps
CPU time 0.79 seconds
Started Mar 17 01:43:58 PM PDT 24
Finished Mar 17 01:43:59 PM PDT 24
Peak memory 203376 kb
Host smart-8ecdf2e2-514d-4b75-ad61-862741d2f256
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386247322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
1386247322
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.796675908
Short name T2012
Test name
Test status
Simulation time 18811938 ps
CPU time 0.79 seconds
Started Mar 17 01:09:59 PM PDT 24
Finished Mar 17 01:10:01 PM PDT 24
Peak memory 203220 kb
Host smart-bda1a929-a02d-4b7e-a58b-c1150af03cf9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796675908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.796675908
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.3531205033
Short name T2198
Test name
Test status
Simulation time 292810392 ps
CPU time 3.63 seconds
Started Mar 17 01:09:56 PM PDT 24
Finished Mar 17 01:10:01 PM PDT 24
Peak memory 215120 kb
Host smart-4ce37b8d-4a74-45be-92b3-4660adcac1f2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531205033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.3531205033
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.801762006
Short name T2171
Test name
Test status
Simulation time 95008661 ps
CPU time 1.63 seconds
Started Mar 17 01:43:57 PM PDT 24
Finished Mar 17 01:43:59 PM PDT 24
Peak memory 215012 kb
Host smart-a59edf15-d42b-4995-86bf-d3f43877e668
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801762006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.801762006
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.2905496633
Short name T2184
Test name
Test status
Simulation time 41270278 ps
CPU time 3.38 seconds
Started Mar 17 01:09:58 PM PDT 24
Finished Mar 17 01:10:03 PM PDT 24
Peak memory 216184 kb
Host smart-f45c50ae-e90a-4dff-bbfd-494bc46406a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905496633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
2905496633
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.705544710
Short name T92
Test name
Test status
Simulation time 382231372 ps
CPU time 3.43 seconds
Started Mar 17 01:43:57 PM PDT 24
Finished Mar 17 01:44:01 PM PDT 24
Peak memory 215216 kb
Host smart-1bc33ddf-e22b-4542-bc33-22a7071deda7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705544710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.705544710
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.1189932296
Short name T2054
Test name
Test status
Simulation time 224577208 ps
CPU time 6.93 seconds
Started Mar 17 01:10:00 PM PDT 24
Finished Mar 17 01:10:07 PM PDT 24
Peak memory 215188 kb
Host smart-21977e2f-efca-443c-85ac-3ce08b953021
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189932296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.1189932296
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.3900663899
Short name T1968
Test name
Test status
Simulation time 1158661781 ps
CPU time 14.29 seconds
Started Mar 17 01:43:59 PM PDT 24
Finished Mar 17 01:44:13 PM PDT 24
Peak memory 215204 kb
Host smart-e3113670-00a1-4806-8b93-5309b36b9d99
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900663899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_devic
e_tl_intg_err.3900663899
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1607095747
Short name T2029
Test name
Test status
Simulation time 810489560 ps
CPU time 2.46 seconds
Started Mar 17 01:43:57 PM PDT 24
Finished Mar 17 01:43:59 PM PDT 24
Peak memory 216184 kb
Host smart-ff32cb44-89b3-42a3-b3c8-1d938f726904
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607095747 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1607095747
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.562760329
Short name T2011
Test name
Test status
Simulation time 50274342 ps
CPU time 4.14 seconds
Started Mar 17 01:10:05 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 217100 kb
Host smart-427c5644-65a0-433e-bd20-bf38112d8b0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562760329 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.562760329
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.1617431375
Short name T2038
Test name
Test status
Simulation time 191394197 ps
CPU time 1.33 seconds
Started Mar 17 01:43:56 PM PDT 24
Finished Mar 17 01:43:58 PM PDT 24
Peak memory 215112 kb
Host smart-290f2c37-8db2-479a-a248-77a756779573
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617431375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
1617431375
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.632109795
Short name T117
Test name
Test status
Simulation time 32505169 ps
CPU time 2.02 seconds
Started Mar 17 01:10:10 PM PDT 24
Finished Mar 17 01:10:12 PM PDT 24
Peak memory 206860 kb
Host smart-89952486-66c9-49ad-9cce-e0a6a68cf166
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632109795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.632109795
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2252199270
Short name T2048
Test name
Test status
Simulation time 21295856 ps
CPU time 0.69 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:09 PM PDT 24
Peak memory 203200 kb
Host smart-50a03ab9-5e00-4c06-9a4d-74f509969b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252199270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2252199270
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.2959641548
Short name T2194
Test name
Test status
Simulation time 21131018 ps
CPU time 0.75 seconds
Started Mar 17 01:44:03 PM PDT 24
Finished Mar 17 01:44:04 PM PDT 24
Peak memory 203268 kb
Host smart-8da925fe-12d7-4fe0-aa81-ed0473c8ce84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959641548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
2959641548
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2350186572
Short name T2003
Test name
Test status
Simulation time 146509025 ps
CPU time 3.53 seconds
Started Mar 17 01:43:58 PM PDT 24
Finished Mar 17 01:44:02 PM PDT 24
Peak memory 215148 kb
Host smart-1acb79d6-c5c8-4661-b776-461ab364699f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350186572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2350186572
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4224227314
Short name T2189
Test name
Test status
Simulation time 189679080 ps
CPU time 4.38 seconds
Started Mar 17 01:10:11 PM PDT 24
Finished Mar 17 01:10:15 PM PDT 24
Peak memory 215104 kb
Host smart-a3dd9e02-6964-4627-a213-531967e70168
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224227314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4224227314
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.2051197534
Short name T94
Test name
Test status
Simulation time 151963034 ps
CPU time 2.05 seconds
Started Mar 17 01:43:56 PM PDT 24
Finished Mar 17 01:43:59 PM PDT 24
Peak memory 215168 kb
Host smart-376da932-f418-4a9d-91eb-410ecbed0eff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051197534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
2051197534
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3703482529
Short name T2076
Test name
Test status
Simulation time 124324137 ps
CPU time 4.19 seconds
Started Mar 17 01:10:09 PM PDT 24
Finished Mar 17 01:10:14 PM PDT 24
Peak memory 215020 kb
Host smart-91b118cb-4a15-4b5b-b487-151d092c10ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703482529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3703482529
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.1462861867
Short name T1995
Test name
Test status
Simulation time 105443165 ps
CPU time 6.62 seconds
Started Mar 17 01:44:02 PM PDT 24
Finished Mar 17 01:44:08 PM PDT 24
Peak memory 215056 kb
Host smart-e1576ba2-ab91-48f2-8479-d2232ce287a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462861867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.1462861867
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2221003576
Short name T159
Test name
Test status
Simulation time 105739754 ps
CPU time 6.96 seconds
Started Mar 17 01:10:08 PM PDT 24
Finished Mar 17 01:10:15 PM PDT 24
Peak memory 215112 kb
Host smart-08ad2c59-e9f5-4056-93bf-a2bb687ecf3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221003576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2221003576
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1954295259
Short name T1998
Test name
Test status
Simulation time 435693414 ps
CPU time 2.77 seconds
Started Mar 17 01:43:59 PM PDT 24
Finished Mar 17 01:44:02 PM PDT 24
Peak memory 216104 kb
Host smart-ce703018-37bb-4baf-ba5f-89b9a06e1221
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1954295259 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1954295259
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3839998168
Short name T1936
Test name
Test status
Simulation time 212313840 ps
CPU time 3.5 seconds
Started Mar 17 01:10:12 PM PDT 24
Finished Mar 17 01:10:16 PM PDT 24
Peak memory 217460 kb
Host smart-76dfe03f-8940-4d7e-ba84-60e3aa16cae9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839998168 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3839998168
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1035783438
Short name T2188
Test name
Test status
Simulation time 87710498 ps
CPU time 2.01 seconds
Started Mar 17 01:43:56 PM PDT 24
Finished Mar 17 01:43:58 PM PDT 24
Peak memory 215100 kb
Host smart-af881183-4bdc-4d38-a7eb-c5fae546ff68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035783438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1035783438
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.791862535
Short name T2187
Test name
Test status
Simulation time 461925366 ps
CPU time 2.92 seconds
Started Mar 17 01:10:11 PM PDT 24
Finished Mar 17 01:10:14 PM PDT 24
Peak memory 215172 kb
Host smart-7f980dd6-27f6-46ea-8469-2f5bc5143a2b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791862535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.791862535
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.524861256
Short name T1915
Test name
Test status
Simulation time 41564623 ps
CPU time 0.74 seconds
Started Mar 17 01:44:00 PM PDT 24
Finished Mar 17 01:44:00 PM PDT 24
Peak memory 203328 kb
Host smart-865b7c83-90be-4647-88c5-f62723ef72e7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524861256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.524861256
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.839290428
Short name T2109
Test name
Test status
Simulation time 18509545 ps
CPU time 0.79 seconds
Started Mar 17 01:10:09 PM PDT 24
Finished Mar 17 01:10:11 PM PDT 24
Peak memory 203128 kb
Host smart-80aef9a3-7322-425f-9c28-6b82e6874c8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839290428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.839290428
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3772460282
Short name T2026
Test name
Test status
Simulation time 80033520 ps
CPU time 2.6 seconds
Started Mar 17 01:43:54 PM PDT 24
Finished Mar 17 01:43:56 PM PDT 24
Peak memory 215164 kb
Host smart-a2fdf6d1-c979-4010-aa1e-f0b2c1be2682
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772460282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
spi_device_same_csr_outstanding.3772460282
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.739922686
Short name T1912
Test name
Test status
Simulation time 59126178 ps
CPU time 1.93 seconds
Started Mar 17 01:10:06 PM PDT 24
Finished Mar 17 01:10:09 PM PDT 24
Peak memory 206928 kb
Host smart-cb085198-170b-4d05-a548-dd228dfcb3b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739922686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.739922686
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.2071273190
Short name T2099
Test name
Test status
Simulation time 411712061 ps
CPU time 2.86 seconds
Started Mar 17 01:43:58 PM PDT 24
Finished Mar 17 01:44:01 PM PDT 24
Peak memory 216152 kb
Host smart-30908756-5669-4c56-8fbc-f1404f7de6de
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071273190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
2071273190
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3829914321
Short name T90
Test name
Test status
Simulation time 130348814 ps
CPU time 2.09 seconds
Started Mar 17 01:10:06 PM PDT 24
Finished Mar 17 01:10:09 PM PDT 24
Peak memory 216300 kb
Host smart-1b1f6a6e-cdeb-4fbb-b6fb-35fd922f5cfa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829914321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3829914321
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3653123941
Short name T2065
Test name
Test status
Simulation time 2020000023 ps
CPU time 21.24 seconds
Started Mar 17 01:10:09 PM PDT 24
Finished Mar 17 01:10:31 PM PDT 24
Peak memory 222224 kb
Host smart-6f930dda-edcd-499b-86cf-be223461f6d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653123941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3653123941
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2804785751
Short name T2115
Test name
Test status
Simulation time 66141621 ps
CPU time 3.28 seconds
Started Mar 17 01:43:58 PM PDT 24
Finished Mar 17 01:44:02 PM PDT 24
Peak memory 216828 kb
Host smart-d508943a-d588-42b9-bbb3-1a4f84614dc3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804785751 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2804785751
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4083700699
Short name T2030
Test name
Test status
Simulation time 236860076 ps
CPU time 1.91 seconds
Started Mar 17 01:10:09 PM PDT 24
Finished Mar 17 01:10:11 PM PDT 24
Peak memory 214984 kb
Host smart-e99500bc-4841-4dd3-9d63-b81ec02bf6a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083700699 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.4083700699
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1547486733
Short name T2070
Test name
Test status
Simulation time 141330108 ps
CPU time 2.48 seconds
Started Mar 17 01:43:55 PM PDT 24
Finished Mar 17 01:43:58 PM PDT 24
Peak memory 206908 kb
Host smart-23b26424-c256-436c-9597-19ad4152a97b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547486733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1547486733
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.2847392503
Short name T118
Test name
Test status
Simulation time 81135681 ps
CPU time 2.14 seconds
Started Mar 17 01:10:08 PM PDT 24
Finished Mar 17 01:10:11 PM PDT 24
Peak memory 206772 kb
Host smart-09518a88-d86a-456a-8ec4-cfa5b5eb2ae6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847392503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
2847392503
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2274686469
Short name T1922
Test name
Test status
Simulation time 37414374 ps
CPU time 0.71 seconds
Started Mar 17 01:43:59 PM PDT 24
Finished Mar 17 01:44:00 PM PDT 24
Peak memory 203268 kb
Host smart-42cfa7b5-16d6-45c8-81a0-bdb17e4e8727
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274686469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2274686469
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.2922400123
Short name T1960
Test name
Test status
Simulation time 49449607 ps
CPU time 0.78 seconds
Started Mar 17 01:10:06 PM PDT 24
Finished Mar 17 01:10:07 PM PDT 24
Peak memory 203276 kb
Host smart-2c7eaa6d-8abb-4206-9f48-efee5c7699df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922400123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
2922400123
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1309790700
Short name T1952
Test name
Test status
Simulation time 231695809 ps
CPU time 4.04 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:12 PM PDT 24
Peak memory 215132 kb
Host smart-4fab44c3-5efd-4885-a177-bee7462dc2e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309790700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1309790700
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3627608517
Short name T1979
Test name
Test status
Simulation time 323703426 ps
CPU time 4.14 seconds
Started Mar 17 01:43:58 PM PDT 24
Finished Mar 17 01:44:02 PM PDT 24
Peak memory 215032 kb
Host smart-9a291cb6-da5f-4cb8-83f8-0dd67257824c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627608517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3627608517
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1831462192
Short name T1970
Test name
Test status
Simulation time 235330943 ps
CPU time 4.09 seconds
Started Mar 17 01:43:59 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 215300 kb
Host smart-2f914dec-a567-4362-8895-934bfa9892c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831462192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1831462192
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3498950876
Short name T2122
Test name
Test status
Simulation time 27048203 ps
CPU time 2.01 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 215316 kb
Host smart-d2b2f41f-5402-4b8a-96de-9d835dd37779
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498950876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3498950876
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3136733428
Short name T157
Test name
Test status
Simulation time 448650230 ps
CPU time 6.89 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:14 PM PDT 24
Peak memory 215496 kb
Host smart-caa2f9c9-3a87-40cf-802f-ce0b1f596368
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136733428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3136733428
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.374982774
Short name T2129
Test name
Test status
Simulation time 3162970606 ps
CPU time 23.02 seconds
Started Mar 17 01:44:00 PM PDT 24
Finished Mar 17 01:44:23 PM PDT 24
Peak memory 215140 kb
Host smart-9c1c98f5-a6d9-4881-9d6e-5283b527e5ce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374982774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device
_tl_intg_err.374982774
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2111546253
Short name T1925
Test name
Test status
Simulation time 99049431 ps
CPU time 1.8 seconds
Started Mar 17 01:44:03 PM PDT 24
Finished Mar 17 01:44:05 PM PDT 24
Peak memory 216112 kb
Host smart-58b09156-de7a-4d03-b53d-aff24961c06d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111546253 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2111546253
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.811286224
Short name T1950
Test name
Test status
Simulation time 53967473 ps
CPU time 3.81 seconds
Started Mar 17 01:10:10 PM PDT 24
Finished Mar 17 01:10:14 PM PDT 24
Peak memory 216912 kb
Host smart-7dc7d05d-c145-42c8-8f43-43300c2c82aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811286224 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.811286224
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.1039059970
Short name T2135
Test name
Test status
Simulation time 150936483 ps
CPU time 1.41 seconds
Started Mar 17 01:43:55 PM PDT 24
Finished Mar 17 01:43:57 PM PDT 24
Peak memory 215112 kb
Host smart-4488d7cb-dcad-4080-aea5-89699fb2f0cc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039059970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
1039059970
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2812066754
Short name T2015
Test name
Test status
Simulation time 34263435 ps
CPU time 1.24 seconds
Started Mar 17 01:10:08 PM PDT 24
Finished Mar 17 01:10:11 PM PDT 24
Peak memory 206812 kb
Host smart-673b950a-1764-409f-b30f-cd56cc73254a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812066754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2812066754
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3003432929
Short name T1961
Test name
Test status
Simulation time 21557085 ps
CPU time 0.73 seconds
Started Mar 17 01:43:58 PM PDT 24
Finished Mar 17 01:43:59 PM PDT 24
Peak memory 203244 kb
Host smart-be579b8b-ee74-458e-9aae-8c994cd16658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003432929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3003432929
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3014939636
Short name T1940
Test name
Test status
Simulation time 19210746 ps
CPU time 0.74 seconds
Started Mar 17 01:10:09 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 203176 kb
Host smart-a99b010e-6877-42ac-852c-1b7d074b46ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014939636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3014939636
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.1907067328
Short name T2120
Test name
Test status
Simulation time 223986022 ps
CPU time 2.72 seconds
Started Mar 17 01:44:03 PM PDT 24
Finished Mar 17 01:44:06 PM PDT 24
Peak memory 215072 kb
Host smart-93811fc0-7a41-47e9-8473-be34446a6eed
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907067328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.1907067328
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2418216531
Short name T2033
Test name
Test status
Simulation time 150461099 ps
CPU time 3.45 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:12 PM PDT 24
Peak memory 215072 kb
Host smart-bd30db6d-f8ed-4005-b6bd-ac03e6a5ccbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418216531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2418216531
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3990699322
Short name T2102
Test name
Test status
Simulation time 316407745 ps
CPU time 4.39 seconds
Started Mar 17 01:10:06 PM PDT 24
Finished Mar 17 01:10:11 PM PDT 24
Peak memory 215164 kb
Host smart-8b4e908d-c1d3-40f4-9ad6-669657ec0400
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990699322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3990699322
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1129890802
Short name T88
Test name
Test status
Simulation time 314174982 ps
CPU time 19.82 seconds
Started Mar 17 01:10:05 PM PDT 24
Finished Mar 17 01:10:25 PM PDT 24
Peak memory 215032 kb
Host smart-2acac0f4-b2dd-437c-a408-5a391ff1e454
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129890802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1129890802
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1458251887
Short name T2134
Test name
Test status
Simulation time 3899394651 ps
CPU time 27.06 seconds
Started Mar 17 01:43:57 PM PDT 24
Finished Mar 17 01:44:24 PM PDT 24
Peak memory 215216 kb
Host smart-4861b64c-9843-456a-86aa-f191fbc1c2cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458251887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1458251887
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3152658455
Short name T2173
Test name
Test status
Simulation time 388355839 ps
CPU time 2.59 seconds
Started Mar 17 01:44:01 PM PDT 24
Finished Mar 17 01:44:04 PM PDT 24
Peak memory 216420 kb
Host smart-edb984dd-4481-45ba-953d-8ecb5a4d326b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152658455 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.3152658455
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.420607039
Short name T1958
Test name
Test status
Simulation time 53584308 ps
CPU time 1.85 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 215052 kb
Host smart-57e4e5d4-583e-49f8-8627-f9170047db1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420607039 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.420607039
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3526714005
Short name T1971
Test name
Test status
Simulation time 314759651 ps
CPU time 2.41 seconds
Started Mar 17 01:44:03 PM PDT 24
Finished Mar 17 01:44:05 PM PDT 24
Peak memory 215160 kb
Host smart-c11b2ec4-7227-43fc-aec6-cb02b6d5a25b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526714005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3526714005
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4063367505
Short name T2181
Test name
Test status
Simulation time 24782901 ps
CPU time 1.36 seconds
Started Mar 17 01:10:10 PM PDT 24
Finished Mar 17 01:10:12 PM PDT 24
Peak memory 215200 kb
Host smart-c5df155f-0d33-475e-a55b-bd4cffab5549
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063367505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4063367505
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1693361118
Short name T1916
Test name
Test status
Simulation time 45624038 ps
CPU time 0.71 seconds
Started Mar 17 01:10:08 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 203228 kb
Host smart-53283f4c-5a68-4e45-97cc-c8e02f727e3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1693361118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1693361118
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.3816410363
Short name T1938
Test name
Test status
Simulation time 17145234 ps
CPU time 0.76 seconds
Started Mar 17 01:44:05 PM PDT 24
Finished Mar 17 01:44:05 PM PDT 24
Peak memory 203316 kb
Host smart-9f1fdd82-1218-44c9-9570-4e84152bd046
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816410363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
3816410363
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1151517116
Short name T2160
Test name
Test status
Simulation time 26318875 ps
CPU time 1.64 seconds
Started Mar 17 01:44:07 PM PDT 24
Finished Mar 17 01:44:09 PM PDT 24
Peak memory 206916 kb
Host smart-a366b686-e71f-46ed-be74-ad8308ac9188
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151517116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1151517116
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.483301736
Short name T2008
Test name
Test status
Simulation time 649171427 ps
CPU time 3.15 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:11 PM PDT 24
Peak memory 215008 kb
Host smart-ad54359d-6313-47b1-8794-12c6f8b1a770
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483301736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.s
pi_device_same_csr_outstanding.483301736
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.130648453
Short name T2156
Test name
Test status
Simulation time 286225832 ps
CPU time 3.61 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:12 PM PDT 24
Peak memory 215076 kb
Host smart-f26c7c47-88a3-4778-a945-bd6e4210817d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130648453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.130648453
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.274092820
Short name T99
Test name
Test status
Simulation time 217836574 ps
CPU time 2.43 seconds
Started Mar 17 01:44:06 PM PDT 24
Finished Mar 17 01:44:09 PM PDT 24
Peak memory 215372 kb
Host smart-9260c6ea-3768-47a7-8c8b-95dd9257f895
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274092820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.274092820
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4122201082
Short name T1977
Test name
Test status
Simulation time 1231350557 ps
CPU time 16.22 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:25 PM PDT 24
Peak memory 215088 kb
Host smart-391ad13f-ef48-45bd-917f-ea72dbf85951
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122201082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4122201082
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.241384214
Short name T2159
Test name
Test status
Simulation time 219030147 ps
CPU time 13.54 seconds
Started Mar 17 01:09:39 PM PDT 24
Finished Mar 17 01:09:52 PM PDT 24
Peak memory 215136 kb
Host smart-595ffe10-a75f-4632-921d-ca56c4ebd591
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241384214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_aliasing.241384214
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.3713480554
Short name T1996
Test name
Test status
Simulation time 309792063 ps
CPU time 8.36 seconds
Started Mar 17 01:43:42 PM PDT 24
Finished Mar 17 01:43:51 PM PDT 24
Peak memory 206800 kb
Host smart-03393515-e0f2-46ab-bf84-70965ba34d4c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713480554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.3713480554
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.2826165375
Short name T2163
Test name
Test status
Simulation time 2225025100 ps
CPU time 12.07 seconds
Started Mar 17 01:09:40 PM PDT 24
Finished Mar 17 01:09:52 PM PDT 24
Peak memory 206876 kb
Host smart-186573c7-17c9-449d-9aff-4c53c74b6085
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826165375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.2826165375
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3795204609
Short name T2132
Test name
Test status
Simulation time 631022677 ps
CPU time 13.24 seconds
Started Mar 17 01:43:48 PM PDT 24
Finished Mar 17 01:44:02 PM PDT 24
Peak memory 206876 kb
Host smart-5ef4b288-b93b-4387-a210-dda0807213a3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795204609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_bit_bash.3795204609
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1383018785
Short name T2155
Test name
Test status
Simulation time 125041349 ps
CPU time 1.47 seconds
Started Mar 17 01:43:43 PM PDT 24
Finished Mar 17 01:43:44 PM PDT 24
Peak memory 206796 kb
Host smart-640193d2-ea3c-4636-b81b-10e1a051574b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383018785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1383018785
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3944924958
Short name T2105
Test name
Test status
Simulation time 89866091 ps
CPU time 0.95 seconds
Started Mar 17 01:09:37 PM PDT 24
Finished Mar 17 01:09:38 PM PDT 24
Peak memory 206272 kb
Host smart-7eb1cd16-5a7e-4437-89ca-c23afb83f06b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944924958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3944924958
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2923386587
Short name T2086
Test name
Test status
Simulation time 59149952 ps
CPU time 1.76 seconds
Started Mar 17 01:43:43 PM PDT 24
Finished Mar 17 01:43:45 PM PDT 24
Peak memory 215128 kb
Host smart-3bec8f23-395d-49b6-81ed-5e18daf63998
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923386587 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2923386587
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1388006502
Short name T2087
Test name
Test status
Simulation time 40200363 ps
CPU time 1.52 seconds
Started Mar 17 01:09:41 PM PDT 24
Finished Mar 17 01:09:43 PM PDT 24
Peak memory 206736 kb
Host smart-59fe6db4-865c-40e4-9dd8-80a5cdc2c0bc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388006502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
388006502
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2976989343
Short name T108
Test name
Test status
Simulation time 67997247 ps
CPU time 2.33 seconds
Started Mar 17 01:43:45 PM PDT 24
Finished Mar 17 01:43:48 PM PDT 24
Peak memory 215136 kb
Host smart-5c714be8-b2e7-4cbb-b0e9-d2aabe98d525
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976989343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
976989343
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1576164082
Short name T1941
Test name
Test status
Simulation time 31158087 ps
CPU time 0.76 seconds
Started Mar 17 01:09:40 PM PDT 24
Finished Mar 17 01:09:42 PM PDT 24
Peak memory 203212 kb
Host smart-9a3a312d-571e-44a4-ab88-d3714f68096e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576164082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
576164082
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1997930729
Short name T2151
Test name
Test status
Simulation time 13420017 ps
CPU time 0.74 seconds
Started Mar 17 01:43:47 PM PDT 24
Finished Mar 17 01:43:47 PM PDT 24
Peak memory 203332 kb
Host smart-3496fc48-5097-4bb2-9908-86ab1f5bfaac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997930729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
997930729
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1921630947
Short name T2017
Test name
Test status
Simulation time 129968521 ps
CPU time 1.39 seconds
Started Mar 17 01:43:44 PM PDT 24
Finished Mar 17 01:43:45 PM PDT 24
Peak memory 215116 kb
Host smart-381279b1-d0f1-4fd6-a659-442989ae87a3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921630947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1921630947
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.3786237276
Short name T1993
Test name
Test status
Simulation time 48511754 ps
CPU time 2.58 seconds
Started Mar 17 01:09:40 PM PDT 24
Finished Mar 17 01:09:43 PM PDT 24
Peak memory 215188 kb
Host smart-86f1ba34-5a9d-46f3-b570-865692d868a7
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786237276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.3786237276
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2266876745
Short name T1964
Test name
Test status
Simulation time 11422207 ps
CPU time 0.68 seconds
Started Mar 17 01:09:40 PM PDT 24
Finished Mar 17 01:09:41 PM PDT 24
Peak memory 203172 kb
Host smart-e871100e-3cff-416f-8e2a-cefe384d5efd
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266876745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2266876745
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.456481139
Short name T2072
Test name
Test status
Simulation time 31377855 ps
CPU time 0.67 seconds
Started Mar 17 01:43:44 PM PDT 24
Finished Mar 17 01:43:45 PM PDT 24
Peak memory 203236 kb
Host smart-88e2bdc2-7303-4857-971b-2f07ca2986bc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456481139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.456481139
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.125642189
Short name T1931
Test name
Test status
Simulation time 112820570 ps
CPU time 3.91 seconds
Started Mar 17 01:09:42 PM PDT 24
Finished Mar 17 01:09:47 PM PDT 24
Peak memory 215144 kb
Host smart-39389f61-9fa8-4e3e-8547-17544c93bda2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125642189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sp
i_device_same_csr_outstanding.125642189
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3696444995
Short name T2174
Test name
Test status
Simulation time 528393626 ps
CPU time 3.14 seconds
Started Mar 17 01:43:45 PM PDT 24
Finished Mar 17 01:43:48 PM PDT 24
Peak memory 215052 kb
Host smart-b2ba45b3-d0fd-4afc-8be0-c50fd6a0a309
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696444995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3696444995
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1439881773
Short name T2157
Test name
Test status
Simulation time 61724695 ps
CPU time 4 seconds
Started Mar 17 01:09:38 PM PDT 24
Finished Mar 17 01:09:42 PM PDT 24
Peak memory 215168 kb
Host smart-bdc4b6bd-b238-479e-bb33-f3a19aa5647e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439881773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
439881773
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.2884440548
Short name T2118
Test name
Test status
Simulation time 199432529 ps
CPU time 1.85 seconds
Started Mar 17 01:43:44 PM PDT 24
Finished Mar 17 01:43:46 PM PDT 24
Peak memory 215052 kb
Host smart-628977ad-8a1d-4f46-ae79-59abeefe8b1f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884440548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2
884440548
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1845416691
Short name T2080
Test name
Test status
Simulation time 1133969404 ps
CPU time 16.92 seconds
Started Mar 17 01:09:51 PM PDT 24
Finished Mar 17 01:10:08 PM PDT 24
Peak memory 215680 kb
Host smart-56bb6e86-cc72-4bd2-8d0d-b419c66ca4d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845416691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1845416691
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.932114063
Short name T2034
Test name
Test status
Simulation time 843733394 ps
CPU time 21.85 seconds
Started Mar 17 01:43:48 PM PDT 24
Finished Mar 17 01:44:11 PM PDT 24
Peak memory 216076 kb
Host smart-58bec6d3-973d-497d-84e3-2ab86bbf70d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932114063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_
tl_intg_err.932114063
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.475768965
Short name T1987
Test name
Test status
Simulation time 24590176 ps
CPU time 0.75 seconds
Started Mar 17 01:44:03 PM PDT 24
Finished Mar 17 01:44:04 PM PDT 24
Peak memory 203308 kb
Host smart-209813a9-e2f7-4494-a1f2-82b3cc7bc7e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475768965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.475768965
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.482774853
Short name T1945
Test name
Test status
Simulation time 36610635 ps
CPU time 0.73 seconds
Started Mar 17 01:10:08 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 203296 kb
Host smart-a6ccc5c0-6f14-406a-b4b9-2aab50f163f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482774853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.482774853
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1747800800
Short name T1981
Test name
Test status
Simulation time 91141497 ps
CPU time 0.73 seconds
Started Mar 17 01:44:02 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 203248 kb
Host smart-1cd776d1-da6b-437b-b70b-d56bd397809b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747800800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1747800800
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.178107521
Short name T2074
Test name
Test status
Simulation time 38573353 ps
CPU time 0.7 seconds
Started Mar 17 01:10:08 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 203216 kb
Host smart-5c54de50-7b2c-4186-8d59-515df8e11c3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178107521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.178107521
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.296791651
Short name T1969
Test name
Test status
Simulation time 12046657 ps
CPU time 0.76 seconds
Started Mar 17 01:44:01 PM PDT 24
Finished Mar 17 01:44:02 PM PDT 24
Peak memory 203308 kb
Host smart-d889955e-82a6-4d36-ab37-f6fc641302b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296791651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.296791651
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.393154490
Short name T1917
Test name
Test status
Simulation time 13487141 ps
CPU time 0.7 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:09 PM PDT 24
Peak memory 203208 kb
Host smart-7132a839-7247-4c1e-8ccf-d561be18bc87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=393154490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.393154490
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1518479578
Short name T2145
Test name
Test status
Simulation time 108884307 ps
CPU time 0.69 seconds
Started Mar 17 01:44:00 PM PDT 24
Finished Mar 17 01:44:01 PM PDT 24
Peak memory 203256 kb
Host smart-5cc5de98-1dbd-4134-8fb4-6c14567254d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518479578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1518479578
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.3844219153
Short name T1924
Test name
Test status
Simulation time 37570058 ps
CPU time 0.71 seconds
Started Mar 17 01:10:06 PM PDT 24
Finished Mar 17 01:10:07 PM PDT 24
Peak memory 203252 kb
Host smart-d0ac9461-2381-422e-9cf9-488d0c8e670c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844219153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
3844219153
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.3939960575
Short name T1943
Test name
Test status
Simulation time 14339860 ps
CPU time 0.77 seconds
Started Mar 17 01:10:10 PM PDT 24
Finished Mar 17 01:10:11 PM PDT 24
Peak memory 203304 kb
Host smart-9d4c1f97-5e13-4042-a2fc-5a8a2fe4444c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939960575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
3939960575
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4195605501
Short name T2161
Test name
Test status
Simulation time 16564066 ps
CPU time 0.72 seconds
Started Mar 17 01:44:01 PM PDT 24
Finished Mar 17 01:44:02 PM PDT 24
Peak memory 203284 kb
Host smart-40da84ba-794f-45c6-b65a-580da0d14be7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195605501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4195605501
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1355038718
Short name T2153
Test name
Test status
Simulation time 43738982 ps
CPU time 0.8 seconds
Started Mar 17 01:44:02 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 203288 kb
Host smart-28cd0702-df46-48f0-93bf-22c003541fd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355038718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1355038718
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.4089136325
Short name T1934
Test name
Test status
Simulation time 21126730 ps
CPU time 0.71 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:09 PM PDT 24
Peak memory 203308 kb
Host smart-a28d9e17-7297-4d92-ba0e-f2df12345de4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089136325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
4089136325
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.1299598264
Short name T2098
Test name
Test status
Simulation time 35297148 ps
CPU time 0.7 seconds
Started Mar 17 01:44:07 PM PDT 24
Finished Mar 17 01:44:08 PM PDT 24
Peak memory 203244 kb
Host smart-c04d69ec-f1bb-44ed-91e4-84d5ef716b54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299598264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
1299598264
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3782559881
Short name T2063
Test name
Test status
Simulation time 59602988 ps
CPU time 0.74 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:08 PM PDT 24
Peak memory 203268 kb
Host smart-130110fa-fede-436a-bd26-12d499fc227f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782559881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3782559881
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.211438186
Short name T2075
Test name
Test status
Simulation time 40615818 ps
CPU time 0.71 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:08 PM PDT 24
Peak memory 203304 kb
Host smart-ae369b61-ae43-4931-abd4-209eaadb0790
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211438186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.211438186
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3795989850
Short name T2125
Test name
Test status
Simulation time 48502744 ps
CPU time 0.7 seconds
Started Mar 17 01:44:06 PM PDT 24
Finished Mar 17 01:44:07 PM PDT 24
Peak memory 203236 kb
Host smart-69b0515a-da7f-47ac-bc75-d61d8ab4aa03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795989850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3795989850
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1070515677
Short name T1914
Test name
Test status
Simulation time 23887266 ps
CPU time 0.77 seconds
Started Mar 17 01:10:08 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 203300 kb
Host smart-d7ed9423-640d-43f0-a864-6607d2f09a97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1070515677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1070515677
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.376626305
Short name T2168
Test name
Test status
Simulation time 33233653 ps
CPU time 0.7 seconds
Started Mar 17 01:44:02 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 203264 kb
Host smart-6268bd4a-2453-4b2c-90b0-b434b848a21b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376626305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.376626305
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3457810045
Short name T2002
Test name
Test status
Simulation time 14448809 ps
CPU time 0.72 seconds
Started Mar 17 01:44:03 PM PDT 24
Finished Mar 17 01:44:04 PM PDT 24
Peak memory 203264 kb
Host smart-d5060683-d231-4346-822d-ae6d32b2655d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457810045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3457810045
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.4058731357
Short name T2107
Test name
Test status
Simulation time 12300772 ps
CPU time 0.73 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:09 PM PDT 24
Peak memory 203252 kb
Host smart-42c05914-df3d-449c-9afc-0edc0b245ffd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058731357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
4058731357
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2804593768
Short name T111
Test name
Test status
Simulation time 1163047474 ps
CPU time 24.48 seconds
Started Mar 17 01:43:46 PM PDT 24
Finished Mar 17 01:44:11 PM PDT 24
Peak memory 215112 kb
Host smart-3255f40f-b285-4cd2-91d7-a4a66f3ab826
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804593768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2804593768
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.577806576
Short name T2183
Test name
Test status
Simulation time 143770483 ps
CPU time 7.73 seconds
Started Mar 17 01:09:37 PM PDT 24
Finished Mar 17 01:09:45 PM PDT 24
Peak memory 215020 kb
Host smart-e472cd40-5e80-47ca-a43e-87d000f736ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577806576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_aliasing.577806576
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2229929361
Short name T2162
Test name
Test status
Simulation time 641908062 ps
CPU time 13.3 seconds
Started Mar 17 01:09:40 PM PDT 24
Finished Mar 17 01:09:54 PM PDT 24
Peak memory 206864 kb
Host smart-4a8a00bb-66a1-4a51-8f23-58473890dd88
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229929361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2229929361
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.434647919
Short name T2085
Test name
Test status
Simulation time 1568479969 ps
CPU time 25.71 seconds
Started Mar 17 01:43:47 PM PDT 24
Finished Mar 17 01:44:14 PM PDT 24
Peak memory 206968 kb
Host smart-5fc15873-5825-4437-987c-8e487d0d15e0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=434647919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_bit_bash.434647919
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.4128839849
Short name T79
Test name
Test status
Simulation time 33361653 ps
CPU time 1.21 seconds
Started Mar 17 01:09:40 PM PDT 24
Finished Mar 17 01:09:42 PM PDT 24
Peak memory 206684 kb
Host smart-8a235350-649b-4926-bafc-5e1466829000
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128839849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.4128839849
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.757904357
Short name T78
Test name
Test status
Simulation time 219039592 ps
CPU time 1.22 seconds
Started Mar 17 01:43:43 PM PDT 24
Finished Mar 17 01:43:44 PM PDT 24
Peak memory 206688 kb
Host smart-645c106d-c2f6-4fe6-94db-ab37e5b4b6db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757904357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.757904357
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2219598673
Short name T2021
Test name
Test status
Simulation time 39968022 ps
CPU time 2.82 seconds
Started Mar 17 01:43:48 PM PDT 24
Finished Mar 17 01:43:51 PM PDT 24
Peak memory 216748 kb
Host smart-bfa56a00-a032-4c2e-917b-834a9f10847a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219598673 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2219598673
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2741288605
Short name T2078
Test name
Test status
Simulation time 216971706 ps
CPU time 3.93 seconds
Started Mar 17 01:09:40 PM PDT 24
Finished Mar 17 01:09:44 PM PDT 24
Peak memory 217056 kb
Host smart-0c274050-e40b-4193-aa61-5bd7c30b9b87
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741288605 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2741288605
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.1727725866
Short name T107
Test name
Test status
Simulation time 73847760 ps
CPU time 1.95 seconds
Started Mar 17 01:43:48 PM PDT 24
Finished Mar 17 01:43:51 PM PDT 24
Peak memory 206856 kb
Host smart-a53edb90-4430-48c8-b0cf-78c2a648686a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727725866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1
727725866
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2676485837
Short name T2103
Test name
Test status
Simulation time 57265157 ps
CPU time 2.19 seconds
Started Mar 17 01:09:38 PM PDT 24
Finished Mar 17 01:09:40 PM PDT 24
Peak memory 206716 kb
Host smart-fe295c9f-3777-4ed8-94d0-537358cf9013
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676485837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
676485837
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1720199666
Short name T2084
Test name
Test status
Simulation time 22325303 ps
CPU time 0.74 seconds
Started Mar 17 01:43:47 PM PDT 24
Finished Mar 17 01:43:47 PM PDT 24
Peak memory 203228 kb
Host smart-00d7a785-ffaf-46a0-ac5e-7745836f04d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720199666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
720199666
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.4003713616
Short name T1939
Test name
Test status
Simulation time 50642019 ps
CPU time 0.76 seconds
Started Mar 17 01:09:39 PM PDT 24
Finished Mar 17 01:09:39 PM PDT 24
Peak memory 203376 kb
Host smart-5672e5cb-effd-4195-9c5d-7b7e0fb6bcbb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003713616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.4
003713616
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3338976547
Short name T2196
Test name
Test status
Simulation time 58829280 ps
CPU time 2.15 seconds
Started Mar 17 01:43:46 PM PDT 24
Finished Mar 17 01:43:49 PM PDT 24
Peak memory 215120 kb
Host smart-dd43c9ba-dcbf-4142-993e-31db6dd03c24
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338976547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3338976547
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.867730721
Short name T2165
Test name
Test status
Simulation time 663681440 ps
CPU time 1.92 seconds
Started Mar 17 01:09:41 PM PDT 24
Finished Mar 17 01:09:43 PM PDT 24
Peak memory 215060 kb
Host smart-15850da3-8097-4205-a44e-01c5ed1079ef
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867730721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.867730721
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1276144805
Short name T2020
Test name
Test status
Simulation time 12709377 ps
CPU time 0.68 seconds
Started Mar 17 01:43:49 PM PDT 24
Finished Mar 17 01:43:50 PM PDT 24
Peak memory 203208 kb
Host smart-c763a5f6-736a-4c47-8a57-7f86dba86c98
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276144805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1276144805
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3877613822
Short name T1948
Test name
Test status
Simulation time 15897525 ps
CPU time 0.64 seconds
Started Mar 17 01:09:38 PM PDT 24
Finished Mar 17 01:09:39 PM PDT 24
Peak memory 203160 kb
Host smart-ee57a3d6-9944-4897-87d3-c97ac9d9f294
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877613822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3877613822
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1406199823
Short name T2144
Test name
Test status
Simulation time 600709759 ps
CPU time 3.15 seconds
Started Mar 17 01:43:50 PM PDT 24
Finished Mar 17 01:43:53 PM PDT 24
Peak memory 215052 kb
Host smart-50ddb6ef-4f3c-48de-b792-3b80319bd430
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406199823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1406199823
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1423196053
Short name T134
Test name
Test status
Simulation time 70889342 ps
CPU time 1.69 seconds
Started Mar 17 01:09:39 PM PDT 24
Finished Mar 17 01:09:42 PM PDT 24
Peak memory 215048 kb
Host smart-fc8c046d-8c2e-4156-b419-e7c69b63feaf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423196053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1423196053
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3881848767
Short name T87
Test name
Test status
Simulation time 150598437 ps
CPU time 2.92 seconds
Started Mar 17 01:43:45 PM PDT 24
Finished Mar 17 01:43:48 PM PDT 24
Peak memory 215200 kb
Host smart-18197b39-db12-4083-8f88-a9b451bd1696
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881848767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
881848767
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.992071511
Short name T101
Test name
Test status
Simulation time 142566768 ps
CPU time 3.66 seconds
Started Mar 17 01:09:40 PM PDT 24
Finished Mar 17 01:09:44 PM PDT 24
Peak memory 216160 kb
Host smart-ac467065-93fd-40c2-bda7-74788c163164
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992071511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.992071511
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.1469682249
Short name T1975
Test name
Test status
Simulation time 1168440286 ps
CPU time 17.87 seconds
Started Mar 17 01:43:48 PM PDT 24
Finished Mar 17 01:44:07 PM PDT 24
Peak memory 215044 kb
Host smart-23a296fb-37ac-4e9c-b8a9-46e050678d46
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469682249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.1469682249
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.377270462
Short name T2158
Test name
Test status
Simulation time 431365494 ps
CPU time 7.56 seconds
Started Mar 17 01:09:38 PM PDT 24
Finished Mar 17 01:09:46 PM PDT 24
Peak memory 215152 kb
Host smart-e9c3f071-2d5c-4807-9ad0-f674a8d7020b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377270462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.377270462
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1955783424
Short name T2148
Test name
Test status
Simulation time 18617036 ps
CPU time 0.8 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 203296 kb
Host smart-8c5b8961-1f2d-462b-9f77-779820f561f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955783424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1955783424
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.340705842
Short name T1923
Test name
Test status
Simulation time 11158481 ps
CPU time 0.74 seconds
Started Mar 17 01:44:02 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 203308 kb
Host smart-5a6ca379-d76c-465d-8bb6-3a53a279fa7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340705842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.340705842
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2440330033
Short name T2130
Test name
Test status
Simulation time 16510349 ps
CPU time 0.73 seconds
Started Mar 17 01:10:08 PM PDT 24
Finished Mar 17 01:10:09 PM PDT 24
Peak memory 203192 kb
Host smart-a29a2af4-f84b-4dca-8068-04f6b37f80a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440330033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2440330033
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2969844622
Short name T1992
Test name
Test status
Simulation time 175489510 ps
CPU time 0.8 seconds
Started Mar 17 01:44:04 PM PDT 24
Finished Mar 17 01:44:05 PM PDT 24
Peak memory 203344 kb
Host smart-e418bcf3-4691-4d5a-9a62-ccd05bf1d149
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969844622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2969844622
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.1289085707
Short name T2060
Test name
Test status
Simulation time 20678028 ps
CPU time 0.78 seconds
Started Mar 17 01:44:02 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 203320 kb
Host smart-f7522606-fcea-4c98-81bd-5bb708b0c071
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289085707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
1289085707
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2983748646
Short name T2119
Test name
Test status
Simulation time 16723115 ps
CPU time 0.71 seconds
Started Mar 17 01:10:08 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 203316 kb
Host smart-870bd61c-c9f8-4afc-a193-359893f430e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983748646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2983748646
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2397983527
Short name T1955
Test name
Test status
Simulation time 88996531 ps
CPU time 0.69 seconds
Started Mar 17 01:10:05 PM PDT 24
Finished Mar 17 01:10:06 PM PDT 24
Peak memory 203228 kb
Host smart-94c1fca3-2a8f-4f2d-addc-46b1c04d2d7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2397983527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2397983527
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.3656397059
Short name T2042
Test name
Test status
Simulation time 20769817 ps
CPU time 0.75 seconds
Started Mar 17 01:44:07 PM PDT 24
Finished Mar 17 01:44:08 PM PDT 24
Peak memory 203316 kb
Host smart-13f3cb9b-ed79-4014-85e3-fd15b2e08a16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656397059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
3656397059
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3204483154
Short name T2182
Test name
Test status
Simulation time 27732664 ps
CPU time 0.76 seconds
Started Mar 17 01:10:07 PM PDT 24
Finished Mar 17 01:10:08 PM PDT 24
Peak memory 203296 kb
Host smart-626c9a59-acc2-44cb-abb2-27bdcdab2ade
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204483154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3204483154
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3571208623
Short name T1921
Test name
Test status
Simulation time 13212124 ps
CPU time 0.7 seconds
Started Mar 17 01:44:03 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 203316 kb
Host smart-263818a8-ed8e-4a3b-aed7-5fee58712139
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571208623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3571208623
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1211058946
Short name T1957
Test name
Test status
Simulation time 22802437 ps
CPU time 0.75 seconds
Started Mar 17 01:10:12 PM PDT 24
Finished Mar 17 01:10:13 PM PDT 24
Peak memory 203372 kb
Host smart-fbeebf5c-c8bb-4809-b7a3-da983217d4ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1211058946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1211058946
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.179062787
Short name T2050
Test name
Test status
Simulation time 47407007 ps
CPU time 0.72 seconds
Started Mar 17 01:44:07 PM PDT 24
Finished Mar 17 01:44:08 PM PDT 24
Peak memory 203244 kb
Host smart-b9a51f15-9d7b-4f70-9dde-159d387e829d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179062787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.179062787
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1600246053
Short name T2052
Test name
Test status
Simulation time 12014898 ps
CPU time 0.69 seconds
Started Mar 17 01:10:10 PM PDT 24
Finished Mar 17 01:10:11 PM PDT 24
Peak memory 203268 kb
Host smart-a51c50ea-5a45-4a75-8bf4-e688c95da6d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600246053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1600246053
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2107518629
Short name T2176
Test name
Test status
Simulation time 48957623 ps
CPU time 0.71 seconds
Started Mar 17 01:44:01 PM PDT 24
Finished Mar 17 01:44:02 PM PDT 24
Peak memory 203204 kb
Host smart-b2a410f5-255c-46a9-ac74-9e5a798b0043
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107518629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2107518629
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.1950545045
Short name T1930
Test name
Test status
Simulation time 43629319 ps
CPU time 0.71 seconds
Started Mar 17 01:44:02 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 203300 kb
Host smart-604b763a-5724-4419-bc7c-309142cd12a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950545045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
1950545045
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2001427244
Short name T2113
Test name
Test status
Simulation time 12313190 ps
CPU time 0.72 seconds
Started Mar 17 01:10:08 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 203092 kb
Host smart-8a13ebf4-6fdc-492d-aced-b3f6cfbcbcf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001427244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2001427244
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1101726960
Short name T2095
Test name
Test status
Simulation time 99392055 ps
CPU time 0.74 seconds
Started Mar 17 01:10:08 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 203120 kb
Host smart-82df1244-c915-4584-84d0-79e15fda0105
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101726960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1101726960
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2941469524
Short name T1956
Test name
Test status
Simulation time 15935343 ps
CPU time 0.7 seconds
Started Mar 17 01:44:02 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 203268 kb
Host smart-3898a489-1590-4b31-b178-44610d7b31f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941469524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2941469524
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.162792709
Short name T2025
Test name
Test status
Simulation time 67723904 ps
CPU time 0.7 seconds
Started Mar 17 01:10:10 PM PDT 24
Finished Mar 17 01:10:11 PM PDT 24
Peak memory 203256 kb
Host smart-51c93d97-2963-484f-b213-65e33d8f6c7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162792709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.162792709
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.722747915
Short name T1963
Test name
Test status
Simulation time 20235594 ps
CPU time 0.74 seconds
Started Mar 17 01:44:05 PM PDT 24
Finished Mar 17 01:44:05 PM PDT 24
Peak memory 203268 kb
Host smart-4a1fc94b-8e87-4c8b-bc41-899cab513319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722747915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.722747915
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.166745306
Short name T110
Test name
Test status
Simulation time 202841859 ps
CPU time 7.1 seconds
Started Mar 17 01:09:49 PM PDT 24
Finished Mar 17 01:09:56 PM PDT 24
Peak memory 206624 kb
Host smart-e016212d-c799-44de-9869-b923a4781792
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166745306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_aliasing.166745306
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1722755010
Short name T114
Test name
Test status
Simulation time 1829157347 ps
CPU time 21.71 seconds
Started Mar 17 01:43:43 PM PDT 24
Finished Mar 17 01:44:05 PM PDT 24
Peak memory 215036 kb
Host smart-078395fc-4c03-4910-bd0f-33315b8313c3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722755010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1722755010
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1182981934
Short name T2202
Test name
Test status
Simulation time 2470702564 ps
CPU time 27.12 seconds
Started Mar 17 01:09:44 PM PDT 24
Finished Mar 17 01:10:12 PM PDT 24
Peak memory 207032 kb
Host smart-dd1591de-c8b4-4806-9b8c-768f369eff61
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182981934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1182981934
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3432064355
Short name T2083
Test name
Test status
Simulation time 2798085579 ps
CPU time 39.17 seconds
Started Mar 17 01:43:46 PM PDT 24
Finished Mar 17 01:44:26 PM PDT 24
Peak memory 207008 kb
Host smart-66554756-f8a6-416f-80c8-f3bf9dd9869a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432064355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3432064355
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2512651741
Short name T77
Test name
Test status
Simulation time 44895862 ps
CPU time 1.45 seconds
Started Mar 17 01:43:47 PM PDT 24
Finished Mar 17 01:43:49 PM PDT 24
Peak memory 216184 kb
Host smart-276dcaf3-0b95-4ac9-8fb8-ac5100bb7df9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512651741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2512651741
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.396807097
Short name T2079
Test name
Test status
Simulation time 18541387 ps
CPU time 1.16 seconds
Started Mar 17 01:09:47 PM PDT 24
Finished Mar 17 01:09:48 PM PDT 24
Peak memory 206820 kb
Host smart-d66a467e-7126-462b-a644-c4423f569799
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396807097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.396807097
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2315889806
Short name T2032
Test name
Test status
Simulation time 142483808 ps
CPU time 2.84 seconds
Started Mar 17 01:09:46 PM PDT 24
Finished Mar 17 01:09:49 PM PDT 24
Peak memory 216360 kb
Host smart-0f08f3bc-b161-48a9-a245-6608a1c83e16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315889806 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2315889806
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.4248148249
Short name T2044
Test name
Test status
Simulation time 25500035 ps
CPU time 1.68 seconds
Started Mar 17 01:43:47 PM PDT 24
Finished Mar 17 01:43:50 PM PDT 24
Peak memory 216080 kb
Host smart-1fdffb29-f6a2-4cb7-ab39-88604b737825
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248148249 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.4248148249
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2699368299
Short name T2088
Test name
Test status
Simulation time 113963271 ps
CPU time 1.9 seconds
Started Mar 17 01:43:47 PM PDT 24
Finished Mar 17 01:43:50 PM PDT 24
Peak memory 206796 kb
Host smart-ac80b822-da9e-49dc-9b08-02facfe2d00b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699368299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
699368299
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.4224272113
Short name T2149
Test name
Test status
Simulation time 78672514 ps
CPU time 1.14 seconds
Started Mar 17 01:09:47 PM PDT 24
Finished Mar 17 01:09:48 PM PDT 24
Peak memory 214916 kb
Host smart-6a515fdf-32db-459e-81ad-8857434824d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224272113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.4
224272113
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1950507446
Short name T1988
Test name
Test status
Simulation time 48560747 ps
CPU time 0.73 seconds
Started Mar 17 01:43:44 PM PDT 24
Finished Mar 17 01:43:45 PM PDT 24
Peak memory 203268 kb
Host smart-ea11b3a6-9daa-4cd9-991c-ae234548b710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950507446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
950507446
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.320203596
Short name T1919
Test name
Test status
Simulation time 32457872 ps
CPU time 0.72 seconds
Started Mar 17 01:09:40 PM PDT 24
Finished Mar 17 01:09:42 PM PDT 24
Peak memory 203212 kb
Host smart-298b9ca6-fd13-472d-a97e-b9b4224f6296
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320203596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.320203596
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3627963169
Short name T2077
Test name
Test status
Simulation time 364484554 ps
CPU time 2.47 seconds
Started Mar 17 01:09:45 PM PDT 24
Finished Mar 17 01:09:48 PM PDT 24
Peak memory 215160 kb
Host smart-d372c7a3-7f5a-4530-b40e-4dbaa570571d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627963169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3627963169
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.4091375657
Short name T113
Test name
Test status
Simulation time 51616576 ps
CPU time 2.17 seconds
Started Mar 17 01:43:45 PM PDT 24
Finished Mar 17 01:43:47 PM PDT 24
Peak memory 215152 kb
Host smart-8561c2b3-fc40-4462-ab7d-f1c296a39281
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091375657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.4091375657
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1194708674
Short name T2185
Test name
Test status
Simulation time 13908287 ps
CPU time 0.67 seconds
Started Mar 17 01:09:51 PM PDT 24
Finished Mar 17 01:09:51 PM PDT 24
Peak memory 203264 kb
Host smart-1cd6b236-df56-4530-ab4d-06d19205c487
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194708674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1194708674
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3423940167
Short name T1954
Test name
Test status
Simulation time 152925808 ps
CPU time 0.66 seconds
Started Mar 17 01:43:45 PM PDT 24
Finished Mar 17 01:43:46 PM PDT 24
Peak memory 203208 kb
Host smart-a203d214-e23d-412c-baff-16d98be186d0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423940167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3423940167
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.251273789
Short name T1994
Test name
Test status
Simulation time 74371912 ps
CPU time 1.88 seconds
Started Mar 17 01:43:44 PM PDT 24
Finished Mar 17 01:43:46 PM PDT 24
Peak memory 206884 kb
Host smart-1a069fbb-6686-4f35-bc0b-9ddf6619453b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251273789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.251273789
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.3502750152
Short name T2096
Test name
Test status
Simulation time 262402804 ps
CPU time 2.82 seconds
Started Mar 17 01:09:46 PM PDT 24
Finished Mar 17 01:09:50 PM PDT 24
Peak memory 214956 kb
Host smart-d49ac722-4ac3-4e68-a67c-bed3c257f846
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502750152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.3502750152
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2188208544
Short name T2131
Test name
Test status
Simulation time 82050279 ps
CPU time 1.26 seconds
Started Mar 17 01:43:41 PM PDT 24
Finished Mar 17 01:43:43 PM PDT 24
Peak memory 215152 kb
Host smart-84794532-57a9-4b3b-a11f-419ae4083a39
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188208544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
188208544
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2832026327
Short name T95
Test name
Test status
Simulation time 246969327 ps
CPU time 1.9 seconds
Started Mar 17 01:09:40 PM PDT 24
Finished Mar 17 01:09:43 PM PDT 24
Peak memory 215108 kb
Host smart-d988a9be-2791-4264-8103-2d28294ca862
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832026327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
832026327
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.113096993
Short name T161
Test name
Test status
Simulation time 581669625 ps
CPU time 18.71 seconds
Started Mar 17 01:43:45 PM PDT 24
Finished Mar 17 01:44:04 PM PDT 24
Peak memory 215048 kb
Host smart-aef216ca-8642-48a8-a2b5-4fc0892fb628
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113096993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.113096993
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.3295709533
Short name T104
Test name
Test status
Simulation time 4412269673 ps
CPU time 28.34 seconds
Started Mar 17 01:09:40 PM PDT 24
Finished Mar 17 01:10:08 PM PDT 24
Peak memory 215588 kb
Host smart-95237f44-73f4-4e8a-a4d3-af0b64278d1f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3295709533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.3295709533
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3218517740
Short name T1911
Test name
Test status
Simulation time 145287302 ps
CPU time 0.7 seconds
Started Mar 17 01:10:12 PM PDT 24
Finished Mar 17 01:10:13 PM PDT 24
Peak memory 203272 kb
Host smart-cc10bac4-48ff-4882-a12e-8fb4e8329213
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218517740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3218517740
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.486457257
Short name T1949
Test name
Test status
Simulation time 18550900 ps
CPU time 0.77 seconds
Started Mar 17 01:44:01 PM PDT 24
Finished Mar 17 01:44:02 PM PDT 24
Peak memory 203304 kb
Host smart-14f1ec48-23d4-41d1-8afb-43adcad547c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486457257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.486457257
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2019517449
Short name T1910
Test name
Test status
Simulation time 48549889 ps
CPU time 0.8 seconds
Started Mar 17 01:44:01 PM PDT 24
Finished Mar 17 01:44:02 PM PDT 24
Peak memory 203312 kb
Host smart-74d0571c-843b-4419-a6f4-d7fe0a9a3d7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019517449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2019517449
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.421049319
Short name T1982
Test name
Test status
Simulation time 22149772 ps
CPU time 0.73 seconds
Started Mar 17 01:10:09 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 203160 kb
Host smart-cb0f4ab7-fb4a-4831-9b07-23da824fbc8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421049319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.421049319
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1557988390
Short name T2013
Test name
Test status
Simulation time 57872065 ps
CPU time 0.77 seconds
Started Mar 17 01:44:04 PM PDT 24
Finished Mar 17 01:44:04 PM PDT 24
Peak memory 203396 kb
Host smart-5df0590f-0924-4290-b835-9fba9a31cb32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557988390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1557988390
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.433251091
Short name T2146
Test name
Test status
Simulation time 12633676 ps
CPU time 0.71 seconds
Started Mar 17 01:10:12 PM PDT 24
Finished Mar 17 01:10:13 PM PDT 24
Peak memory 203276 kb
Host smart-2ba089a5-b264-4afc-a53a-ab5bf15a7792
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433251091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.433251091
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1623336276
Short name T2106
Test name
Test status
Simulation time 14491700 ps
CPU time 0.72 seconds
Started Mar 17 01:10:09 PM PDT 24
Finished Mar 17 01:10:11 PM PDT 24
Peak memory 203192 kb
Host smart-553d63bf-a29f-44ae-b6a4-7ce93a0dcc94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1623336276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1623336276
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2857292292
Short name T1932
Test name
Test status
Simulation time 14325489 ps
CPU time 0.73 seconds
Started Mar 17 01:44:02 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 203200 kb
Host smart-d9773290-359e-49c6-8ddb-f3b46843c80a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857292292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2857292292
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.1870584522
Short name T2046
Test name
Test status
Simulation time 48228305 ps
CPU time 0.75 seconds
Started Mar 17 01:10:10 PM PDT 24
Finished Mar 17 01:10:11 PM PDT 24
Peak memory 203276 kb
Host smart-9e5d437f-9cb0-4ed0-b201-8811b1d7d5d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870584522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
1870584522
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2978112408
Short name T2053
Test name
Test status
Simulation time 17744328 ps
CPU time 0.73 seconds
Started Mar 17 01:44:04 PM PDT 24
Finished Mar 17 01:44:04 PM PDT 24
Peak memory 203276 kb
Host smart-88728ae0-01b2-4924-bb5b-221293eb98e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978112408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2978112408
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2178054474
Short name T1935
Test name
Test status
Simulation time 13586616 ps
CPU time 0.76 seconds
Started Mar 17 01:10:08 PM PDT 24
Finished Mar 17 01:10:10 PM PDT 24
Peak memory 203160 kb
Host smart-50b401fa-9641-4f6c-a9d5-3c89a0fca068
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178054474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2178054474
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3353674053
Short name T2058
Test name
Test status
Simulation time 42907268 ps
CPU time 0.77 seconds
Started Mar 17 01:44:02 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 203232 kb
Host smart-72811604-6976-40e5-831b-8dea1444f274
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353674053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3353674053
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3594497540
Short name T1927
Test name
Test status
Simulation time 19959920 ps
CPU time 0.76 seconds
Started Mar 17 01:44:05 PM PDT 24
Finished Mar 17 01:44:07 PM PDT 24
Peak memory 203384 kb
Host smart-eec75078-1995-4001-b8c2-04a77dbe489e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594497540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3594497540
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.960320370
Short name T2094
Test name
Test status
Simulation time 12637687 ps
CPU time 0.73 seconds
Started Mar 17 01:10:15 PM PDT 24
Finished Mar 17 01:10:16 PM PDT 24
Peak memory 203248 kb
Host smart-88ab232a-3284-4b7d-9ab4-efb6b139fc8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960320370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.960320370
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2106220045
Short name T2016
Test name
Test status
Simulation time 25353122 ps
CPU time 0.73 seconds
Started Mar 17 01:10:13 PM PDT 24
Finished Mar 17 01:10:14 PM PDT 24
Peak memory 203188 kb
Host smart-b2385b2e-d419-414b-ad29-4b108251cb59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106220045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2106220045
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.457903449
Short name T2061
Test name
Test status
Simulation time 18229429 ps
CPU time 0.78 seconds
Started Mar 17 01:44:03 PM PDT 24
Finished Mar 17 01:44:04 PM PDT 24
Peak memory 203300 kb
Host smart-6874b625-381d-4bba-a73a-7f3df9fb72ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457903449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.457903449
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1912117109
Short name T2036
Test name
Test status
Simulation time 48715379 ps
CPU time 0.76 seconds
Started Mar 17 01:44:03 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 203328 kb
Host smart-d3c21645-c757-4418-ab4f-6c275146e7c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912117109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1912117109
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.550172885
Short name T2018
Test name
Test status
Simulation time 24777080 ps
CPU time 0.72 seconds
Started Mar 17 01:10:12 PM PDT 24
Finished Mar 17 01:10:12 PM PDT 24
Peak memory 203164 kb
Host smart-a5775c1c-7a09-4540-87db-b8307056f7ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550172885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.550172885
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.2110515397
Short name T2064
Test name
Test status
Simulation time 13758149 ps
CPU time 0.7 seconds
Started Mar 17 01:44:05 PM PDT 24
Finished Mar 17 01:44:05 PM PDT 24
Peak memory 203300 kb
Host smart-66d6ab90-c7ca-433a-aff1-d5a864a3a81b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110515397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
2110515397
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.560120761
Short name T1913
Test name
Test status
Simulation time 32511014 ps
CPU time 0.73 seconds
Started Mar 17 01:10:12 PM PDT 24
Finished Mar 17 01:10:13 PM PDT 24
Peak memory 203296 kb
Host smart-221c5088-21ae-4deb-8d0f-04f869d1a6fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560120761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.560120761
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.2896314628
Short name T2045
Test name
Test status
Simulation time 22434527 ps
CPU time 1.74 seconds
Started Mar 17 01:43:48 PM PDT 24
Finished Mar 17 01:43:51 PM PDT 24
Peak memory 215168 kb
Host smart-e6b29950-1e06-4a36-81aa-f330f6fc0cf9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896314628 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.2896314628
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3192951744
Short name T2191
Test name
Test status
Simulation time 380312899 ps
CPU time 3 seconds
Started Mar 17 01:09:45 PM PDT 24
Finished Mar 17 01:09:48 PM PDT 24
Peak memory 216420 kb
Host smart-0f3994e4-fe89-4bdd-b07a-6419a56ee4a5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192951744 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.3192951744
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3957001461
Short name T2121
Test name
Test status
Simulation time 77022019 ps
CPU time 1.44 seconds
Started Mar 17 01:43:48 PM PDT 24
Finished Mar 17 01:43:50 PM PDT 24
Peak memory 206748 kb
Host smart-c0f2434e-4f9c-4b7e-9018-41c61f66761b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957001461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
957001461
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.63888799
Short name T2116
Test name
Test status
Simulation time 151966366 ps
CPU time 2.15 seconds
Started Mar 17 01:09:47 PM PDT 24
Finished Mar 17 01:09:49 PM PDT 24
Peak memory 215032 kb
Host smart-42ac391e-4fc5-4a15-82c3-0f7778297dde
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63888799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.63888799
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.3488756291
Short name T2154
Test name
Test status
Simulation time 24411717 ps
CPU time 0.69 seconds
Started Mar 17 01:09:46 PM PDT 24
Finished Mar 17 01:09:46 PM PDT 24
Peak memory 203248 kb
Host smart-75184bc6-1b84-4387-b2cf-2c2d80fba0ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3488756291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3
488756291
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.75347419
Short name T2093
Test name
Test status
Simulation time 33972912 ps
CPU time 0.81 seconds
Started Mar 17 01:43:46 PM PDT 24
Finished Mar 17 01:43:47 PM PDT 24
Peak memory 203272 kb
Host smart-b1ec2af5-b6ae-44bf-b7d7-6b5bf329f8fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75347419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.75347419
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1030874682
Short name T2197
Test name
Test status
Simulation time 1399758461 ps
CPU time 4.21 seconds
Started Mar 17 01:09:46 PM PDT 24
Finished Mar 17 01:09:50 PM PDT 24
Peak memory 215148 kb
Host smart-59e41c52-ab92-4d09-8dc9-a7952ff1a51f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1030874682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1030874682
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.828320906
Short name T2007
Test name
Test status
Simulation time 207388133 ps
CPU time 1.99 seconds
Started Mar 17 01:43:48 PM PDT 24
Finished Mar 17 01:43:51 PM PDT 24
Peak memory 206600 kb
Host smart-418dc34c-47b3-4eb8-ab67-c82a3d850504
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828320906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sp
i_device_same_csr_outstanding.828320906
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1101429650
Short name T2019
Test name
Test status
Simulation time 634379310 ps
CPU time 2.38 seconds
Started Mar 17 01:09:45 PM PDT 24
Finished Mar 17 01:09:47 PM PDT 24
Peak memory 215056 kb
Host smart-c5b4a513-b1ed-49f7-976f-ecba513dcba7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101429650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
101429650
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3109789956
Short name T2193
Test name
Test status
Simulation time 389429617 ps
CPU time 4.9 seconds
Started Mar 17 01:43:47 PM PDT 24
Finished Mar 17 01:43:53 PM PDT 24
Peak memory 215436 kb
Host smart-a73eb5a9-02c1-4295-9114-0d302fa34133
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3109789956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
109789956
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2783023840
Short name T2001
Test name
Test status
Simulation time 214030527 ps
CPU time 12.02 seconds
Started Mar 17 01:43:47 PM PDT 24
Finished Mar 17 01:44:00 PM PDT 24
Peak memory 215520 kb
Host smart-81a0ae8b-de54-483a-9e76-197f21541df2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783023840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2783023840
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.4086613498
Short name T160
Test name
Test status
Simulation time 660860551 ps
CPU time 16.46 seconds
Started Mar 17 01:09:46 PM PDT 24
Finished Mar 17 01:10:03 PM PDT 24
Peak memory 215652 kb
Host smart-75f6c179-873c-4d84-9da9-a1e04302e2f2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086613498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.4086613498
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1342168473
Short name T1976
Test name
Test status
Simulation time 443852534 ps
CPU time 2.9 seconds
Started Mar 17 01:09:49 PM PDT 24
Finished Mar 17 01:09:52 PM PDT 24
Peak memory 216588 kb
Host smart-7b2f2f23-67e2-43c4-b79f-6eacca15bc2c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342168473 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1342168473
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3847888451
Short name T135
Test name
Test status
Simulation time 750553747 ps
CPU time 1.88 seconds
Started Mar 17 01:43:49 PM PDT 24
Finished Mar 17 01:43:51 PM PDT 24
Peak memory 215184 kb
Host smart-03867163-64ea-4df3-9ed7-89e49f2ca6e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847888451 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3847888451
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2872091821
Short name T116
Test name
Test status
Simulation time 34533220 ps
CPU time 1.18 seconds
Started Mar 17 01:09:49 PM PDT 24
Finished Mar 17 01:09:51 PM PDT 24
Peak memory 214936 kb
Host smart-cb502644-b944-46f6-b69b-eee41e0fd97f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872091821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
872091821
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.3670226228
Short name T2147
Test name
Test status
Simulation time 97282342 ps
CPU time 1.91 seconds
Started Mar 17 01:43:51 PM PDT 24
Finished Mar 17 01:43:53 PM PDT 24
Peak memory 206744 kb
Host smart-b91aa013-6b29-486c-82b4-e6ba42bc3383
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670226228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3
670226228
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.2668890341
Short name T1951
Test name
Test status
Simulation time 42775602 ps
CPU time 0.76 seconds
Started Mar 17 01:43:48 PM PDT 24
Finished Mar 17 01:43:50 PM PDT 24
Peak memory 203140 kb
Host smart-fa1c8806-7486-4094-830e-4c541e5ae14a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668890341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.2
668890341
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.701159862
Short name T1946
Test name
Test status
Simulation time 14366609 ps
CPU time 0.81 seconds
Started Mar 17 01:09:46 PM PDT 24
Finished Mar 17 01:09:48 PM PDT 24
Peak memory 203296 kb
Host smart-02fe966c-6608-41f9-81b5-d4bc6d025a81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701159862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.701159862
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2413223488
Short name T1989
Test name
Test status
Simulation time 1031677300 ps
CPU time 4.17 seconds
Started Mar 17 01:43:51 PM PDT 24
Finished Mar 17 01:43:55 PM PDT 24
Peak memory 215120 kb
Host smart-4d5722d3-7f5f-42d5-bb2d-daa266114a0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413223488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2413223488
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.889650292
Short name T1937
Test name
Test status
Simulation time 226169369 ps
CPU time 3.09 seconds
Started Mar 17 01:09:46 PM PDT 24
Finished Mar 17 01:09:49 PM PDT 24
Peak memory 215132 kb
Host smart-a4b352da-1eff-477a-b656-449662f721d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889650292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.889650292
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1700375021
Short name T1974
Test name
Test status
Simulation time 367073395 ps
CPU time 2.87 seconds
Started Mar 17 01:09:49 PM PDT 24
Finished Mar 17 01:09:52 PM PDT 24
Peak memory 214944 kb
Host smart-946c9815-02db-4405-8a3c-fb52ddac5c1b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1700375021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
700375021
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.697408026
Short name T2057
Test name
Test status
Simulation time 228154143 ps
CPU time 2.07 seconds
Started Mar 17 01:43:46 PM PDT 24
Finished Mar 17 01:43:49 PM PDT 24
Peak memory 215468 kb
Host smart-7c1a8c80-2649-4245-8983-85cdbfb53066
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697408026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.697408026
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1423411222
Short name T2031
Test name
Test status
Simulation time 2015958417 ps
CPU time 15.17 seconds
Started Mar 17 01:43:44 PM PDT 24
Finished Mar 17 01:43:59 PM PDT 24
Peak memory 215400 kb
Host smart-9bd010ab-bc3a-43e6-8dd1-0a8431551a31
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423411222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1423411222
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2913803417
Short name T2152
Test name
Test status
Simulation time 1289537447 ps
CPU time 20.7 seconds
Started Mar 17 01:09:45 PM PDT 24
Finished Mar 17 01:10:05 PM PDT 24
Peak memory 215168 kb
Host smart-8ec1c96a-fcea-4749-9de9-164171de5af4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913803417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2913803417
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.1940339309
Short name T2139
Test name
Test status
Simulation time 27699429 ps
CPU time 1.98 seconds
Started Mar 17 01:43:51 PM PDT 24
Finished Mar 17 01:43:54 PM PDT 24
Peak memory 215080 kb
Host smart-445f5195-d1af-41ff-a96c-8c986bfafcd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940339309 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.1940339309
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3173038554
Short name T2199
Test name
Test status
Simulation time 31094813 ps
CPU time 1.93 seconds
Started Mar 17 01:09:47 PM PDT 24
Finished Mar 17 01:09:49 PM PDT 24
Peak memory 215144 kb
Host smart-26826ad9-5e23-416c-8c16-f92b37bd94ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173038554 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3173038554
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.1679206668
Short name T2167
Test name
Test status
Simulation time 100556565 ps
CPU time 2.79 seconds
Started Mar 17 01:43:54 PM PDT 24
Finished Mar 17 01:43:57 PM PDT 24
Peak memory 215128 kb
Host smart-fbf807c9-7fd0-4825-8e3f-db07fc5f5a27
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679206668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.1
679206668
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3425967242
Short name T2138
Test name
Test status
Simulation time 29331105 ps
CPU time 1.89 seconds
Started Mar 17 01:09:47 PM PDT 24
Finished Mar 17 01:09:49 PM PDT 24
Peak memory 214944 kb
Host smart-38fe6b46-7b17-4c6d-83b3-86f337d88b6c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425967242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
425967242
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3175880677
Short name T2192
Test name
Test status
Simulation time 40799322 ps
CPU time 0.69 seconds
Started Mar 17 01:43:52 PM PDT 24
Finished Mar 17 01:43:52 PM PDT 24
Peak memory 203244 kb
Host smart-9ff0f9be-5e28-4424-8570-4a7c99703bd4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175880677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
175880677
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3796731439
Short name T2123
Test name
Test status
Simulation time 14008530 ps
CPU time 0.75 seconds
Started Mar 17 01:09:46 PM PDT 24
Finished Mar 17 01:09:47 PM PDT 24
Peak memory 203288 kb
Host smart-11049e6d-d55a-490f-a013-64502f1c6a4a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796731439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
796731439
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.265454512
Short name T1959
Test name
Test status
Simulation time 110209764 ps
CPU time 3.89 seconds
Started Mar 17 01:43:51 PM PDT 24
Finished Mar 17 01:43:55 PM PDT 24
Peak memory 215156 kb
Host smart-9fbe2961-9345-495d-8e43-5805e4b8574c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265454512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sp
i_device_same_csr_outstanding.265454512
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.4069738576
Short name T2100
Test name
Test status
Simulation time 422182786 ps
CPU time 3.14 seconds
Started Mar 17 01:09:51 PM PDT 24
Finished Mar 17 01:09:54 PM PDT 24
Peak memory 215124 kb
Host smart-24263214-c3f0-4afe-ba04-c4650c4005ec
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069738576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.4069738576
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1515479960
Short name T84
Test name
Test status
Simulation time 60912209 ps
CPU time 4.56 seconds
Started Mar 17 01:09:45 PM PDT 24
Finished Mar 17 01:09:49 PM PDT 24
Peak memory 215176 kb
Host smart-0f6bee27-7f08-4b7a-805a-3873b1728a3e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515479960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
515479960
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.3887222148
Short name T2178
Test name
Test status
Simulation time 171481555 ps
CPU time 4.61 seconds
Started Mar 17 01:43:49 PM PDT 24
Finished Mar 17 01:43:54 PM PDT 24
Peak memory 215208 kb
Host smart-a07f5156-9d22-429b-9401-d59c875ed88d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887222148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.3
887222148
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3727552195
Short name T2009
Test name
Test status
Simulation time 258893289 ps
CPU time 7.42 seconds
Started Mar 17 01:09:44 PM PDT 24
Finished Mar 17 01:09:52 PM PDT 24
Peak memory 215312 kb
Host smart-7362c012-b43b-4eb8-9407-0f11e39468ab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727552195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3727552195
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4248848599
Short name T158
Test name
Test status
Simulation time 2847726358 ps
CPU time 22.04 seconds
Started Mar 17 01:43:48 PM PDT 24
Finished Mar 17 01:44:11 PM PDT 24
Peak memory 215164 kb
Host smart-758c5b4e-b040-42ab-8fd3-642a588cc48e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248848599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4248848599
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1867438343
Short name T105
Test name
Test status
Simulation time 218637306 ps
CPU time 1.65 seconds
Started Mar 17 01:43:51 PM PDT 24
Finished Mar 17 01:43:52 PM PDT 24
Peak memory 216108 kb
Host smart-6aa2618c-77aa-44bc-829c-bb50f5c57699
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867438343 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1867438343
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4247192163
Short name T2200
Test name
Test status
Simulation time 130525148 ps
CPU time 4 seconds
Started Mar 17 01:09:48 PM PDT 24
Finished Mar 17 01:09:53 PM PDT 24
Peak memory 217672 kb
Host smart-cc3340d7-6443-4c83-8028-ba2355d9b951
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247192163 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.4247192163
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2066539784
Short name T1929
Test name
Test status
Simulation time 41590243 ps
CPU time 2.5 seconds
Started Mar 17 01:43:49 PM PDT 24
Finished Mar 17 01:43:52 PM PDT 24
Peak memory 215112 kb
Host smart-bb0cc062-1bc2-4030-85c5-7ef93d93bce2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066539784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
066539784
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2656947118
Short name T2040
Test name
Test status
Simulation time 80203967 ps
CPU time 2.66 seconds
Started Mar 17 01:09:47 PM PDT 24
Finished Mar 17 01:09:51 PM PDT 24
Peak memory 215136 kb
Host smart-dcfd6a53-a15e-4688-a879-fcc274fa06b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656947118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
656947118
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.2463316170
Short name T2006
Test name
Test status
Simulation time 12945343 ps
CPU time 0.71 seconds
Started Mar 17 01:43:49 PM PDT 24
Finished Mar 17 01:43:50 PM PDT 24
Peak memory 203316 kb
Host smart-55c319f9-8a1a-421d-971e-2fbee7941483
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2463316170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2
463316170
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3041723655
Short name T2126
Test name
Test status
Simulation time 12329201 ps
CPU time 0.76 seconds
Started Mar 17 01:09:47 PM PDT 24
Finished Mar 17 01:09:48 PM PDT 24
Peak memory 203264 kb
Host smart-87ad0d36-6af5-44ad-aab7-f796a35f5bfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041723655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
041723655
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2177523634
Short name T2108
Test name
Test status
Simulation time 150438649 ps
CPU time 4.16 seconds
Started Mar 17 01:09:46 PM PDT 24
Finished Mar 17 01:09:50 PM PDT 24
Peak memory 214960 kb
Host smart-9ec4297f-d39a-4143-a6e5-5ed6e40e90e9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177523634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.2177523634
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3711544055
Short name T1991
Test name
Test status
Simulation time 108912066 ps
CPU time 3.14 seconds
Started Mar 17 01:43:52 PM PDT 24
Finished Mar 17 01:43:55 PM PDT 24
Peak memory 215012 kb
Host smart-22f78b70-e892-4471-998d-3bd68d7f58c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711544055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3711544055
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.270197071
Short name T2142
Test name
Test status
Simulation time 198089467 ps
CPU time 4.27 seconds
Started Mar 17 01:43:51 PM PDT 24
Finished Mar 17 01:43:55 PM PDT 24
Peak memory 215208 kb
Host smart-125e47d4-79f3-422b-a6c1-588737a99be3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270197071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.270197071
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3920675683
Short name T2186
Test name
Test status
Simulation time 56613968 ps
CPU time 4.63 seconds
Started Mar 17 01:09:50 PM PDT 24
Finished Mar 17 01:09:55 PM PDT 24
Peak memory 215004 kb
Host smart-f40f9f85-c90d-4196-974c-a79bd4e3b448
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920675683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
920675683
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1090000078
Short name T163
Test name
Test status
Simulation time 11856623128 ps
CPU time 25.87 seconds
Started Mar 17 01:43:55 PM PDT 24
Finished Mar 17 01:44:22 PM PDT 24
Peak memory 215196 kb
Host smart-0bf31f2b-13c7-46f0-8d49-7aa1a2231c4b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090000078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1090000078
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.1201920853
Short name T164
Test name
Test status
Simulation time 109737677 ps
CPU time 6.89 seconds
Started Mar 17 01:09:49 PM PDT 24
Finished Mar 17 01:09:56 PM PDT 24
Peak memory 215124 kb
Host smart-12e7b9ab-1518-4d3c-8d9e-593643452ab3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201920853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.1201920853
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1064052310
Short name T2136
Test name
Test status
Simulation time 46481071 ps
CPU time 1.77 seconds
Started Mar 17 01:09:54 PM PDT 24
Finished Mar 17 01:09:56 PM PDT 24
Peak memory 215048 kb
Host smart-9e0b3016-c802-4926-9e5f-43ab588a3d27
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064052310 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1064052310
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.693148325
Short name T2117
Test name
Test status
Simulation time 49019638 ps
CPU time 1.89 seconds
Started Mar 17 01:43:53 PM PDT 24
Finished Mar 17 01:43:55 PM PDT 24
Peak memory 215060 kb
Host smart-a535f3ee-b025-4ba8-b948-c906ad766647
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693148325 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.693148325
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.290768342
Short name T2081
Test name
Test status
Simulation time 41970863 ps
CPU time 1.42 seconds
Started Mar 17 01:09:57 PM PDT 24
Finished Mar 17 01:10:00 PM PDT 24
Peak memory 214964 kb
Host smart-3b76cb48-6e56-4067-9ffa-27cc63e83518
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290768342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.290768342
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3046889527
Short name T2195
Test name
Test status
Simulation time 231708930 ps
CPU time 2.97 seconds
Started Mar 17 01:43:51 PM PDT 24
Finished Mar 17 01:43:54 PM PDT 24
Peak memory 215092 kb
Host smart-f4f67af4-b4bb-4afa-817f-fd9a3b7d2829
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046889527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
046889527
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1823162464
Short name T2097
Test name
Test status
Simulation time 16059057 ps
CPU time 0.69 seconds
Started Mar 17 01:43:49 PM PDT 24
Finished Mar 17 01:43:50 PM PDT 24
Peak memory 203208 kb
Host smart-9741a3e7-f942-4d7d-aca9-fec4b7837c1a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823162464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
823162464
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.3879032698
Short name T2089
Test name
Test status
Simulation time 182741605 ps
CPU time 0.73 seconds
Started Mar 17 01:09:57 PM PDT 24
Finished Mar 17 01:09:59 PM PDT 24
Peak memory 203248 kb
Host smart-2ab417cc-8acb-46e2-9cec-52f691f6d9c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879032698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.3
879032698
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1524861167
Short name T1918
Test name
Test status
Simulation time 476069410 ps
CPU time 3.25 seconds
Started Mar 17 01:09:57 PM PDT 24
Finished Mar 17 01:10:01 PM PDT 24
Peak memory 215140 kb
Host smart-15aefd13-75aa-4029-9f40-63bcf2f71746
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524861167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.1524861167
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.557737216
Short name T2059
Test name
Test status
Simulation time 104418009 ps
CPU time 1.6 seconds
Started Mar 17 01:43:51 PM PDT 24
Finished Mar 17 01:43:53 PM PDT 24
Peak memory 215020 kb
Host smart-469ce796-1e6e-4af1-98bc-a6e52c4056cc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557737216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sp
i_device_same_csr_outstanding.557737216
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.1627613993
Short name T2004
Test name
Test status
Simulation time 65379981 ps
CPU time 5 seconds
Started Mar 17 01:43:50 PM PDT 24
Finished Mar 17 01:43:55 PM PDT 24
Peak memory 215344 kb
Host smart-696ea82e-e2db-432d-a712-445abd6f3802
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627613993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.1
627613993
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.4183411634
Short name T2179
Test name
Test status
Simulation time 37948945 ps
CPU time 2.69 seconds
Started Mar 17 01:09:49 PM PDT 24
Finished Mar 17 01:09:52 PM PDT 24
Peak memory 215252 kb
Host smart-18611ded-04c9-4af5-84cf-3026a75b9acb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183411634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.4
183411634
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2490280341
Short name T2028
Test name
Test status
Simulation time 2553177090 ps
CPU time 15.34 seconds
Started Mar 17 01:09:47 PM PDT 24
Finished Mar 17 01:10:03 PM PDT 24
Peak memory 216020 kb
Host smart-75380e65-6964-4d1e-a727-4d3e83b1a89b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490280341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2490280341
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1870034068
Short name T733
Test name
Test status
Simulation time 12795586 ps
CPU time 0.68 seconds
Started Mar 17 03:12:46 PM PDT 24
Finished Mar 17 03:12:48 PM PDT 24
Peak memory 204936 kb
Host smart-b069172a-46b0-4390-85fd-4b3dbaf054bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870034068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
870034068
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.208778174
Short name T420
Test name
Test status
Simulation time 7310615387 ps
CPU time 5.95 seconds
Started Mar 17 01:28:21 PM PDT 24
Finished Mar 17 01:28:27 PM PDT 24
Peak memory 233172 kb
Host smart-7802c141-bdac-4e91-b59e-4d9176c8af87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208778174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.208778174
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.938570070
Short name T496
Test name
Test status
Simulation time 168071786 ps
CPU time 2.82 seconds
Started Mar 17 03:12:37 PM PDT 24
Finished Mar 17 03:12:40 PM PDT 24
Peak memory 233324 kb
Host smart-c92cbe79-74a1-4fb2-828d-27c0e23bd4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938570070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.938570070
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3295187699
Short name T1534
Test name
Test status
Simulation time 50128309 ps
CPU time 0.75 seconds
Started Mar 17 01:28:18 PM PDT 24
Finished Mar 17 01:28:18 PM PDT 24
Peak memory 205896 kb
Host smart-c36863a1-587b-4bf2-aa4a-bc13c45bdfc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295187699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3295187699
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.4155652802
Short name T1738
Test name
Test status
Simulation time 21014061 ps
CPU time 0.75 seconds
Started Mar 17 03:12:23 PM PDT 24
Finished Mar 17 03:12:24 PM PDT 24
Peak memory 205176 kb
Host smart-3032f568-f596-4786-98c1-a10575527331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155652802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.4155652802
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1610911529
Short name T1470
Test name
Test status
Simulation time 113330015101 ps
CPU time 421.64 seconds
Started Mar 17 01:28:23 PM PDT 24
Finished Mar 17 01:35:25 PM PDT 24
Peak memory 265740 kb
Host smart-0a786389-1320-4b21-856d-79a2aee08b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1610911529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1610911529
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.3752307071
Short name T347
Test name
Test status
Simulation time 29768158020 ps
CPU time 148.27 seconds
Started Mar 17 03:12:42 PM PDT 24
Finished Mar 17 03:15:10 PM PDT 24
Peak memory 249032 kb
Host smart-f53451a1-d61e-4521-88b1-bdd8dcd60e38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752307071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.3752307071
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.272788007
Short name T1401
Test name
Test status
Simulation time 15513254552 ps
CPU time 106.14 seconds
Started Mar 17 03:12:40 PM PDT 24
Finished Mar 17 03:14:27 PM PDT 24
Peak memory 234860 kb
Host smart-530d029f-698c-47d2-a4f4-3c674c3fee9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272788007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.272788007
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3205910496
Short name T1880
Test name
Test status
Simulation time 49630065908 ps
CPU time 283.41 seconds
Started Mar 17 01:28:23 PM PDT 24
Finished Mar 17 01:33:07 PM PDT 24
Peak memory 269120 kb
Host smart-64719c5f-1b7f-4a56-aa46-1284b89d429f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205910496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3205910496
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3622722161
Short name T714
Test name
Test status
Simulation time 3461506483 ps
CPU time 49.75 seconds
Started Mar 17 03:12:41 PM PDT 24
Finished Mar 17 03:13:31 PM PDT 24
Peak memory 240528 kb
Host smart-3fec0161-3e07-441f-a1d6-b09d337d0197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622722161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3622722161
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.117115163
Short name T592
Test name
Test status
Simulation time 7301940779 ps
CPU time 37.43 seconds
Started Mar 17 01:28:22 PM PDT 24
Finished Mar 17 01:28:59 PM PDT 24
Peak memory 250052 kb
Host smart-2d73f404-de05-4c39-ad92-e175648921c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117115163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.117115163
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3349396875
Short name T1280
Test name
Test status
Simulation time 2350051721 ps
CPU time 11.22 seconds
Started Mar 17 03:12:36 PM PDT 24
Finished Mar 17 03:12:47 PM PDT 24
Peak memory 232532 kb
Host smart-4fe80f51-b500-45e8-88c3-749d13762c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349396875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3349396875
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1744699659
Short name T180
Test name
Test status
Simulation time 909931627 ps
CPU time 3.82 seconds
Started Mar 17 01:28:25 PM PDT 24
Finished Mar 17 01:28:29 PM PDT 24
Peak memory 232648 kb
Host smart-ddff954f-69d2-4f8f-bc2c-ea86f00233d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744699659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1744699659
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_intercept.4070165995
Short name T920
Test name
Test status
Simulation time 485143642 ps
CPU time 3.21 seconds
Started Mar 17 03:12:37 PM PDT 24
Finished Mar 17 03:12:40 PM PDT 24
Peak memory 233952 kb
Host smart-2612c578-6543-4977-909a-f3169c0904b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070165995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.4070165995
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.2403068817
Short name T948
Test name
Test status
Simulation time 8622358350 ps
CPU time 28.95 seconds
Started Mar 17 03:12:38 PM PDT 24
Finished Mar 17 03:13:07 PM PDT 24
Peak memory 239900 kb
Host smart-66e5dc79-e585-4017-af48-2fce729e348f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403068817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.2403068817
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.548910395
Short name T402
Test name
Test status
Simulation time 5207221680 ps
CPU time 18.75 seconds
Started Mar 17 01:28:22 PM PDT 24
Finished Mar 17 01:28:41 PM PDT 24
Peak memory 232240 kb
Host smart-db759bc0-9e09-45f7-a32c-2d2c1fa8690f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548910395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.548910395
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2394602175
Short name T1332
Test name
Test status
Simulation time 163622242 ps
CPU time 2.32 seconds
Started Mar 17 01:28:28 PM PDT 24
Finished Mar 17 01:28:31 PM PDT 24
Peak memory 223108 kb
Host smart-505646d3-0daf-43f3-a80a-7f817c545461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394602175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2394602175
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.3583094325
Short name T999
Test name
Test status
Simulation time 438799563 ps
CPU time 2.72 seconds
Started Mar 17 03:12:33 PM PDT 24
Finished Mar 17 03:12:36 PM PDT 24
Peak memory 217528 kb
Host smart-93ad6102-929a-4593-b349-bf8081efbde6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583094325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.3583094325
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.1070620189
Short name T1142
Test name
Test status
Simulation time 616583869 ps
CPU time 7.7 seconds
Started Mar 17 03:12:33 PM PDT 24
Finished Mar 17 03:12:41 PM PDT 24
Peak memory 226996 kb
Host smart-a1a847e8-a6b6-4c55-a8fb-ee8cbdb5c584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070620189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.1070620189
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.554552998
Short name T464
Test name
Test status
Simulation time 15376540161 ps
CPU time 10.82 seconds
Started Mar 17 01:28:21 PM PDT 24
Finished Mar 17 01:28:32 PM PDT 24
Peak memory 224100 kb
Host smart-212ed063-081f-40e4-906c-beb2f3e47c7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554552998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.554552998
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.1282022670
Short name T1504
Test name
Test status
Simulation time 57346685 ps
CPU time 0.73 seconds
Started Mar 17 03:12:28 PM PDT 24
Finished Mar 17 03:12:29 PM PDT 24
Peak memory 216000 kb
Host smart-3ea6fa86-706e-4329-9d14-459a83a77814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282022670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.1282022670
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.2691283371
Short name T700
Test name
Test status
Simulation time 18399832 ps
CPU time 0.75 seconds
Started Mar 17 01:28:17 PM PDT 24
Finished Mar 17 01:28:18 PM PDT 24
Peak memory 215748 kb
Host smart-a2de67b3-96b4-4e8a-898b-765f1db65eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691283371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2691283371
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1770705740
Short name T1321
Test name
Test status
Simulation time 2659738364 ps
CPU time 5.02 seconds
Started Mar 17 03:12:41 PM PDT 24
Finished Mar 17 03:12:46 PM PDT 24
Peak memory 222324 kb
Host smart-e8d633ea-4740-455a-8060-5f6db5ae50b5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1770705740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1770705740
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3261592385
Short name T820
Test name
Test status
Simulation time 232946776 ps
CPU time 3.75 seconds
Started Mar 17 01:28:24 PM PDT 24
Finished Mar 17 01:28:28 PM PDT 24
Peak memory 218248 kb
Host smart-ea185b35-ccbf-41d1-9a66-5916c4d721be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3261592385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3261592385
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.3966824561
Short name T66
Test name
Test status
Simulation time 358891049 ps
CPU time 1.18 seconds
Started Mar 17 01:28:21 PM PDT 24
Finished Mar 17 01:28:23 PM PDT 24
Peak memory 236572 kb
Host smart-b7d81953-6b72-4c3d-9485-920e92ce0f48
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966824561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3966824561
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.72115972
Short name T566
Test name
Test status
Simulation time 57570710 ps
CPU time 1.17 seconds
Started Mar 17 01:28:23 PM PDT 24
Finished Mar 17 01:28:25 PM PDT 24
Peak memory 206304 kb
Host smart-3eba6c38-7dd4-47d8-a98b-a25aa8a3a7f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72115972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_
all.72115972
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2505243236
Short name T1527
Test name
Test status
Simulation time 4358092419 ps
CPU time 43.79 seconds
Started Mar 17 01:28:17 PM PDT 24
Finished Mar 17 01:29:01 PM PDT 24
Peak memory 215944 kb
Host smart-47c73bae-8d3a-4f86-9b1c-ffc69406faa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505243236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2505243236
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.666456273
Short name T1175
Test name
Test status
Simulation time 4206516053 ps
CPU time 31.87 seconds
Started Mar 17 03:12:28 PM PDT 24
Finished Mar 17 03:13:00 PM PDT 24
Peak memory 220600 kb
Host smart-e9d418cb-86a4-408f-9f38-99fa3012a83e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666456273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.666456273
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1685494534
Short name T1348
Test name
Test status
Simulation time 4468807634 ps
CPU time 4.21 seconds
Started Mar 17 03:12:27 PM PDT 24
Finished Mar 17 03:12:31 PM PDT 24
Peak memory 216100 kb
Host smart-aaf037a3-76fd-44b6-a5da-5aae1a5b82a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685494534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1685494534
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2973734346
Short name T639
Test name
Test status
Simulation time 2227849461 ps
CPU time 4.42 seconds
Started Mar 17 01:28:16 PM PDT 24
Finished Mar 17 01:28:21 PM PDT 24
Peak memory 215900 kb
Host smart-f7d0c3d7-a3a9-4136-a03d-458a20847650
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973734346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2973734346
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2436813898
Short name T954
Test name
Test status
Simulation time 37964651 ps
CPU time 0.7 seconds
Started Mar 17 03:12:32 PM PDT 24
Finished Mar 17 03:12:32 PM PDT 24
Peak memory 205456 kb
Host smart-dfba5e62-341d-463d-899d-5a26019b87d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436813898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2436813898
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.3320420809
Short name T1310
Test name
Test status
Simulation time 272717313 ps
CPU time 1.75 seconds
Started Mar 17 01:28:22 PM PDT 24
Finished Mar 17 01:28:24 PM PDT 24
Peak memory 216044 kb
Host smart-97081d1f-af95-474e-b744-a182bd6616a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3320420809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.3320420809
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.1658493120
Short name T1538
Test name
Test status
Simulation time 87448068 ps
CPU time 1.01 seconds
Started Mar 17 03:12:32 PM PDT 24
Finished Mar 17 03:12:33 PM PDT 24
Peak memory 205424 kb
Host smart-cd14f7c6-abeb-46d8-97b0-9375743b86ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658493120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.1658493120
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.459542544
Short name T1158
Test name
Test status
Simulation time 60005206 ps
CPU time 0.91 seconds
Started Mar 17 01:28:22 PM PDT 24
Finished Mar 17 01:28:23 PM PDT 24
Peak memory 206232 kb
Host smart-9cb31009-f5c7-4143-983f-3f21b8f31b2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459542544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.459542544
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3071415861
Short name T1065
Test name
Test status
Simulation time 64348564223 ps
CPU time 22.03 seconds
Started Mar 17 01:28:24 PM PDT 24
Finished Mar 17 01:28:46 PM PDT 24
Peak memory 219176 kb
Host smart-94d46c00-fe1d-4a0f-befa-7601f9df68f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071415861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3071415861
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/0.spi_device_upload.309907850
Short name T882
Test name
Test status
Simulation time 5936574745 ps
CPU time 19.35 seconds
Started Mar 17 03:12:36 PM PDT 24
Finished Mar 17 03:12:56 PM PDT 24
Peak memory 234044 kb
Host smart-d8b92563-9f96-41f8-8cf6-588c6e8d8efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309907850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.309907850
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3977773452
Short name T306
Test name
Test status
Simulation time 13849498 ps
CPU time 0.72 seconds
Started Mar 17 03:12:59 PM PDT 24
Finished Mar 17 03:13:00 PM PDT 24
Peak memory 205004 kb
Host smart-4a12c58f-2fbe-41f9-8417-0b2ddda5fd79
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977773452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
977773452
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.761039633
Short name T791
Test name
Test status
Simulation time 23818666 ps
CPU time 0.74 seconds
Started Mar 17 01:28:33 PM PDT 24
Finished Mar 17 01:28:34 PM PDT 24
Peak memory 204860 kb
Host smart-96ef5513-0178-4eb0-865a-ebd60206d2d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761039633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.761039633
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1156413975
Short name T1640
Test name
Test status
Simulation time 3246659862 ps
CPU time 5.1 seconds
Started Mar 17 01:28:33 PM PDT 24
Finished Mar 17 01:28:38 PM PDT 24
Peak memory 219864 kb
Host smart-a3a59eb7-0c17-4e10-b5da-a9f3dd84e683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156413975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1156413975
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1979296112
Short name T530
Test name
Test status
Simulation time 119677242 ps
CPU time 2.6 seconds
Started Mar 17 03:12:56 PM PDT 24
Finished Mar 17 03:12:59 PM PDT 24
Peak memory 233176 kb
Host smart-ee34ffac-c1bb-4fb6-bebb-f289f45477a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979296112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1979296112
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3032960259
Short name T519
Test name
Test status
Simulation time 39948053 ps
CPU time 0.76 seconds
Started Mar 17 03:12:47 PM PDT 24
Finished Mar 17 03:12:48 PM PDT 24
Peak memory 205172 kb
Host smart-07074f54-5c37-40a2-b739-35fab9c51d0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032960259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3032960259
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3877784109
Short name T713
Test name
Test status
Simulation time 68984476 ps
CPU time 0.74 seconds
Started Mar 17 01:28:27 PM PDT 24
Finished Mar 17 01:28:28 PM PDT 24
Peak memory 204984 kb
Host smart-532878fe-8597-443b-abc8-4177d88db319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877784109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3877784109
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3326915638
Short name T715
Test name
Test status
Simulation time 21594437978 ps
CPU time 72.13 seconds
Started Mar 17 01:28:34 PM PDT 24
Finished Mar 17 01:29:46 PM PDT 24
Peak memory 250180 kb
Host smart-677be350-e14d-402b-ba08-40dd9c9a6f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326915638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3326915638
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.3996396485
Short name T1582
Test name
Test status
Simulation time 23002925334 ps
CPU time 121.96 seconds
Started Mar 17 03:12:54 PM PDT 24
Finished Mar 17 03:14:56 PM PDT 24
Peak memory 252276 kb
Host smart-0b32fe02-fc11-425b-bba3-b6583842460a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996396485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.3996396485
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.4226950333
Short name T455
Test name
Test status
Simulation time 2289238978 ps
CPU time 9.9 seconds
Started Mar 17 01:28:37 PM PDT 24
Finished Mar 17 01:28:47 PM PDT 24
Peak memory 220160 kb
Host smart-716c86f9-b4ed-48cb-b135-accca0de9afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226950333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.4226950333
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1396185057
Short name T1879
Test name
Test status
Simulation time 17957056472 ps
CPU time 70.37 seconds
Started Mar 17 03:12:59 PM PDT 24
Finished Mar 17 03:14:10 PM PDT 24
Peak memory 251716 kb
Host smart-514e9633-50d3-4092-9308-11c09dd90895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396185057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1396185057
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.1439325582
Short name T777
Test name
Test status
Simulation time 20804816760 ps
CPU time 90.76 seconds
Started Mar 17 01:28:35 PM PDT 24
Finished Mar 17 01:30:06 PM PDT 24
Peak memory 251452 kb
Host smart-ab8eb7b1-99b8-4655-9478-0e905df93eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439325582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.1439325582
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1583056578
Short name T1073
Test name
Test status
Simulation time 7249942875 ps
CPU time 27.77 seconds
Started Mar 17 01:28:35 PM PDT 24
Finished Mar 17 01:29:03 PM PDT 24
Peak memory 237056 kb
Host smart-36b4c4f0-101d-4631-8440-9f36beb7ff96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1583056578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1583056578
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.495875072
Short name T658
Test name
Test status
Simulation time 60284952179 ps
CPU time 77.74 seconds
Started Mar 17 03:12:53 PM PDT 24
Finished Mar 17 03:14:11 PM PDT 24
Peak memory 248912 kb
Host smart-2600f0bc-6ef0-4f3a-be8f-b1f507a73035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495875072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.495875072
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1164990559
Short name T1192
Test name
Test status
Simulation time 358127973 ps
CPU time 2.99 seconds
Started Mar 17 01:28:30 PM PDT 24
Finished Mar 17 01:28:33 PM PDT 24
Peak memory 224052 kb
Host smart-9d0c4b62-9306-4dec-b9d7-18eb63b57b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164990559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1164990559
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_intercept.2955515523
Short name T178
Test name
Test status
Simulation time 4784079030 ps
CPU time 16.52 seconds
Started Mar 17 03:12:50 PM PDT 24
Finished Mar 17 03:13:07 PM PDT 24
Peak memory 222016 kb
Host smart-ddb49dcc-e2d6-4ee3-b3d0-eed03c40e6d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2955515523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2955515523
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3166433184
Short name T1309
Test name
Test status
Simulation time 163147135711 ps
CPU time 42.69 seconds
Started Mar 17 01:28:26 PM PDT 24
Finished Mar 17 01:29:09 PM PDT 24
Peak memory 232256 kb
Host smart-5d425458-a9c1-4e12-b5d8-7f3ccc3ed282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166433184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3166433184
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.946084446
Short name T1170
Test name
Test status
Simulation time 6391944618 ps
CPU time 7.72 seconds
Started Mar 17 03:12:53 PM PDT 24
Finished Mar 17 03:13:01 PM PDT 24
Peak memory 222496 kb
Host smart-70d996b1-e5d1-402e-8bf4-55e4dc7c1c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=946084446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.946084446
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_mem_parity.230117232
Short name T1429
Test name
Test status
Simulation time 98844632 ps
CPU time 1.03 seconds
Started Mar 17 01:28:29 PM PDT 24
Finished Mar 17 01:28:30 PM PDT 24
Peak memory 217744 kb
Host smart-3faa413e-0756-43e4-bf5b-72c9c58facb3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230117232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
1.spi_device_mem_parity.230117232
Directory /workspace/1.spi_device_mem_parity/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.1065089629
Short name T444
Test name
Test status
Simulation time 11071178796 ps
CPU time 31.35 seconds
Started Mar 17 01:28:29 PM PDT 24
Finished Mar 17 01:29:00 PM PDT 24
Peak memory 247424 kb
Host smart-b00baddf-53a6-4fa8-a0a6-e9977b3b388e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1065089629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.1065089629
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.4173636891
Short name T1446
Test name
Test status
Simulation time 6660876218 ps
CPU time 8.57 seconds
Started Mar 17 03:12:49 PM PDT 24
Finished Mar 17 03:12:58 PM PDT 24
Peak memory 233656 kb
Host smart-a356007d-f193-4ee4-8656-1f4e9236c7e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173636891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.4173636891
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1958632642
Short name T652
Test name
Test status
Simulation time 13176443992 ps
CPU time 20.59 seconds
Started Mar 17 03:12:50 PM PDT 24
Finished Mar 17 03:13:11 PM PDT 24
Peak memory 235004 kb
Host smart-4db6c789-8765-4a3c-b803-a9c65333997c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958632642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1958632642
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.63802956
Short name T236
Test name
Test status
Simulation time 34526329025 ps
CPU time 24.07 seconds
Started Mar 17 01:28:31 PM PDT 24
Finished Mar 17 01:28:56 PM PDT 24
Peak memory 233296 kb
Host smart-7a3e683c-1add-419e-a96d-b1535566a13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63802956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.63802956
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.1904124243
Short name T1903
Test name
Test status
Simulation time 31601586 ps
CPU time 0.7 seconds
Started Mar 17 01:28:30 PM PDT 24
Finished Mar 17 01:28:30 PM PDT 24
Peak memory 215772 kb
Host smart-acb73fa0-c8ea-41e2-bc2e-dc57e743063f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904124243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.1904124243
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_ram_cfg.290650479
Short name T1734
Test name
Test status
Simulation time 22619328 ps
CPU time 0.79 seconds
Started Mar 17 03:12:45 PM PDT 24
Finished Mar 17 03:12:46 PM PDT 24
Peak memory 216056 kb
Host smart-3fb11493-a9b6-4cea-b32f-2d50abe8ff2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290650479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_ram_cfg.290650479
Directory /workspace/1.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.2559234371
Short name T1414
Test name
Test status
Simulation time 1608341701 ps
CPU time 3.29 seconds
Started Mar 17 03:12:56 PM PDT 24
Finished Mar 17 03:12:59 PM PDT 24
Peak memory 218640 kb
Host smart-51f78908-2e58-4406-873a-b609274c18f3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2559234371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.2559234371
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.967528378
Short name T1757
Test name
Test status
Simulation time 3355276619 ps
CPU time 7.12 seconds
Started Mar 17 01:28:34 PM PDT 24
Finished Mar 17 01:28:41 PM PDT 24
Peak memory 218312 kb
Host smart-a017801c-1280-4c16-9172-db0887b60bb1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=967528378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.967528378
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2121681164
Short name T57
Test name
Test status
Simulation time 55152900 ps
CPU time 1.12 seconds
Started Mar 17 01:28:33 PM PDT 24
Finished Mar 17 01:28:34 PM PDT 24
Peak memory 234660 kb
Host smart-a202e88b-be12-4ad3-a273-a28578fbe7ea
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121681164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2121681164
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3228295439
Short name T61
Test name
Test status
Simulation time 40904325 ps
CPU time 1 seconds
Started Mar 17 03:12:59 PM PDT 24
Finished Mar 17 03:13:01 PM PDT 24
Peak memory 234852 kb
Host smart-0e992f14-8e54-438a-b2bc-548241d4162f
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228295439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3228295439
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.163449774
Short name T377
Test name
Test status
Simulation time 46635064024 ps
CPU time 323.74 seconds
Started Mar 17 01:28:34 PM PDT 24
Finished Mar 17 01:33:58 PM PDT 24
Peak memory 256960 kb
Host smart-f6c14468-338f-4b23-8bbf-a1e52f1d249b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163449774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.163449774
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.3362948755
Short name T1006
Test name
Test status
Simulation time 139539354326 ps
CPU time 815.55 seconds
Started Mar 17 03:13:00 PM PDT 24
Finished Mar 17 03:26:37 PM PDT 24
Peak memory 283840 kb
Host smart-ec048f9d-0f5e-4785-adbd-32f51e0bb5c5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3362948755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.3362948755
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.2035827408
Short name T1846
Test name
Test status
Simulation time 79891234526 ps
CPU time 51.46 seconds
Started Mar 17 01:28:29 PM PDT 24
Finished Mar 17 01:29:20 PM PDT 24
Peak memory 215908 kb
Host smart-bcbb0a32-e611-458e-bfaa-e2a3b8795f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035827408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2035827408
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2404241815
Short name T1070
Test name
Test status
Simulation time 176888560 ps
CPU time 1.07 seconds
Started Mar 17 03:12:46 PM PDT 24
Finished Mar 17 03:12:48 PM PDT 24
Peak memory 205472 kb
Host smart-0b0860e1-4935-40a9-a881-513663cfeebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404241815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2404241815
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.3091579727
Short name T1277
Test name
Test status
Simulation time 13449980934 ps
CPU time 21.14 seconds
Started Mar 17 01:28:29 PM PDT 24
Finished Mar 17 01:28:50 PM PDT 24
Peak memory 215804 kb
Host smart-d0c8cb9b-36a2-4e47-80ed-35b2728d4659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091579727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.3091579727
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2438850671
Short name T1769
Test name
Test status
Simulation time 169641123 ps
CPU time 1.92 seconds
Started Mar 17 03:12:50 PM PDT 24
Finished Mar 17 03:12:52 PM PDT 24
Peak memory 216088 kb
Host smart-accc646e-bd30-4e73-b15f-4e95b87f08e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438850671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2438850671
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.2657693014
Short name T1851
Test name
Test status
Simulation time 113124475 ps
CPU time 4.74 seconds
Started Mar 17 01:28:29 PM PDT 24
Finished Mar 17 01:28:34 PM PDT 24
Peak memory 215920 kb
Host smart-d7cd03e8-3841-4eca-8942-d8700c3a0ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657693014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2657693014
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3261731729
Short name T665
Test name
Test status
Simulation time 175850692 ps
CPU time 0.97 seconds
Started Mar 17 01:28:28 PM PDT 24
Finished Mar 17 01:28:29 PM PDT 24
Peak memory 206148 kb
Host smart-df7f2ddd-01c3-48cc-9f87-811864972eb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261731729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3261731729
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3907029281
Short name T1054
Test name
Test status
Simulation time 114857713 ps
CPU time 0.81 seconds
Started Mar 17 03:12:51 PM PDT 24
Finished Mar 17 03:12:51 PM PDT 24
Peak memory 205388 kb
Host smart-a8e3ce8f-e387-4d98-828e-61c97f8e4d78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3907029281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3907029281
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.3484493011
Short name T1477
Test name
Test status
Simulation time 1687325590 ps
CPU time 10.87 seconds
Started Mar 17 01:28:31 PM PDT 24
Finished Mar 17 01:28:42 PM PDT 24
Peak memory 228708 kb
Host smart-c7389e0a-7a8a-4024-8da7-c5cc4756e0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484493011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.3484493011
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_upload.859935469
Short name T220
Test name
Test status
Simulation time 7052661350 ps
CPU time 21.04 seconds
Started Mar 17 03:12:57 PM PDT 24
Finished Mar 17 03:13:18 PM PDT 24
Peak memory 227080 kb
Host smart-3c2334b9-5e98-4a48-8c2e-47f146f28556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859935469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.859935469
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1242726180
Short name T1802
Test name
Test status
Simulation time 13132364 ps
CPU time 0.75 seconds
Started Mar 17 01:29:41 PM PDT 24
Finished Mar 17 01:29:42 PM PDT 24
Peak memory 204848 kb
Host smart-4e2d8578-9bb3-440d-9055-1f0398556820
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242726180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1242726180
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.2163069584
Short name T50
Test name
Test status
Simulation time 42749927 ps
CPU time 0.71 seconds
Started Mar 17 03:14:22 PM PDT 24
Finished Mar 17 03:14:22 PM PDT 24
Peak memory 204420 kb
Host smart-8ce38dd4-5b23-4271-8965-26c267c11f16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163069584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
2163069584
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1838646342
Short name T632
Test name
Test status
Simulation time 21032794927 ps
CPU time 15.64 seconds
Started Mar 17 01:29:39 PM PDT 24
Finished Mar 17 01:29:55 PM PDT 24
Peak memory 234064 kb
Host smart-8f3ebd25-d529-401e-8326-48f629b6ed87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838646342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1838646342
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3057811774
Short name T773
Test name
Test status
Simulation time 87920418 ps
CPU time 3.05 seconds
Started Mar 17 03:14:14 PM PDT 24
Finished Mar 17 03:14:17 PM PDT 24
Peak memory 219688 kb
Host smart-5a998943-c4df-4400-853f-6022bf5b3510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057811774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3057811774
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3372063933
Short name T1744
Test name
Test status
Simulation time 19055041 ps
CPU time 0.9 seconds
Started Mar 17 01:29:32 PM PDT 24
Finished Mar 17 01:29:33 PM PDT 24
Peak memory 205972 kb
Host smart-2e7ea228-fbc9-4e07-8246-368a185831a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372063933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3372063933
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.94847266
Short name T300
Test name
Test status
Simulation time 19071627 ps
CPU time 0.76 seconds
Started Mar 17 03:14:09 PM PDT 24
Finished Mar 17 03:14:10 PM PDT 24
Peak memory 205492 kb
Host smart-61a98d70-64b5-47eb-95d3-f5201a0797d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94847266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.94847266
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.1596977597
Short name T1593
Test name
Test status
Simulation time 102098969363 ps
CPU time 235.04 seconds
Started Mar 17 03:14:14 PM PDT 24
Finished Mar 17 03:18:10 PM PDT 24
Peak memory 248104 kb
Host smart-1f0d8bf9-329c-4656-b72d-88081344cd9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596977597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.1596977597
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2085907542
Short name T169
Test name
Test status
Simulation time 54917518451 ps
CPU time 119.55 seconds
Started Mar 17 01:29:40 PM PDT 24
Finished Mar 17 01:31:40 PM PDT 24
Peak memory 240180 kb
Host smart-e7d5d643-6c0d-4ec3-9fae-f1e95bb723af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085907542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2085907542
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3931473939
Short name T626
Test name
Test status
Simulation time 67937825737 ps
CPU time 204.97 seconds
Started Mar 17 03:14:14 PM PDT 24
Finished Mar 17 03:17:39 PM PDT 24
Peak memory 255320 kb
Host smart-9e8225b3-b29c-487a-8911-ccbc21848a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931473939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3931473939
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.1767593321
Short name T15
Test name
Test status
Simulation time 40715904125 ps
CPU time 95.27 seconds
Started Mar 17 01:29:39 PM PDT 24
Finished Mar 17 01:31:15 PM PDT 24
Peak memory 262224 kb
Host smart-898be67e-39b8-457f-9db1-7eb08c08a974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767593321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.1767593321
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3503632992
Short name T16
Test name
Test status
Simulation time 8056458812 ps
CPU time 84.69 seconds
Started Mar 17 03:14:21 PM PDT 24
Finished Mar 17 03:15:46 PM PDT 24
Peak memory 252280 kb
Host smart-ae85f8c1-4d61-4c4b-991b-a0d2b1533bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503632992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3503632992
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1605940773
Short name T1869
Test name
Test status
Simulation time 787293929 ps
CPU time 15.42 seconds
Started Mar 17 01:29:39 PM PDT 24
Finished Mar 17 01:29:55 PM PDT 24
Peak memory 238244 kb
Host smart-ef49e1c7-4be9-484b-a221-710f93031fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605940773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1605940773
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3080613176
Short name T1608
Test name
Test status
Simulation time 797234834 ps
CPU time 19.27 seconds
Started Mar 17 03:14:14 PM PDT 24
Finished Mar 17 03:14:35 PM PDT 24
Peak memory 233780 kb
Host smart-c0f86c1b-d3c1-41f0-b0ff-b366132a9385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080613176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3080613176
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3606947660
Short name T1503
Test name
Test status
Simulation time 2463403772 ps
CPU time 9.38 seconds
Started Mar 17 03:14:13 PM PDT 24
Finished Mar 17 03:14:23 PM PDT 24
Peak memory 233544 kb
Host smart-6eccd23e-7b76-4af3-a964-8d4f1bfba408
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606947660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3606947660
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_intercept.624662620
Short name T375
Test name
Test status
Simulation time 227640308 ps
CPU time 4.05 seconds
Started Mar 17 01:29:42 PM PDT 24
Finished Mar 17 01:29:47 PM PDT 24
Peak memory 223984 kb
Host smart-a14f9c58-9459-4990-9fd8-756ac4bcc392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=624662620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.624662620
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1977649664
Short name T795
Test name
Test status
Simulation time 466243330 ps
CPU time 6.73 seconds
Started Mar 17 03:14:13 PM PDT 24
Finished Mar 17 03:14:19 PM PDT 24
Peak memory 238960 kb
Host smart-aee5b4c1-bc53-47ad-b9c6-5a34d3e14863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977649664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1977649664
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.573199849
Short name T1770
Test name
Test status
Simulation time 3271824838 ps
CPU time 13.95 seconds
Started Mar 17 01:29:39 PM PDT 24
Finished Mar 17 01:29:54 PM PDT 24
Peak memory 228908 kb
Host smart-7beae74a-7a81-49e9-a293-8b5be14bb068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573199849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.573199849
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_mem_parity.1591351808
Short name T1157
Test name
Test status
Simulation time 41327124 ps
CPU time 1.07 seconds
Started Mar 17 01:29:34 PM PDT 24
Finished Mar 17 01:29:35 PM PDT 24
Peak memory 216520 kb
Host smart-bf8a7d5e-3413-4b61-8308-1e1c6d871da7
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591351808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 10.spi_device_mem_parity.1591351808
Directory /workspace/10.spi_device_mem_parity/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.18364476
Short name T526
Test name
Test status
Simulation time 2592791521 ps
CPU time 6.45 seconds
Started Mar 17 03:14:17 PM PDT 24
Finished Mar 17 03:14:24 PM PDT 24
Peak memory 235100 kb
Host smart-9f53bb00-5bcb-478f-8033-d3f07391c68c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18364476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.18364476
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.436555553
Short name T555
Test name
Test status
Simulation time 311176060 ps
CPU time 4.63 seconds
Started Mar 17 01:29:41 PM PDT 24
Finished Mar 17 01:29:45 PM PDT 24
Peak memory 233208 kb
Host smart-fc68c645-8946-47ef-9e8b-ccb073aa8327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436555553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap
.436555553
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3354591322
Short name T593
Test name
Test status
Simulation time 7678448225 ps
CPU time 25.41 seconds
Started Mar 17 03:14:14 PM PDT 24
Finished Mar 17 03:14:40 PM PDT 24
Peak memory 233272 kb
Host smart-c255e0ec-66fc-43a1-9034-b0eb96bbae9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354591322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3354591322
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.3981583767
Short name T726
Test name
Test status
Simulation time 79275528 ps
CPU time 2.48 seconds
Started Mar 17 01:29:36 PM PDT 24
Finished Mar 17 01:29:38 PM PDT 24
Peak memory 232272 kb
Host smart-c9312797-37a0-47ba-a12c-45483d9196a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981583767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.3981583767
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_ram_cfg.3315943423
Short name T1119
Test name
Test status
Simulation time 18019462 ps
CPU time 0.73 seconds
Started Mar 17 01:29:32 PM PDT 24
Finished Mar 17 01:29:33 PM PDT 24
Peak memory 215760 kb
Host smart-9c01c0ca-de15-48cc-9f52-e6087350968a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315943423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_ram_cfg.3315943423
Directory /workspace/10.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1110111782
Short name T725
Test name
Test status
Simulation time 1640544976 ps
CPU time 4.42 seconds
Started Mar 17 01:29:40 PM PDT 24
Finished Mar 17 01:29:45 PM PDT 24
Peak memory 218336 kb
Host smart-e6279cfd-7122-494f-bbc0-6623563ba8a3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1110111782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1110111782
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.2626787159
Short name T745
Test name
Test status
Simulation time 724995199 ps
CPU time 3.56 seconds
Started Mar 17 03:14:15 PM PDT 24
Finished Mar 17 03:14:19 PM PDT 24
Peak memory 219864 kb
Host smart-6744687b-e422-4485-ab1a-4c52d3d0eecf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2626787159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.2626787159
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1902722752
Short name T1781
Test name
Test status
Simulation time 7508476974 ps
CPU time 76.35 seconds
Started Mar 17 03:14:22 PM PDT 24
Finished Mar 17 03:15:38 PM PDT 24
Peak memory 254716 kb
Host smart-857a7202-984b-46cb-b134-5f41f1b8bfc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902722752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1902722752
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.568254925
Short name T141
Test name
Test status
Simulation time 43105107873 ps
CPU time 149.67 seconds
Started Mar 17 01:29:41 PM PDT 24
Finished Mar 17 01:32:11 PM PDT 24
Peak memory 234612 kb
Host smart-f7e57add-01b0-4ec9-9665-9c2fe5890b78
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568254925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stres
s_all.568254925
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.158966293
Short name T1480
Test name
Test status
Simulation time 1625189377 ps
CPU time 21.06 seconds
Started Mar 17 03:14:09 PM PDT 24
Finished Mar 17 03:14:31 PM PDT 24
Peak memory 216340 kb
Host smart-e6cc3752-e555-4da5-8009-4bb18f0d3ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158966293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.158966293
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.4284380741
Short name T823
Test name
Test status
Simulation time 35709202089 ps
CPU time 54.55 seconds
Started Mar 17 01:29:34 PM PDT 24
Finished Mar 17 01:30:29 PM PDT 24
Peak memory 215916 kb
Host smart-71af2bbf-4e65-4784-a2f1-d70661613a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284380741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.4284380741
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1754988605
Short name T863
Test name
Test status
Simulation time 32308010503 ps
CPU time 16.31 seconds
Started Mar 17 03:14:10 PM PDT 24
Finished Mar 17 03:14:26 PM PDT 24
Peak memory 217136 kb
Host smart-393f96a4-142d-4adf-b509-2a44d31189bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754988605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1754988605
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2673649761
Short name T331
Test name
Test status
Simulation time 21405118007 ps
CPU time 17 seconds
Started Mar 17 01:29:33 PM PDT 24
Finished Mar 17 01:29:50 PM PDT 24
Peak memory 215976 kb
Host smart-a4ae7dfb-b643-46a6-b0ef-a80ba1dd54c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673649761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2673649761
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.2767917049
Short name T326
Test name
Test status
Simulation time 384143943 ps
CPU time 1.45 seconds
Started Mar 17 03:14:13 PM PDT 24
Finished Mar 17 03:14:15 PM PDT 24
Peak memory 216076 kb
Host smart-7ca35d8b-2d84-458a-985f-fadfe42cc57c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767917049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2767917049
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.303229804
Short name T990
Test name
Test status
Simulation time 57356545 ps
CPU time 1.13 seconds
Started Mar 17 01:29:33 PM PDT 24
Finished Mar 17 01:29:34 PM PDT 24
Peak memory 207468 kb
Host smart-99ea18ee-a18d-4a8c-81ae-840f4ea14b62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303229804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.303229804
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1010114013
Short name T732
Test name
Test status
Simulation time 52086836 ps
CPU time 0.86 seconds
Started Mar 17 03:14:16 PM PDT 24
Finished Mar 17 03:14:17 PM PDT 24
Peak memory 205384 kb
Host smart-87c53a5c-9e24-45db-8446-06c1e36759cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010114013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1010114013
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.866192797
Short name T1641
Test name
Test status
Simulation time 108819397 ps
CPU time 0.77 seconds
Started Mar 17 01:29:32 PM PDT 24
Finished Mar 17 01:29:33 PM PDT 24
Peak memory 205228 kb
Host smart-49971a6f-e6d8-422a-b1c0-d625981fe618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866192797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.866192797
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.3642910929
Short name T1087
Test name
Test status
Simulation time 1390085073 ps
CPU time 6.8 seconds
Started Mar 17 03:14:14 PM PDT 24
Finished Mar 17 03:14:21 PM PDT 24
Peak memory 235216 kb
Host smart-27f16f47-3236-4562-9f17-f553864f95e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642910929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3642910929
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_upload.4019277722
Short name T1659
Test name
Test status
Simulation time 10143218996 ps
CPU time 18.57 seconds
Started Mar 17 01:29:40 PM PDT 24
Finished Mar 17 01:29:59 PM PDT 24
Peak memory 236692 kb
Host smart-51fb2a9a-a095-4dc4-a99f-d128d4417de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019277722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.4019277722
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.10846690
Short name T691
Test name
Test status
Simulation time 13106041 ps
CPU time 0.74 seconds
Started Mar 17 01:29:39 PM PDT 24
Finished Mar 17 01:29:41 PM PDT 24
Peak memory 205204 kb
Host smart-1364b24e-46e4-4ac3-b832-e6c9db6365ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10846690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.10846690
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3834337909
Short name T789
Test name
Test status
Simulation time 101504509 ps
CPU time 0.72 seconds
Started Mar 17 03:14:22 PM PDT 24
Finished Mar 17 03:14:23 PM PDT 24
Peak memory 205312 kb
Host smart-7cb90acb-470e-4da3-9a95-5a80fbe13c72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834337909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3834337909
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.2225128525
Short name T631
Test name
Test status
Simulation time 107438777 ps
CPU time 2.54 seconds
Started Mar 17 01:29:41 PM PDT 24
Finished Mar 17 01:29:44 PM PDT 24
Peak memory 233312 kb
Host smart-fdfb30e3-aa65-4b82-8fda-7329bb4529cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225128525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.2225128525
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3516940215
Short name T1281
Test name
Test status
Simulation time 241445502 ps
CPU time 4.44 seconds
Started Mar 17 03:14:23 PM PDT 24
Finished Mar 17 03:14:27 PM PDT 24
Peak memory 239732 kb
Host smart-b6fa6e6a-0641-4c8f-85ae-dc7c6c9e6380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516940215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3516940215
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3391280596
Short name T1317
Test name
Test status
Simulation time 34928284 ps
CPU time 0.77 seconds
Started Mar 17 03:14:18 PM PDT 24
Finished Mar 17 03:14:19 PM PDT 24
Peak memory 205112 kb
Host smart-cc70d8fa-9b48-4566-add3-edc37edd46bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391280596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3391280596
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.508705971
Short name T1362
Test name
Test status
Simulation time 45962978 ps
CPU time 0.77 seconds
Started Mar 17 01:29:40 PM PDT 24
Finished Mar 17 01:29:41 PM PDT 24
Peak memory 206036 kb
Host smart-365cd680-1001-4b58-9780-c4729fc8daed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508705971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.508705971
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.1322826803
Short name T240
Test name
Test status
Simulation time 17553277176 ps
CPU time 102.64 seconds
Started Mar 17 01:29:40 PM PDT 24
Finished Mar 17 01:31:23 PM PDT 24
Peak memory 248692 kb
Host smart-0ca6b1cd-e1dd-4730-98ff-b993662ca4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322826803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1322826803
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.512430127
Short name T1254
Test name
Test status
Simulation time 60077702249 ps
CPU time 82.58 seconds
Started Mar 17 03:14:21 PM PDT 24
Finished Mar 17 03:15:44 PM PDT 24
Peak memory 265128 kb
Host smart-009d3ee4-8332-43ac-b5bc-a0f2a7f0b088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512430127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.512430127
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3083167034
Short name T1198
Test name
Test status
Simulation time 387372867197 ps
CPU time 555.15 seconds
Started Mar 17 03:14:18 PM PDT 24
Finished Mar 17 03:23:34 PM PDT 24
Peak memory 271072 kb
Host smart-15711dd2-0887-442f-ac2e-1e8bfea41ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083167034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3083167034
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.912507288
Short name T1323
Test name
Test status
Simulation time 5880906028 ps
CPU time 94.62 seconds
Started Mar 17 01:29:40 PM PDT 24
Finished Mar 17 01:31:15 PM PDT 24
Peak memory 264708 kb
Host smart-46b13e41-0032-460b-83e5-0a4678ab62d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912507288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.912507288
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.139731410
Short name T1137
Test name
Test status
Simulation time 56461117832 ps
CPU time 416.75 seconds
Started Mar 17 01:29:40 PM PDT 24
Finished Mar 17 01:36:37 PM PDT 24
Peak memory 263136 kb
Host smart-3a181494-67bc-4e34-90ff-db66155d38f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139731410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.139731410
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.2630398550
Short name T1600
Test name
Test status
Simulation time 8385502750 ps
CPU time 105.3 seconds
Started Mar 17 03:14:24 PM PDT 24
Finished Mar 17 03:16:09 PM PDT 24
Peak memory 254744 kb
Host smart-8b094edd-0dae-4604-8976-d8570f18e745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630398550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.2630398550
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.1926465017
Short name T1755
Test name
Test status
Simulation time 623958461 ps
CPU time 8.68 seconds
Started Mar 17 03:14:21 PM PDT 24
Finished Mar 17 03:14:30 PM PDT 24
Peak memory 236244 kb
Host smart-f6a2b3c2-9552-46de-adf1-89f0d05dd471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926465017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1926465017
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3626543158
Short name T1117
Test name
Test status
Simulation time 2740337960 ps
CPU time 5.28 seconds
Started Mar 17 01:29:39 PM PDT 24
Finished Mar 17 01:29:44 PM PDT 24
Peak memory 218408 kb
Host smart-29d83d96-4cdd-4862-ac46-dd6bd453472f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626543158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3626543158
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1860593734
Short name T1028
Test name
Test status
Simulation time 395779644 ps
CPU time 5.12 seconds
Started Mar 17 03:14:17 PM PDT 24
Finished Mar 17 03:14:23 PM PDT 24
Peak memory 218500 kb
Host smart-c56b0738-30b3-4dab-9219-3bc971b3efd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860593734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1860593734
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_intercept.1982126080
Short name T1557
Test name
Test status
Simulation time 16282160773 ps
CPU time 13.47 seconds
Started Mar 17 01:29:39 PM PDT 24
Finished Mar 17 01:29:52 PM PDT 24
Peak memory 218264 kb
Host smart-26f29ad0-5d0d-4d96-9c80-b3a7792c8f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982126080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1982126080
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.1669144880
Short name T1136
Test name
Test status
Simulation time 34700943 ps
CPU time 2.27 seconds
Started Mar 17 01:29:38 PM PDT 24
Finished Mar 17 01:29:40 PM PDT 24
Peak memory 223900 kb
Host smart-14b1f394-7f1f-4dc1-a206-a08cc364c526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669144880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.1669144880
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.2040891739
Short name T224
Test name
Test status
Simulation time 19710914101 ps
CPU time 63.71 seconds
Started Mar 17 03:14:22 PM PDT 24
Finished Mar 17 03:15:25 PM PDT 24
Peak memory 239256 kb
Host smart-ab98ba97-1e03-4e8c-ac95-3b036c09eb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040891739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.2040891739
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_mem_parity.891024244
Short name T20
Test name
Test status
Simulation time 124863421 ps
CPU time 1.12 seconds
Started Mar 17 01:29:39 PM PDT 24
Finished Mar 17 01:29:41 PM PDT 24
Peak memory 216484 kb
Host smart-9957afb9-dc05-4bc4-aee1-515dc6665a74
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891024244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
11.spi_device_mem_parity.891024244
Directory /workspace/11.spi_device_mem_parity/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1307796424
Short name T1482
Test name
Test status
Simulation time 21048322603 ps
CPU time 22.19 seconds
Started Mar 17 03:14:19 PM PDT 24
Finished Mar 17 03:14:42 PM PDT 24
Peak memory 239720 kb
Host smart-fe39da3e-8fe1-46ff-9495-2bef8984b05c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307796424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1307796424
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.2486612877
Short name T173
Test name
Test status
Simulation time 46590098792 ps
CPU time 20.3 seconds
Started Mar 17 01:29:39 PM PDT 24
Finished Mar 17 01:30:01 PM PDT 24
Peak memory 224124 kb
Host smart-c0a3723a-a7fb-45a9-a044-e3f784c41219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486612877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.2486612877
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.174053447
Short name T520
Test name
Test status
Simulation time 1494889321 ps
CPU time 7.12 seconds
Started Mar 17 03:14:20 PM PDT 24
Finished Mar 17 03:14:27 PM PDT 24
Peak memory 224296 kb
Host smart-5f19cae2-dd81-4cf0-ac19-29d19822a2fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174053447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.174053447
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.528996812
Short name T484
Test name
Test status
Simulation time 63423492669 ps
CPU time 25.08 seconds
Started Mar 17 01:29:42 PM PDT 24
Finished Mar 17 01:30:07 PM PDT 24
Peak memory 217468 kb
Host smart-003a649a-39bd-495c-b08d-b3024728adc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528996812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.528996812
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.4000202471
Short name T599
Test name
Test status
Simulation time 19315033 ps
CPU time 0.75 seconds
Started Mar 17 01:29:41 PM PDT 24
Finished Mar 17 01:29:42 PM PDT 24
Peak memory 215784 kb
Host smart-b5d90fd8-f915-47d5-b2a3-f8698282b846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000202471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.4000202471
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_ram_cfg.855970153
Short name T534
Test name
Test status
Simulation time 19479638 ps
CPU time 0.78 seconds
Started Mar 17 03:14:17 PM PDT 24
Finished Mar 17 03:14:18 PM PDT 24
Peak memory 216056 kb
Host smart-f360dc4a-4c0f-43a3-be8f-b5e9f8a9594b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855970153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_ram_cfg.855970153
Directory /workspace/11.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.539992037
Short name T1596
Test name
Test status
Simulation time 120550036 ps
CPU time 3.57 seconds
Started Mar 17 03:14:17 PM PDT 24
Finished Mar 17 03:14:21 PM PDT 24
Peak memory 221992 kb
Host smart-78ce11da-faac-4e13-bff4-fca8b0eb2593
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=539992037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dire
ct.539992037
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2735890146
Short name T1758
Test name
Test status
Simulation time 1347751022 ps
CPU time 19.85 seconds
Started Mar 17 03:14:18 PM PDT 24
Finished Mar 17 03:14:38 PM PDT 24
Peak memory 216080 kb
Host smart-9aea615a-bbac-40d8-83d7-0caced1e8194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735890146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2735890146
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2979565347
Short name T1074
Test name
Test status
Simulation time 7370931822 ps
CPU time 38.68 seconds
Started Mar 17 01:29:38 PM PDT 24
Finished Mar 17 01:30:17 PM PDT 24
Peak memory 215936 kb
Host smart-8468b98e-0a50-4a9d-935a-f730add6a022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979565347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2979565347
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.2053566308
Short name T1150
Test name
Test status
Simulation time 38003432950 ps
CPU time 12.43 seconds
Started Mar 17 01:29:42 PM PDT 24
Finished Mar 17 01:29:54 PM PDT 24
Peak memory 215924 kb
Host smart-2fbc7e5b-c4b0-4e53-ab6c-ce54cdcc3914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053566308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2053566308
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.4286082867
Short name T1565
Test name
Test status
Simulation time 6319941797 ps
CPU time 16.8 seconds
Started Mar 17 03:14:17 PM PDT 24
Finished Mar 17 03:14:34 PM PDT 24
Peak memory 216080 kb
Host smart-2e485acd-b833-4dff-9e4e-2e544a4febd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286082867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.4286082867
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3439265164
Short name T908
Test name
Test status
Simulation time 22648578 ps
CPU time 1.39 seconds
Started Mar 17 01:29:39 PM PDT 24
Finished Mar 17 01:29:41 PM PDT 24
Peak memory 217272 kb
Host smart-1ca5c12d-cd5f-4346-a4b2-1a560bf2d6bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439265164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3439265164
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4093222215
Short name T774
Test name
Test status
Simulation time 21245942 ps
CPU time 0.74 seconds
Started Mar 17 03:14:23 PM PDT 24
Finished Mar 17 03:14:23 PM PDT 24
Peak memory 205440 kb
Host smart-c46c6f3c-4cb4-4dbf-bfff-8c1157cdb8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093222215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4093222215
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1763327080
Short name T1515
Test name
Test status
Simulation time 28509557 ps
CPU time 0.73 seconds
Started Mar 17 03:14:22 PM PDT 24
Finished Mar 17 03:14:23 PM PDT 24
Peak memory 205368 kb
Host smart-e87664b1-f4be-4391-9a9d-5bb781367ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763327080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1763327080
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.4230818291
Short name T868
Test name
Test status
Simulation time 125677626 ps
CPU time 0.83 seconds
Started Mar 17 01:29:39 PM PDT 24
Finished Mar 17 01:29:41 PM PDT 24
Peak memory 205164 kb
Host smart-a48d2cb8-b9e7-48b7-954b-4df3f8edbcb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230818291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.4230818291
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.2003174019
Short name T861
Test name
Test status
Simulation time 20809253482 ps
CPU time 17.31 seconds
Started Mar 17 03:14:21 PM PDT 24
Finished Mar 17 03:14:38 PM PDT 24
Peak memory 236684 kb
Host smart-2a254c28-76a0-4971-95bf-bde06b07cf6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003174019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2003174019
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_upload.672585155
Short name T830
Test name
Test status
Simulation time 142319728809 ps
CPU time 33.93 seconds
Started Mar 17 01:29:41 PM PDT 24
Finished Mar 17 01:30:15 PM PDT 24
Peak memory 228232 kb
Host smart-9a12ca1c-6fd5-46dd-91cc-ad3728f20198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672585155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.672585155
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2682760865
Short name T451
Test name
Test status
Simulation time 58454435 ps
CPU time 0.76 seconds
Started Mar 17 03:14:28 PM PDT 24
Finished Mar 17 03:14:29 PM PDT 24
Peak memory 204984 kb
Host smart-9d10b3bf-d01a-40f8-95e5-84993761ad06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682760865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2682760865
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.690181065
Short name T1653
Test name
Test status
Simulation time 14509078 ps
CPU time 0.74 seconds
Started Mar 17 01:29:45 PM PDT 24
Finished Mar 17 01:29:46 PM PDT 24
Peak memory 204856 kb
Host smart-a0d1a6b9-6ef7-413a-9683-a46933d7ccf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690181065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.690181065
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.1508479193
Short name T1529
Test name
Test status
Simulation time 1869523953 ps
CPU time 4.35 seconds
Started Mar 17 01:29:46 PM PDT 24
Finished Mar 17 01:29:51 PM PDT 24
Peak memory 224052 kb
Host smart-3d79f949-2588-4d9a-b3f6-0065abd2cf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508479193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.1508479193
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3099802
Short name T44
Test name
Test status
Simulation time 41017838 ps
CPU time 2.73 seconds
Started Mar 17 03:14:24 PM PDT 24
Finished Mar 17 03:14:27 PM PDT 24
Peak memory 233052 kb
Host smart-cd3f7d3b-c74b-4ec6-906a-0e056784aa16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3099802
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.357206414
Short name T1418
Test name
Test status
Simulation time 18423738 ps
CPU time 0.79 seconds
Started Mar 17 03:14:24 PM PDT 24
Finished Mar 17 03:14:25 PM PDT 24
Peak memory 206120 kb
Host smart-e51936b4-c68b-49b1-bad7-e4497fc92f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357206414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.357206414
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3694362799
Short name T607
Test name
Test status
Simulation time 22194954 ps
CPU time 0.76 seconds
Started Mar 17 01:29:40 PM PDT 24
Finished Mar 17 01:29:41 PM PDT 24
Peak memory 204944 kb
Host smart-17c92e07-88a3-4636-a0e3-1b6702ade315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694362799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3694362799
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2960649660
Short name T191
Test name
Test status
Simulation time 44668294238 ps
CPU time 218.07 seconds
Started Mar 17 03:14:28 PM PDT 24
Finished Mar 17 03:18:07 PM PDT 24
Peak memory 265384 kb
Host smart-2f54b5c0-6f50-426c-9ed2-d896cba792f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960649660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2960649660
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.3167116613
Short name T387
Test name
Test status
Simulation time 25380480822 ps
CPU time 66.45 seconds
Started Mar 17 01:29:44 PM PDT 24
Finished Mar 17 01:30:51 PM PDT 24
Peak memory 256908 kb
Host smart-559d6e3a-0cb8-4f93-b55b-38d9a360dae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167116613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.3167116613
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1699972425
Short name T921
Test name
Test status
Simulation time 20853718011 ps
CPU time 67.29 seconds
Started Mar 17 01:29:45 PM PDT 24
Finished Mar 17 01:30:52 PM PDT 24
Peak memory 248712 kb
Host smart-411596fc-f40b-4910-85c6-2b3736062d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699972425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1699972425
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1868281864
Short name T1610
Test name
Test status
Simulation time 73671462690 ps
CPU time 62.65 seconds
Started Mar 17 03:14:27 PM PDT 24
Finished Mar 17 03:15:30 PM PDT 24
Peak memory 222308 kb
Host smart-12466e78-0585-4194-9fd3-4b3c06d60e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868281864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1868281864
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.2703717508
Short name T840
Test name
Test status
Simulation time 4240988432 ps
CPU time 51.47 seconds
Started Mar 17 03:14:26 PM PDT 24
Finished Mar 17 03:15:18 PM PDT 24
Peak memory 240496 kb
Host smart-7317c8ed-fd37-4cab-a086-0694b3476423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703717508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.2703717508
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.295536364
Short name T1569
Test name
Test status
Simulation time 7170297148 ps
CPU time 88.91 seconds
Started Mar 17 01:29:44 PM PDT 24
Finished Mar 17 01:31:13 PM PDT 24
Peak memory 249564 kb
Host smart-7364d45c-b078-4075-8a89-43a09d2b3f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295536364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.295536364
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1529429503
Short name T440
Test name
Test status
Simulation time 569724992 ps
CPU time 9.1 seconds
Started Mar 17 01:29:44 PM PDT 24
Finished Mar 17 01:29:53 PM PDT 24
Peak memory 224032 kb
Host smart-9f059a1d-6c2c-4f36-8a51-62a91ff69d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529429503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1529429503
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.1679523484
Short name T1086
Test name
Test status
Simulation time 10193073946 ps
CPU time 15.98 seconds
Started Mar 17 03:14:26 PM PDT 24
Finished Mar 17 03:14:42 PM PDT 24
Peak memory 247520 kb
Host smart-e28bbec1-acc4-4e9d-8340-fb10b2c7c050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679523484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1679523484
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.2772325054
Short name T208
Test name
Test status
Simulation time 5209727447 ps
CPU time 8.49 seconds
Started Mar 17 01:29:45 PM PDT 24
Finished Mar 17 01:29:54 PM PDT 24
Peak memory 232940 kb
Host smart-92547fcb-2a3e-4435-8610-41c564210cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772325054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.2772325054
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_intercept.492663778
Short name T213
Test name
Test status
Simulation time 831457064 ps
CPU time 4 seconds
Started Mar 17 03:14:26 PM PDT 24
Finished Mar 17 03:14:30 PM PDT 24
Peak memory 219504 kb
Host smart-15f34996-0174-4c0c-8352-8716ef4e8cae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=492663778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.492663778
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.132093103
Short name T1017
Test name
Test status
Simulation time 1572754538 ps
CPU time 5.32 seconds
Started Mar 17 03:14:24 PM PDT 24
Finished Mar 17 03:14:30 PM PDT 24
Peak memory 220132 kb
Host smart-46d95ca2-9a78-4c74-9990-f7af1b954e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132093103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.132093103
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.3050018619
Short name T1215
Test name
Test status
Simulation time 10499236516 ps
CPU time 20.18 seconds
Started Mar 17 01:29:43 PM PDT 24
Finished Mar 17 01:30:04 PM PDT 24
Peak memory 224012 kb
Host smart-8e58b199-9205-4452-a1c2-187b44ff2a36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050018619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.3050018619
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_mem_parity.1686775151
Short name T1494
Test name
Test status
Simulation time 29588734 ps
CPU time 1.09 seconds
Started Mar 17 01:29:42 PM PDT 24
Finished Mar 17 01:29:43 PM PDT 24
Peak memory 216476 kb
Host smart-2434335d-bc43-4b84-81df-4bf06a911888
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686775151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 12.spi_device_mem_parity.1686775151
Directory /workspace/12.spi_device_mem_parity/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3064236050
Short name T1683
Test name
Test status
Simulation time 2292916595 ps
CPU time 4.32 seconds
Started Mar 17 01:29:45 PM PDT 24
Finished Mar 17 01:29:49 PM PDT 24
Peak memory 216884 kb
Host smart-ad5257cd-95b7-4678-b7b4-60dc7132ca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064236050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3064236050
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.3577984508
Short name T1805
Test name
Test status
Simulation time 6033956524 ps
CPU time 10.02 seconds
Started Mar 17 03:14:20 PM PDT 24
Finished Mar 17 03:14:31 PM PDT 24
Peak memory 228828 kb
Host smart-9c8c893b-65f8-4162-8a6d-0bde03534cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577984508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.3577984508
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2490749566
Short name T230
Test name
Test status
Simulation time 19734841365 ps
CPU time 15.56 seconds
Started Mar 17 01:29:47 PM PDT 24
Finished Mar 17 01:30:03 PM PDT 24
Peak memory 233424 kb
Host smart-be6d1d78-e32c-4422-bf19-3a112e60e96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2490749566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2490749566
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.571777126
Short name T850
Test name
Test status
Simulation time 7439855207 ps
CPU time 20.41 seconds
Started Mar 17 03:14:22 PM PDT 24
Finished Mar 17 03:14:43 PM PDT 24
Peak memory 226168 kb
Host smart-09bc611f-b018-48d8-9215-6b64fb2b177e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571777126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.571777126
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.1403217990
Short name T1031
Test name
Test status
Simulation time 48543575 ps
CPU time 0.75 seconds
Started Mar 17 01:29:43 PM PDT 24
Finished Mar 17 01:29:44 PM PDT 24
Peak memory 215812 kb
Host smart-317829bb-d4e9-4de6-b96b-067e84a16778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403217990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.1403217990
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_ram_cfg.3308160281
Short name T611
Test name
Test status
Simulation time 61425866 ps
CPU time 0.75 seconds
Started Mar 17 03:14:21 PM PDT 24
Finished Mar 17 03:14:22 PM PDT 24
Peak memory 216056 kb
Host smart-8fd68a12-895e-4114-9146-1bacc61f52b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308160281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_ram_cfg.3308160281
Directory /workspace/12.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.353338333
Short name T337
Test name
Test status
Simulation time 1332209143 ps
CPU time 3.38 seconds
Started Mar 17 01:29:45 PM PDT 24
Finished Mar 17 01:29:48 PM PDT 24
Peak memory 218004 kb
Host smart-418afbcf-047a-42d9-8ec5-c9906d295aea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=353338333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.353338333
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.875039285
Short name T1694
Test name
Test status
Simulation time 3055014032 ps
CPU time 6.47 seconds
Started Mar 17 03:14:27 PM PDT 24
Finished Mar 17 03:14:34 PM PDT 24
Peak memory 220204 kb
Host smart-6bf4022e-740c-466c-a147-95dbc2253247
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=875039285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.875039285
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1766881700
Short name T971
Test name
Test status
Simulation time 56674463 ps
CPU time 1.03 seconds
Started Mar 17 03:14:27 PM PDT 24
Finished Mar 17 03:14:28 PM PDT 24
Peak memory 206876 kb
Host smart-8ffaec22-5842-4796-a17e-3a2d9e93c89d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766881700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1766881700
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1943082275
Short name T40
Test name
Test status
Simulation time 155155854628 ps
CPU time 280.05 seconds
Started Mar 17 01:29:46 PM PDT 24
Finished Mar 17 01:34:26 PM PDT 24
Peak memory 251668 kb
Host smart-9e47bd85-ccbd-4f84-8c94-68089d7d3baa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943082275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1943082275
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2453670400
Short name T1519
Test name
Test status
Simulation time 1124606489 ps
CPU time 6.69 seconds
Started Mar 17 03:14:22 PM PDT 24
Finished Mar 17 03:14:29 PM PDT 24
Peak memory 216128 kb
Host smart-0c671d36-82e9-481d-8134-334c7a70a289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453670400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2453670400
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2519253797
Short name T1786
Test name
Test status
Simulation time 2638239770 ps
CPU time 37.19 seconds
Started Mar 17 01:29:39 PM PDT 24
Finished Mar 17 01:30:17 PM PDT 24
Peak memory 220472 kb
Host smart-dfe223ba-754e-411d-8e91-493f67e5dde8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519253797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2519253797
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3252186060
Short name T1863
Test name
Test status
Simulation time 1788644735 ps
CPU time 10.33 seconds
Started Mar 17 03:14:24 PM PDT 24
Finished Mar 17 03:14:35 PM PDT 24
Peak memory 216012 kb
Host smart-effad134-404f-4edb-92c7-0666e5bbed35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252186060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3252186060
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.727367965
Short name T1118
Test name
Test status
Simulation time 4060489668 ps
CPU time 15.34 seconds
Started Mar 17 01:29:39 PM PDT 24
Finished Mar 17 01:29:56 PM PDT 24
Peak memory 215896 kb
Host smart-94337087-f660-4ef1-9129-6311b7d46089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727367965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.727367965
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.2741724698
Short name T1010
Test name
Test status
Simulation time 208517899 ps
CPU time 1.53 seconds
Started Mar 17 01:29:41 PM PDT 24
Finished Mar 17 01:29:43 PM PDT 24
Peak memory 215904 kb
Host smart-b268ca90-1f06-4ad1-a837-bb9d28856f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741724698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.2741724698
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.3425371723
Short name T875
Test name
Test status
Simulation time 237499946 ps
CPU time 3.52 seconds
Started Mar 17 03:14:21 PM PDT 24
Finished Mar 17 03:14:25 PM PDT 24
Peak memory 216112 kb
Host smart-143fe398-6101-405a-9c3d-449ca25ad67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425371723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.3425371723
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.117332963
Short name T1473
Test name
Test status
Simulation time 24027262 ps
CPU time 0.81 seconds
Started Mar 17 01:29:40 PM PDT 24
Finished Mar 17 01:29:41 PM PDT 24
Peak memory 205160 kb
Host smart-b768c3ec-45c0-4dd5-8abd-d8f0c5dc8096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117332963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.117332963
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.3454032707
Short name T1272
Test name
Test status
Simulation time 235385160 ps
CPU time 0.91 seconds
Started Mar 17 03:14:21 PM PDT 24
Finished Mar 17 03:14:22 PM PDT 24
Peak memory 205436 kb
Host smart-c6d30aef-b5a7-4814-99f1-0b7470f776f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454032707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.3454032707
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2514984120
Short name T790
Test name
Test status
Simulation time 1917250070 ps
CPU time 7.6 seconds
Started Mar 17 01:29:44 PM PDT 24
Finished Mar 17 01:29:52 PM PDT 24
Peak memory 220780 kb
Host smart-1cb74fd6-16b6-470d-8c86-c57c931cdb70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514984120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2514984120
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_upload.908510015
Short name T498
Test name
Test status
Simulation time 1359151564 ps
CPU time 4.57 seconds
Started Mar 17 03:14:23 PM PDT 24
Finished Mar 17 03:14:27 PM PDT 24
Peak memory 235456 kb
Host smart-ae9cef2b-6251-4122-9889-bc65362316c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=908510015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.908510015
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.2125633173
Short name T1634
Test name
Test status
Simulation time 11030888 ps
CPU time 0.73 seconds
Started Mar 17 01:30:04 PM PDT 24
Finished Mar 17 01:30:05 PM PDT 24
Peak memory 204840 kb
Host smart-71a1a67a-47ad-445b-b1f3-13101dd74718
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125633173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
2125633173
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.4069437846
Short name T1495
Test name
Test status
Simulation time 22513519 ps
CPU time 0.72 seconds
Started Mar 17 03:14:36 PM PDT 24
Finished Mar 17 03:14:37 PM PDT 24
Peak memory 204452 kb
Host smart-8cef77cd-d4d6-4e88-8380-9c9bb2e80aaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069437846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
4069437846
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2579344239
Short name T1764
Test name
Test status
Simulation time 766291213 ps
CPU time 3.15 seconds
Started Mar 17 01:29:53 PM PDT 24
Finished Mar 17 01:29:56 PM PDT 24
Peak memory 233296 kb
Host smart-14593012-b5e5-4723-a314-bdae876dcb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579344239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2579344239
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2909491137
Short name T45
Test name
Test status
Simulation time 125481741 ps
CPU time 2.23 seconds
Started Mar 17 03:14:31 PM PDT 24
Finished Mar 17 03:14:34 PM PDT 24
Peak memory 218472 kb
Host smart-ebb656e2-0d4a-4132-8ac8-e23c6088a4fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909491137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2909491137
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1259628829
Short name T794
Test name
Test status
Simulation time 31980502 ps
CPU time 0.79 seconds
Started Mar 17 03:14:28 PM PDT 24
Finished Mar 17 03:14:30 PM PDT 24
Peak memory 205176 kb
Host smart-68218ca8-c6a4-4185-aac9-a413d45d284f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259628829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1259628829
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.3358972547
Short name T303
Test name
Test status
Simulation time 73514564 ps
CPU time 0.79 seconds
Started Mar 17 01:29:44 PM PDT 24
Finished Mar 17 01:29:45 PM PDT 24
Peak memory 205956 kb
Host smart-b72ca968-4a0d-414c-9284-6cc9aa21d5d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358972547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3358972547
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2471712906
Short name T263
Test name
Test status
Simulation time 295854981179 ps
CPU time 269.74 seconds
Started Mar 17 01:29:50 PM PDT 24
Finished Mar 17 01:34:20 PM PDT 24
Peak memory 255956 kb
Host smart-d43bb62e-7f76-4e26-9843-a172e2d7ba75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2471712906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2471712906
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3667842189
Short name T203
Test name
Test status
Simulation time 7037426141 ps
CPU time 52.06 seconds
Started Mar 17 01:29:52 PM PDT 24
Finished Mar 17 01:30:44 PM PDT 24
Peak memory 248896 kb
Host smart-a6d5793a-5206-4769-884d-4088ef1e933c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667842189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3667842189
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3718814450
Short name T495
Test name
Test status
Simulation time 47372000763 ps
CPU time 303.77 seconds
Started Mar 17 03:14:35 PM PDT 24
Finished Mar 17 03:19:39 PM PDT 24
Peak memory 249040 kb
Host smart-d9a143f4-f829-4916-94a3-58c6003a5d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718814450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3718814450
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.18416518
Short name T17
Test name
Test status
Simulation time 11258575651 ps
CPU time 93.53 seconds
Started Mar 17 01:29:51 PM PDT 24
Finished Mar 17 01:31:24 PM PDT 24
Peak memory 251288 kb
Host smart-149be643-dc8d-4f71-94d8-7970ff63d4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18416518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.18416518
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.1848552256
Short name T565
Test name
Test status
Simulation time 103539468296 ps
CPU time 171.48 seconds
Started Mar 17 03:14:31 PM PDT 24
Finished Mar 17 03:17:23 PM PDT 24
Peak memory 234088 kb
Host smart-07924818-802b-49b2-80b1-067d6ae8ebf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848552256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.1848552256
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.4025819219
Short name T1611
Test name
Test status
Simulation time 16940074403 ps
CPU time 28.72 seconds
Started Mar 17 03:14:33 PM PDT 24
Finished Mar 17 03:15:03 PM PDT 24
Peak memory 240636 kb
Host smart-d9f92b30-6679-4360-89a5-b0a31f87cd2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025819219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.4025819219
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_intercept.138336975
Short name T1324
Test name
Test status
Simulation time 1801275389 ps
CPU time 8.3 seconds
Started Mar 17 01:29:50 PM PDT 24
Finished Mar 17 01:29:58 PM PDT 24
Peak memory 223996 kb
Host smart-48ebe572-f687-40f0-87d2-fc13d3562c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138336975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.138336975
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_intercept.1607819885
Short name T1842
Test name
Test status
Simulation time 2261905498 ps
CPU time 5.47 seconds
Started Mar 17 03:14:39 PM PDT 24
Finished Mar 17 03:14:44 PM PDT 24
Peak memory 235152 kb
Host smart-02e2259e-956c-4e6b-9df7-e3c992fb9f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607819885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1607819885
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2543828757
Short name T1044
Test name
Test status
Simulation time 1973215132 ps
CPU time 7.02 seconds
Started Mar 17 03:14:32 PM PDT 24
Finished Mar 17 03:14:40 PM PDT 24
Peak memory 238860 kb
Host smart-b33d2754-31c0-4e36-8124-9a07c83aa936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543828757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2543828757
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3925931160
Short name T689
Test name
Test status
Simulation time 1586027763 ps
CPU time 10.87 seconds
Started Mar 17 01:29:50 PM PDT 24
Finished Mar 17 01:30:01 PM PDT 24
Peak memory 240324 kb
Host smart-b28fafef-a595-4ec7-9078-f85a8d390ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925931160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3925931160
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_mem_parity.3912406214
Short name T989
Test name
Test status
Simulation time 61671670 ps
CPU time 1.02 seconds
Started Mar 17 01:29:50 PM PDT 24
Finished Mar 17 01:29:51 PM PDT 24
Peak memory 217728 kb
Host smart-d1e92b6e-a832-4452-8768-2ddcc0f5bafb
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912406214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 13.spi_device_mem_parity.3912406214
Directory /workspace/13.spi_device_mem_parity/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1996936949
Short name T1652
Test name
Test status
Simulation time 772939793 ps
CPU time 2.97 seconds
Started Mar 17 01:29:49 PM PDT 24
Finished Mar 17 01:29:52 PM PDT 24
Peak memory 216560 kb
Host smart-4e82f091-ae33-430b-a0cb-03a819a4d87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1996936949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1996936949
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2570616847
Short name T1450
Test name
Test status
Simulation time 6007507570 ps
CPU time 7.14 seconds
Started Mar 17 03:14:36 PM PDT 24
Finished Mar 17 03:14:43 PM PDT 24
Peak memory 219508 kb
Host smart-e4bd29a5-70af-41b1-aea5-5bc0dec6de56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570616847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2570616847
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1386666070
Short name T470
Test name
Test status
Simulation time 741452981 ps
CPU time 6.19 seconds
Started Mar 17 03:14:34 PM PDT 24
Finished Mar 17 03:14:41 PM PDT 24
Peak memory 240188 kb
Host smart-269ce6ef-5ee8-447e-8fb5-5bd5927221e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386666070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1386666070
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2992861970
Short name T1172
Test name
Test status
Simulation time 709449736 ps
CPU time 6.02 seconds
Started Mar 17 01:29:52 PM PDT 24
Finished Mar 17 01:29:58 PM PDT 24
Peak memory 226208 kb
Host smart-944435dc-cb59-4021-af94-4d3b03013508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992861970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2992861970
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.1099055222
Short name T818
Test name
Test status
Simulation time 78958481 ps
CPU time 0.71 seconds
Started Mar 17 01:29:52 PM PDT 24
Finished Mar 17 01:29:53 PM PDT 24
Peak memory 215724 kb
Host smart-d53b42a8-4c8f-466d-b3cb-c4af404cc517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099055222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.1099055222
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_ram_cfg.442139877
Short name T1705
Test name
Test status
Simulation time 25209452 ps
CPU time 0.74 seconds
Started Mar 17 03:14:27 PM PDT 24
Finished Mar 17 03:14:28 PM PDT 24
Peak memory 216048 kb
Host smart-ecccf729-069a-4fe3-b820-76ab161f1589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442139877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_ram_cfg.442139877
Directory /workspace/13.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.2745729313
Short name T524
Test name
Test status
Simulation time 1097167975 ps
CPU time 6.29 seconds
Started Mar 17 01:29:52 PM PDT 24
Finished Mar 17 01:29:59 PM PDT 24
Peak memory 222232 kb
Host smart-05a23cc7-6865-4245-b708-dfe6961cabc7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2745729313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.2745729313
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.370131302
Short name T1092
Test name
Test status
Simulation time 1299642485 ps
CPU time 3.18 seconds
Started Mar 17 03:14:32 PM PDT 24
Finished Mar 17 03:14:36 PM PDT 24
Peak memory 218664 kb
Host smart-efb14033-7a36-4007-9b56-f804a4018cf2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=370131302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.370131302
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3685083405
Short name T1760
Test name
Test status
Simulation time 129826013 ps
CPU time 0.92 seconds
Started Mar 17 01:29:49 PM PDT 24
Finished Mar 17 01:29:50 PM PDT 24
Peak memory 206116 kb
Host smart-5ed1a6f2-13aa-4374-b7cd-99fca596b145
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685083405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3685083405
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.409983273
Short name T1723
Test name
Test status
Simulation time 8578078370 ps
CPU time 116.96 seconds
Started Mar 17 03:14:39 PM PDT 24
Finished Mar 17 03:16:36 PM PDT 24
Peak memory 266040 kb
Host smart-4282aaee-cfd9-493c-877f-f089a285739d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409983273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.409983273
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1108266102
Short name T1685
Test name
Test status
Simulation time 6996599737 ps
CPU time 45 seconds
Started Mar 17 01:29:50 PM PDT 24
Finished Mar 17 01:30:35 PM PDT 24
Peak memory 215944 kb
Host smart-0f1a2073-d554-434a-98f6-7e85bf1b186f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108266102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1108266102
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.902655727
Short name T1469
Test name
Test status
Simulation time 9611573766 ps
CPU time 24.49 seconds
Started Mar 17 03:14:31 PM PDT 24
Finished Mar 17 03:14:56 PM PDT 24
Peak memory 216220 kb
Host smart-f61fcfc2-e795-46e7-998c-cb6153b1b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902655727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.902655727
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.117551748
Short name T1487
Test name
Test status
Simulation time 1610590909 ps
CPU time 6.79 seconds
Started Mar 17 01:29:50 PM PDT 24
Finished Mar 17 01:29:56 PM PDT 24
Peak memory 215796 kb
Host smart-e96ae126-8065-495e-8b47-09bebd171b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117551748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.117551748
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.243366435
Short name T1780
Test name
Test status
Simulation time 2710040180 ps
CPU time 7.69 seconds
Started Mar 17 03:14:31 PM PDT 24
Finished Mar 17 03:14:39 PM PDT 24
Peak memory 216100 kb
Host smart-d6c86e3c-0e5d-42ea-8545-86a74c3fe9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243366435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.243366435
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.122802807
Short name T1433
Test name
Test status
Simulation time 144866898 ps
CPU time 1.8 seconds
Started Mar 17 01:29:53 PM PDT 24
Finished Mar 17 01:29:54 PM PDT 24
Peak memory 215836 kb
Host smart-655f0170-01c2-4acb-a2f6-87c7a8625d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=122802807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.122802807
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2020858429
Short name T1643
Test name
Test status
Simulation time 55296751 ps
CPU time 2 seconds
Started Mar 17 03:14:32 PM PDT 24
Finished Mar 17 03:14:35 PM PDT 24
Peak memory 216108 kb
Host smart-4cdfa002-fe6a-43a5-9648-18ef5c2cb32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020858429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2020858429
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.133412668
Short name T1898
Test name
Test status
Simulation time 122343160 ps
CPU time 0.74 seconds
Started Mar 17 01:29:50 PM PDT 24
Finished Mar 17 01:29:51 PM PDT 24
Peak memory 205144 kb
Host smart-44e49d95-6ddf-4476-828e-380b815bd1e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133412668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.133412668
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.347383521
Short name T1100
Test name
Test status
Simulation time 21068992 ps
CPU time 0.74 seconds
Started Mar 17 03:14:31 PM PDT 24
Finished Mar 17 03:14:32 PM PDT 24
Peak memory 205372 kb
Host smart-b62378d9-93d2-407f-9752-72874fd318c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347383521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.347383521
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1889883415
Short name T1347
Test name
Test status
Simulation time 916192378 ps
CPU time 5.35 seconds
Started Mar 17 03:14:36 PM PDT 24
Finished Mar 17 03:14:41 PM PDT 24
Peak memory 237292 kb
Host smart-1311635b-5416-445e-bdfd-66a7e2324945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889883415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1889883415
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_upload.3492860217
Short name T1400
Test name
Test status
Simulation time 3465913023 ps
CPU time 9.48 seconds
Started Mar 17 01:29:51 PM PDT 24
Finished Mar 17 01:30:00 PM PDT 24
Peak memory 235820 kb
Host smart-e5f70b53-369c-48b6-a0b8-d4a8fea47106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492860217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3492860217
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.324051715
Short name T508
Test name
Test status
Simulation time 11757870 ps
CPU time 0.74 seconds
Started Mar 17 01:30:02 PM PDT 24
Finished Mar 17 01:30:03 PM PDT 24
Peak memory 204312 kb
Host smart-e5326d6d-a407-428d-9f9f-088460e018b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324051715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.324051715
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.982766564
Short name T692
Test name
Test status
Simulation time 17934657 ps
CPU time 0.7 seconds
Started Mar 17 03:14:42 PM PDT 24
Finished Mar 17 03:14:43 PM PDT 24
Peak memory 204416 kb
Host smart-d243e5ed-0468-48e4-a42d-d50fa915fbbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982766564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.982766564
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.2794774773
Short name T997
Test name
Test status
Simulation time 14557127942 ps
CPU time 13.09 seconds
Started Mar 17 03:14:41 PM PDT 24
Finished Mar 17 03:14:55 PM PDT 24
Peak memory 233352 kb
Host smart-381bf1f5-4b95-43d2-a04a-18ce5014ee33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794774773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.2794774773
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.905399455
Short name T1567
Test name
Test status
Simulation time 643456846 ps
CPU time 4.05 seconds
Started Mar 17 01:29:57 PM PDT 24
Finished Mar 17 01:30:01 PM PDT 24
Peak memory 224048 kb
Host smart-0dc79405-e99c-4497-bd7b-6aa10382ac36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905399455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.905399455
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.3175079840
Short name T1514
Test name
Test status
Simulation time 129734368 ps
CPU time 0.79 seconds
Started Mar 17 03:14:35 PM PDT 24
Finished Mar 17 03:14:36 PM PDT 24
Peak memory 206152 kb
Host smart-135404ca-ac7f-4cb9-ba50-b157d1985b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175079840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.3175079840
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.4099677084
Short name T550
Test name
Test status
Simulation time 42391070 ps
CPU time 0.79 seconds
Started Mar 17 01:29:55 PM PDT 24
Finished Mar 17 01:29:56 PM PDT 24
Peak memory 206004 kb
Host smart-d3416249-f226-4e1f-906b-66c14b6013b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099677084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4099677084
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.3111375383
Short name T349
Test name
Test status
Simulation time 3437538963 ps
CPU time 50.23 seconds
Started Mar 17 03:14:41 PM PDT 24
Finished Mar 17 03:15:32 PM PDT 24
Peak memory 263080 kb
Host smart-69d4cffe-88fd-4da2-b41a-11551d9276ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111375383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.3111375383
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.474830017
Short name T206
Test name
Test status
Simulation time 106542772263 ps
CPU time 506.35 seconds
Started Mar 17 01:30:05 PM PDT 24
Finished Mar 17 01:38:33 PM PDT 24
Peak memory 256928 kb
Host smart-44924f74-d720-4fae-b8b9-1dd42d638654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474830017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.474830017
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2321322664
Short name T1801
Test name
Test status
Simulation time 27120242117 ps
CPU time 164.97 seconds
Started Mar 17 01:30:05 PM PDT 24
Finished Mar 17 01:32:51 PM PDT 24
Peak memory 249804 kb
Host smart-556dad18-1eb3-42f3-9931-954432c749ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321322664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2321322664
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2630061578
Short name T1536
Test name
Test status
Simulation time 5579393152 ps
CPU time 59.16 seconds
Started Mar 17 03:14:41 PM PDT 24
Finished Mar 17 03:15:41 PM PDT 24
Peak memory 256220 kb
Host smart-2de870d6-1daf-47be-9ddf-2853bdf3fa15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630061578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2630061578
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.4195576273
Short name T172
Test name
Test status
Simulation time 118806789919 ps
CPU time 234.5 seconds
Started Mar 17 03:14:42 PM PDT 24
Finished Mar 17 03:18:37 PM PDT 24
Peak memory 252476 kb
Host smart-1a256f07-614f-48dc-8cb2-7669e938301c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195576273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.4195576273
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1200064848
Short name T1886
Test name
Test status
Simulation time 2456867594 ps
CPU time 12.67 seconds
Started Mar 17 01:29:56 PM PDT 24
Finished Mar 17 01:30:08 PM PDT 24
Peak memory 232172 kb
Host smart-c8ca3154-8bda-4b9f-894c-657e13de36d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1200064848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1200064848
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.3792137983
Short name T1187
Test name
Test status
Simulation time 49138212373 ps
CPU time 61.33 seconds
Started Mar 17 03:14:47 PM PDT 24
Finished Mar 17 03:15:49 PM PDT 24
Peak memory 247060 kb
Host smart-be17a506-0cec-44d1-a884-783ea3257625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792137983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.3792137983
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.2162641739
Short name T1385
Test name
Test status
Simulation time 605853284 ps
CPU time 3.16 seconds
Started Mar 17 03:14:41 PM PDT 24
Finished Mar 17 03:14:45 PM PDT 24
Peak memory 217500 kb
Host smart-8e0f36ae-05d7-4e9b-acc4-8662114b8f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162641739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.2162641739
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3793056424
Short name T1350
Test name
Test status
Simulation time 259592736 ps
CPU time 2.45 seconds
Started Mar 17 01:29:57 PM PDT 24
Finished Mar 17 01:29:59 PM PDT 24
Peak memory 224036 kb
Host smart-31b1ebcb-3565-494a-b607-9f2c2ce43f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793056424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3793056424
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.231271306
Short name T708
Test name
Test status
Simulation time 9397155292 ps
CPU time 23.57 seconds
Started Mar 17 01:29:56 PM PDT 24
Finished Mar 17 01:30:19 PM PDT 24
Peak memory 234036 kb
Host smart-04a1d3a2-dcb9-4c0f-a170-b36db5c390fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231271306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.231271306
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2950607530
Short name T1291
Test name
Test status
Simulation time 3444754956 ps
CPU time 13.43 seconds
Started Mar 17 03:14:47 PM PDT 24
Finished Mar 17 03:15:01 PM PDT 24
Peak memory 221700 kb
Host smart-30c015cd-d514-4992-bb97-9f8593810028
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950607530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2950607530
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_mem_parity.3418119799
Short name T1360
Test name
Test status
Simulation time 34106254 ps
CPU time 1.02 seconds
Started Mar 17 01:29:55 PM PDT 24
Finished Mar 17 01:29:56 PM PDT 24
Peak memory 217844 kb
Host smart-04bc90d7-a99e-43c7-b815-108ad9872b07
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3418119799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 14.spi_device_mem_parity.3418119799
Directory /workspace/14.spi_device_mem_parity/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1735836514
Short name T510
Test name
Test status
Simulation time 9000041295 ps
CPU time 23.17 seconds
Started Mar 17 01:29:57 PM PDT 24
Finished Mar 17 01:30:20 PM PDT 24
Peak memory 245496 kb
Host smart-b3aa6a71-47f8-4106-af15-47833276be08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735836514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1735836514
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3084897382
Short name T187
Test name
Test status
Simulation time 600261209 ps
CPU time 2.54 seconds
Started Mar 17 03:14:40 PM PDT 24
Finished Mar 17 03:14:43 PM PDT 24
Peak memory 233140 kb
Host smart-a1a55882-0a45-4a05-b617-cccf09ef5cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084897382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3084897382
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.2309906675
Short name T1811
Test name
Test status
Simulation time 5933714365 ps
CPU time 9.87 seconds
Started Mar 17 01:29:56 PM PDT 24
Finished Mar 17 01:30:06 PM PDT 24
Peak memory 229052 kb
Host smart-9c28993d-33b6-4709-a5e8-aa0cfb809440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2309906675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.2309906675
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.3356629493
Short name T1766
Test name
Test status
Simulation time 2485028013 ps
CPU time 11.78 seconds
Started Mar 17 03:14:37 PM PDT 24
Finished Mar 17 03:14:49 PM PDT 24
Peak memory 228568 kb
Host smart-65a7fbdf-b516-4af5-9207-5419009b753a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356629493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.3356629493
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.1241180779
Short name T1407
Test name
Test status
Simulation time 27202993 ps
CPU time 0.73 seconds
Started Mar 17 01:29:55 PM PDT 24
Finished Mar 17 01:29:56 PM PDT 24
Peak memory 215772 kb
Host smart-793d217d-0b3b-4488-b4f1-97c8fd07c762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241180779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.1241180779
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_ram_cfg.3741845727
Short name T644
Test name
Test status
Simulation time 32994834 ps
CPU time 0.76 seconds
Started Mar 17 03:14:37 PM PDT 24
Finished Mar 17 03:14:38 PM PDT 24
Peak memory 216024 kb
Host smart-7bd866e5-153d-4615-a2ee-704c7523adc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741845727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_ram_cfg.3741845727
Directory /workspace/14.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.1016461178
Short name T687
Test name
Test status
Simulation time 1186182712 ps
CPU time 4.56 seconds
Started Mar 17 01:29:55 PM PDT 24
Finished Mar 17 01:30:00 PM PDT 24
Peak memory 221776 kb
Host smart-27829769-3c34-4541-8820-186177af3b34
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1016461178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.1016461178
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3333573311
Short name T1222
Test name
Test status
Simulation time 1860726020 ps
CPU time 5.7 seconds
Started Mar 17 03:14:47 PM PDT 24
Finished Mar 17 03:14:53 PM PDT 24
Peak memory 221508 kb
Host smart-e8445a6a-fad0-4a0b-ae9d-d24d47acfb7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3333573311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3333573311
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.2801696584
Short name T1221
Test name
Test status
Simulation time 59432833642 ps
CPU time 167.21 seconds
Started Mar 17 03:14:48 PM PDT 24
Finished Mar 17 03:17:36 PM PDT 24
Peak memory 240848 kb
Host smart-ed803939-80b0-4943-878e-1a2c473a006f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801696584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.2801696584
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.4252367027
Short name T142
Test name
Test status
Simulation time 85145397 ps
CPU time 0.94 seconds
Started Mar 17 01:30:02 PM PDT 24
Finished Mar 17 01:30:03 PM PDT 24
Peak memory 206324 kb
Host smart-2cc216f1-a6ca-4f8a-8a68-bc3fe27f79b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252367027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.4252367027
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1073718152
Short name T1584
Test name
Test status
Simulation time 3342081591 ps
CPU time 43.41 seconds
Started Mar 17 03:14:38 PM PDT 24
Finished Mar 17 03:15:21 PM PDT 24
Peak memory 216192 kb
Host smart-e82250f3-0b09-41ac-9254-0b8724892e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073718152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1073718152
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.3879492650
Short name T1180
Test name
Test status
Simulation time 1570701831 ps
CPU time 6.01 seconds
Started Mar 17 01:29:57 PM PDT 24
Finished Mar 17 01:30:03 PM PDT 24
Peak memory 215880 kb
Host smart-efe7b7fd-7d6a-41fb-8369-5cf78b53ee2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879492650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3879492650
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.1750942039
Short name T1168
Test name
Test status
Simulation time 1226178939 ps
CPU time 1.93 seconds
Started Mar 17 01:29:57 PM PDT 24
Finished Mar 17 01:29:59 PM PDT 24
Peak memory 207244 kb
Host smart-8b082af5-f670-46d6-99f5-f2122b975320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750942039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.1750942039
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.67208419
Short name T1888
Test name
Test status
Simulation time 12635474992 ps
CPU time 13.44 seconds
Started Mar 17 03:14:34 PM PDT 24
Finished Mar 17 03:14:48 PM PDT 24
Peak memory 216056 kb
Host smart-86039b8b-8707-45b5-9fd2-708d73325598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67208419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.67208419
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.1164001718
Short name T1828
Test name
Test status
Simulation time 118848132 ps
CPU time 2.25 seconds
Started Mar 17 01:29:55 PM PDT 24
Finished Mar 17 01:29:58 PM PDT 24
Peak memory 215916 kb
Host smart-20496008-957a-4aaa-ac04-34b94e5af9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164001718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.1164001718
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.3592462165
Short name T1255
Test name
Test status
Simulation time 437452468 ps
CPU time 3.88 seconds
Started Mar 17 03:14:37 PM PDT 24
Finished Mar 17 03:14:41 PM PDT 24
Peak memory 216040 kb
Host smart-5fc8a076-a279-47a4-bd67-ce8ece7b017b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592462165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3592462165
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3117279285
Short name T1015
Test name
Test status
Simulation time 153149820 ps
CPU time 0.84 seconds
Started Mar 17 01:29:57 PM PDT 24
Finished Mar 17 01:29:58 PM PDT 24
Peak memory 205184 kb
Host smart-7faad95f-79d4-4998-b0e9-ba035d967311
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117279285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3117279285
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3526493014
Short name T361
Test name
Test status
Simulation time 89288768 ps
CPU time 0.95 seconds
Started Mar 17 03:14:41 PM PDT 24
Finished Mar 17 03:14:42 PM PDT 24
Peak memory 205448 kb
Host smart-a249733b-dd9b-4a96-90a0-65b730497420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526493014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3526493014
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3104052433
Short name T1714
Test name
Test status
Simulation time 9088561449 ps
CPU time 4.83 seconds
Started Mar 17 03:14:42 PM PDT 24
Finished Mar 17 03:14:47 PM PDT 24
Peak memory 218560 kb
Host smart-a2836c50-1d0f-40e4-9a08-13c68bfb89b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104052433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3104052433
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_upload.3459706391
Short name T624
Test name
Test status
Simulation time 6142798180 ps
CPU time 18.29 seconds
Started Mar 17 01:29:57 PM PDT 24
Finished Mar 17 01:30:15 PM PDT 24
Peak memory 218564 kb
Host smart-2797a221-8cb1-4e84-818f-ed4f49c55e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459706391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3459706391
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2247476939
Short name T1241
Test name
Test status
Simulation time 103754004 ps
CPU time 0.71 seconds
Started Mar 17 01:30:05 PM PDT 24
Finished Mar 17 01:30:06 PM PDT 24
Peak memory 204276 kb
Host smart-c4ab8190-41f5-4d37-8350-8a4b552d3bce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247476939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2247476939
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3189846477
Short name T1845
Test name
Test status
Simulation time 23038550 ps
CPU time 0.71 seconds
Started Mar 17 03:14:47 PM PDT 24
Finished Mar 17 03:14:49 PM PDT 24
Peak memory 205024 kb
Host smart-3006d4e3-b1a3-4bc0-a235-c5d65ba74c9c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189846477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3189846477
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2759526504
Short name T436
Test name
Test status
Simulation time 3352303356 ps
CPU time 3.43 seconds
Started Mar 17 01:30:01 PM PDT 24
Finished Mar 17 01:30:04 PM PDT 24
Peak memory 224024 kb
Host smart-a041ba4c-74cd-485c-bcf6-9c0de13a2d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759526504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2759526504
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.4281115640
Short name T74
Test name
Test status
Simulation time 490846627 ps
CPU time 4.01 seconds
Started Mar 17 03:14:45 PM PDT 24
Finished Mar 17 03:14:50 PM PDT 24
Peak memory 237060 kb
Host smart-c31fd5a6-c511-4c48-badd-52a4aead640c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281115640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.4281115640
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.1713947658
Short name T416
Test name
Test status
Simulation time 46991422 ps
CPU time 0.74 seconds
Started Mar 17 03:14:46 PM PDT 24
Finished Mar 17 03:14:47 PM PDT 24
Peak memory 206168 kb
Host smart-7127e633-a311-4097-aef4-723dc44fa7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713947658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.1713947658
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3521144152
Short name T1664
Test name
Test status
Simulation time 56892393 ps
CPU time 0.75 seconds
Started Mar 17 01:30:02 PM PDT 24
Finished Mar 17 01:30:03 PM PDT 24
Peak memory 205296 kb
Host smart-3c7bcbb7-3ce0-47f4-af70-86c932b0e64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521144152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3521144152
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1601347585
Short name T264
Test name
Test status
Simulation time 5764128967 ps
CPU time 20.73 seconds
Started Mar 17 03:14:46 PM PDT 24
Finished Mar 17 03:15:07 PM PDT 24
Peak memory 234644 kb
Host smart-cc6d2e93-7d82-4a59-ab2f-2ecae7b31099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1601347585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1601347585
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2019935887
Short name T267
Test name
Test status
Simulation time 5073951313 ps
CPU time 62.29 seconds
Started Mar 17 01:30:06 PM PDT 24
Finished Mar 17 01:31:09 PM PDT 24
Peak memory 264392 kb
Host smart-f733b4d1-89fd-434d-9a6f-6dc163fcae58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019935887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2019935887
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.3946243833
Short name T463
Test name
Test status
Simulation time 7428668330 ps
CPU time 61.09 seconds
Started Mar 17 03:14:49 PM PDT 24
Finished Mar 17 03:15:51 PM PDT 24
Peak memory 222236 kb
Host smart-cb824072-f113-483c-989c-f558783e14cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946243833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.3946243833
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1240022353
Short name T1112
Test name
Test status
Simulation time 13336205836 ps
CPU time 90.34 seconds
Started Mar 17 01:30:06 PM PDT 24
Finished Mar 17 01:31:37 PM PDT 24
Peak memory 235592 kb
Host smart-6c264783-9deb-49f9-990c-c0cae15be842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240022353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1240022353
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3151986033
Short name T1901
Test name
Test status
Simulation time 4410589329 ps
CPU time 102.08 seconds
Started Mar 17 03:14:44 PM PDT 24
Finished Mar 17 03:16:27 PM PDT 24
Peak memory 255620 kb
Host smart-ac68c2a5-65c6-4603-83ae-78ff5e9b93db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151986033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3151986033
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.1113454046
Short name T591
Test name
Test status
Simulation time 53722501985 ps
CPU time 66.39 seconds
Started Mar 17 01:30:10 PM PDT 24
Finished Mar 17 01:31:17 PM PDT 24
Peak memory 240124 kb
Host smart-4e0031eb-195b-4b51-a32e-4fc7a71a8762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113454046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.1113454046
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.2678592039
Short name T720
Test name
Test status
Simulation time 10612337728 ps
CPU time 46.74 seconds
Started Mar 17 03:14:46 PM PDT 24
Finished Mar 17 03:15:33 PM PDT 24
Peak memory 235452 kb
Host smart-a174d623-352f-47c7-8f08-953e3176a4ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678592039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.2678592039
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_intercept.2298396165
Short name T193
Test name
Test status
Simulation time 2645674309 ps
CPU time 8.86 seconds
Started Mar 17 03:14:47 PM PDT 24
Finished Mar 17 03:14:56 PM PDT 24
Peak memory 224368 kb
Host smart-c68902c7-a06b-49dc-876f-d942fc20f11c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298396165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.2298396165
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1412459255
Short name T769
Test name
Test status
Simulation time 68698179919 ps
CPU time 44.61 seconds
Started Mar 17 03:14:43 PM PDT 24
Finished Mar 17 03:15:28 PM PDT 24
Peak memory 237260 kb
Host smart-b378953b-dc57-4732-ab5b-9197b82ee55d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412459255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1412459255
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.1929541813
Short name T870
Test name
Test status
Simulation time 155799072 ps
CPU time 3.6 seconds
Started Mar 17 01:30:01 PM PDT 24
Finished Mar 17 01:30:05 PM PDT 24
Peak memory 223960 kb
Host smart-97631ba5-192b-48dd-8579-bc0e12b768a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929541813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.1929541813
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_mem_parity.1305057318
Short name T579
Test name
Test status
Simulation time 45274880 ps
CPU time 1.11 seconds
Started Mar 17 01:30:01 PM PDT 24
Finished Mar 17 01:30:03 PM PDT 24
Peak memory 216480 kb
Host smart-74bc4adc-f463-4bd7-889a-6271ce3fbc94
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305057318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 15.spi_device_mem_parity.1305057318
Directory /workspace/15.spi_device_mem_parity/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1577064878
Short name T702
Test name
Test status
Simulation time 7700581229 ps
CPU time 11.17 seconds
Started Mar 17 01:30:01 PM PDT 24
Finished Mar 17 01:30:12 PM PDT 24
Peak memory 226828 kb
Host smart-89847614-87a9-4ad6-8127-55ad7006f27b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577064878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1577064878
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1820892843
Short name T556
Test name
Test status
Simulation time 996109738 ps
CPU time 4.79 seconds
Started Mar 17 03:14:44 PM PDT 24
Finished Mar 17 03:14:49 PM PDT 24
Peak memory 237312 kb
Host smart-4e4b80ac-ab34-49cf-86c3-43d931c012dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820892843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1820892843
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3271769875
Short name T1022
Test name
Test status
Simulation time 6981498584 ps
CPU time 10.5 seconds
Started Mar 17 01:30:10 PM PDT 24
Finished Mar 17 01:30:21 PM PDT 24
Peak memory 244496 kb
Host smart-348044b8-4a79-4308-8a8e-62f7af24224a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271769875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3271769875
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3557357145
Short name T367
Test name
Test status
Simulation time 8491545478 ps
CPU time 21.97 seconds
Started Mar 17 03:14:44 PM PDT 24
Finished Mar 17 03:15:06 PM PDT 24
Peak memory 224480 kb
Host smart-68bc53bc-007e-4d9e-b2c6-4753e558c270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557357145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3557357145
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.497404940
Short name T1184
Test name
Test status
Simulation time 39730199 ps
CPU time 0.76 seconds
Started Mar 17 01:30:02 PM PDT 24
Finished Mar 17 01:30:03 PM PDT 24
Peak memory 215824 kb
Host smart-08e999d1-7a05-4fa2-a60f-f2d82bb6f55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497404940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.497404940
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_ram_cfg.769583738
Short name T1075
Test name
Test status
Simulation time 19991590 ps
CPU time 0.76 seconds
Started Mar 17 03:14:43 PM PDT 24
Finished Mar 17 03:14:44 PM PDT 24
Peak memory 216048 kb
Host smart-3bd9a4b1-7e65-4b86-a785-b926692bb14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769583738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_ram_cfg.769583738
Directory /workspace/15.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1532291157
Short name T325
Test name
Test status
Simulation time 1252674613 ps
CPU time 3.36 seconds
Started Mar 17 01:30:02 PM PDT 24
Finished Mar 17 01:30:05 PM PDT 24
Peak memory 218232 kb
Host smart-5a2c458b-d8b0-49f0-8c0c-d1fca92fa83a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1532291157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1532291157
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.2322643748
Short name T1728
Test name
Test status
Simulation time 444184110 ps
CPU time 3.7 seconds
Started Mar 17 03:14:46 PM PDT 24
Finished Mar 17 03:14:50 PM PDT 24
Peak memory 221452 kb
Host smart-023567f8-dc09-473a-943a-34abedaf1e67
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2322643748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.2322643748
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.921976941
Short name T1211
Test name
Test status
Simulation time 32543467188 ps
CPU time 281.8 seconds
Started Mar 17 03:14:46 PM PDT 24
Finished Mar 17 03:19:28 PM PDT 24
Peak memory 262796 kb
Host smart-1ed158af-a7f3-41c9-a676-71a81b1f8872
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921976941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.921976941
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.289490364
Short name T286
Test name
Test status
Simulation time 6700233393 ps
CPU time 26.92 seconds
Started Mar 17 03:14:45 PM PDT 24
Finished Mar 17 03:15:13 PM PDT 24
Peak memory 220000 kb
Host smart-ad59ce87-f1f6-4b39-822d-f2d184c82f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289490364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.289490364
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.597779455
Short name T289
Test name
Test status
Simulation time 16531233422 ps
CPU time 30.62 seconds
Started Mar 17 01:30:01 PM PDT 24
Finished Mar 17 01:30:32 PM PDT 24
Peak memory 215820 kb
Host smart-574fe34c-8c14-4d84-befb-52a220c486eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=597779455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.597779455
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.786329685
Short name T75
Test name
Test status
Simulation time 7381434598 ps
CPU time 6.04 seconds
Started Mar 17 01:30:10 PM PDT 24
Finished Mar 17 01:30:16 PM PDT 24
Peak memory 215868 kb
Host smart-3445ff11-24f3-4af0-beee-96dfd59789a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786329685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.786329685
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.866979695
Short name T984
Test name
Test status
Simulation time 1703663237 ps
CPU time 11.27 seconds
Started Mar 17 03:14:41 PM PDT 24
Finished Mar 17 03:14:53 PM PDT 24
Peak memory 215936 kb
Host smart-737ba669-81a9-436e-a3a5-b4cbdf26a469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866979695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.866979695
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2671298375
Short name T1788
Test name
Test status
Simulation time 19331057 ps
CPU time 1.24 seconds
Started Mar 17 01:30:00 PM PDT 24
Finished Mar 17 01:30:02 PM PDT 24
Peak memory 215880 kb
Host smart-d2a4898e-a484-4443-88c1-849c81a769d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671298375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2671298375
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.4014955405
Short name T1421
Test name
Test status
Simulation time 84224652 ps
CPU time 1.18 seconds
Started Mar 17 03:14:44 PM PDT 24
Finished Mar 17 03:14:46 PM PDT 24
Peak memory 206996 kb
Host smart-583cc764-e22a-498e-a4b2-5331b55509ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014955405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.4014955405
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2625066895
Short name T480
Test name
Test status
Simulation time 135915116 ps
CPU time 0.78 seconds
Started Mar 17 03:14:46 PM PDT 24
Finished Mar 17 03:14:48 PM PDT 24
Peak memory 205444 kb
Host smart-f791ba9c-da95-407b-8240-d2d6375fe8c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625066895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2625066895
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.766650367
Short name T537
Test name
Test status
Simulation time 886904428 ps
CPU time 0.95 seconds
Started Mar 17 01:30:00 PM PDT 24
Finished Mar 17 01:30:01 PM PDT 24
Peak memory 205140 kb
Host smart-d4ba024d-215a-44a6-a994-f14ebe357666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766650367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.766650367
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2577247891
Short name T1812
Test name
Test status
Simulation time 1044467318 ps
CPU time 7.35 seconds
Started Mar 17 03:14:44 PM PDT 24
Finished Mar 17 03:14:52 PM PDT 24
Peak memory 218324 kb
Host smart-f2946f35-37b9-4fcd-8ff2-eb56cbfb8c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577247891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2577247891
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_upload.3800358521
Short name T629
Test name
Test status
Simulation time 33522458219 ps
CPU time 28.82 seconds
Started Mar 17 01:30:01 PM PDT 24
Finished Mar 17 01:30:30 PM PDT 24
Peak memory 231624 kb
Host smart-b59d758d-14d1-481a-9557-a0a25a6210bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800358521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.3800358521
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2663908978
Short name T414
Test name
Test status
Simulation time 15124983 ps
CPU time 0.72 seconds
Started Mar 17 01:30:12 PM PDT 24
Finished Mar 17 01:30:13 PM PDT 24
Peak memory 204804 kb
Host smart-5259bdab-9dcc-40a8-ab4f-00fcb7066846
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663908978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2663908978
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.3393174106
Short name T317
Test name
Test status
Simulation time 25179593 ps
CPU time 0.73 seconds
Started Mar 17 03:14:55 PM PDT 24
Finished Mar 17 03:14:56 PM PDT 24
Peak memory 205012 kb
Host smart-40e72e4f-78df-4705-8415-18f22076cca2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393174106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
3393174106
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1511491749
Short name T1602
Test name
Test status
Simulation time 231087452 ps
CPU time 3.69 seconds
Started Mar 17 01:30:06 PM PDT 24
Finished Mar 17 01:30:11 PM PDT 24
Peak memory 220408 kb
Host smart-38f8f98b-55d3-4002-977e-5c947519e16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511491749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1511491749
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.3393792883
Short name T1523
Test name
Test status
Simulation time 2424066824 ps
CPU time 9.4 seconds
Started Mar 17 03:14:54 PM PDT 24
Finished Mar 17 03:15:04 PM PDT 24
Peak memory 234312 kb
Host smart-702d457c-d1a0-45f6-8025-be7296b555c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393792883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3393792883
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1810266967
Short name T1594
Test name
Test status
Simulation time 29511188 ps
CPU time 0.76 seconds
Started Mar 17 03:14:44 PM PDT 24
Finished Mar 17 03:14:46 PM PDT 24
Peak memory 205472 kb
Host smart-329eb131-febb-4843-8038-b38b23a8384b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810266967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1810266967
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2447526657
Short name T1209
Test name
Test status
Simulation time 13487257 ps
CPU time 0.79 seconds
Started Mar 17 01:30:08 PM PDT 24
Finished Mar 17 01:30:09 PM PDT 24
Peak memory 206328 kb
Host smart-ff67b67f-db4c-40c8-a5e8-8687d986b703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447526657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2447526657
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.276042876
Short name T787
Test name
Test status
Simulation time 10903631234 ps
CPU time 27.95 seconds
Started Mar 17 03:14:56 PM PDT 24
Finished Mar 17 03:15:24 PM PDT 24
Peak memory 234932 kb
Host smart-b77ee291-deff-4acb-b64c-f6987c59e9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276042876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.276042876
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3908211166
Short name T586
Test name
Test status
Simulation time 21335283137 ps
CPU time 9.75 seconds
Started Mar 17 01:30:06 PM PDT 24
Finished Mar 17 01:30:17 PM PDT 24
Peak memory 234328 kb
Host smart-512ab0d5-b74d-41e4-98bd-e0c2da59d6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908211166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3908211166
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.1343667801
Short name T690
Test name
Test status
Simulation time 18848512246 ps
CPU time 102.42 seconds
Started Mar 17 03:14:53 PM PDT 24
Finished Mar 17 03:16:35 PM PDT 24
Peak memory 255296 kb
Host smart-215811de-ce2f-4af5-90c6-e4e816056724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343667801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1343667801
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.861462067
Short name T37
Test name
Test status
Simulation time 517139582082 ps
CPU time 421.88 seconds
Started Mar 17 01:30:07 PM PDT 24
Finished Mar 17 01:37:10 PM PDT 24
Peak memory 263844 kb
Host smart-d8b938cf-6d67-41fb-94b0-32bf1f8739c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861462067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle
.861462067
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.101544271
Short name T645
Test name
Test status
Simulation time 38999671494 ps
CPU time 53.22 seconds
Started Mar 17 01:30:08 PM PDT 24
Finished Mar 17 01:31:02 PM PDT 24
Peak memory 240208 kb
Host smart-f993510e-e757-4e9e-b79b-fdf773a6ade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101544271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.101544271
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.682016811
Short name T1612
Test name
Test status
Simulation time 9962308283 ps
CPU time 53.24 seconds
Started Mar 17 03:14:58 PM PDT 24
Finished Mar 17 03:15:51 PM PDT 24
Peak memory 240712 kb
Host smart-158dd7e6-ff29-4a59-8f22-6606a0eaab76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682016811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.682016811
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1304860743
Short name T1599
Test name
Test status
Simulation time 2329730149 ps
CPU time 6.19 seconds
Started Mar 17 01:30:06 PM PDT 24
Finished Mar 17 01:30:13 PM PDT 24
Peak memory 233008 kb
Host smart-4c40f4ec-fa28-4e03-8d62-03a0d29bf1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304860743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1304860743
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_intercept.291030662
Short name T955
Test name
Test status
Simulation time 15569645834 ps
CPU time 8.97 seconds
Started Mar 17 03:14:49 PM PDT 24
Finished Mar 17 03:14:58 PM PDT 24
Peak memory 219284 kb
Host smart-666849e8-e66c-4a46-ba64-ea25657fca69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291030662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.291030662
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.1567589652
Short name T344
Test name
Test status
Simulation time 2461804465 ps
CPU time 16.23 seconds
Started Mar 17 03:14:54 PM PDT 24
Finished Mar 17 03:15:10 PM PDT 24
Peak memory 245460 kb
Host smart-26777621-bfe8-47c0-b600-4a39bb9249ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567589652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1567589652
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2176911442
Short name T1618
Test name
Test status
Simulation time 9862580713 ps
CPU time 23.57 seconds
Started Mar 17 01:30:09 PM PDT 24
Finished Mar 17 01:30:33 PM PDT 24
Peak memory 228020 kb
Host smart-95e334a7-0467-477e-a5e0-3967f703eb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176911442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2176911442
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_mem_parity.2807953128
Short name T1435
Test name
Test status
Simulation time 25337628 ps
CPU time 1.08 seconds
Started Mar 17 01:30:09 PM PDT 24
Finished Mar 17 01:30:11 PM PDT 24
Peak memory 216352 kb
Host smart-01b1ebc8-f0ee-4b94-8165-9e01c8a48541
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807953128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 16.spi_device_mem_parity.2807953128
Directory /workspace/16.spi_device_mem_parity/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3420205365
Short name T262
Test name
Test status
Simulation time 446569683 ps
CPU time 3.81 seconds
Started Mar 17 01:30:08 PM PDT 24
Finished Mar 17 01:30:13 PM PDT 24
Peak memory 223964 kb
Host smart-a23be71b-c6c9-46f4-9749-71a1afa99ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420205365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3420205365
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.4258052709
Short name T785
Test name
Test status
Simulation time 4684317714 ps
CPU time 9.2 seconds
Started Mar 17 03:14:50 PM PDT 24
Finished Mar 17 03:15:00 PM PDT 24
Peak memory 224336 kb
Host smart-16503d64-e9e6-40da-872d-2ca1ea195363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258052709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.4258052709
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1478022039
Short name T801
Test name
Test status
Simulation time 3052318510 ps
CPU time 8.47 seconds
Started Mar 17 01:30:07 PM PDT 24
Finished Mar 17 01:30:17 PM PDT 24
Peak memory 240472 kb
Host smart-9acd4e57-49de-47b1-a9ad-2384e9dcfab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478022039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1478022039
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1986789751
Short name T1234
Test name
Test status
Simulation time 1070135005 ps
CPU time 5.17 seconds
Started Mar 17 03:14:48 PM PDT 24
Finished Mar 17 03:14:54 PM PDT 24
Peak memory 216656 kb
Host smart-8a8e146b-ab4a-4f65-b13d-e55afaba9aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986789751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1986789751
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.4039444441
Short name T1115
Test name
Test status
Simulation time 36571863 ps
CPU time 0.74 seconds
Started Mar 17 03:14:49 PM PDT 24
Finished Mar 17 03:14:50 PM PDT 24
Peak memory 216020 kb
Host smart-425162e7-f018-4704-ac7a-59eeb3b92757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039444441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.4039444441
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_ram_cfg.4227764627
Short name T1698
Test name
Test status
Simulation time 18654344 ps
CPU time 0.75 seconds
Started Mar 17 01:30:06 PM PDT 24
Finished Mar 17 01:30:08 PM PDT 24
Peak memory 215808 kb
Host smart-c17ada1f-6ae7-4cb4-900a-34ca12c556fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227764627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_ram_cfg.4227764627
Directory /workspace/16.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1937970734
Short name T1176
Test name
Test status
Simulation time 1397045999 ps
CPU time 3.85 seconds
Started Mar 17 03:14:54 PM PDT 24
Finished Mar 17 03:14:58 PM PDT 24
Peak memory 221584 kb
Host smart-7e1c27fb-56e3-4c45-b58c-813ffd7359fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1937970734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1937970734
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2819818769
Short name T1076
Test name
Test status
Simulation time 732071188 ps
CPU time 4.28 seconds
Started Mar 17 01:30:06 PM PDT 24
Finished Mar 17 01:30:11 PM PDT 24
Peak memory 219612 kb
Host smart-df272db5-1da9-4524-9f05-75b10f09c2d4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2819818769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2819818769
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2247507401
Short name T1171
Test name
Test status
Simulation time 199325996688 ps
CPU time 414.11 seconds
Started Mar 17 01:30:06 PM PDT 24
Finished Mar 17 01:37:02 PM PDT 24
Peak memory 273300 kb
Host smart-e4700a42-cecb-47c9-8817-1dd4b1320948
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247507401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2247507401
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2716342439
Short name T140
Test name
Test status
Simulation time 38491286994 ps
CPU time 262.54 seconds
Started Mar 17 03:14:54 PM PDT 24
Finished Mar 17 03:19:17 PM PDT 24
Peak memory 254824 kb
Host smart-803f07ad-7283-4f72-b130-0308acc5bc04
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2716342439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2716342439
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.1094862768
Short name T1208
Test name
Test status
Simulation time 8768308423 ps
CPU time 53.29 seconds
Started Mar 17 01:30:07 PM PDT 24
Finished Mar 17 01:31:02 PM PDT 24
Peak memory 215908 kb
Host smart-0141d49f-a204-4339-ac96-d002366f1745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094862768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.1094862768
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.700849587
Short name T1365
Test name
Test status
Simulation time 5670428801 ps
CPU time 33.14 seconds
Started Mar 17 03:14:49 PM PDT 24
Finished Mar 17 03:15:22 PM PDT 24
Peak memory 217636 kb
Host smart-780a1372-2d86-448f-8962-51151982c49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700849587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.700849587
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1420273395
Short name T1710
Test name
Test status
Simulation time 1586162854 ps
CPU time 9.44 seconds
Started Mar 17 01:30:09 PM PDT 24
Finished Mar 17 01:30:19 PM PDT 24
Peak memory 215908 kb
Host smart-472f33be-c8ae-47a7-aae8-d82105137e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420273395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1420273395
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.94973651
Short name T314
Test name
Test status
Simulation time 1397942146 ps
CPU time 7.19 seconds
Started Mar 17 03:14:48 PM PDT 24
Finished Mar 17 03:14:56 PM PDT 24
Peak memory 216108 kb
Host smart-8f6af015-7981-4f39-bce0-419deade497a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=94973651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.94973651
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1454933374
Short name T888
Test name
Test status
Simulation time 40908927 ps
CPU time 1.35 seconds
Started Mar 17 03:14:50 PM PDT 24
Finished Mar 17 03:14:52 PM PDT 24
Peak memory 216096 kb
Host smart-71a36be9-9713-46d0-8fc5-34c1d40a6349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454933374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1454933374
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.770944257
Short name T1546
Test name
Test status
Simulation time 40010104 ps
CPU time 2 seconds
Started Mar 17 01:30:08 PM PDT 24
Finished Mar 17 01:30:11 PM PDT 24
Peak memory 215952 kb
Host smart-73a05957-8498-4b9f-b68b-b49f3042c120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770944257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.770944257
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3809962634
Short name T804
Test name
Test status
Simulation time 176604960 ps
CPU time 0.77 seconds
Started Mar 17 03:14:50 PM PDT 24
Finished Mar 17 03:14:51 PM PDT 24
Peak memory 205384 kb
Host smart-458492c2-6855-49d2-9b80-794db6d7ecbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809962634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3809962634
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.762861688
Short name T6
Test name
Test status
Simulation time 24501217 ps
CPU time 0.74 seconds
Started Mar 17 01:30:08 PM PDT 24
Finished Mar 17 01:30:09 PM PDT 24
Peak memory 205084 kb
Host smart-988baf30-03a6-4901-8aa0-2df627a3d7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762861688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.762861688
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1606088970
Short name T762
Test name
Test status
Simulation time 641796824 ps
CPU time 3.92 seconds
Started Mar 17 03:14:53 PM PDT 24
Finished Mar 17 03:14:57 PM PDT 24
Peak memory 219684 kb
Host smart-30b21f3e-8226-4b15-9057-22b8832d7e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606088970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1606088970
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_upload.2751605570
Short name T1358
Test name
Test status
Simulation time 1021698706 ps
CPU time 9.88 seconds
Started Mar 17 01:30:07 PM PDT 24
Finished Mar 17 01:30:18 PM PDT 24
Peak memory 232688 kb
Host smart-c8ca3582-ea51-4980-805c-d6e8d2136568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751605570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2751605570
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.1054742774
Short name T918
Test name
Test status
Simulation time 16704056 ps
CPU time 0.71 seconds
Started Mar 17 01:30:15 PM PDT 24
Finished Mar 17 01:30:16 PM PDT 24
Peak memory 204876 kb
Host smart-f9c8edda-6e76-44ca-a000-7dbe2c034cae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054742774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
1054742774
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.3718841752
Short name T1579
Test name
Test status
Simulation time 37940978 ps
CPU time 0.74 seconds
Started Mar 17 03:14:56 PM PDT 24
Finished Mar 17 03:14:57 PM PDT 24
Peak memory 205056 kb
Host smart-f93394af-11c4-4d76-8788-fdf9bc9c056a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718841752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
3718841752
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.174455597
Short name T1849
Test name
Test status
Simulation time 3381491417 ps
CPU time 4.07 seconds
Started Mar 17 01:30:12 PM PDT 24
Finished Mar 17 01:30:17 PM PDT 24
Peak memory 224164 kb
Host smart-99b192cf-1ff1-4422-b438-68cef2cf781f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174455597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.174455597
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.711160923
Short name T896
Test name
Test status
Simulation time 676225479 ps
CPU time 4.08 seconds
Started Mar 17 03:15:02 PM PDT 24
Finished Mar 17 03:15:07 PM PDT 24
Peak memory 218708 kb
Host smart-949c1070-479c-4119-a615-e4363084fa55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711160923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.711160923
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1607957731
Short name T932
Test name
Test status
Simulation time 18772238 ps
CPU time 0.78 seconds
Started Mar 17 03:14:53 PM PDT 24
Finished Mar 17 03:14:54 PM PDT 24
Peak memory 206124 kb
Host smart-aa3f4535-6b41-48ed-a074-76ddc0fef28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607957731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1607957731
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3309460889
Short name T957
Test name
Test status
Simulation time 15079257 ps
CPU time 0.74 seconds
Started Mar 17 01:30:13 PM PDT 24
Finished Mar 17 01:30:14 PM PDT 24
Peak memory 205272 kb
Host smart-cf3edaef-940b-4b29-b387-f681983570ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309460889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3309460889
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2668874898
Short name T378
Test name
Test status
Simulation time 4036214664 ps
CPU time 25.26 seconds
Started Mar 17 01:30:14 PM PDT 24
Finished Mar 17 01:30:40 PM PDT 24
Peak memory 248420 kb
Host smart-18518931-b362-4418-82e7-aa7a83ac782e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668874898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2668874898
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.795865039
Short name T604
Test name
Test status
Simulation time 37781178487 ps
CPU time 216.55 seconds
Started Mar 17 03:14:58 PM PDT 24
Finished Mar 17 03:18:35 PM PDT 24
Peak memory 261848 kb
Host smart-2a98c0e4-9474-4faf-a0dc-411c74ee2463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795865039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.795865039
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1579068934
Short name T1002
Test name
Test status
Simulation time 890309269600 ps
CPU time 361.96 seconds
Started Mar 17 01:30:15 PM PDT 24
Finished Mar 17 01:36:17 PM PDT 24
Peak memory 266228 kb
Host smart-60995a09-1858-4a0f-8fe0-60defcbbcfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579068934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1579068934
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.3451324413
Short name T435
Test name
Test status
Simulation time 2365183335 ps
CPU time 38.78 seconds
Started Mar 17 03:14:56 PM PDT 24
Finished Mar 17 03:15:35 PM PDT 24
Peak memory 234212 kb
Host smart-a81a8672-5bea-462d-9698-0d6520b7c322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451324413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.3451324413
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.2588255823
Short name T757
Test name
Test status
Simulation time 26891460249 ps
CPU time 202.77 seconds
Started Mar 17 03:15:02 PM PDT 24
Finished Mar 17 03:18:25 PM PDT 24
Peak memory 249044 kb
Host smart-236ca5e9-1e5c-425d-80ae-93cf466fe288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588255823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.2588255823
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.986836102
Short name T18
Test name
Test status
Simulation time 59683031402 ps
CPU time 201.88 seconds
Started Mar 17 01:30:15 PM PDT 24
Finished Mar 17 01:33:37 PM PDT 24
Peak memory 257032 kb
Host smart-98a78e8b-469a-448e-86c5-017dd2e65830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986836102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.986836102
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3136821593
Short name T1660
Test name
Test status
Simulation time 1030186294 ps
CPU time 11.37 seconds
Started Mar 17 01:30:14 PM PDT 24
Finished Mar 17 01:30:25 PM PDT 24
Peak memory 229952 kb
Host smart-50ea2ba5-86f1-416a-abd4-3e27df7dc935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136821593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3136821593
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3155572849
Short name T901
Test name
Test status
Simulation time 30087956311 ps
CPU time 27.51 seconds
Started Mar 17 03:14:59 PM PDT 24
Finished Mar 17 03:15:27 PM PDT 24
Peak memory 255336 kb
Host smart-13e91eff-8b67-4118-ad97-4230b5eab6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155572849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3155572849
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.3540318998
Short name T434
Test name
Test status
Simulation time 1465993889 ps
CPU time 4.92 seconds
Started Mar 17 03:14:57 PM PDT 24
Finished Mar 17 03:15:02 PM PDT 24
Peak memory 217428 kb
Host smart-a9be4481-9a27-42b5-b383-113c1d9dfaea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540318998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.3540318998
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_intercept.4146016305
Short name T1292
Test name
Test status
Simulation time 23870181756 ps
CPU time 10.4 seconds
Started Mar 17 01:30:15 PM PDT 24
Finished Mar 17 01:30:26 PM PDT 24
Peak memory 233328 kb
Host smart-618d4d37-d9e1-47fb-9b07-d48091337893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146016305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.4146016305
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.2163840253
Short name T357
Test name
Test status
Simulation time 13579687878 ps
CPU time 21.48 seconds
Started Mar 17 03:14:56 PM PDT 24
Finished Mar 17 03:15:18 PM PDT 24
Peak memory 218212 kb
Host smart-f7902ed1-660b-4b8d-97c8-7c60932328f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163840253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.2163840253
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.559371601
Short name T382
Test name
Test status
Simulation time 3121483220 ps
CPU time 9.95 seconds
Started Mar 17 01:30:13 PM PDT 24
Finished Mar 17 01:30:23 PM PDT 24
Peak memory 232176 kb
Host smart-fa942a40-e050-4043-aaea-8bb8b9eee590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559371601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.559371601
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_mem_parity.4157550387
Short name T616
Test name
Test status
Simulation time 30344995 ps
CPU time 1.04 seconds
Started Mar 17 01:30:15 PM PDT 24
Finished Mar 17 01:30:16 PM PDT 24
Peak memory 217704 kb
Host smart-190a23f9-d7cc-4818-985a-c6c50bff41ee
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157550387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 17.spi_device_mem_parity.4157550387
Directory /workspace/17.spi_device_mem_parity/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1224254512
Short name T1250
Test name
Test status
Simulation time 7575517977 ps
CPU time 18.63 seconds
Started Mar 17 03:14:59 PM PDT 24
Finished Mar 17 03:15:17 PM PDT 24
Peak memory 219376 kb
Host smart-679c1d9e-77b4-4d4a-b1a6-d5399cf70b34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224254512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1224254512
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.339372324
Short name T1442
Test name
Test status
Simulation time 5998133300 ps
CPU time 6.93 seconds
Started Mar 17 01:30:16 PM PDT 24
Finished Mar 17 01:30:23 PM PDT 24
Peak memory 217948 kb
Host smart-11182728-7c38-4fb1-a03e-596847dac5a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339372324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap
.339372324
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.1384280828
Short name T1318
Test name
Test status
Simulation time 678036096 ps
CPU time 5.63 seconds
Started Mar 17 03:15:03 PM PDT 24
Finished Mar 17 03:15:09 PM PDT 24
Peak memory 234780 kb
Host smart-24870cbd-2e0c-4f93-b69b-cc6fac04989b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1384280828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1384280828
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2669653517
Short name T541
Test name
Test status
Simulation time 16525458391 ps
CPU time 13.99 seconds
Started Mar 17 01:30:14 PM PDT 24
Finished Mar 17 01:30:28 PM PDT 24
Peak memory 236864 kb
Host smart-bf5b6f42-b6c0-4b68-8507-d650159bdbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669653517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2669653517
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.2217326859
Short name T981
Test name
Test status
Simulation time 28385124 ps
CPU time 0.75 seconds
Started Mar 17 01:30:14 PM PDT 24
Finished Mar 17 01:30:15 PM PDT 24
Peak memory 215752 kb
Host smart-1e2c1732-4bad-458f-bf2f-887601b7a222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217326859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.2217326859
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_ram_cfg.2878895140
Short name T56
Test name
Test status
Simulation time 57588978 ps
CPU time 0.75 seconds
Started Mar 17 03:14:53 PM PDT 24
Finished Mar 17 03:14:53 PM PDT 24
Peak memory 215996 kb
Host smart-b8df7f7c-727f-4a28-8470-807349a96ffe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2878895140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_ram_cfg.2878895140
Directory /workspace/17.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1129779445
Short name T549
Test name
Test status
Simulation time 1172452298 ps
CPU time 4.46 seconds
Started Mar 17 01:30:14 PM PDT 24
Finished Mar 17 01:30:19 PM PDT 24
Peak memory 218220 kb
Host smart-451bc7e0-b050-4b52-ae14-6a9399b4a31f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1129779445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1129779445
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2031605591
Short name T1120
Test name
Test status
Simulation time 1040156981 ps
CPU time 6.33 seconds
Started Mar 17 03:14:58 PM PDT 24
Finished Mar 17 03:15:04 PM PDT 24
Peak memory 221960 kb
Host smart-ff07082b-a23b-4ba0-a663-29bbadda6586
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2031605591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2031605591
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.888051707
Short name T1199
Test name
Test status
Simulation time 8319655169 ps
CPU time 79.98 seconds
Started Mar 17 03:14:58 PM PDT 24
Finished Mar 17 03:16:19 PM PDT 24
Peak memory 257196 kb
Host smart-1656fe28-e8e6-43ed-b207-b0578aab2fa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888051707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stres
s_all.888051707
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.2341621312
Short name T469
Test name
Test status
Simulation time 9209226483 ps
CPU time 20.45 seconds
Started Mar 17 03:14:57 PM PDT 24
Finished Mar 17 03:15:17 PM PDT 24
Peak memory 218140 kb
Host smart-2bf0a0ed-a037-4be8-9d32-d349d17f623a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341621312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.2341621312
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.92712270
Short name T1826
Test name
Test status
Simulation time 12509607361 ps
CPU time 45.22 seconds
Started Mar 17 01:30:13 PM PDT 24
Finished Mar 17 01:30:58 PM PDT 24
Peak memory 215940 kb
Host smart-7c5821b9-9b33-43c5-ba2e-09edd707339a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92712270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.92712270
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3572200802
Short name T1882
Test name
Test status
Simulation time 455798661 ps
CPU time 1.2 seconds
Started Mar 17 01:30:12 PM PDT 24
Finished Mar 17 01:30:14 PM PDT 24
Peak memory 206256 kb
Host smart-0b6ddd54-77d2-47a6-a25e-eb6d6e9950b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572200802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3572200802
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.3829348501
Short name T1189
Test name
Test status
Simulation time 2758607516 ps
CPU time 2.66 seconds
Started Mar 17 03:14:53 PM PDT 24
Finished Mar 17 03:14:56 PM PDT 24
Peak memory 207632 kb
Host smart-06ca9115-a8cc-4602-b949-10250652c469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829348501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3829348501
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.528413267
Short name T736
Test name
Test status
Simulation time 913477253 ps
CPU time 3.65 seconds
Started Mar 17 03:15:00 PM PDT 24
Finished Mar 17 03:15:04 PM PDT 24
Peak memory 216000 kb
Host smart-9c41ec80-1433-4e91-95f9-9fc6f705e202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528413267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.528413267
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.853688188
Short name T1889
Test name
Test status
Simulation time 74269702 ps
CPU time 1.76 seconds
Started Mar 17 01:30:16 PM PDT 24
Finished Mar 17 01:30:17 PM PDT 24
Peak memory 215928 kb
Host smart-e32926db-def0-4872-9c93-cf91c5e4d9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853688188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.853688188
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1812826509
Short name T1475
Test name
Test status
Simulation time 87651024 ps
CPU time 0.92 seconds
Started Mar 17 01:30:12 PM PDT 24
Finished Mar 17 01:30:13 PM PDT 24
Peak memory 205232 kb
Host smart-b825296b-9595-47ca-9458-244b9ab23573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812826509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1812826509
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1905366521
Short name T1799
Test name
Test status
Simulation time 82766991 ps
CPU time 0.99 seconds
Started Mar 17 03:14:58 PM PDT 24
Finished Mar 17 03:14:59 PM PDT 24
Peak memory 205428 kb
Host smart-54705367-270a-471a-8afd-085c2a20c1c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905366521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1905366521
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1166399811
Short name T1736
Test name
Test status
Simulation time 22623849487 ps
CPU time 11.34 seconds
Started Mar 17 01:30:12 PM PDT 24
Finished Mar 17 01:30:24 PM PDT 24
Peak memory 234712 kb
Host smart-406bb629-32c9-48d7-86b2-db932af2c83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166399811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1166399811
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_upload.1168290402
Short name T760
Test name
Test status
Simulation time 530660606 ps
CPU time 5 seconds
Started Mar 17 03:14:58 PM PDT 24
Finished Mar 17 03:15:03 PM PDT 24
Peak memory 218332 kb
Host smart-4db32168-2e34-49a2-9e96-39dc221a3dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168290402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1168290402
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.216052701
Short name T1456
Test name
Test status
Simulation time 12298507 ps
CPU time 0.7 seconds
Started Mar 17 01:30:18 PM PDT 24
Finished Mar 17 01:30:19 PM PDT 24
Peak memory 204256 kb
Host smart-ebd6c13c-1e5b-47d3-9d5b-0cf6a3608606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216052701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.216052701
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.2686504639
Short name T1326
Test name
Test status
Simulation time 30506088 ps
CPU time 0.7 seconds
Started Mar 17 03:15:07 PM PDT 24
Finished Mar 17 03:15:08 PM PDT 24
Peak memory 205364 kb
Host smart-ed25fe26-2be2-4de3-a83d-465768d97146
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686504639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
2686504639
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.1648293257
Short name T1625
Test name
Test status
Simulation time 586364106 ps
CPU time 3.43 seconds
Started Mar 17 03:15:03 PM PDT 24
Finished Mar 17 03:15:07 PM PDT 24
Peak memory 234584 kb
Host smart-1dc6955d-2e9d-4db9-a7e2-9758309b0f3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648293257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.1648293257
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.562263790
Short name T214
Test name
Test status
Simulation time 4229537415 ps
CPU time 6.05 seconds
Started Mar 17 01:30:21 PM PDT 24
Finished Mar 17 01:30:27 PM PDT 24
Peak memory 233516 kb
Host smart-59bfbe8d-9533-453d-bf74-0c7a55d5a898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562263790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.562263790
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1385857834
Short name T1361
Test name
Test status
Simulation time 20518528 ps
CPU time 0.79 seconds
Started Mar 17 01:30:15 PM PDT 24
Finished Mar 17 01:30:16 PM PDT 24
Peak memory 205972 kb
Host smart-67db0ea0-c757-494c-bdb0-a3eef8b706d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385857834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1385857834
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.364298681
Short name T1465
Test name
Test status
Simulation time 12682373 ps
CPU time 0.77 seconds
Started Mar 17 03:15:02 PM PDT 24
Finished Mar 17 03:15:03 PM PDT 24
Peak memory 206204 kb
Host smart-ca623233-aa63-421b-9aed-ca3ca895fbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364298681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.364298681
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3241042425
Short name T1597
Test name
Test status
Simulation time 7588031917 ps
CPU time 13.48 seconds
Started Mar 17 03:15:02 PM PDT 24
Finished Mar 17 03:15:15 PM PDT 24
Peak memory 221828 kb
Host smart-ff8606c0-3d8e-4ec0-b622-098eea0caa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241042425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3241042425
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.4060006274
Short name T1859
Test name
Test status
Simulation time 5661302021 ps
CPU time 50.57 seconds
Started Mar 17 01:30:21 PM PDT 24
Finished Mar 17 01:31:12 PM PDT 24
Peak memory 248728 kb
Host smart-c1c5824f-74ca-447b-8d0a-d943a2b21e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060006274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.4060006274
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3363663134
Short name T1751
Test name
Test status
Simulation time 41236068521 ps
CPU time 313.59 seconds
Started Mar 17 03:15:02 PM PDT 24
Finished Mar 17 03:20:16 PM PDT 24
Peak memory 250280 kb
Host smart-8d18f3d8-1218-42d8-a8dc-b79b04362371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363663134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3363663134
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.4289900523
Short name T200
Test name
Test status
Simulation time 4719380003 ps
CPU time 63.76 seconds
Started Mar 17 01:30:19 PM PDT 24
Finished Mar 17 01:31:22 PM PDT 24
Peak memory 254124 kb
Host smart-20cdf94b-63d6-45b2-b82b-c08febf4ef98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289900523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.4289900523
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1563979224
Short name T1052
Test name
Test status
Simulation time 67045058735 ps
CPU time 133.39 seconds
Started Mar 17 01:30:18 PM PDT 24
Finished Mar 17 01:32:32 PM PDT 24
Peak memory 248256 kb
Host smart-1d888cc3-2603-4a75-9467-43813d654543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563979224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1563979224
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.3982804103
Short name T1658
Test name
Test status
Simulation time 47291592710 ps
CPU time 126.97 seconds
Started Mar 17 03:15:05 PM PDT 24
Finished Mar 17 03:17:13 PM PDT 24
Peak memory 265896 kb
Host smart-4ad73b93-dcd1-41ee-9b37-16794684cb03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982804103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.3982804103
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.270187903
Short name T1080
Test name
Test status
Simulation time 1946402316 ps
CPU time 15.49 seconds
Started Mar 17 01:30:28 PM PDT 24
Finished Mar 17 01:30:44 PM PDT 24
Peak memory 249584 kb
Host smart-b30a0aa1-abbf-419d-86d6-7071f9b60095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270187903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.270187903
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3708574300
Short name T666
Test name
Test status
Simulation time 54529221994 ps
CPU time 36.76 seconds
Started Mar 17 03:15:02 PM PDT 24
Finished Mar 17 03:15:40 PM PDT 24
Peak memory 248232 kb
Host smart-0a83ec5f-4830-45c6-893c-dd3c4f465ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708574300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3708574300
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.273885777
Short name T323
Test name
Test status
Simulation time 338580754 ps
CPU time 2.57 seconds
Started Mar 17 01:30:29 PM PDT 24
Finished Mar 17 01:30:32 PM PDT 24
Peak memory 217920 kb
Host smart-2b18bd49-12ba-4734-86bd-2ad47d7cc1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273885777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.273885777
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_intercept.725785601
Short name T873
Test name
Test status
Simulation time 2052035852 ps
CPU time 7.91 seconds
Started Mar 17 03:15:03 PM PDT 24
Finished Mar 17 03:15:11 PM PDT 24
Peak memory 219576 kb
Host smart-9a5bf61e-a6d7-48b1-9876-c09c6f361b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725785601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.725785601
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3572852999
Short name T1800
Test name
Test status
Simulation time 133164468 ps
CPU time 2.96 seconds
Started Mar 17 03:15:03 PM PDT 24
Finished Mar 17 03:15:06 PM PDT 24
Peak memory 233488 kb
Host smart-754fe599-b1b4-4dc1-be0f-45667d515526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572852999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3572852999
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.819216576
Short name T1777
Test name
Test status
Simulation time 7895625123 ps
CPU time 30.23 seconds
Started Mar 17 01:30:29 PM PDT 24
Finished Mar 17 01:31:00 PM PDT 24
Peak memory 236896 kb
Host smart-52da3835-b969-4125-9542-99fc4573593d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=819216576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.819216576
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_mem_parity.3083634045
Short name T1232
Test name
Test status
Simulation time 61231104 ps
CPU time 1.08 seconds
Started Mar 17 01:30:17 PM PDT 24
Finished Mar 17 01:30:18 PM PDT 24
Peak memory 216496 kb
Host smart-0c7fa35f-a595-45cf-9703-c0ced4839792
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083634045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 18.spi_device_mem_parity.3083634045
Directory /workspace/18.spi_device_mem_parity/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.653006686
Short name T243
Test name
Test status
Simulation time 401191015 ps
CPU time 7.09 seconds
Started Mar 17 03:15:01 PM PDT 24
Finished Mar 17 03:15:09 PM PDT 24
Peak memory 234372 kb
Host smart-7a2a6675-906c-495a-9de0-d1b42d05594e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653006686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap
.653006686
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.91746085
Short name T544
Test name
Test status
Simulation time 570322769 ps
CPU time 5.09 seconds
Started Mar 17 01:30:27 PM PDT 24
Finished Mar 17 01:30:33 PM PDT 24
Peak memory 237676 kb
Host smart-03516936-f818-49cd-8027-7f7964595479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91746085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.91746085
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1301334246
Short name T979
Test name
Test status
Simulation time 1104423999 ps
CPU time 3.73 seconds
Started Mar 17 03:15:03 PM PDT 24
Finished Mar 17 03:15:07 PM PDT 24
Peak memory 216552 kb
Host smart-1fb2294e-cd8e-4ee0-9364-7285b7e485e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1301334246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1301334246
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.2125212892
Short name T1775
Test name
Test status
Simulation time 401601150 ps
CPU time 4.11 seconds
Started Mar 17 01:30:22 PM PDT 24
Finished Mar 17 01:30:26 PM PDT 24
Peak memory 224120 kb
Host smart-2884dfb8-a389-4be9-81ca-d88cce9c7305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125212892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2125212892
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.3938632366
Short name T615
Test name
Test status
Simulation time 25633534 ps
CPU time 0.73 seconds
Started Mar 17 03:14:59 PM PDT 24
Finished Mar 17 03:14:59 PM PDT 24
Peak memory 216044 kb
Host smart-75bd902f-1903-4b55-b22a-f16b758a375b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938632366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.3938632366
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_ram_cfg.3984198773
Short name T1891
Test name
Test status
Simulation time 24299106 ps
CPU time 0.71 seconds
Started Mar 17 01:30:12 PM PDT 24
Finished Mar 17 01:30:13 PM PDT 24
Peak memory 215772 kb
Host smart-fcccd308-69f1-4f6e-9c93-eeab2aac3a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984198773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_ram_cfg.3984198773
Directory /workspace/18.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2825993219
Short name T128
Test name
Test status
Simulation time 2300708470 ps
CPU time 5.17 seconds
Started Mar 17 01:30:18 PM PDT 24
Finished Mar 17 01:30:23 PM PDT 24
Peak memory 218596 kb
Host smart-ee428ccd-132b-413f-ad7c-acd9edb2fb87
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2825993219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2825993219
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.4221114413
Short name T348
Test name
Test status
Simulation time 131577373 ps
CPU time 3.05 seconds
Started Mar 17 03:15:03 PM PDT 24
Finished Mar 17 03:15:06 PM PDT 24
Peak memory 218432 kb
Host smart-b51babf8-c0b0-4c42-98a0-c626694b199b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4221114413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.4221114413
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.4161926688
Short name T139
Test name
Test status
Simulation time 2631246732 ps
CPU time 37.1 seconds
Started Mar 17 01:30:21 PM PDT 24
Finished Mar 17 01:30:58 PM PDT 24
Peak memory 248812 kb
Host smart-464163b7-74b5-44f5-a23a-279671422466
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161926688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.4161926688
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.4274764309
Short name T1646
Test name
Test status
Simulation time 73322299949 ps
CPU time 554.54 seconds
Started Mar 17 03:15:08 PM PDT 24
Finished Mar 17 03:24:22 PM PDT 24
Peak memory 252040 kb
Host smart-c3df0696-8d97-4ff8-918c-5366a97f1734
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274764309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.4274764309
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3645355808
Short name T601
Test name
Test status
Simulation time 115648436616 ps
CPU time 48.03 seconds
Started Mar 17 01:30:17 PM PDT 24
Finished Mar 17 01:31:05 PM PDT 24
Peak memory 215992 kb
Host smart-9dbdf63b-587b-4c07-ae69-a62dbae3b272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645355808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3645355808
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.602951852
Short name T1589
Test name
Test status
Simulation time 23650610818 ps
CPU time 72.74 seconds
Started Mar 17 03:15:02 PM PDT 24
Finished Mar 17 03:16:15 PM PDT 24
Peak memory 216212 kb
Host smart-77db4b70-9256-4817-ad7b-210c0b21b7a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602951852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.602951852
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2846301135
Short name T1097
Test name
Test status
Simulation time 2574902820 ps
CPU time 10.69 seconds
Started Mar 17 03:15:00 PM PDT 24
Finished Mar 17 03:15:11 PM PDT 24
Peak memory 215912 kb
Host smart-7ea12aec-7b44-4ad1-862b-185212c5c7b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846301135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2846301135
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.3701671017
Short name T1422
Test name
Test status
Simulation time 64964595 ps
CPU time 1.01 seconds
Started Mar 17 01:30:13 PM PDT 24
Finished Mar 17 01:30:14 PM PDT 24
Peak memory 205372 kb
Host smart-68baa72b-edfa-4c4c-bc6b-b89ae666f119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3701671017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3701671017
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2103004083
Short name T893
Test name
Test status
Simulation time 24238318 ps
CPU time 1.27 seconds
Started Mar 17 03:15:01 PM PDT 24
Finished Mar 17 03:15:03 PM PDT 24
Peak memory 216028 kb
Host smart-8f5e2ceb-f1c9-4ca9-8022-8a9d61f3f14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103004083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2103004083
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2430130413
Short name T630
Test name
Test status
Simulation time 383890309 ps
CPU time 4.26 seconds
Started Mar 17 01:30:19 PM PDT 24
Finished Mar 17 01:30:23 PM PDT 24
Peak memory 216124 kb
Host smart-75c2b7b5-dbee-4e45-a2e9-40595dae8507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430130413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2430130413
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.2701644056
Short name T1868
Test name
Test status
Simulation time 49655234 ps
CPU time 0.9 seconds
Started Mar 17 01:30:19 PM PDT 24
Finished Mar 17 01:30:20 PM PDT 24
Peak memory 206144 kb
Host smart-eedaee61-c1cc-4867-88a1-f7df9a75bba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701644056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.2701644056
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.3632255972
Short name T1379
Test name
Test status
Simulation time 19060471 ps
CPU time 0.78 seconds
Started Mar 17 03:15:05 PM PDT 24
Finished Mar 17 03:15:05 PM PDT 24
Peak memory 205388 kb
Host smart-e1e13480-6c5a-47e2-9670-06837f2199a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3632255972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3632255972
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.3230839867
Short name T1448
Test name
Test status
Simulation time 883478608 ps
CPU time 10.39 seconds
Started Mar 17 03:15:03 PM PDT 24
Finished Mar 17 03:15:14 PM PDT 24
Peak memory 234032 kb
Host smart-ab64e8d9-e61e-4eaf-a53b-74f2023c4441
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230839867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.3230839867
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_upload.4003522768
Short name T1308
Test name
Test status
Simulation time 1604299485 ps
CPU time 10.57 seconds
Started Mar 17 01:30:18 PM PDT 24
Finished Mar 17 01:30:29 PM PDT 24
Peak memory 234492 kb
Host smart-6006ca04-8136-49f9-8e8e-fef1128ec9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003522768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.4003522768
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.358512753
Short name T1412
Test name
Test status
Simulation time 23470731 ps
CPU time 0.69 seconds
Started Mar 17 01:30:28 PM PDT 24
Finished Mar 17 01:30:29 PM PDT 24
Peak memory 204220 kb
Host smart-cfda59a6-1470-471c-921b-a5b84eb7cbfb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358512753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.358512753
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.647848820
Short name T1877
Test name
Test status
Simulation time 54691292 ps
CPU time 0.77 seconds
Started Mar 17 03:15:13 PM PDT 24
Finished Mar 17 03:15:14 PM PDT 24
Peak memory 205068 kb
Host smart-dea581da-d7d9-4daa-a730-f172bd756f0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647848820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.647848820
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3213707629
Short name T1217
Test name
Test status
Simulation time 43186311 ps
CPU time 2.54 seconds
Started Mar 17 03:15:12 PM PDT 24
Finished Mar 17 03:15:14 PM PDT 24
Peak memory 234028 kb
Host smart-c976aa87-91c3-45df-8cd3-427508782238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213707629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3213707629
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.858113687
Short name T1036
Test name
Test status
Simulation time 72161203 ps
CPU time 2.77 seconds
Started Mar 17 01:30:20 PM PDT 24
Finished Mar 17 01:30:23 PM PDT 24
Peak memory 233212 kb
Host smart-08976d4a-7d36-4c7f-bbad-93fb1c810dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858113687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.858113687
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3293373342
Short name T1094
Test name
Test status
Simulation time 18355532 ps
CPU time 0.75 seconds
Started Mar 17 01:30:23 PM PDT 24
Finished Mar 17 01:30:23 PM PDT 24
Peak memory 204932 kb
Host smart-f8b3f6de-a076-497b-8b60-42bbf6c28bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293373342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3293373342
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.891276988
Short name T1460
Test name
Test status
Simulation time 15093820 ps
CPU time 0.8 seconds
Started Mar 17 03:15:11 PM PDT 24
Finished Mar 17 03:15:12 PM PDT 24
Peak memory 206176 kb
Host smart-79b61b5c-0009-4619-8037-789d47f8b9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891276988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.891276988
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.2238222179
Short name T1388
Test name
Test status
Simulation time 90422278366 ps
CPU time 75.07 seconds
Started Mar 17 03:15:11 PM PDT 24
Finished Mar 17 03:16:26 PM PDT 24
Peak memory 256116 kb
Host smart-ebd3e7a8-7f8d-4f9f-8f04-2e937b933151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238222179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.2238222179
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3442996947
Short name T177
Test name
Test status
Simulation time 57071616787 ps
CPU time 77.82 seconds
Started Mar 17 01:30:26 PM PDT 24
Finished Mar 17 01:31:44 PM PDT 24
Peak memory 248712 kb
Host smart-87df4075-ac8f-4217-83a6-d4caaf1a6320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442996947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3442996947
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.126674310
Short name T833
Test name
Test status
Simulation time 5199774845 ps
CPU time 55.33 seconds
Started Mar 17 01:30:28 PM PDT 24
Finished Mar 17 01:31:24 PM PDT 24
Peak memory 232516 kb
Host smart-ea8680ba-29aa-4280-8da3-4f818bc23b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126674310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.126674310
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.2644008198
Short name T271
Test name
Test status
Simulation time 59946713112 ps
CPU time 261.55 seconds
Started Mar 17 03:15:12 PM PDT 24
Finished Mar 17 03:19:34 PM PDT 24
Peak memory 262172 kb
Host smart-f53bc337-aba3-4a5f-a352-f90cea2ec5a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644008198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2644008198
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3708488200
Short name T793
Test name
Test status
Simulation time 63333880852 ps
CPU time 65.68 seconds
Started Mar 17 03:15:11 PM PDT 24
Finished Mar 17 03:16:17 PM PDT 24
Peak memory 249044 kb
Host smart-22b6e809-1da4-4c0b-bd02-d27c7c0bcb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708488200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3708488200
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.4062653703
Short name T919
Test name
Test status
Simulation time 50401272494 ps
CPU time 372.16 seconds
Started Mar 17 01:30:26 PM PDT 24
Finished Mar 17 01:36:39 PM PDT 24
Peak memory 264736 kb
Host smart-b236a164-07fc-4fe1-854d-523795507561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062653703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.4062653703
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1672833103
Short name T1395
Test name
Test status
Simulation time 4100743321 ps
CPU time 6.12 seconds
Started Mar 17 01:30:25 PM PDT 24
Finished Mar 17 01:30:31 PM PDT 24
Peak memory 249656 kb
Host smart-b086fae2-8041-4f68-81ba-eee16d59b27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672833103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1672833103
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.2435688480
Short name T1369
Test name
Test status
Simulation time 7338593408 ps
CPU time 37.6 seconds
Started Mar 17 03:15:13 PM PDT 24
Finished Mar 17 03:15:51 PM PDT 24
Peak memory 238696 kb
Host smart-6d421bdb-0b05-467f-b405-51a27f64b693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435688480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2435688480
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3070691459
Short name T1575
Test name
Test status
Simulation time 1626744231 ps
CPU time 6.36 seconds
Started Mar 17 03:15:07 PM PDT 24
Finished Mar 17 03:15:13 PM PDT 24
Peak memory 233772 kb
Host smart-1bfee45b-29c8-49e7-ac38-5370db7d7817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070691459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3070691459
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_intercept.3389041195
Short name T880
Test name
Test status
Simulation time 1567750520 ps
CPU time 5.75 seconds
Started Mar 17 01:30:18 PM PDT 24
Finished Mar 17 01:30:24 PM PDT 24
Peak memory 238432 kb
Host smart-829dfe7f-bc70-439a-a72d-37b503690c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389041195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.3389041195
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.2129126637
Short name T1268
Test name
Test status
Simulation time 595756120 ps
CPU time 5.94 seconds
Started Mar 17 01:30:17 PM PDT 24
Finished Mar 17 01:30:23 PM PDT 24
Peak memory 226220 kb
Host smart-fa1be9e6-6239-484d-af6f-8e04ce980145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2129126637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2129126637
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3040875700
Short name T1066
Test name
Test status
Simulation time 5325251188 ps
CPU time 10.19 seconds
Started Mar 17 03:15:11 PM PDT 24
Finished Mar 17 03:15:22 PM PDT 24
Peak memory 236248 kb
Host smart-28e99c91-7214-420f-90bf-5fdd999f25c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040875700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3040875700
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_mem_parity.736924703
Short name T1498
Test name
Test status
Simulation time 24066382 ps
CPU time 0.98 seconds
Started Mar 17 01:30:19 PM PDT 24
Finished Mar 17 01:30:21 PM PDT 24
Peak memory 217776 kb
Host smart-c6caa10b-5f9a-483a-8eee-5970089ef48d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736924703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
19.spi_device_mem_parity.736924703
Directory /workspace/19.spi_device_mem_parity/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.234832657
Short name T1853
Test name
Test status
Simulation time 4012858383 ps
CPU time 3.69 seconds
Started Mar 17 01:30:22 PM PDT 24
Finished Mar 17 01:30:26 PM PDT 24
Peak memory 233288 kb
Host smart-c6a90462-0fcc-41b9-863c-171da0ea2602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234832657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.234832657
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.769883868
Short name T1246
Test name
Test status
Simulation time 2446778861 ps
CPU time 15.82 seconds
Started Mar 17 03:15:06 PM PDT 24
Finished Mar 17 03:15:22 PM PDT 24
Peak memory 239768 kb
Host smart-e6c7b299-9eb6-4668-a68b-d070888ed452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769883868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.769883868
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1199002242
Short name T1463
Test name
Test status
Simulation time 7654732528 ps
CPU time 13.85 seconds
Started Mar 17 01:30:29 PM PDT 24
Finished Mar 17 01:30:43 PM PDT 24
Peak memory 232340 kb
Host smart-5908fcfb-0eca-4647-9976-4cb94f21e107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199002242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1199002242
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2736253822
Short name T1455
Test name
Test status
Simulation time 249105533 ps
CPU time 5.06 seconds
Started Mar 17 03:15:10 PM PDT 24
Finished Mar 17 03:15:15 PM PDT 24
Peak memory 232976 kb
Host smart-62d37bd6-8789-4d6a-a47d-c736cafd8ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736253822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2736253822
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.3415700444
Short name T538
Test name
Test status
Simulation time 17875742 ps
CPU time 0.81 seconds
Started Mar 17 03:15:07 PM PDT 24
Finished Mar 17 03:15:08 PM PDT 24
Peak memory 216004 kb
Host smart-081ff8b8-ab2d-4361-b834-41cb6649c9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415700444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.3415700444
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_ram_cfg.3838057141
Short name T506
Test name
Test status
Simulation time 78213474 ps
CPU time 0.76 seconds
Started Mar 17 01:30:19 PM PDT 24
Finished Mar 17 01:30:20 PM PDT 24
Peak memory 215768 kb
Host smart-8eba41af-7a1e-4fba-878b-ba51a87bee54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838057141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_ram_cfg.3838057141
Directory /workspace/19.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3046787385
Short name T637
Test name
Test status
Simulation time 19138126287 ps
CPU time 5.61 seconds
Started Mar 17 03:15:14 PM PDT 24
Finished Mar 17 03:15:19 PM PDT 24
Peak memory 220012 kb
Host smart-b52168d8-b1da-44f3-96c1-e7b716e34783
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3046787385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3046787385
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.616392855
Short name T1724
Test name
Test status
Simulation time 3255571009 ps
CPU time 4.38 seconds
Started Mar 17 01:30:25 PM PDT 24
Finished Mar 17 01:30:29 PM PDT 24
Peak memory 222000 kb
Host smart-82d9a495-2efb-4961-a3ea-7285d1241e1e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=616392855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.616392855
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3305950774
Short name T49
Test name
Test status
Simulation time 42610699 ps
CPU time 0.93 seconds
Started Mar 17 03:15:13 PM PDT 24
Finished Mar 17 03:15:14 PM PDT 24
Peak memory 206216 kb
Host smart-e162f6e8-ae28-49d0-b428-1ab9eea577c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305950774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3305950774
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.3343151930
Short name T963
Test name
Test status
Simulation time 48994707 ps
CPU time 1.03 seconds
Started Mar 17 01:30:26 PM PDT 24
Finished Mar 17 01:30:27 PM PDT 24
Peak memory 206620 kb
Host smart-8a487af1-ecbb-45d5-bba6-ffd413fd9daa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343151930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.3343151930
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2357876586
Short name T296
Test name
Test status
Simulation time 9047094816 ps
CPU time 25.75 seconds
Started Mar 17 01:30:29 PM PDT 24
Finished Mar 17 01:30:55 PM PDT 24
Peak memory 215956 kb
Host smart-9e6c7902-a815-4835-beb6-4beabb9a2b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357876586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2357876586
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2449109500
Short name T580
Test name
Test status
Simulation time 63528599393 ps
CPU time 56.82 seconds
Started Mar 17 03:15:07 PM PDT 24
Finished Mar 17 03:16:04 PM PDT 24
Peak memory 216116 kb
Host smart-8e2b4680-623f-4554-83e6-c53e3e1d69c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449109500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2449109500
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.2612538312
Short name T602
Test name
Test status
Simulation time 6342804912 ps
CPU time 20.66 seconds
Started Mar 17 01:30:19 PM PDT 24
Finished Mar 17 01:30:40 PM PDT 24
Peak memory 215936 kb
Host smart-64be44ba-45c2-4cbb-92a0-8c93c193971e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612538312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2612538312
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.3858508068
Short name T1186
Test name
Test status
Simulation time 562340744 ps
CPU time 3.4 seconds
Started Mar 17 03:15:07 PM PDT 24
Finished Mar 17 03:15:11 PM PDT 24
Peak memory 215944 kb
Host smart-ce9f66a4-3b60-4388-9092-a4a517f474c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858508068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.3858508068
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2339505477
Short name T806
Test name
Test status
Simulation time 72943334 ps
CPU time 1.5 seconds
Started Mar 17 01:30:18 PM PDT 24
Finished Mar 17 01:30:20 PM PDT 24
Peak memory 215872 kb
Host smart-58a63e43-9d99-49c1-8c75-349fbf8d7616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339505477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2339505477
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3099886635
Short name T915
Test name
Test status
Simulation time 161696936 ps
CPU time 1.36 seconds
Started Mar 17 03:15:07 PM PDT 24
Finished Mar 17 03:15:09 PM PDT 24
Peak memory 207632 kb
Host smart-eed12210-6568-4b7e-87cf-5e44bf6a17e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099886635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3099886635
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2472020721
Short name T1748
Test name
Test status
Simulation time 133214143 ps
CPU time 1.12 seconds
Started Mar 17 01:30:18 PM PDT 24
Finished Mar 17 01:30:20 PM PDT 24
Peak memory 205596 kb
Host smart-accdb6a7-9249-4036-b876-ec8fbbdaa7c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472020721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2472020721
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.271517230
Short name T859
Test name
Test status
Simulation time 80785341 ps
CPU time 0.81 seconds
Started Mar 17 03:15:11 PM PDT 24
Finished Mar 17 03:15:12 PM PDT 24
Peak memory 205448 kb
Host smart-da1058f9-0a96-465b-9261-b8340442328d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271517230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.271517230
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2093425113
Short name T1560
Test name
Test status
Simulation time 348075409 ps
CPU time 3.48 seconds
Started Mar 17 01:30:17 PM PDT 24
Finished Mar 17 01:30:21 PM PDT 24
Peak memory 224044 kb
Host smart-37a8c2c2-891c-4a8f-b22e-0954e2aebe37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093425113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2093425113
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_upload.4245726324
Short name T1182
Test name
Test status
Simulation time 73336944038 ps
CPU time 28.76 seconds
Started Mar 17 03:15:11 PM PDT 24
Finished Mar 17 03:15:40 PM PDT 24
Peak memory 232568 kb
Host smart-a5b0553e-147f-4953-a2c3-c34a1b4e3712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245726324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.4245726324
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1999188047
Short name T748
Test name
Test status
Simulation time 107853665 ps
CPU time 0.69 seconds
Started Mar 17 03:13:06 PM PDT 24
Finished Mar 17 03:13:07 PM PDT 24
Peak memory 205032 kb
Host smart-feb4a2f9-439b-42c3-b275-37d5c6d41db0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999188047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
999188047
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4262689803
Short name T682
Test name
Test status
Simulation time 17098413 ps
CPU time 0.71 seconds
Started Mar 17 01:28:48 PM PDT 24
Finished Mar 17 01:28:49 PM PDT 24
Peak memory 204836 kb
Host smart-b4b3de07-9196-424b-acea-8348e6eb10d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262689803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
262689803
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1355594447
Short name T1663
Test name
Test status
Simulation time 320043190 ps
CPU time 2.83 seconds
Started Mar 17 03:13:03 PM PDT 24
Finished Mar 17 03:13:06 PM PDT 24
Peak memory 224236 kb
Host smart-6d8a3b1d-2faf-4154-beac-9769248c8f27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355594447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1355594447
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1763148009
Short name T1485
Test name
Test status
Simulation time 376586233 ps
CPU time 3.1 seconds
Started Mar 17 01:28:46 PM PDT 24
Finished Mar 17 01:28:49 PM PDT 24
Peak memory 217584 kb
Host smart-379363ae-52bb-43fb-860c-6e933e989df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1763148009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1763148009
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.3511085488
Short name T783
Test name
Test status
Simulation time 22054542 ps
CPU time 0.81 seconds
Started Mar 17 01:28:41 PM PDT 24
Finished Mar 17 01:28:42 PM PDT 24
Peak memory 206004 kb
Host smart-29a18273-dd93-43bf-9c8d-013887abd096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511085488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3511085488
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.86102367
Short name T1703
Test name
Test status
Simulation time 166602107 ps
CPU time 0.75 seconds
Started Mar 17 03:12:59 PM PDT 24
Finished Mar 17 03:13:01 PM PDT 24
Peak memory 205196 kb
Host smart-dba45794-7c46-43dd-87dc-21599f943ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86102367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.86102367
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.19523027
Short name T457
Test name
Test status
Simulation time 2901273815 ps
CPU time 14.14 seconds
Started Mar 17 01:28:47 PM PDT 24
Finished Mar 17 01:29:01 PM PDT 24
Peak memory 237020 kb
Host smart-255baed0-6404-4068-ad3c-cf6f4865290d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19523027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.19523027
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1924185303
Short name T5
Test name
Test status
Simulation time 40581213793 ps
CPU time 260.06 seconds
Started Mar 17 01:28:47 PM PDT 24
Finished Mar 17 01:33:07 PM PDT 24
Peak memory 261364 kb
Host smart-ce3fcc41-7fd0-4309-8efd-deef7cddc561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924185303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1924185303
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2865207252
Short name T253
Test name
Test status
Simulation time 94413167512 ps
CPU time 492.5 seconds
Started Mar 17 03:13:04 PM PDT 24
Finished Mar 17 03:21:16 PM PDT 24
Peak memory 281696 kb
Host smart-2d405018-5280-4d0e-b0ce-0733bc254f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865207252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2865207252
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1430296033
Short name T123
Test name
Test status
Simulation time 50141350381 ps
CPU time 95.8 seconds
Started Mar 17 01:28:47 PM PDT 24
Finished Mar 17 01:30:23 PM PDT 24
Peak memory 256592 kb
Host smart-eb2d7c32-1973-4ee4-8466-bd0eb2ab2158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1430296033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1430296033
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1940148597
Short name T1472
Test name
Test status
Simulation time 54618291741 ps
CPU time 415.94 seconds
Started Mar 17 03:13:03 PM PDT 24
Finished Mar 17 03:19:59 PM PDT 24
Peak memory 264568 kb
Host smart-76f7da43-ae6a-4715-ab1e-eff7a1033631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940148597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1940148597
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3429398588
Short name T1041
Test name
Test status
Simulation time 6643495024 ps
CPU time 32.04 seconds
Started Mar 17 01:28:50 PM PDT 24
Finished Mar 17 01:29:22 PM PDT 24
Peak memory 231780 kb
Host smart-b19e1e0a-fd55-4299-8ee2-25a26347206e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429398588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3429398588
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3342527409
Short name T406
Test name
Test status
Simulation time 19177954770 ps
CPU time 8.93 seconds
Started Mar 17 01:28:43 PM PDT 24
Finished Mar 17 01:28:53 PM PDT 24
Peak memory 233396 kb
Host smart-5a0be657-df1d-4883-b638-a175ef639737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342527409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3342527409
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_intercept.507378984
Short name T738
Test name
Test status
Simulation time 3179116271 ps
CPU time 4.57 seconds
Started Mar 17 03:13:07 PM PDT 24
Finished Mar 17 03:13:11 PM PDT 24
Peak memory 219512 kb
Host smart-d5c1f569-cb63-4f69-ae65-5f18bd68fae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507378984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.507378984
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1975296784
Short name T1847
Test name
Test status
Simulation time 6349284485 ps
CPU time 7.83 seconds
Started Mar 17 03:13:07 PM PDT 24
Finished Mar 17 03:13:14 PM PDT 24
Peak memory 236300 kb
Host smart-d1fa0951-84f3-4e75-80ec-4dedf4ae4f53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975296784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1975296784
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3666914286
Short name T1141
Test name
Test status
Simulation time 763046870 ps
CPU time 8.42 seconds
Started Mar 17 01:28:40 PM PDT 24
Finished Mar 17 01:28:49 PM PDT 24
Peak memory 217880 kb
Host smart-56a6092c-5cdc-4ace-8a7a-ca28e1339fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666914286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3666914286
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_mem_parity.789033747
Short name T1511
Test name
Test status
Simulation time 32248981 ps
CPU time 1.06 seconds
Started Mar 17 01:28:41 PM PDT 24
Finished Mar 17 01:28:42 PM PDT 24
Peak memory 216492 kb
Host smart-4e98db0b-5395-4ad7-9119-3527167990bd
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789033747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
2.spi_device_mem_parity.789033747
Directory /workspace/2.spi_device_mem_parity/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2575990100
Short name T233
Test name
Test status
Simulation time 393648106 ps
CPU time 2.83 seconds
Started Mar 17 01:28:42 PM PDT 24
Finished Mar 17 01:28:46 PM PDT 24
Peak memory 218016 kb
Host smart-24e3eb70-152a-45b6-af56-9b5841df170f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575990100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2575990100
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.3833612802
Short name T1140
Test name
Test status
Simulation time 8346046571 ps
CPU time 8.08 seconds
Started Mar 17 03:12:59 PM PDT 24
Finished Mar 17 03:13:08 PM PDT 24
Peak memory 217524 kb
Host smart-0d786f18-e0aa-42d2-9455-0fc664374e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833612802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.3833612802
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2371011637
Short name T391
Test name
Test status
Simulation time 50400086541 ps
CPU time 39.24 seconds
Started Mar 17 03:12:59 PM PDT 24
Finished Mar 17 03:13:39 PM PDT 24
Peak memory 252288 kb
Host smart-8c091d2a-e88f-4c6e-969d-88c7cf099011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371011637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2371011637
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.376422251
Short name T1129
Test name
Test status
Simulation time 2026723245 ps
CPU time 9.22 seconds
Started Mar 17 01:28:42 PM PDT 24
Finished Mar 17 01:28:52 PM PDT 24
Peak memory 233196 kb
Host smart-9978d6ab-d5f1-4ce8-b371-b40e96f28d76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376422251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.376422251
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.2469244028
Short name T1502
Test name
Test status
Simulation time 41599916 ps
CPU time 0.74 seconds
Started Mar 17 01:28:40 PM PDT 24
Finished Mar 17 01:28:41 PM PDT 24
Peak memory 215752 kb
Host smart-5585da5e-27e6-4257-ae6a-e9a7dc6c39c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469244028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.2469244028
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_ram_cfg.4035740760
Short name T55
Test name
Test status
Simulation time 24035814 ps
CPU time 0.76 seconds
Started Mar 17 03:12:59 PM PDT 24
Finished Mar 17 03:13:00 PM PDT 24
Peak memory 216024 kb
Host smart-e26907bd-392a-4a1d-84da-c19b7a3491e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035740760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_ram_cfg.4035740760
Directory /workspace/2.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.1334972553
Short name T362
Test name
Test status
Simulation time 2920145644 ps
CPU time 6.28 seconds
Started Mar 17 03:13:03 PM PDT 24
Finished Mar 17 03:13:10 PM PDT 24
Peak memory 222640 kb
Host smart-4220bad9-e0f8-4ca1-8eac-9b119826a707
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1334972553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.1334972553
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.3712018196
Short name T343
Test name
Test status
Simulation time 198178597 ps
CPU time 4.19 seconds
Started Mar 17 01:28:48 PM PDT 24
Finished Mar 17 01:28:53 PM PDT 24
Peak memory 222324 kb
Host smart-192184ad-1ff5-4595-84f9-f6d21a401ec2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3712018196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.3712018196
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2224983085
Short name T59
Test name
Test status
Simulation time 131345308 ps
CPU time 1.08 seconds
Started Mar 17 01:28:47 PM PDT 24
Finished Mar 17 01:28:48 PM PDT 24
Peak memory 235096 kb
Host smart-86aac45b-68e6-4c3e-aaf3-3fe1026bb621
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224983085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2224983085
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.4089315794
Short name T64
Test name
Test status
Simulation time 38360206 ps
CPU time 0.99 seconds
Started Mar 17 03:13:06 PM PDT 24
Finished Mar 17 03:13:07 PM PDT 24
Peak memory 234900 kb
Host smart-f0ab8f14-7feb-4992-a545-1cdc1f84c018
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089315794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.4089315794
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.2691341837
Short name T567
Test name
Test status
Simulation time 49783619366 ps
CPU time 107.33 seconds
Started Mar 17 03:13:06 PM PDT 24
Finished Mar 17 03:14:53 PM PDT 24
Peak memory 251060 kb
Host smart-4535b341-406d-4155-9dbd-224fefd7cbc7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691341837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.2691341837
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3202041957
Short name T1633
Test name
Test status
Simulation time 4366820181 ps
CPU time 22.83 seconds
Started Mar 17 01:28:41 PM PDT 24
Finished Mar 17 01:29:04 PM PDT 24
Peak memory 216088 kb
Host smart-03cb1151-34a3-49c0-9cab-c15c0b434702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202041957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3202041957
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.776212718
Short name T685
Test name
Test status
Simulation time 12559811164 ps
CPU time 27.46 seconds
Started Mar 17 03:12:58 PM PDT 24
Finished Mar 17 03:13:26 PM PDT 24
Peak memory 216124 kb
Host smart-fa577a33-d3f9-43e1-8d2d-339a9499b4ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776212718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.776212718
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2626367091
Short name T313
Test name
Test status
Simulation time 130937708 ps
CPU time 1.68 seconds
Started Mar 17 01:28:43 PM PDT 24
Finished Mar 17 01:28:46 PM PDT 24
Peak memory 207488 kb
Host smart-07763457-9b2e-4ed4-9a58-8a4e196b5a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626367091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2626367091
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2990557147
Short name T330
Test name
Test status
Simulation time 974472517 ps
CPU time 6.89 seconds
Started Mar 17 03:12:58 PM PDT 24
Finished Mar 17 03:13:05 PM PDT 24
Peak memory 216000 kb
Host smart-66da4ddc-8c1a-4278-8f6b-2ba25278c1e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990557147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2990557147
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3025849072
Short name T1177
Test name
Test status
Simulation time 455483491 ps
CPU time 4.16 seconds
Started Mar 17 03:13:01 PM PDT 24
Finished Mar 17 03:13:05 PM PDT 24
Peak memory 216132 kb
Host smart-fb7fa892-abdc-4921-b42a-3bbca56aa86a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025849072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3025849072
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3945551442
Short name T686
Test name
Test status
Simulation time 526207854 ps
CPU time 3.89 seconds
Started Mar 17 01:28:42 PM PDT 24
Finished Mar 17 01:28:47 PM PDT 24
Peak memory 215824 kb
Host smart-0f3319e3-4a97-41ba-a4c5-8e44873aba66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945551442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3945551442
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3560203313
Short name T975
Test name
Test status
Simulation time 123002784 ps
CPU time 0.86 seconds
Started Mar 17 01:28:43 PM PDT 24
Finished Mar 17 01:28:45 PM PDT 24
Peak memory 205136 kb
Host smart-9cd25415-c294-49d6-974a-bd7478670c35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560203313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3560203313
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.3609143516
Short name T958
Test name
Test status
Simulation time 515004632 ps
CPU time 1.13 seconds
Started Mar 17 03:12:58 PM PDT 24
Finished Mar 17 03:12:59 PM PDT 24
Peak memory 206400 kb
Host smart-424112f6-388c-442c-a2a0-afbc6901f02c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609143516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.3609143516
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1287016722
Short name T1267
Test name
Test status
Simulation time 46003964698 ps
CPU time 38.21 seconds
Started Mar 17 03:13:06 PM PDT 24
Finished Mar 17 03:13:44 PM PDT 24
Peak memory 243320 kb
Host smart-cdcb7825-35bd-44d0-a932-b08d651537d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287016722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1287016722
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_upload.761385978
Short name T851
Test name
Test status
Simulation time 5580481924 ps
CPU time 11.62 seconds
Started Mar 17 01:28:51 PM PDT 24
Finished Mar 17 01:29:03 PM PDT 24
Peak memory 223940 kb
Host smart-c9af4a99-7b4c-48ab-8910-4cee39d25ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761385978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.761385978
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3199907898
Short name T1045
Test name
Test status
Simulation time 17634770 ps
CPU time 0.73 seconds
Started Mar 17 01:30:30 PM PDT 24
Finished Mar 17 01:30:32 PM PDT 24
Peak memory 205196 kb
Host smart-bc240314-2d6d-4da3-89e6-db351bc17e22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199907898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3199907898
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3974836932
Short name T1354
Test name
Test status
Simulation time 21870570 ps
CPU time 0.71 seconds
Started Mar 17 03:15:15 PM PDT 24
Finished Mar 17 03:15:15 PM PDT 24
Peak memory 204428 kb
Host smart-6d792939-76fb-419b-8b62-543f0f967f70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974836932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3974836932
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2738871718
Short name T1131
Test name
Test status
Simulation time 793853965 ps
CPU time 2.44 seconds
Started Mar 17 01:30:30 PM PDT 24
Finished Mar 17 01:30:33 PM PDT 24
Peak memory 217948 kb
Host smart-934bfbb4-1eb4-4918-aaf6-3d34d4357c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738871718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2738871718
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2858011170
Short name T1406
Test name
Test status
Simulation time 191336759 ps
CPU time 3.2 seconds
Started Mar 17 03:15:18 PM PDT 24
Finished Mar 17 03:15:22 PM PDT 24
Peak memory 233224 kb
Host smart-8a04d8a4-0140-4f48-ab8f-7071762c5ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858011170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2858011170
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3166739275
Short name T906
Test name
Test status
Simulation time 66910461 ps
CPU time 0.78 seconds
Started Mar 17 01:30:28 PM PDT 24
Finished Mar 17 01:30:29 PM PDT 24
Peak memory 204980 kb
Host smart-994d60a9-a019-4a15-bc6c-d5d4aa4b69ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166739275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3166739275
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.3697729685
Short name T1875
Test name
Test status
Simulation time 30571281 ps
CPU time 0.75 seconds
Started Mar 17 03:15:12 PM PDT 24
Finished Mar 17 03:15:13 PM PDT 24
Peak memory 205456 kb
Host smart-9bd86958-9ee6-4670-985b-6ad7aa1e4a21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697729685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.3697729685
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1293635413
Short name T1007
Test name
Test status
Simulation time 1224561622 ps
CPU time 4.79 seconds
Started Mar 17 03:15:16 PM PDT 24
Finished Mar 17 03:15:20 PM PDT 24
Peak memory 236716 kb
Host smart-d11f006e-6fcc-4bec-8ca2-f210869c88d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293635413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1293635413
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1323131853
Short name T155
Test name
Test status
Simulation time 12438751948 ps
CPU time 53.8 seconds
Started Mar 17 01:30:30 PM PDT 24
Finished Mar 17 01:31:25 PM PDT 24
Peak memory 255516 kb
Host smart-717a668a-343a-4e4c-bcab-6213264f27e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323131853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1323131853
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.3768397608
Short name T43
Test name
Test status
Simulation time 151086715853 ps
CPU time 592.3 seconds
Started Mar 17 03:15:17 PM PDT 24
Finished Mar 17 03:25:09 PM PDT 24
Peak memory 257184 kb
Host smart-24896be0-5c9e-43e6-a7ae-28957a985897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768397608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.3768397608
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.632217703
Short name T259
Test name
Test status
Simulation time 18740549414 ps
CPU time 105.16 seconds
Started Mar 17 01:30:31 PM PDT 24
Finished Mar 17 01:32:18 PM PDT 24
Peak memory 251068 kb
Host smart-c5b55f04-a4dc-4b01-8846-53c1016b5edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632217703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.632217703
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.1557101774
Short name T269
Test name
Test status
Simulation time 8565053036 ps
CPU time 82.82 seconds
Started Mar 17 01:30:39 PM PDT 24
Finished Mar 17 01:32:02 PM PDT 24
Peak memory 262792 kb
Host smart-a72d4e3d-e8e2-44cc-b1e9-a96d6da097bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1557101774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.1557101774
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.264344124
Short name T1474
Test name
Test status
Simulation time 48236671986 ps
CPU time 364.83 seconds
Started Mar 17 03:15:16 PM PDT 24
Finished Mar 17 03:21:21 PM PDT 24
Peak memory 255688 kb
Host smart-64dc503e-19c2-4a6a-8a4f-3317dcb21309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264344124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.264344124
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.26914553
Short name T279
Test name
Test status
Simulation time 25456406970 ps
CPU time 35.23 seconds
Started Mar 17 03:15:16 PM PDT 24
Finished Mar 17 03:15:51 PM PDT 24
Peak memory 224348 kb
Host smart-60f5d2eb-0be1-42e0-81db-2d51998e0b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26914553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.26914553
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.60493967
Short name T973
Test name
Test status
Simulation time 8869863826 ps
CPU time 36.44 seconds
Started Mar 17 01:30:33 PM PDT 24
Finished Mar 17 01:31:11 PM PDT 24
Peak memory 234804 kb
Host smart-c2684d1d-5912-407c-a618-63b9df1a5214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60493967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.60493967
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.1712108394
Short name T1290
Test name
Test status
Simulation time 697851666 ps
CPU time 4.89 seconds
Started Mar 17 01:30:32 PM PDT 24
Finished Mar 17 01:30:38 PM PDT 24
Peak memory 233660 kb
Host smart-688904c8-d80c-4c49-af4f-35cb9f91e4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712108394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.1712108394
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3846285493
Short name T1122
Test name
Test status
Simulation time 1739362864 ps
CPU time 3.65 seconds
Started Mar 17 03:15:15 PM PDT 24
Finished Mar 17 03:15:19 PM PDT 24
Peak memory 218508 kb
Host smart-f3876f07-a478-4213-a86c-cbc930c5f160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846285493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3846285493
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.1144967880
Short name T711
Test name
Test status
Simulation time 4497476183 ps
CPU time 18.01 seconds
Started Mar 17 01:30:31 PM PDT 24
Finished Mar 17 01:30:50 PM PDT 24
Peak memory 229196 kb
Host smart-4eae8539-6b93-465f-923e-da7b5f759702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144967880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.1144967880
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.680523264
Short name T226
Test name
Test status
Simulation time 4691658371 ps
CPU time 18.67 seconds
Started Mar 17 03:15:15 PM PDT 24
Finished Mar 17 03:15:34 PM PDT 24
Peak memory 240440 kb
Host smart-85484a33-f26e-4d3c-b7cd-1ac92f5a0f66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=680523264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.680523264
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1145157473
Short name T1344
Test name
Test status
Simulation time 539011425 ps
CPU time 4.85 seconds
Started Mar 17 01:30:25 PM PDT 24
Finished Mar 17 01:30:30 PM PDT 24
Peak memory 235512 kb
Host smart-41ad1cd3-08b1-4d5d-a6d5-455028cc9cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145157473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1145157473
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.1759332920
Short name T1257
Test name
Test status
Simulation time 1277819690 ps
CPU time 2.95 seconds
Started Mar 17 03:15:13 PM PDT 24
Finished Mar 17 03:15:16 PM PDT 24
Peak memory 224228 kb
Host smart-2b4dbe97-e619-4896-8974-2983b22e548f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759332920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.1759332920
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1651877537
Short name T327
Test name
Test status
Simulation time 11192932307 ps
CPU time 10.52 seconds
Started Mar 17 01:30:24 PM PDT 24
Finished Mar 17 01:30:35 PM PDT 24
Peak memory 217056 kb
Host smart-250ae1f4-41bb-4b9a-9d50-0ae74dadee21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651877537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1651877537
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.3474964354
Short name T1592
Test name
Test status
Simulation time 479461707 ps
CPU time 7.86 seconds
Started Mar 17 03:15:11 PM PDT 24
Finished Mar 17 03:15:19 PM PDT 24
Peak memory 232884 kb
Host smart-9841bf12-b4c8-4b38-82e9-0e55e5847802
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474964354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3474964354
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2656893062
Short name T902
Test name
Test status
Simulation time 1926779044 ps
CPU time 5.32 seconds
Started Mar 17 01:30:32 PM PDT 24
Finished Mar 17 01:30:39 PM PDT 24
Peak memory 219640 kb
Host smart-0efb9408-8fa7-4fa9-8e18-1205accde000
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2656893062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2656893062
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2943501528
Short name T354
Test name
Test status
Simulation time 2400613791 ps
CPU time 4.56 seconds
Started Mar 17 03:15:14 PM PDT 24
Finished Mar 17 03:15:19 PM PDT 24
Peak memory 219620 kb
Host smart-41ea5ea3-7bf1-4b59-b0f7-1e654efbbd56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2943501528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2943501528
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2772131517
Short name T1603
Test name
Test status
Simulation time 38951372 ps
CPU time 1.01 seconds
Started Mar 17 01:30:30 PM PDT 24
Finished Mar 17 01:30:32 PM PDT 24
Peak memory 206368 kb
Host smart-a960f563-428a-4ee5-9ac3-f0b3d1b5a7df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772131517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2772131517
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.1371639928
Short name T924
Test name
Test status
Simulation time 8863596998 ps
CPU time 42.63 seconds
Started Mar 17 01:30:28 PM PDT 24
Finished Mar 17 01:31:11 PM PDT 24
Peak memory 215856 kb
Host smart-5e7c8d82-3b55-4104-84d3-94a17094a12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371639928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1371639928
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.2206647604
Short name T1555
Test name
Test status
Simulation time 1342926928 ps
CPU time 13.97 seconds
Started Mar 17 03:15:12 PM PDT 24
Finished Mar 17 03:15:26 PM PDT 24
Peak memory 216072 kb
Host smart-568ae9a3-e81d-44c0-9f86-4287faabd2e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206647604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.2206647604
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1368583923
Short name T1865
Test name
Test status
Simulation time 1446934497 ps
CPU time 3.78 seconds
Started Mar 17 01:30:28 PM PDT 24
Finished Mar 17 01:30:32 PM PDT 24
Peak memory 215760 kb
Host smart-f922eb1b-a97a-4dda-b68b-725f704d4fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1368583923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1368583923
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.4114753546
Short name T297
Test name
Test status
Simulation time 2726497047 ps
CPU time 7.41 seconds
Started Mar 17 03:15:10 PM PDT 24
Finished Mar 17 03:15:18 PM PDT 24
Peak memory 216032 kb
Host smart-21ca683e-8c03-4844-9ec6-dfd50e40cc08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114753546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.4114753546
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.258103468
Short name T545
Test name
Test status
Simulation time 84270786 ps
CPU time 3.56 seconds
Started Mar 17 01:30:25 PM PDT 24
Finished Mar 17 01:30:29 PM PDT 24
Peak memory 215868 kb
Host smart-243214f3-912a-4b83-9840-21eef6027fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258103468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.258103468
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.2939802578
Short name T961
Test name
Test status
Simulation time 511148383 ps
CPU time 4.43 seconds
Started Mar 17 03:15:10 PM PDT 24
Finished Mar 17 03:15:15 PM PDT 24
Peak memory 216084 kb
Host smart-27dfe33d-d81f-48fd-8486-8fcb26ee516f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939802578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.2939802578
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.3920461617
Short name T548
Test name
Test status
Simulation time 70275506 ps
CPU time 0.78 seconds
Started Mar 17 01:30:28 PM PDT 24
Finished Mar 17 01:30:29 PM PDT 24
Peak memory 205176 kb
Host smart-31d418e7-e085-47b7-81fc-b19b673a8061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920461617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3920461617
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.4054762058
Short name T485
Test name
Test status
Simulation time 305180739 ps
CPU time 1 seconds
Started Mar 17 03:15:11 PM PDT 24
Finished Mar 17 03:15:12 PM PDT 24
Peak memory 205432 kb
Host smart-f77e625f-49f2-434d-af97-61be571cccee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054762058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.4054762058
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.3275178988
Short name T1339
Test name
Test status
Simulation time 393735518 ps
CPU time 4.26 seconds
Started Mar 17 01:30:36 PM PDT 24
Finished Mar 17 01:30:41 PM PDT 24
Peak memory 219300 kb
Host smart-af083fef-b3d1-4d4c-ae9f-25c456f8e195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275178988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3275178988
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_upload.3650681156
Short name T1038
Test name
Test status
Simulation time 942717056 ps
CPU time 5.96 seconds
Started Mar 17 03:15:16 PM PDT 24
Finished Mar 17 03:15:22 PM PDT 24
Peak memory 235060 kb
Host smart-ec649472-b166-4828-a8b5-985b6fbc0061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650681156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.3650681156
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.1174062831
Short name T970
Test name
Test status
Simulation time 16253843 ps
CPU time 0.75 seconds
Started Mar 17 03:15:19 PM PDT 24
Finished Mar 17 03:15:20 PM PDT 24
Peak memory 204956 kb
Host smart-0d69ae2d-0a69-4131-b064-2088815f45e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174062831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
1174062831
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.835399387
Short name T1637
Test name
Test status
Simulation time 32816919 ps
CPU time 0.7 seconds
Started Mar 17 01:30:37 PM PDT 24
Finished Mar 17 01:30:38 PM PDT 24
Peak memory 204224 kb
Host smart-a8dae51a-0447-435e-9ebb-9d5f962f658d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835399387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.835399387
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2839230456
Short name T1719
Test name
Test status
Simulation time 196540071 ps
CPU time 3.03 seconds
Started Mar 17 01:30:30 PM PDT 24
Finished Mar 17 01:30:34 PM PDT 24
Peak memory 233480 kb
Host smart-46ec4f67-3636-4063-9c14-27c74709e8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839230456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2839230456
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.631282088
Short name T304
Test name
Test status
Simulation time 66425759 ps
CPU time 2.73 seconds
Started Mar 17 03:15:19 PM PDT 24
Finished Mar 17 03:15:22 PM PDT 24
Peak memory 233572 kb
Host smart-81e41683-03b1-400b-9799-e6d295a37de8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631282088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.631282088
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.3275793643
Short name T1753
Test name
Test status
Simulation time 26337678 ps
CPU time 0.75 seconds
Started Mar 17 03:15:17 PM PDT 24
Finished Mar 17 03:15:17 PM PDT 24
Peak memory 205156 kb
Host smart-b4a31470-60e5-4786-baf9-c927ca170d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3275793643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3275793643
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4277282279
Short name T299
Test name
Test status
Simulation time 135472081 ps
CPU time 0.77 seconds
Started Mar 17 01:30:32 PM PDT 24
Finished Mar 17 01:30:34 PM PDT 24
Peak memory 206048 kb
Host smart-d4c6b9ab-ced5-4861-8ce7-5c7c799d872f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277282279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4277282279
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3139339655
Short name T1082
Test name
Test status
Simulation time 99350836520 ps
CPU time 219.32 seconds
Started Mar 17 01:30:36 PM PDT 24
Finished Mar 17 01:34:17 PM PDT 24
Peak memory 265432 kb
Host smart-51004562-2636-4d49-8fa9-9348b72dffc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139339655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3139339655
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.787741364
Short name T231
Test name
Test status
Simulation time 86963161828 ps
CPU time 377.56 seconds
Started Mar 17 03:15:20 PM PDT 24
Finished Mar 17 03:21:38 PM PDT 24
Peak memory 264664 kb
Host smart-db7e3ce0-147b-4da1-b0e6-864e9c9fcf70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787741364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.787741364
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.2533008941
Short name T781
Test name
Test status
Simulation time 7830908169 ps
CPU time 136.52 seconds
Started Mar 17 03:15:20 PM PDT 24
Finished Mar 17 03:17:37 PM PDT 24
Peak memory 254544 kb
Host smart-5f6ac219-ca41-4412-a653-9f56ea7965bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2533008941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2533008941
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3591542770
Short name T1572
Test name
Test status
Simulation time 3481705031 ps
CPU time 62.49 seconds
Started Mar 17 01:30:38 PM PDT 24
Finished Mar 17 01:31:41 PM PDT 24
Peak memory 248760 kb
Host smart-fdee3550-77ab-496c-ab81-4f291cc0b55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591542770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3591542770
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1395720575
Short name T1506
Test name
Test status
Simulation time 34252632300 ps
CPU time 328.68 seconds
Started Mar 17 01:30:41 PM PDT 24
Finished Mar 17 01:36:10 PM PDT 24
Peak memory 272232 kb
Host smart-04760813-436d-43ba-b791-c23b99bc9a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395720575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1395720575
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.830115779
Short name T179
Test name
Test status
Simulation time 48388093291 ps
CPU time 338.7 seconds
Started Mar 17 03:15:19 PM PDT 24
Finished Mar 17 03:20:58 PM PDT 24
Peak memory 250500 kb
Host smart-9aa738f0-e6dd-4546-8dbf-53e63bd95938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830115779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.830115779
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1573088105
Short name T1774
Test name
Test status
Simulation time 6378605751 ps
CPU time 37 seconds
Started Mar 17 01:30:31 PM PDT 24
Finished Mar 17 01:31:09 PM PDT 24
Peak memory 239680 kb
Host smart-23deb21b-8795-422c-b980-567aa79d8b6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573088105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1573088105
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.169266651
Short name T1200
Test name
Test status
Simulation time 1160790392 ps
CPU time 9.3 seconds
Started Mar 17 03:15:21 PM PDT 24
Finished Mar 17 03:15:30 PM PDT 24
Peak memory 234788 kb
Host smart-602ec806-ef09-4b54-b62d-1c1eb55b80c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169266651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.169266651
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_intercept.224399745
Short name T995
Test name
Test status
Simulation time 1057790897 ps
CPU time 5.41 seconds
Started Mar 17 03:15:21 PM PDT 24
Finished Mar 17 03:15:26 PM PDT 24
Peak memory 218528 kb
Host smart-f9947b91-9635-47b2-874f-063b602326e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224399745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.224399745
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_intercept.2499324861
Short name T1870
Test name
Test status
Simulation time 110393925 ps
CPU time 2.32 seconds
Started Mar 17 01:30:32 PM PDT 24
Finished Mar 17 01:30:36 PM PDT 24
Peak memory 216216 kb
Host smart-81b69b45-eeea-4c84-9158-3624cb5a4a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499324861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.2499324861
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2846357108
Short name T1782
Test name
Test status
Simulation time 2007341431 ps
CPU time 7.47 seconds
Started Mar 17 01:30:29 PM PDT 24
Finished Mar 17 01:30:37 PM PDT 24
Peak memory 221508 kb
Host smart-2eb0a018-dffb-4438-859e-1798a70399af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846357108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2846357108
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.3910367514
Short name T194
Test name
Test status
Simulation time 2909451575 ps
CPU time 17.26 seconds
Started Mar 17 03:15:19 PM PDT 24
Finished Mar 17 03:15:37 PM PDT 24
Peak memory 229004 kb
Host smart-3179a589-4e98-47ec-8784-6a6c455a6c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910367514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.3910367514
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1537598026
Short name T563
Test name
Test status
Simulation time 8879144302 ps
CPU time 10.7 seconds
Started Mar 17 03:15:21 PM PDT 24
Finished Mar 17 03:15:31 PM PDT 24
Peak memory 216568 kb
Host smart-1585b7fc-22ab-489f-a35b-21b3e6810b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537598026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1537598026
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.904637492
Short name T832
Test name
Test status
Simulation time 405795155 ps
CPU time 2.78 seconds
Started Mar 17 01:30:31 PM PDT 24
Finished Mar 17 01:30:35 PM PDT 24
Peak memory 224008 kb
Host smart-88710dd5-a009-42fb-8b16-fb49079f8763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904637492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap
.904637492
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.1049450491
Short name T1825
Test name
Test status
Simulation time 482116538 ps
CPU time 5.97 seconds
Started Mar 17 01:30:31 PM PDT 24
Finished Mar 17 01:30:38 PM PDT 24
Peak memory 217548 kb
Host smart-f49c87f6-c5dc-4f70-ac86-512beb909872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049450491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1049450491
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.806814423
Short name T1682
Test name
Test status
Simulation time 651817350 ps
CPU time 3.03 seconds
Started Mar 17 03:15:17 PM PDT 24
Finished Mar 17 03:15:20 PM PDT 24
Peak memory 217504 kb
Host smart-b505e05e-2172-4a93-9b19-77984d18b723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806814423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.806814423
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.1616183795
Short name T734
Test name
Test status
Simulation time 220069175 ps
CPU time 3.5 seconds
Started Mar 17 01:30:32 PM PDT 24
Finished Mar 17 01:30:37 PM PDT 24
Peak memory 218136 kb
Host smart-d1e9914e-d56d-4433-9a04-8e642a31c191
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1616183795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.1616183795
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3474196519
Short name T1383
Test name
Test status
Simulation time 2650096570 ps
CPU time 5.13 seconds
Started Mar 17 03:15:19 PM PDT 24
Finished Mar 17 03:15:24 PM PDT 24
Peak memory 219732 kb
Host smart-aa585f07-0616-4ba4-9223-e6582d2efaa6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3474196519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3474196519
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.1648899283
Short name T241
Test name
Test status
Simulation time 324522039979 ps
CPU time 575.23 seconds
Started Mar 17 01:30:37 PM PDT 24
Finished Mar 17 01:40:14 PM PDT 24
Peak memory 269744 kb
Host smart-9d9973d6-8a9b-4fcd-ac91-eef7c06773d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648899283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.1648899283
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1534411975
Short name T350
Test name
Test status
Simulation time 44869400687 ps
CPU time 37.5 seconds
Started Mar 17 01:30:34 PM PDT 24
Finished Mar 17 01:31:13 PM PDT 24
Peak memory 215856 kb
Host smart-c428bc6f-32c5-43c1-b9e6-b20641e655c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534411975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1534411975
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1751334007
Short name T1836
Test name
Test status
Simulation time 1216194495 ps
CPU time 22.28 seconds
Started Mar 17 03:15:16 PM PDT 24
Finished Mar 17 03:15:38 PM PDT 24
Peak memory 216136 kb
Host smart-feb77f2b-92ab-4574-b8d1-af340f1fa386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751334007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1751334007
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3264490242
Short name T1132
Test name
Test status
Simulation time 9729996916 ps
CPU time 29.69 seconds
Started Mar 17 01:30:34 PM PDT 24
Finished Mar 17 01:31:04 PM PDT 24
Peak memory 215772 kb
Host smart-dd7b945b-2567-4746-9dd5-28002fd556d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264490242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3264490242
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3585895720
Short name T751
Test name
Test status
Simulation time 6560328757 ps
CPU time 6.39 seconds
Started Mar 17 03:15:18 PM PDT 24
Finished Mar 17 03:15:25 PM PDT 24
Peak memory 216092 kb
Host smart-3b34c0a0-a32c-445b-8beb-d06e0e9750a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585895720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3585895720
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.1695128820
Short name T680
Test name
Test status
Simulation time 63799346 ps
CPU time 0.92 seconds
Started Mar 17 01:30:30 PM PDT 24
Finished Mar 17 01:30:32 PM PDT 24
Peak memory 206496 kb
Host smart-6db9dc05-7480-48d6-9191-a55472775c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695128820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.1695128820
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3259055300
Short name T518
Test name
Test status
Simulation time 162184166 ps
CPU time 3.08 seconds
Started Mar 17 03:15:16 PM PDT 24
Finished Mar 17 03:15:19 PM PDT 24
Peak memory 216160 kb
Host smart-cdf9210d-4920-412e-bdf1-470359a6f3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259055300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3259055300
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2393595830
Short name T298
Test name
Test status
Simulation time 96747852 ps
CPU time 0.85 seconds
Started Mar 17 01:30:31 PM PDT 24
Finished Mar 17 01:30:33 PM PDT 24
Peak memory 205156 kb
Host smart-8a7530fe-55f9-4ba0-abb1-99a346899013
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393595830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2393595830
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.2710331533
Short name T1160
Test name
Test status
Simulation time 23215034 ps
CPU time 0.78 seconds
Started Mar 17 03:15:19 PM PDT 24
Finished Mar 17 03:15:20 PM PDT 24
Peak memory 205436 kb
Host smart-df62a114-3987-4892-9890-763121be9062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710331533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2710331533
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1918833965
Short name T613
Test name
Test status
Simulation time 25461119750 ps
CPU time 26.07 seconds
Started Mar 17 03:15:22 PM PDT 24
Finished Mar 17 03:15:48 PM PDT 24
Peak memory 228536 kb
Host smart-0072eb85-8718-49f0-9276-dff524c62952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918833965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1918833965
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_upload.2277644326
Short name T1554
Test name
Test status
Simulation time 3418867734 ps
CPU time 14.56 seconds
Started Mar 17 01:30:29 PM PDT 24
Finished Mar 17 01:30:45 PM PDT 24
Peak memory 233720 kb
Host smart-2c2ee1d4-baee-40a8-a11e-923f04242615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277644326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2277644326
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1408423383
Short name T1501
Test name
Test status
Simulation time 40310538 ps
CPU time 0.74 seconds
Started Mar 17 01:30:48 PM PDT 24
Finished Mar 17 01:30:49 PM PDT 24
Peak memory 204300 kb
Host smart-d8a270aa-39f7-4bb6-80f1-5548126dd839
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408423383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1408423383
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1416452070
Short name T509
Test name
Test status
Simulation time 22402330 ps
CPU time 0.76 seconds
Started Mar 17 03:15:28 PM PDT 24
Finished Mar 17 03:15:29 PM PDT 24
Peak memory 205016 kb
Host smart-d06d228a-49be-457c-8cda-53d04bad529b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416452070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1416452070
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2253226017
Short name T1677
Test name
Test status
Simulation time 280078166 ps
CPU time 2.1 seconds
Started Mar 17 01:30:39 PM PDT 24
Finished Mar 17 01:30:41 PM PDT 24
Peak memory 218004 kb
Host smart-876b6553-3fa9-49f8-95d1-ab00852db629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253226017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2253226017
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2329554044
Short name T1696
Test name
Test status
Simulation time 308644397 ps
CPU time 2.92 seconds
Started Mar 17 03:15:26 PM PDT 24
Finished Mar 17 03:15:29 PM PDT 24
Peak memory 233528 kb
Host smart-836c653a-0275-4a5b-83f2-d1b96556e836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329554044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2329554044
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3762889987
Short name T1059
Test name
Test status
Simulation time 39779323 ps
CPU time 0.81 seconds
Started Mar 17 01:30:38 PM PDT 24
Finished Mar 17 01:30:39 PM PDT 24
Peak memory 205312 kb
Host smart-2ac45e1b-a77e-4b88-ba12-be7a433db0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762889987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3762889987
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.511914526
Short name T1794
Test name
Test status
Simulation time 16912467 ps
CPU time 0.8 seconds
Started Mar 17 03:15:19 PM PDT 24
Finished Mar 17 03:15:20 PM PDT 24
Peak memory 206184 kb
Host smart-be8dd6b2-a1f4-4b03-8081-62d3017ed71d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511914526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.511914526
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.2540284499
Short name T1166
Test name
Test status
Simulation time 92957099355 ps
CPU time 137.57 seconds
Started Mar 17 03:15:27 PM PDT 24
Finished Mar 17 03:17:44 PM PDT 24
Peak memory 266036 kb
Host smart-07fd9d92-04fc-4b01-994c-85222c667b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2540284499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2540284499
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.340764947
Short name T1063
Test name
Test status
Simulation time 26248748752 ps
CPU time 103.84 seconds
Started Mar 17 01:30:36 PM PDT 24
Finished Mar 17 01:32:20 PM PDT 24
Peak memory 264908 kb
Host smart-ddb58586-e9be-44c7-86a2-c7abc8e29b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340764947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.340764947
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.3852559106
Short name T360
Test name
Test status
Simulation time 299910471675 ps
CPU time 260.19 seconds
Started Mar 17 03:15:26 PM PDT 24
Finished Mar 17 03:19:46 PM PDT 24
Peak memory 250372 kb
Host smart-f4216abd-1e75-47ef-bd8b-87d846b415e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852559106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.3852559106
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.714464010
Short name T1678
Test name
Test status
Simulation time 17268342277 ps
CPU time 105.94 seconds
Started Mar 17 01:30:36 PM PDT 24
Finished Mar 17 01:32:24 PM PDT 24
Peak memory 269448 kb
Host smart-a783caf8-3da7-4eae-99ea-6de9174bc265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=714464010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.714464010
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.449890792
Short name T928
Test name
Test status
Simulation time 122221178192 ps
CPU time 194.94 seconds
Started Mar 17 03:15:24 PM PDT 24
Finished Mar 17 03:18:40 PM PDT 24
Peak memory 249040 kb
Host smart-b32d09dc-b612-47dc-bcee-ca4b057379e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449890792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle
.449890792
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.4187064207
Short name T807
Test name
Test status
Simulation time 402366994 ps
CPU time 12.5 seconds
Started Mar 17 03:15:24 PM PDT 24
Finished Mar 17 03:15:37 PM PDT 24
Peak memory 233944 kb
Host smart-f166ac9d-a4be-4b8c-8e79-abc9e3fbf62c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187064207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.4187064207
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.4242822926
Short name T1275
Test name
Test status
Simulation time 13658245053 ps
CPU time 40.66 seconds
Started Mar 17 01:30:35 PM PDT 24
Finished Mar 17 01:31:16 PM PDT 24
Peak memory 230468 kb
Host smart-42f9d895-e4d8-4100-b1a2-22506efd91fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242822926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.4242822926
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.1343307388
Short name T1298
Test name
Test status
Simulation time 561692959 ps
CPU time 4.23 seconds
Started Mar 17 01:30:35 PM PDT 24
Finished Mar 17 01:30:41 PM PDT 24
Peak memory 234576 kb
Host smart-636db67a-5d2a-41ca-acfb-7429b03b1d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343307388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.1343307388
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_intercept.3597117350
Short name T1824
Test name
Test status
Simulation time 3254152294 ps
CPU time 4.92 seconds
Started Mar 17 03:15:24 PM PDT 24
Finished Mar 17 03:15:28 PM PDT 24
Peak memory 219536 kb
Host smart-f37181fa-58c8-4efd-a4da-47984955ed13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597117350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3597117350
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2164039198
Short name T1026
Test name
Test status
Simulation time 972473880 ps
CPU time 12.47 seconds
Started Mar 17 03:15:26 PM PDT 24
Finished Mar 17 03:15:39 PM PDT 24
Peak memory 246572 kb
Host smart-2cb24f7c-44ed-4e41-8874-0e89fa5a3db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2164039198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2164039198
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.3343552155
Short name T1227
Test name
Test status
Simulation time 713922630 ps
CPU time 5.09 seconds
Started Mar 17 01:30:37 PM PDT 24
Finished Mar 17 01:30:43 PM PDT 24
Peak memory 218880 kb
Host smart-7d72a1ed-4deb-405d-8d52-6a47712d8c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343552155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.3343552155
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2705874584
Short name T486
Test name
Test status
Simulation time 498828811 ps
CPU time 6.02 seconds
Started Mar 17 01:30:37 PM PDT 24
Finished Mar 17 01:30:44 PM PDT 24
Peak memory 224212 kb
Host smart-ac99c9e5-a029-4cd1-aa39-8401c9c45dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705874584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2705874584
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2781609967
Short name T483
Test name
Test status
Simulation time 16187647060 ps
CPU time 11.12 seconds
Started Mar 17 03:15:26 PM PDT 24
Finished Mar 17 03:15:37 PM PDT 24
Peak memory 234568 kb
Host smart-fc944512-e383-446c-8314-2d8716d4a1b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781609967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2781609967
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2764815359
Short name T1328
Test name
Test status
Simulation time 1384357358 ps
CPU time 6.56 seconds
Started Mar 17 03:15:25 PM PDT 24
Finished Mar 17 03:15:32 PM PDT 24
Peak memory 238612 kb
Host smart-b4f4bc52-a880-479b-b799-dcbde7f250ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764815359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2764815359
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.4208534595
Short name T71
Test name
Test status
Simulation time 478539338 ps
CPU time 7.52 seconds
Started Mar 17 01:30:37 PM PDT 24
Finished Mar 17 01:30:46 PM PDT 24
Peak memory 240172 kb
Host smart-10904039-fd61-41e8-a41f-6da39fa305a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4208534595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.4208534595
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1847479903
Short name T441
Test name
Test status
Simulation time 3272863995 ps
CPU time 4.38 seconds
Started Mar 17 01:30:36 PM PDT 24
Finished Mar 17 01:30:41 PM PDT 24
Peak memory 218924 kb
Host smart-46435503-937c-4540-a25c-342afd58008a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1847479903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1847479903
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3758356370
Short name T1590
Test name
Test status
Simulation time 1677677564 ps
CPU time 4.62 seconds
Started Mar 17 03:15:24 PM PDT 24
Finished Mar 17 03:15:29 PM PDT 24
Peak memory 222684 kb
Host smart-d2ef0972-c4e2-40ad-b7ba-bdb2265d6716
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3758356370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3758356370
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1836783001
Short name T437
Test name
Test status
Simulation time 91818021 ps
CPU time 1.23 seconds
Started Mar 17 01:30:47 PM PDT 24
Finished Mar 17 01:30:48 PM PDT 24
Peak memory 205696 kb
Host smart-0591c8dd-61c4-44a3-8d95-314e25fdd44e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836783001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1836783001
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2546086968
Short name T42
Test name
Test status
Simulation time 164263637466 ps
CPU time 1192.14 seconds
Started Mar 17 03:15:24 PM PDT 24
Finished Mar 17 03:35:16 PM PDT 24
Peak memory 281792 kb
Host smart-5daa55eb-8259-4257-afc3-d14a6867ece5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546086968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2546086968
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.1274499138
Short name T1726
Test name
Test status
Simulation time 1376382879 ps
CPU time 14.93 seconds
Started Mar 17 03:15:21 PM PDT 24
Finished Mar 17 03:15:36 PM PDT 24
Peak memory 216072 kb
Host smart-77d8f942-6499-429b-ba7e-8c1dbd6a5ea5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274499138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1274499138
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.474293631
Short name T608
Test name
Test status
Simulation time 29354615134 ps
CPU time 37.49 seconds
Started Mar 17 01:30:36 PM PDT 24
Finished Mar 17 01:31:15 PM PDT 24
Peak memory 215868 kb
Host smart-0bff4330-a715-4474-8580-50611d716f9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474293631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.474293631
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2478825726
Short name T1778
Test name
Test status
Simulation time 6878811745 ps
CPU time 20.41 seconds
Started Mar 17 01:30:37 PM PDT 24
Finished Mar 17 01:30:58 PM PDT 24
Peak memory 215944 kb
Host smart-45e98fe7-82ff-4edc-acb1-a84250834f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2478825726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2478825726
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.2930535871
Short name T996
Test name
Test status
Simulation time 29624527923 ps
CPU time 22.79 seconds
Started Mar 17 03:15:20 PM PDT 24
Finished Mar 17 03:15:43 PM PDT 24
Peak memory 216076 kb
Host smart-91f60d3e-d37e-4975-a945-0816f215a1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930535871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.2930535871
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2247760336
Short name T909
Test name
Test status
Simulation time 632019292 ps
CPU time 1.47 seconds
Started Mar 17 03:15:23 PM PDT 24
Finished Mar 17 03:15:25 PM PDT 24
Peak memory 216124 kb
Host smart-c2b82147-72c0-4841-a771-b067fda05d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247760336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2247760336
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3095637809
Short name T333
Test name
Test status
Simulation time 208200960 ps
CPU time 3.74 seconds
Started Mar 17 01:30:36 PM PDT 24
Finished Mar 17 01:30:40 PM PDT 24
Peak memory 215852 kb
Host smart-2c0f35d9-4b22-42e2-bad8-c1371adf3d82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095637809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3095637809
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3682307424
Short name T1133
Test name
Test status
Simulation time 23299000 ps
CPU time 0.77 seconds
Started Mar 17 01:30:39 PM PDT 24
Finished Mar 17 01:30:40 PM PDT 24
Peak memory 205156 kb
Host smart-6a28e634-d9de-4999-82c8-9d3622370d4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682307424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3682307424
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.707860552
Short name T1024
Test name
Test status
Simulation time 99754599 ps
CPU time 0.93 seconds
Started Mar 17 03:15:25 PM PDT 24
Finished Mar 17 03:15:26 PM PDT 24
Peak memory 206444 kb
Host smart-4406fc86-9936-4149-be8b-b6ee1fc818f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707860552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.707860552
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.1309418712
Short name T410
Test name
Test status
Simulation time 51453432777 ps
CPU time 41.77 seconds
Started Mar 17 03:15:23 PM PDT 24
Finished Mar 17 03:16:05 PM PDT 24
Peak memory 228208 kb
Host smart-6f7db4bb-89bb-4170-ac29-993caaf5b6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309418712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1309418712
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_upload.1904948195
Short name T1548
Test name
Test status
Simulation time 1469870836 ps
CPU time 9.35 seconds
Started Mar 17 01:30:38 PM PDT 24
Finished Mar 17 01:30:48 PM PDT 24
Peak memory 220400 kb
Host smart-fc8b027c-2161-4b69-8929-b692259adf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904948195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.1904948195
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3421409484
Short name T52
Test name
Test status
Simulation time 41846391 ps
CPU time 0.72 seconds
Started Mar 17 01:30:43 PM PDT 24
Finished Mar 17 01:30:44 PM PDT 24
Peak memory 204280 kb
Host smart-98fec7c7-fb92-4ec2-8fb4-18aa653bc07c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421409484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3421409484
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.4222128090
Short name T1492
Test name
Test status
Simulation time 25223148 ps
CPU time 0.75 seconds
Started Mar 17 03:15:33 PM PDT 24
Finished Mar 17 03:15:34 PM PDT 24
Peak memory 203924 kb
Host smart-72e8ad8e-e3ab-4f95-9b3d-d80719b5dae1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222128090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
4222128090
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.4181656789
Short name T1153
Test name
Test status
Simulation time 2180458822 ps
CPU time 3.87 seconds
Started Mar 17 01:30:42 PM PDT 24
Finished Mar 17 01:30:46 PM PDT 24
Peak memory 224064 kb
Host smart-031a8832-cc47-488f-ac5e-0f7fea07ade4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181656789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.4181656789
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.823261422
Short name T1756
Test name
Test status
Simulation time 14918663562 ps
CPU time 10.32 seconds
Started Mar 17 03:15:28 PM PDT 24
Finished Mar 17 03:15:38 PM PDT 24
Peak memory 233688 kb
Host smart-2788881d-4283-4322-b7ae-8830be77bc07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823261422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.823261422
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3023875381
Short name T1440
Test name
Test status
Simulation time 51574407 ps
CPU time 0.79 seconds
Started Mar 17 03:15:24 PM PDT 24
Finished Mar 17 03:15:25 PM PDT 24
Peak memory 205200 kb
Host smart-b6d80074-1144-46ef-b71a-6fcdff8f3174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023875381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3023875381
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3071459925
Short name T614
Test name
Test status
Simulation time 21455190 ps
CPU time 0.75 seconds
Started Mar 17 01:30:47 PM PDT 24
Finished Mar 17 01:30:48 PM PDT 24
Peak memory 204104 kb
Host smart-258b5458-8d2f-48fa-a850-d42c6e478dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071459925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3071459925
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.2362294627
Short name T1737
Test name
Test status
Simulation time 257288646922 ps
CPU time 217.13 seconds
Started Mar 17 01:30:44 PM PDT 24
Finished Mar 17 01:34:22 PM PDT 24
Peak memory 248632 kb
Host smart-73d7f075-27d2-45ae-b3a0-6860794a0386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2362294627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.2362294627
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.3552372104
Short name T190
Test name
Test status
Simulation time 12109198365 ps
CPU time 78.8 seconds
Started Mar 17 03:15:31 PM PDT 24
Finished Mar 17 03:16:50 PM PDT 24
Peak memory 245012 kb
Host smart-3868a977-a9c2-4f15-a71b-bda6a7d5b678
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552372104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3552372104
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1381134849
Short name T225
Test name
Test status
Simulation time 27927358713 ps
CPU time 92.19 seconds
Started Mar 17 03:15:29 PM PDT 24
Finished Mar 17 03:17:01 PM PDT 24
Peak memory 253364 kb
Host smart-547c5bfd-ac25-4024-932c-5026a4e83e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381134849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1381134849
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.944735290
Short name T1345
Test name
Test status
Simulation time 447498841211 ps
CPU time 622.95 seconds
Started Mar 17 01:30:42 PM PDT 24
Finished Mar 17 01:41:06 PM PDT 24
Peak memory 264880 kb
Host smart-cdc95c82-2484-4627-995d-637e07c4d3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944735290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.944735290
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.175648387
Short name T245
Test name
Test status
Simulation time 39451071458 ps
CPU time 242.15 seconds
Started Mar 17 03:15:28 PM PDT 24
Finished Mar 17 03:19:30 PM PDT 24
Peak memory 251800 kb
Host smart-e061fad5-a30c-4f85-998d-077bd02ee310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175648387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.175648387
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2354110330
Short name T1692
Test name
Test status
Simulation time 7149037870 ps
CPU time 104 seconds
Started Mar 17 01:30:45 PM PDT 24
Finished Mar 17 01:32:29 PM PDT 24
Peak memory 253324 kb
Host smart-f959debf-0f82-41ce-88a4-fd9810d1bf0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354110330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2354110330
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1047513083
Short name T282
Test name
Test status
Simulation time 616144216 ps
CPU time 9.6 seconds
Started Mar 17 03:15:28 PM PDT 24
Finished Mar 17 03:15:38 PM PDT 24
Peak memory 239120 kb
Host smart-4dd352ac-6890-4554-8ee6-450c597c118a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047513083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1047513083
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3423402903
Short name T846
Test name
Test status
Simulation time 869695788 ps
CPU time 8.02 seconds
Started Mar 17 01:30:47 PM PDT 24
Finished Mar 17 01:30:55 PM PDT 24
Peak memory 245060 kb
Host smart-85230666-269a-4f09-9200-b1ca492c269c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423402903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3423402903
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.144249157
Short name T335
Test name
Test status
Simulation time 1663372886 ps
CPU time 5.19 seconds
Started Mar 17 01:30:43 PM PDT 24
Finished Mar 17 01:30:48 PM PDT 24
Peak memory 233932 kb
Host smart-f4709610-1ef4-4f00-b99d-8e8389e965a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144249157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.144249157
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_intercept.3760811737
Short name T836
Test name
Test status
Simulation time 1744112247 ps
CPU time 6.58 seconds
Started Mar 17 03:15:28 PM PDT 24
Finished Mar 17 03:15:35 PM PDT 24
Peak memory 219408 kb
Host smart-af788c55-1eb4-49e3-bc60-388a4e54b337
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760811737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.3760811737
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3286856336
Short name T661
Test name
Test status
Simulation time 12365854608 ps
CPU time 19.51 seconds
Started Mar 17 01:30:43 PM PDT 24
Finished Mar 17 01:31:02 PM PDT 24
Peak memory 251496 kb
Host smart-c8af950f-0e61-49d8-b245-b1b8f82017ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286856336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3286856336
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.500303450
Short name T610
Test name
Test status
Simulation time 32317337460 ps
CPU time 9.47 seconds
Started Mar 17 03:15:28 PM PDT 24
Finished Mar 17 03:15:37 PM PDT 24
Peak memory 218848 kb
Host smart-28cdde18-79fc-444b-ab48-b460fa1d41db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=500303450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.500303450
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1021480617
Short name T1526
Test name
Test status
Simulation time 274609929 ps
CPU time 2.31 seconds
Started Mar 17 03:15:30 PM PDT 24
Finished Mar 17 03:15:33 PM PDT 24
Peak memory 224288 kb
Host smart-17da2bbf-b18f-4b97-9e76-3a2510281020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021480617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1021480617
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.964006642
Short name T890
Test name
Test status
Simulation time 16484440559 ps
CPU time 12.29 seconds
Started Mar 17 01:30:45 PM PDT 24
Finished Mar 17 01:30:57 PM PDT 24
Peak memory 232344 kb
Host smart-27fc9cfc-bafe-444c-b44b-544fcb6405de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964006642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap
.964006642
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1644553853
Short name T1353
Test name
Test status
Simulation time 47898587029 ps
CPU time 21.6 seconds
Started Mar 17 01:30:43 PM PDT 24
Finished Mar 17 01:31:05 PM PDT 24
Peak memory 217376 kb
Host smart-a63e4d6e-3529-4668-baaa-bda71b9db706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644553853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1644553853
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.66508271
Short name T1093
Test name
Test status
Simulation time 300551367 ps
CPU time 2.72 seconds
Started Mar 17 03:15:30 PM PDT 24
Finished Mar 17 03:15:33 PM PDT 24
Peak memory 233488 kb
Host smart-5db5daed-b9c2-41a1-a52a-42934f40db6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66508271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.66508271
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3255547775
Short name T355
Test name
Test status
Simulation time 2788970477 ps
CPU time 5.78 seconds
Started Mar 17 03:15:28 PM PDT 24
Finished Mar 17 03:15:34 PM PDT 24
Peak memory 220300 kb
Host smart-4715a411-7f53-4917-a680-e73c16751f1a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3255547775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3255547775
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.4035891553
Short name T404
Test name
Test status
Simulation time 437421794 ps
CPU time 4.03 seconds
Started Mar 17 01:30:45 PM PDT 24
Finished Mar 17 01:30:49 PM PDT 24
Peak memory 221896 kb
Host smart-c45197f6-e193-4b10-8625-6014687678e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4035891553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.4035891553
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.1580745279
Short name T703
Test name
Test status
Simulation time 37798364552 ps
CPU time 108.71 seconds
Started Mar 17 01:30:44 PM PDT 24
Finished Mar 17 01:32:33 PM PDT 24
Peak memory 271148 kb
Host smart-598d13cf-f806-4da5-85c3-58a0189591ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580745279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.1580745279
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1936416946
Short name T290
Test name
Test status
Simulation time 2873005298 ps
CPU time 44.04 seconds
Started Mar 17 03:15:32 PM PDT 24
Finished Mar 17 03:16:16 PM PDT 24
Peak memory 216168 kb
Host smart-baa5d563-7a21-46c7-9679-64979d45c3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936416946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1936416946
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.796177752
Short name T1835
Test name
Test status
Simulation time 25334853956 ps
CPU time 32.18 seconds
Started Mar 17 01:30:43 PM PDT 24
Finished Mar 17 01:31:16 PM PDT 24
Peak memory 216016 kb
Host smart-fb5edd61-0888-439d-b703-bc8b33c56d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796177752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.796177752
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2832096796
Short name T428
Test name
Test status
Simulation time 19500994151 ps
CPU time 16.51 seconds
Started Mar 17 01:30:42 PM PDT 24
Finished Mar 17 01:30:59 PM PDT 24
Peak memory 215932 kb
Host smart-f2487268-d7ed-4c97-b4ea-3304ea520d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832096796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2832096796
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.3774333029
Short name T1591
Test name
Test status
Simulation time 5812031968 ps
CPU time 5.67 seconds
Started Mar 17 03:15:29 PM PDT 24
Finished Mar 17 03:15:35 PM PDT 24
Peak memory 216108 kb
Host smart-a68a3747-657c-4365-834a-55dbd1c5c0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774333029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.3774333029
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3421824679
Short name T688
Test name
Test status
Simulation time 67520151 ps
CPU time 1.62 seconds
Started Mar 17 03:15:34 PM PDT 24
Finished Mar 17 03:15:35 PM PDT 24
Peak memory 216164 kb
Host smart-65b2646c-9287-4477-bad6-d044aa934f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421824679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3421824679
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.4006508701
Short name T887
Test name
Test status
Simulation time 39447362 ps
CPU time 0.78 seconds
Started Mar 17 01:30:42 PM PDT 24
Finished Mar 17 01:30:43 PM PDT 24
Peak memory 205164 kb
Host smart-64198c31-22c8-4999-86cc-f0cb7cff9a3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006508701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.4006508701
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3399566216
Short name T146
Test name
Test status
Simulation time 106164401 ps
CPU time 0.99 seconds
Started Mar 17 03:15:28 PM PDT 24
Finished Mar 17 03:15:29 PM PDT 24
Peak memory 206456 kb
Host smart-f3bdb7fa-a369-4aee-93d6-ecdad029be43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399566216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3399566216
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.948709792
Short name T824
Test name
Test status
Simulation time 771395578 ps
CPU time 1.25 seconds
Started Mar 17 01:30:43 PM PDT 24
Finished Mar 17 01:30:44 PM PDT 24
Peak memory 206176 kb
Host smart-82b4b02e-2134-4060-9e1a-99a7ff4c503c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948709792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.948709792
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1040466790
Short name T1174
Test name
Test status
Simulation time 182439456 ps
CPU time 4.21 seconds
Started Mar 17 01:30:43 PM PDT 24
Finished Mar 17 01:30:47 PM PDT 24
Peak memory 232944 kb
Host smart-8e41b95d-839b-45f6-b95f-5bc87fe92006
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040466790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1040466790
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_upload.2462242699
Short name T1747
Test name
Test status
Simulation time 5212096266 ps
CPU time 23.59 seconds
Started Mar 17 03:15:33 PM PDT 24
Finished Mar 17 03:15:56 PM PDT 24
Peak memory 231924 kb
Host smart-70fb4a5f-8fc7-4c7f-82a7-59f984256695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462242699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2462242699
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1573934721
Short name T1106
Test name
Test status
Simulation time 16402748 ps
CPU time 0.74 seconds
Started Mar 17 03:15:42 PM PDT 24
Finished Mar 17 03:15:43 PM PDT 24
Peak memory 205008 kb
Host smart-4083f532-8f5f-4d9f-a3fe-cabf3d3d865d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573934721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1573934721
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.2313908599
Short name T826
Test name
Test status
Simulation time 43452805 ps
CPU time 0.68 seconds
Started Mar 17 01:30:51 PM PDT 24
Finished Mar 17 01:30:51 PM PDT 24
Peak memory 205156 kb
Host smart-a181a542-e52d-4d06-97fa-6e2e9e3fb4da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313908599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
2313908599
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.3796964953
Short name T472
Test name
Test status
Simulation time 257751030 ps
CPU time 4.12 seconds
Started Mar 17 03:15:33 PM PDT 24
Finished Mar 17 03:15:38 PM PDT 24
Peak memory 219000 kb
Host smart-af6e4d42-22a2-46a2-9f4a-7f97de3dc04d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796964953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3796964953
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.710844211
Short name T917
Test name
Test status
Simulation time 9888254945 ps
CPU time 5.16 seconds
Started Mar 17 01:30:54 PM PDT 24
Finished Mar 17 01:30:59 PM PDT 24
Peak memory 218828 kb
Host smart-b3bb341f-59c5-493f-95ef-eec2ced7dd72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710844211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.710844211
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1902884979
Short name T458
Test name
Test status
Simulation time 15653251 ps
CPU time 0.78 seconds
Started Mar 17 01:30:50 PM PDT 24
Finished Mar 17 01:30:51 PM PDT 24
Peak memory 205008 kb
Host smart-9f1f1073-1256-4371-906b-ff67c8e1200e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902884979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1902884979
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3708321261
Short name T1624
Test name
Test status
Simulation time 119677213 ps
CPU time 0.81 seconds
Started Mar 17 03:15:31 PM PDT 24
Finished Mar 17 03:15:31 PM PDT 24
Peak memory 206520 kb
Host smart-b342fb66-4c06-493f-8e5e-472c7cf01a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708321261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3708321261
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2631125930
Short name T1702
Test name
Test status
Simulation time 8362781402 ps
CPU time 35.59 seconds
Started Mar 17 03:15:33 PM PDT 24
Finished Mar 17 03:16:09 PM PDT 24
Peak memory 249004 kb
Host smart-8bdf520e-f181-41c7-a2d6-e7b70f98cc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631125930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2631125930
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.3545960089
Short name T443
Test name
Test status
Simulation time 7765394150 ps
CPU time 14.49 seconds
Started Mar 17 01:30:48 PM PDT 24
Finished Mar 17 01:31:03 PM PDT 24
Peak memory 218736 kb
Host smart-8be03f72-4b5c-4fcf-9c3e-dfc1708dd239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545960089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.3545960089
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1315489221
Short name T523
Test name
Test status
Simulation time 700991910673 ps
CPU time 613.86 seconds
Started Mar 17 01:30:50 PM PDT 24
Finished Mar 17 01:41:04 PM PDT 24
Peak memory 252888 kb
Host smart-3e87d67f-943b-4db7-9153-3d5c279f5ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315489221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1315489221
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.1936274039
Short name T237
Test name
Test status
Simulation time 182547778519 ps
CPU time 117.07 seconds
Started Mar 17 03:15:35 PM PDT 24
Finished Mar 17 03:17:32 PM PDT 24
Peak memory 254220 kb
Host smart-dc0dc164-dd12-4558-a3c7-5374d9c5510b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936274039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1936274039
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.1884163180
Short name T1016
Test name
Test status
Simulation time 18440213233 ps
CPU time 150.51 seconds
Started Mar 17 03:15:34 PM PDT 24
Finished Mar 17 03:18:05 PM PDT 24
Peak memory 257188 kb
Host smart-e7e96b4d-fe1b-4e3b-acfc-9d70b7d42822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884163180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.1884163180
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2908070166
Short name T737
Test name
Test status
Simulation time 99775252825 ps
CPU time 548.89 seconds
Started Mar 17 01:30:51 PM PDT 24
Finished Mar 17 01:40:00 PM PDT 24
Peak memory 269944 kb
Host smart-6aa785f7-e257-4dd4-9464-1661a4502673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908070166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2908070166
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1769266433
Short name T885
Test name
Test status
Simulation time 26705526329 ps
CPU time 38.29 seconds
Started Mar 17 01:30:49 PM PDT 24
Finished Mar 17 01:31:28 PM PDT 24
Peak memory 249756 kb
Host smart-1c7d0022-48aa-4f00-b274-de67d9386eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769266433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1769266433
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.617023003
Short name T1021
Test name
Test status
Simulation time 7838760588 ps
CPU time 37.72 seconds
Started Mar 17 03:15:31 PM PDT 24
Finished Mar 17 03:16:09 PM PDT 24
Peak memory 237008 kb
Host smart-409c89ca-ac6c-4b40-9963-90662abb17b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617023003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.617023003
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3770254421
Short name T676
Test name
Test status
Simulation time 336563097 ps
CPU time 3.75 seconds
Started Mar 17 03:15:34 PM PDT 24
Finished Mar 17 03:15:37 PM PDT 24
Peak memory 218452 kb
Host smart-775f5ae4-a7a4-4883-a86d-31fababf7d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770254421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3770254421
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_intercept.394436650
Short name T1606
Test name
Test status
Simulation time 3052329772 ps
CPU time 7.64 seconds
Started Mar 17 01:30:50 PM PDT 24
Finished Mar 17 01:30:58 PM PDT 24
Peak memory 224112 kb
Host smart-0e81ba10-0179-4f63-9189-ace27feaf5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394436650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.394436650
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1129013080
Short name T430
Test name
Test status
Simulation time 359283108 ps
CPU time 3.7 seconds
Started Mar 17 01:30:50 PM PDT 24
Finished Mar 17 01:30:53 PM PDT 24
Peak memory 224028 kb
Host smart-41a9ef8d-11db-44c9-a58e-0f39ad887c3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129013080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1129013080
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2262073710
Short name T219
Test name
Test status
Simulation time 22110393365 ps
CPU time 39.08 seconds
Started Mar 17 03:15:31 PM PDT 24
Finished Mar 17 03:16:10 PM PDT 24
Peak memory 247108 kb
Host smart-a7ebd825-b554-4bb0-8b6e-054d21085b8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262073710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2262073710
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.224617546
Short name T829
Test name
Test status
Simulation time 53395625034 ps
CPU time 35.32 seconds
Started Mar 17 01:30:51 PM PDT 24
Finished Mar 17 01:31:27 PM PDT 24
Peak memory 232328 kb
Host smart-e18496a1-8cac-4fe4-9c4d-514eabb2eb86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224617546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap
.224617546
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3279150752
Short name T1601
Test name
Test status
Simulation time 32583169162 ps
CPU time 23.59 seconds
Started Mar 17 03:15:33 PM PDT 24
Finished Mar 17 03:15:56 PM PDT 24
Peak memory 233648 kb
Host smart-791c6ecc-ceba-4f29-8324-cc9b6e64d96d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279150752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3279150752
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2326627909
Short name T884
Test name
Test status
Simulation time 5646888991 ps
CPU time 7.28 seconds
Started Mar 17 01:30:53 PM PDT 24
Finished Mar 17 01:31:01 PM PDT 24
Peak memory 233504 kb
Host smart-e3c711ee-eac0-4946-a98d-3c8c5cc610e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326627909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2326627909
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2451726004
Short name T866
Test name
Test status
Simulation time 292976201 ps
CPU time 2.94 seconds
Started Mar 17 03:15:32 PM PDT 24
Finished Mar 17 03:15:35 PM PDT 24
Peak memory 224292 kb
Host smart-d3374a2d-b850-4894-8a40-5929a177c410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2451726004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2451726004
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2412055239
Short name T392
Test name
Test status
Simulation time 573156681 ps
CPU time 4.3 seconds
Started Mar 17 03:15:33 PM PDT 24
Finished Mar 17 03:15:37 PM PDT 24
Peak memory 220140 kb
Host smart-006ee01c-0f0a-4f1b-b7d0-4764f86e8473
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2412055239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2412055239
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3486786124
Short name T1062
Test name
Test status
Simulation time 1131013848 ps
CPU time 4.01 seconds
Started Mar 17 01:30:49 PM PDT 24
Finished Mar 17 01:30:54 PM PDT 24
Peak memory 218564 kb
Host smart-640ec513-48b7-41b6-bce3-e883d7d7ff4c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3486786124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3486786124
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1619761756
Short name T442
Test name
Test status
Simulation time 69310792 ps
CPU time 0.91 seconds
Started Mar 17 03:15:32 PM PDT 24
Finished Mar 17 03:15:33 PM PDT 24
Peak memory 205580 kb
Host smart-0b6d89e3-ee2a-4942-a19a-9bd2c76522a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619761756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1619761756
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.809332962
Short name T907
Test name
Test status
Simulation time 45405936806 ps
CPU time 142.51 seconds
Started Mar 17 01:30:48 PM PDT 24
Finished Mar 17 01:33:11 PM PDT 24
Peak memory 252224 kb
Host smart-7860eab4-100a-4569-89c5-5b2a25ec1c1a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809332962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stres
s_all.809332962
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.1345572842
Short name T82
Test name
Test status
Simulation time 5851918876 ps
CPU time 38.56 seconds
Started Mar 17 03:15:29 PM PDT 24
Finished Mar 17 03:16:08 PM PDT 24
Peak memory 216244 kb
Host smart-1083518d-490b-4a58-864c-7585c56f8437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345572842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1345572842
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3978841971
Short name T1876
Test name
Test status
Simulation time 4324325725 ps
CPU time 32.04 seconds
Started Mar 17 01:30:49 PM PDT 24
Finished Mar 17 01:31:21 PM PDT 24
Peak memory 215960 kb
Host smart-6afee9f4-808f-4c29-b4ac-4a89e3769c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978841971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3978841971
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.2120817781
Short name T1453
Test name
Test status
Simulation time 50796165955 ps
CPU time 24.66 seconds
Started Mar 17 03:15:33 PM PDT 24
Finished Mar 17 03:15:58 PM PDT 24
Peak memory 215584 kb
Host smart-30983d12-9547-4298-92d4-db811143d710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120817781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.2120817781
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.880843999
Short name T1471
Test name
Test status
Simulation time 700852636 ps
CPU time 3.13 seconds
Started Mar 17 01:30:50 PM PDT 24
Finished Mar 17 01:30:53 PM PDT 24
Peak memory 215876 kb
Host smart-39d2ef76-4924-4068-9411-60560551937b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880843999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.880843999
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.1588404361
Short name T403
Test name
Test status
Simulation time 102613153 ps
CPU time 1.98 seconds
Started Mar 17 03:15:28 PM PDT 24
Finished Mar 17 03:15:30 PM PDT 24
Peak memory 207852 kb
Host smart-88a51999-96e8-4efd-955c-bf930ea61057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588404361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1588404361
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2512689471
Short name T345
Test name
Test status
Simulation time 19402608 ps
CPU time 0.99 seconds
Started Mar 17 01:30:56 PM PDT 24
Finished Mar 17 01:30:58 PM PDT 24
Peak memory 207176 kb
Host smart-f790d982-73f3-4537-afaa-54a82b574607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512689471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2512689471
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.372386596
Short name T978
Test name
Test status
Simulation time 110771222 ps
CPU time 0.83 seconds
Started Mar 17 03:15:30 PM PDT 24
Finished Mar 17 03:15:31 PM PDT 24
Peak memory 205384 kb
Host smart-58f94ad5-f1ba-4a55-9dc9-f6bf217ef4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372386596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.372386596
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.377011557
Short name T841
Test name
Test status
Simulation time 137811225 ps
CPU time 0.86 seconds
Started Mar 17 01:30:48 PM PDT 24
Finished Mar 17 01:30:50 PM PDT 24
Peak memory 205120 kb
Host smart-685ac4fc-a4b0-4733-83e2-d9a16cde9e57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377011557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.377011557
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.589379671
Short name T546
Test name
Test status
Simulation time 18984606014 ps
CPU time 38.92 seconds
Started Mar 17 01:30:48 PM PDT 24
Finished Mar 17 01:31:28 PM PDT 24
Peak memory 240432 kb
Host smart-384cc8f7-57a4-4d26-a07c-16fc0b9b0b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589379671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.589379671
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_upload.730826315
Short name T223
Test name
Test status
Simulation time 257958659 ps
CPU time 3.43 seconds
Started Mar 17 03:15:35 PM PDT 24
Finished Mar 17 03:15:38 PM PDT 24
Peak memory 218608 kb
Host smart-f5f77daa-19a0-4ee7-8813-fa3dd1e0adb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730826315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.730826315
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.201167683
Short name T1553
Test name
Test status
Simulation time 38757259 ps
CPU time 0.73 seconds
Started Mar 17 03:15:42 PM PDT 24
Finished Mar 17 03:15:43 PM PDT 24
Peak memory 204408 kb
Host smart-62c795ec-7d7f-4907-9ce7-d61ad72237f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201167683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.201167683
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.2460543968
Short name T684
Test name
Test status
Simulation time 39580340 ps
CPU time 0.69 seconds
Started Mar 17 01:30:54 PM PDT 24
Finished Mar 17 01:30:55 PM PDT 24
Peak memory 205180 kb
Host smart-e338f5ee-a17b-4521-91ba-5f5739e35ab9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460543968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
2460543968
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3018974715
Short name T709
Test name
Test status
Simulation time 531365194 ps
CPU time 3.44 seconds
Started Mar 17 01:30:55 PM PDT 24
Finished Mar 17 01:30:59 PM PDT 24
Peak memory 217808 kb
Host smart-bd8aedd9-555d-4ec0-8e0c-3d8ccc9cd221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018974715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3018974715
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.4127585126
Short name T1000
Test name
Test status
Simulation time 14798394378 ps
CPU time 9.22 seconds
Started Mar 17 03:15:41 PM PDT 24
Finished Mar 17 03:15:50 PM PDT 24
Peak memory 234412 kb
Host smart-ece4d2f7-7d06-4d19-b413-4b6a69b8ecdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127585126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.4127585126
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3505111667
Short name T730
Test name
Test status
Simulation time 254504326 ps
CPU time 0.79 seconds
Started Mar 17 01:30:49 PM PDT 24
Finished Mar 17 01:30:50 PM PDT 24
Peak memory 206028 kb
Host smart-c5624be0-b228-49a1-bcd8-fca0de941fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505111667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3505111667
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.59933680
Short name T1154
Test name
Test status
Simulation time 18397922 ps
CPU time 0.76 seconds
Started Mar 17 03:15:42 PM PDT 24
Finished Mar 17 03:15:43 PM PDT 24
Peak memory 205112 kb
Host smart-c1c7ebcf-eea1-4ffb-b735-92215afa011a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59933680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.59933680
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.4163501206
Short name T1375
Test name
Test status
Simulation time 421069033934 ps
CPU time 140.33 seconds
Started Mar 17 03:15:41 PM PDT 24
Finished Mar 17 03:18:02 PM PDT 24
Peak memory 253568 kb
Host smart-94d42bc2-d4e9-4ebc-b290-3fa85a78d91e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163501206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.4163501206
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.515736516
Short name T1230
Test name
Test status
Simulation time 33315618229 ps
CPU time 50.82 seconds
Started Mar 17 01:30:53 PM PDT 24
Finished Mar 17 01:31:44 PM PDT 24
Peak memory 240416 kb
Host smart-9b736243-18d3-47ee-ad1f-c046052c384c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515736516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.515736516
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1483076379
Short name T1340
Test name
Test status
Simulation time 9472843399 ps
CPU time 57.99 seconds
Started Mar 17 01:30:53 PM PDT 24
Finished Mar 17 01:31:51 PM PDT 24
Peak memory 249796 kb
Host smart-b25f807c-2f88-4d36-b6b9-9dfeba2df3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483076379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1483076379
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.191023190
Short name T1113
Test name
Test status
Simulation time 7995593474 ps
CPU time 16.47 seconds
Started Mar 17 03:15:41 PM PDT 24
Finished Mar 17 03:15:57 PM PDT 24
Peak memory 221008 kb
Host smart-52af23fe-6439-4ecf-9b23-9bb7086fc5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191023190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.191023190
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.319495756
Short name T252
Test name
Test status
Simulation time 59555653186 ps
CPU time 237.66 seconds
Started Mar 17 01:30:59 PM PDT 24
Finished Mar 17 01:34:57 PM PDT 24
Peak memory 252156 kb
Host smart-85570d9a-1854-4a04-8dc3-607c746227ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319495756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.319495756
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.2815302262
Short name T1843
Test name
Test status
Simulation time 6460902887 ps
CPU time 20.52 seconds
Started Mar 17 01:30:54 PM PDT 24
Finished Mar 17 01:31:15 PM PDT 24
Peak memory 233304 kb
Host smart-8ade344a-d244-41ba-ad6b-17e975c361cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815302262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.2815302262
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.4256545183
Short name T710
Test name
Test status
Simulation time 863521158 ps
CPU time 11.81 seconds
Started Mar 17 03:15:38 PM PDT 24
Finished Mar 17 03:15:50 PM PDT 24
Peak memory 231600 kb
Host smart-af755736-6c45-47b0-a4e3-11e2dff5b9a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256545183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.4256545183
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1827906505
Short name T1009
Test name
Test status
Simulation time 416119227 ps
CPU time 3.3 seconds
Started Mar 17 03:15:36 PM PDT 24
Finished Mar 17 03:15:39 PM PDT 24
Peak memory 219744 kb
Host smart-34aa1457-8005-4136-9586-21a52dae7a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827906505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1827906505
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_intercept.741594961
Short name T1203
Test name
Test status
Simulation time 754997568 ps
CPU time 4.39 seconds
Started Mar 17 01:30:55 PM PDT 24
Finished Mar 17 01:30:59 PM PDT 24
Peak memory 233924 kb
Host smart-a814534b-c280-4e96-921b-cd3dd5024244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741594961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.741594961
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.4258976091
Short name T1067
Test name
Test status
Simulation time 62929104829 ps
CPU time 31.97 seconds
Started Mar 17 01:30:53 PM PDT 24
Finished Mar 17 01:31:25 PM PDT 24
Peak memory 223240 kb
Host smart-c2cbf597-91b6-4fb2-8241-393735687949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258976091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.4258976091
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.509702012
Short name T507
Test name
Test status
Simulation time 6225972906 ps
CPU time 14.04 seconds
Started Mar 17 03:15:40 PM PDT 24
Finished Mar 17 03:15:54 PM PDT 24
Peak memory 233620 kb
Host smart-7910ec3e-7226-43f3-92e9-a962b506e39d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509702012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.509702012
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2149800065
Short name T1858
Test name
Test status
Simulation time 6974945851 ps
CPU time 11.12 seconds
Started Mar 17 01:30:57 PM PDT 24
Finished Mar 17 01:31:08 PM PDT 24
Peak memory 237308 kb
Host smart-a2ff1fdc-acb0-420c-94c6-bfc2f3e2ab05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149800065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2149800065
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3180173346
Short name T184
Test name
Test status
Simulation time 11096221527 ps
CPU time 21.56 seconds
Started Mar 17 03:15:40 PM PDT 24
Finished Mar 17 03:16:02 PM PDT 24
Peak memory 239120 kb
Host smart-211e77f6-d445-42fe-965d-f18d5d4f0f85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180173346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3180173346
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1788919205
Short name T1543
Test name
Test status
Simulation time 8219489751 ps
CPU time 24.05 seconds
Started Mar 17 03:15:41 PM PDT 24
Finished Mar 17 03:16:05 PM PDT 24
Peak memory 234676 kb
Host smart-4b91b851-d059-4e2a-b921-48b527eabf30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1788919205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1788919205
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.958008628
Short name T588
Test name
Test status
Simulation time 10225874052 ps
CPU time 28.28 seconds
Started Mar 17 01:30:55 PM PDT 24
Finished Mar 17 01:31:23 PM PDT 24
Peak memory 240492 kb
Host smart-f89672af-2de9-4bca-84a2-7adb9f11e9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958008628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.958008628
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1184506074
Short name T889
Test name
Test status
Simulation time 358116632 ps
CPU time 4.13 seconds
Started Mar 17 01:30:54 PM PDT 24
Finished Mar 17 01:30:59 PM PDT 24
Peak memory 218404 kb
Host smart-125a7030-a8c3-4256-8ada-7d2036faea2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1184506074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1184506074
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.650814870
Short name T647
Test name
Test status
Simulation time 1662118345 ps
CPU time 3.62 seconds
Started Mar 17 03:15:42 PM PDT 24
Finished Mar 17 03:15:46 PM PDT 24
Peak memory 220284 kb
Host smart-16620bf9-b258-4642-84be-6ffcda200ac6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=650814870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.650814870
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1309853947
Short name T822
Test name
Test status
Simulation time 52671701 ps
CPU time 1.09 seconds
Started Mar 17 03:15:41 PM PDT 24
Finished Mar 17 03:15:42 PM PDT 24
Peak memory 206480 kb
Host smart-237b7d08-e6b7-4011-933f-ea246c9b18a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309853947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1309853947
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.3315042440
Short name T634
Test name
Test status
Simulation time 194117397451 ps
CPU time 355.2 seconds
Started Mar 17 01:30:53 PM PDT 24
Finished Mar 17 01:36:48 PM PDT 24
Peak memory 267212 kb
Host smart-e50934cf-e92b-47c3-9acd-fd83b67272a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315042440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3315042440
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.3591046427
Short name T1306
Test name
Test status
Simulation time 10507861902 ps
CPU time 55.42 seconds
Started Mar 17 01:30:59 PM PDT 24
Finished Mar 17 01:31:55 PM PDT 24
Peak memory 215996 kb
Host smart-593b3759-436e-4958-bb34-45266fc4ae50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591046427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.3591046427
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.505519870
Short name T1651
Test name
Test status
Simulation time 4130389264 ps
CPU time 23.01 seconds
Started Mar 17 03:15:38 PM PDT 24
Finished Mar 17 03:16:01 PM PDT 24
Peak memory 216136 kb
Host smart-c15a92e3-d53e-4a16-873a-9dc54142f284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505519870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.505519870
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.2102725042
Short name T1496
Test name
Test status
Simulation time 82391379096 ps
CPU time 25.25 seconds
Started Mar 17 01:30:56 PM PDT 24
Finished Mar 17 01:31:21 PM PDT 24
Peak memory 215836 kb
Host smart-d742b7e2-1821-46d6-ac30-46eb66280d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102725042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.2102725042
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3060525679
Short name T1334
Test name
Test status
Simulation time 650664692 ps
CPU time 3.18 seconds
Started Mar 17 03:15:39 PM PDT 24
Finished Mar 17 03:15:42 PM PDT 24
Peak memory 216020 kb
Host smart-9ac4b5ed-836f-4981-815e-892b3a18cf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060525679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3060525679
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1302496025
Short name T1539
Test name
Test status
Simulation time 63384330 ps
CPU time 1.76 seconds
Started Mar 17 01:30:53 PM PDT 24
Finished Mar 17 01:30:55 PM PDT 24
Peak memory 215880 kb
Host smart-552b2ee8-82ca-47cb-9232-d8e56b230375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302496025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1302496025
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3845492584
Short name T1205
Test name
Test status
Simulation time 54764376 ps
CPU time 0.82 seconds
Started Mar 17 03:15:37 PM PDT 24
Finished Mar 17 03:15:39 PM PDT 24
Peak memory 205492 kb
Host smart-eb1ce56a-8e9b-4618-a69a-60183405925b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845492584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3845492584
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3737640029
Short name T1729
Test name
Test status
Simulation time 47149182 ps
CPU time 0.93 seconds
Started Mar 17 01:30:54 PM PDT 24
Finished Mar 17 01:30:55 PM PDT 24
Peak memory 206256 kb
Host smart-092b2937-22df-4360-94bf-6e7d8b183733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737640029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3737640029
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.4147375532
Short name T1391
Test name
Test status
Simulation time 213971621 ps
CPU time 0.82 seconds
Started Mar 17 03:15:42 PM PDT 24
Finished Mar 17 03:15:43 PM PDT 24
Peak memory 205416 kb
Host smart-d8ad7dd9-cd6d-4f23-a7a4-95e6321f847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147375532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.4147375532
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.2965244914
Short name T1588
Test name
Test status
Simulation time 78483805 ps
CPU time 2.5 seconds
Started Mar 17 01:30:54 PM PDT 24
Finished Mar 17 01:30:57 PM PDT 24
Peak memory 215908 kb
Host smart-c4f0b599-d75a-4acb-9638-f6a151b60b14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965244914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.2965244914
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_upload.4017688348
Short name T1111
Test name
Test status
Simulation time 3011937584 ps
CPU time 11.53 seconds
Started Mar 17 03:15:40 PM PDT 24
Finished Mar 17 03:15:52 PM PDT 24
Peak memory 227216 kb
Host smart-76082be6-db4a-4cc8-90a5-1b98f2b59b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017688348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.4017688348
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1718316061
Short name T528
Test name
Test status
Simulation time 46223437 ps
CPU time 0.8 seconds
Started Mar 17 01:31:03 PM PDT 24
Finished Mar 17 01:31:04 PM PDT 24
Peak memory 205172 kb
Host smart-5b109738-b414-4a4e-85fb-e29d425738ee
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718316061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1718316061
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4240197539
Short name T1048
Test name
Test status
Simulation time 14872276 ps
CPU time 0.73 seconds
Started Mar 17 03:15:46 PM PDT 24
Finished Mar 17 03:15:48 PM PDT 24
Peak memory 204968 kb
Host smart-c64ac912-5770-4aec-8875-f04cbbdbff56
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240197539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4240197539
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.2060572785
Short name T1078
Test name
Test status
Simulation time 2752291696 ps
CPU time 4.28 seconds
Started Mar 17 03:15:40 PM PDT 24
Finished Mar 17 03:15:45 PM PDT 24
Peak memory 224404 kb
Host smart-cc6022b3-c2b1-4a51-8c73-a6871814b54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060572785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.2060572785
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.941984499
Short name T460
Test name
Test status
Simulation time 1262505268 ps
CPU time 6.04 seconds
Started Mar 17 01:30:53 PM PDT 24
Finished Mar 17 01:30:59 PM PDT 24
Peak memory 218448 kb
Host smart-b46b3cc7-cbfa-47f8-b46e-9a04fa29a2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941984499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.941984499
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1111284117
Short name T619
Test name
Test status
Simulation time 22071899 ps
CPU time 0.76 seconds
Started Mar 17 01:30:55 PM PDT 24
Finished Mar 17 01:30:55 PM PDT 24
Peak memory 204956 kb
Host smart-4e4f9724-ebdc-4a5b-9004-8f260dfb5f84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1111284117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1111284117
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.1532956714
Short name T886
Test name
Test status
Simulation time 75863185 ps
CPU time 0.84 seconds
Started Mar 17 03:15:42 PM PDT 24
Finished Mar 17 03:15:43 PM PDT 24
Peak memory 206200 kb
Host smart-160a6ccb-3ce7-46c4-b9ce-862ef9378f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532956714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.1532956714
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.3959000924
Short name T1399
Test name
Test status
Simulation time 145538450061 ps
CPU time 247.83 seconds
Started Mar 17 01:31:00 PM PDT 24
Finished Mar 17 01:35:08 PM PDT 24
Peak memory 271944 kb
Host smart-1edcb1da-94a1-4458-bd9b-495ebd1bc328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959000924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.3959000924
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.416169393
Short name T175
Test name
Test status
Simulation time 220429123222 ps
CPU time 213.9 seconds
Started Mar 17 03:15:48 PM PDT 24
Finished Mar 17 03:19:22 PM PDT 24
Peak memory 240748 kb
Host smart-6cfd38c1-2f99-41d9-b960-396d4a1128ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416169393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.416169393
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2582300472
Short name T844
Test name
Test status
Simulation time 8450384479 ps
CPU time 105.1 seconds
Started Mar 17 03:15:47 PM PDT 24
Finished Mar 17 03:17:33 PM PDT 24
Peak memory 256320 kb
Host smart-afc39bc2-fd08-48a8-b365-99b72cafa1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582300472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2582300472
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.2700966528
Short name T1305
Test name
Test status
Simulation time 18558256294 ps
CPU time 137.31 seconds
Started Mar 17 01:31:00 PM PDT 24
Finished Mar 17 01:33:18 PM PDT 24
Peak memory 248768 kb
Host smart-20b1938e-5ebb-4add-8011-db051f641910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700966528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2700966528
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2275908230
Short name T1662
Test name
Test status
Simulation time 207313948216 ps
CPU time 180.99 seconds
Started Mar 17 01:31:01 PM PDT 24
Finished Mar 17 01:34:02 PM PDT 24
Peak memory 267432 kb
Host smart-36139ee0-cfcf-4c7d-ab3a-cd082ed9372c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275908230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2275908230
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3819715197
Short name T1424
Test name
Test status
Simulation time 411866467381 ps
CPU time 720.26 seconds
Started Mar 17 03:15:45 PM PDT 24
Finished Mar 17 03:27:47 PM PDT 24
Peak memory 273244 kb
Host smart-42d35d19-90e9-4d3d-b76c-97f327b7e1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819715197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3819715197
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2515856810
Short name T1164
Test name
Test status
Simulation time 486527799 ps
CPU time 16.62 seconds
Started Mar 17 03:15:41 PM PDT 24
Finished Mar 17 03:15:58 PM PDT 24
Peak memory 246872 kb
Host smart-3898cee5-9c7b-4f93-853c-fd61797d7bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515856810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2515856810
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3147042805
Short name T448
Test name
Test status
Simulation time 2431555451 ps
CPU time 19.92 seconds
Started Mar 17 01:31:02 PM PDT 24
Finished Mar 17 01:31:22 PM PDT 24
Peak memory 233296 kb
Host smart-698e95c1-b51e-4b7c-821b-2138fe91aa5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147042805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3147042805
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_intercept.10785751
Short name T1750
Test name
Test status
Simulation time 4624114022 ps
CPU time 5.81 seconds
Started Mar 17 03:15:45 PM PDT 24
Finished Mar 17 03:15:51 PM PDT 24
Peak memory 217544 kb
Host smart-e27727ef-94d6-4761-920c-8c8d3ee79dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10785751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.10785751
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4247165743
Short name T554
Test name
Test status
Simulation time 2148210399 ps
CPU time 8.8 seconds
Started Mar 17 01:30:57 PM PDT 24
Finished Mar 17 01:31:06 PM PDT 24
Peak memory 234092 kb
Host smart-dd0680e4-89d5-4dec-be44-1270ffde0c09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4247165743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4247165743
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1395965025
Short name T727
Test name
Test status
Simulation time 12025638010 ps
CPU time 17.03 seconds
Started Mar 17 01:30:55 PM PDT 24
Finished Mar 17 01:31:12 PM PDT 24
Peak memory 236252 kb
Host smart-22559dd3-3e3e-45d8-8d34-054dc4e04416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395965025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1395965025
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.2005656730
Short name T969
Test name
Test status
Simulation time 17086390332 ps
CPU time 15.09 seconds
Started Mar 17 03:15:42 PM PDT 24
Finished Mar 17 03:15:57 PM PDT 24
Peak memory 230072 kb
Host smart-53ce70ff-5245-4448-8075-f8c5ca12e93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005656730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2005656730
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.2484472865
Short name T1088
Test name
Test status
Simulation time 1009039459 ps
CPU time 6.94 seconds
Started Mar 17 01:30:53 PM PDT 24
Finished Mar 17 01:31:00 PM PDT 24
Peak memory 223980 kb
Host smart-acc01d6c-cb35-4bd9-827c-7e8fedaf5e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484472865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.2484472865
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3298509008
Short name T1104
Test name
Test status
Simulation time 6194548117 ps
CPU time 21.67 seconds
Started Mar 17 03:15:42 PM PDT 24
Finished Mar 17 03:16:03 PM PDT 24
Peak memory 233744 kb
Host smart-26b7fe46-cf3d-4f10-898f-a80400a85538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298509008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3298509008
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.185340688
Short name T46
Test name
Test status
Simulation time 5337274769 ps
CPU time 14.57 seconds
Started Mar 17 01:30:59 PM PDT 24
Finished Mar 17 01:31:14 PM PDT 24
Peak memory 217692 kb
Host smart-4d65d0e6-6f6e-4448-80e1-40b46eddc91d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185340688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.185340688
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2446433395
Short name T1530
Test name
Test status
Simulation time 4194563788 ps
CPU time 13.84 seconds
Started Mar 17 03:15:41 PM PDT 24
Finished Mar 17 03:15:55 PM PDT 24
Peak memory 236752 kb
Host smart-f161bba2-4808-465b-9e1f-bea761c97584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446433395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2446433395
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1427638764
Short name T952
Test name
Test status
Simulation time 673462660 ps
CPU time 5.32 seconds
Started Mar 17 01:31:01 PM PDT 24
Finished Mar 17 01:31:06 PM PDT 24
Peak memory 221768 kb
Host smart-f97608d8-d83e-45d1-bb99-74eeed1b0f7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1427638764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1427638764
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.4255779264
Short name T1709
Test name
Test status
Simulation time 1379854696 ps
CPU time 3.88 seconds
Started Mar 17 03:15:45 PM PDT 24
Finished Mar 17 03:15:49 PM PDT 24
Peak memory 218484 kb
Host smart-f6823931-23d9-4741-887c-36c63ddfdc8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4255779264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.4255779264
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3788722856
Short name T1513
Test name
Test status
Simulation time 89274701 ps
CPU time 0.95 seconds
Started Mar 17 03:15:48 PM PDT 24
Finished Mar 17 03:15:50 PM PDT 24
Peak memory 206536 kb
Host smart-957b8f0b-dae0-406f-8d74-27e0431bb092
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788722856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3788722856
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3428368807
Short name T288
Test name
Test status
Simulation time 18138361151 ps
CPU time 50.37 seconds
Started Mar 17 03:15:42 PM PDT 24
Finished Mar 17 03:16:33 PM PDT 24
Peak memory 216200 kb
Host smart-282da6d1-06ea-4fcc-aec7-f3dca8a8def6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428368807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3428368807
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.3766688545
Short name T450
Test name
Test status
Simulation time 6917431074 ps
CPU time 24.29 seconds
Started Mar 17 01:30:56 PM PDT 24
Finished Mar 17 01:31:21 PM PDT 24
Peak memory 215944 kb
Host smart-df3c17d7-58f6-4f0a-83b5-aedaf3716db8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766688545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3766688545
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2450929610
Short name T308
Test name
Test status
Simulation time 5273762793 ps
CPU time 2.31 seconds
Started Mar 17 01:30:56 PM PDT 24
Finished Mar 17 01:30:58 PM PDT 24
Peak memory 207544 kb
Host smart-576b708e-a2d8-47fa-9b52-96bfd26852bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450929610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2450929610
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.257365035
Short name T1666
Test name
Test status
Simulation time 9462035844 ps
CPU time 9.33 seconds
Started Mar 17 03:15:45 PM PDT 24
Finished Mar 17 03:15:55 PM PDT 24
Peak memory 216120 kb
Host smart-188f7bd0-4cbf-4620-933d-3acebde4fbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257365035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.257365035
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2150314484
Short name T1665
Test name
Test status
Simulation time 41472706 ps
CPU time 0.87 seconds
Started Mar 17 03:15:41 PM PDT 24
Finished Mar 17 03:15:43 PM PDT 24
Peak memory 206804 kb
Host smart-d098d46b-cbdd-4a1d-aa09-ae6c0a9834ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2150314484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2150314484
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.3573526321
Short name T1381
Test name
Test status
Simulation time 34299358 ps
CPU time 0.85 seconds
Started Mar 17 01:30:53 PM PDT 24
Finished Mar 17 01:30:54 PM PDT 24
Peak memory 206244 kb
Host smart-b31cacf2-65bf-46d6-a175-c4ce7b1732da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573526321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3573526321
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2503601425
Short name T1151
Test name
Test status
Simulation time 42961811 ps
CPU time 0.91 seconds
Started Mar 17 03:15:42 PM PDT 24
Finished Mar 17 03:15:43 PM PDT 24
Peak memory 206468 kb
Host smart-aeeb7133-c51e-47bf-8f9e-645885d2015c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503601425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2503601425
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.4037728176
Short name T1003
Test name
Test status
Simulation time 204594046 ps
CPU time 0.92 seconds
Started Mar 17 01:30:55 PM PDT 24
Finished Mar 17 01:30:56 PM PDT 24
Peak memory 205180 kb
Host smart-0e090939-b500-49ff-ab82-f862a5c171cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037728176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.4037728176
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1726552292
Short name T1712
Test name
Test status
Simulation time 3497712224 ps
CPU time 8.78 seconds
Started Mar 17 03:15:41 PM PDT 24
Finished Mar 17 03:15:50 PM PDT 24
Peak memory 234188 kb
Host smart-e4becfec-89ca-4b7a-9ece-2842c1648adf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726552292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1726552292
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_upload.3739846359
Short name T192
Test name
Test status
Simulation time 1149639560 ps
CPU time 8.57 seconds
Started Mar 17 01:30:55 PM PDT 24
Finished Mar 17 01:31:04 PM PDT 24
Peak memory 236468 kb
Host smart-6a7c48fe-3ba6-491f-8197-4c6c5c008907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739846359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3739846359
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.1277692530
Short name T1148
Test name
Test status
Simulation time 12894710 ps
CPU time 0.71 seconds
Started Mar 17 03:15:52 PM PDT 24
Finished Mar 17 03:15:53 PM PDT 24
Peak memory 205016 kb
Host smart-d5a5d3f7-8a59-4329-96ad-b2c316e40343
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277692530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
1277692530
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.4242189115
Short name T1793
Test name
Test status
Simulation time 24724880 ps
CPU time 0.69 seconds
Started Mar 17 01:31:05 PM PDT 24
Finished Mar 17 01:31:06 PM PDT 24
Peak memory 204232 kb
Host smart-4f73891f-7c0d-48f2-a762-c5c873bdfdb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242189115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
4242189115
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1862680206
Short name T494
Test name
Test status
Simulation time 461594296 ps
CPU time 2.32 seconds
Started Mar 17 03:15:52 PM PDT 24
Finished Mar 17 03:15:55 PM PDT 24
Peak memory 218340 kb
Host smart-f79e6c0b-21ed-4cee-9199-f53c19c513ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862680206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1862680206
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.3854893808
Short name T148
Test name
Test status
Simulation time 7586945870 ps
CPU time 15.17 seconds
Started Mar 17 01:31:09 PM PDT 24
Finished Mar 17 01:31:24 PM PDT 24
Peak memory 234280 kb
Host smart-e36af3be-0590-48ea-8d0b-8dd6f346ec81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854893808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.3854893808
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.1921896247
Short name T939
Test name
Test status
Simulation time 60435119 ps
CPU time 0.77 seconds
Started Mar 17 03:15:46 PM PDT 24
Finished Mar 17 03:15:48 PM PDT 24
Peak memory 206172 kb
Host smart-d86914cf-f984-4853-938c-6346a42b3aae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921896247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1921896247
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.4215903541
Short name T1081
Test name
Test status
Simulation time 16960025 ps
CPU time 0.87 seconds
Started Mar 17 01:31:00 PM PDT 24
Finished Mar 17 01:31:01 PM PDT 24
Peak memory 205988 kb
Host smart-3a95b6b7-5762-4047-b893-8cedbd3e4d04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215903541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.4215903541
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2862589226
Short name T671
Test name
Test status
Simulation time 53708507753 ps
CPU time 75.76 seconds
Started Mar 17 01:31:04 PM PDT 24
Finished Mar 17 01:32:20 PM PDT 24
Peak memory 240492 kb
Host smart-75e149a4-e6a3-4ad3-bac8-d7852d51fed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862589226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2862589226
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.1817700225
Short name T1462
Test name
Test status
Simulation time 79547968553 ps
CPU time 168.15 seconds
Started Mar 17 01:31:06 PM PDT 24
Finished Mar 17 01:33:54 PM PDT 24
Peak memory 255140 kb
Host smart-c8fea5b1-607f-48e3-bce9-32275e2b9271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817700225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.1817700225
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2152266591
Short name T874
Test name
Test status
Simulation time 124593840498 ps
CPU time 795.94 seconds
Started Mar 17 03:15:50 PM PDT 24
Finished Mar 17 03:29:07 PM PDT 24
Peak memory 265752 kb
Host smart-b027ebbf-8a49-420f-a521-ae4970df634b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152266591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2152266591
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1451458805
Short name T38
Test name
Test status
Simulation time 9046433611 ps
CPU time 93.45 seconds
Started Mar 17 03:15:51 PM PDT 24
Finished Mar 17 03:17:25 PM PDT 24
Peak memory 252084 kb
Host smart-b3f493cd-31e2-49da-ae53-0acd5540ab00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451458805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1451458805
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3047850825
Short name T232
Test name
Test status
Simulation time 116398867526 ps
CPU time 503.48 seconds
Started Mar 17 01:31:08 PM PDT 24
Finished Mar 17 01:39:32 PM PDT 24
Peak memory 254480 kb
Host smart-5c73f7b1-fb4b-4ad4-8deb-876031ee1a9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047850825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3047850825
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.1603654439
Short name T1752
Test name
Test status
Simulation time 19540496709 ps
CPU time 31.05 seconds
Started Mar 17 03:15:52 PM PDT 24
Finished Mar 17 03:16:24 PM PDT 24
Peak memory 232604 kb
Host smart-fb041f1c-c953-407a-bb71-ce7e604364e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603654439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.1603654439
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2094924143
Short name T389
Test name
Test status
Simulation time 1971453183 ps
CPU time 13.33 seconds
Started Mar 17 01:31:06 PM PDT 24
Finished Mar 17 01:31:19 PM PDT 24
Peak memory 222136 kb
Host smart-e6f374f6-7958-454a-b838-e015c7ccdca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094924143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2094924143
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3337659845
Short name T951
Test name
Test status
Simulation time 2768995815 ps
CPU time 11.12 seconds
Started Mar 17 01:31:03 PM PDT 24
Finished Mar 17 01:31:14 PM PDT 24
Peak memory 233364 kb
Host smart-dde2e939-f519-4cf8-84f2-8545d972c431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337659845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3337659845
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_intercept.3489452822
Short name T1556
Test name
Test status
Simulation time 10366540717 ps
CPU time 9.37 seconds
Started Mar 17 03:15:48 PM PDT 24
Finished Mar 17 03:15:58 PM PDT 24
Peak memory 234764 kb
Host smart-d01de3bc-3148-48bb-ac47-3ff8265279a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489452822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3489452822
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2174687060
Short name T991
Test name
Test status
Simulation time 8895046649 ps
CPU time 26.44 seconds
Started Mar 17 03:15:51 PM PDT 24
Finished Mar 17 03:16:17 PM PDT 24
Peak memory 239808 kb
Host smart-b4010023-93f6-467b-b01d-ea51c18fbf38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174687060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2174687060
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2204887801
Short name T1521
Test name
Test status
Simulation time 890138308 ps
CPU time 7.37 seconds
Started Mar 17 01:30:59 PM PDT 24
Finished Mar 17 01:31:07 PM PDT 24
Peak memory 232212 kb
Host smart-1574366a-9fda-488e-9a25-e8800560e32c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204887801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2204887801
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2475575631
Short name T860
Test name
Test status
Simulation time 8293492249 ps
CPU time 4.34 seconds
Started Mar 17 01:31:02 PM PDT 24
Finished Mar 17 01:31:07 PM PDT 24
Peak memory 218004 kb
Host smart-0f0e1ff1-fc96-466d-ad09-5af40ec1cc85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475575631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2475575631
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.4141424830
Short name T1259
Test name
Test status
Simulation time 25530650542 ps
CPU time 34.35 seconds
Started Mar 17 03:15:46 PM PDT 24
Finished Mar 17 03:16:21 PM PDT 24
Peak memory 238504 kb
Host smart-e1af81e2-80fa-45d5-a978-c327e83554bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141424830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.4141424830
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3613578220
Short name T1335
Test name
Test status
Simulation time 31513182572 ps
CPU time 25.01 seconds
Started Mar 17 03:15:47 PM PDT 24
Finished Mar 17 03:16:12 PM PDT 24
Peak memory 224380 kb
Host smart-f9b11f5e-8c63-4471-a001-07b026508812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613578220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3613578220
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.942302454
Short name T1374
Test name
Test status
Simulation time 10428105271 ps
CPU time 29.59 seconds
Started Mar 17 01:31:04 PM PDT 24
Finished Mar 17 01:31:33 PM PDT 24
Peak memory 233264 kb
Host smart-bd1618ab-eb47-461c-946d-5aed5e71abf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942302454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.942302454
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.1797030951
Short name T501
Test name
Test status
Simulation time 135005369 ps
CPU time 3.95 seconds
Started Mar 17 03:15:51 PM PDT 24
Finished Mar 17 03:15:56 PM PDT 24
Peak memory 221868 kb
Host smart-ac6c4d8a-19b2-4866-9242-071b46ea2b92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1797030951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.1797030951
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.2320834361
Short name T941
Test name
Test status
Simulation time 5761260783 ps
CPU time 6.72 seconds
Started Mar 17 01:31:06 PM PDT 24
Finished Mar 17 01:31:13 PM PDT 24
Peak memory 222552 kb
Host smart-82553c8a-81a9-48be-aa3f-296ee73f4332
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2320834361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.2320834361
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.292378572
Short name T120
Test name
Test status
Simulation time 111833195659 ps
CPU time 767.33 seconds
Started Mar 17 01:31:07 PM PDT 24
Finished Mar 17 01:43:55 PM PDT 24
Peak memory 266184 kb
Host smart-b16f0230-a83c-48f1-aa2b-a985c9f6dde0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292378572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.292378572
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.406244665
Short name T750
Test name
Test status
Simulation time 202322618 ps
CPU time 1.15 seconds
Started Mar 17 03:15:51 PM PDT 24
Finished Mar 17 03:15:53 PM PDT 24
Peak memory 206956 kb
Host smart-d9ad6e34-5f80-4d41-9968-441cb9de3622
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406244665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.406244665
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.1812876751
Short name T1256
Test name
Test status
Simulation time 11285780286 ps
CPU time 58 seconds
Started Mar 17 01:31:02 PM PDT 24
Finished Mar 17 01:32:00 PM PDT 24
Peak memory 215916 kb
Host smart-e3669790-5f38-48d8-8019-952ec2a794e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812876751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.1812876751
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3984990106
Short name T291
Test name
Test status
Simulation time 9246766973 ps
CPU time 49.25 seconds
Started Mar 17 03:15:48 PM PDT 24
Finished Mar 17 03:16:37 PM PDT 24
Peak memory 216340 kb
Host smart-a2ce67c0-192b-4980-b0b8-91e461c3620d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984990106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3984990106
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.1961179768
Short name T983
Test name
Test status
Simulation time 10759730151 ps
CPU time 3.66 seconds
Started Mar 17 01:31:02 PM PDT 24
Finished Mar 17 01:31:06 PM PDT 24
Peak memory 215972 kb
Host smart-3431c625-17d2-485b-948e-f350bad90890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961179768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.1961179768
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3560573805
Short name T525
Test name
Test status
Simulation time 1581014026 ps
CPU time 9.63 seconds
Started Mar 17 03:15:46 PM PDT 24
Finished Mar 17 03:15:57 PM PDT 24
Peak memory 215984 kb
Host smart-7e170307-98f6-46bd-951e-8fa7368a436b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560573805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3560573805
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2804575727
Short name T445
Test name
Test status
Simulation time 86813037 ps
CPU time 3.84 seconds
Started Mar 17 01:31:00 PM PDT 24
Finished Mar 17 01:31:04 PM PDT 24
Peak memory 215824 kb
Host smart-b7a313b3-f5de-485c-9847-d85770ce6ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804575727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2804575727
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.4164491626
Short name T876
Test name
Test status
Simulation time 325882678 ps
CPU time 1.73 seconds
Started Mar 17 03:15:47 PM PDT 24
Finished Mar 17 03:15:50 PM PDT 24
Peak memory 216076 kb
Host smart-17fa477c-4b6b-4eb6-b361-e0ee0e4a7a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164491626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.4164491626
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.2990447281
Short name T405
Test name
Test status
Simulation time 68959055 ps
CPU time 0.95 seconds
Started Mar 17 01:31:00 PM PDT 24
Finished Mar 17 01:31:01 PM PDT 24
Peak memory 206224 kb
Host smart-5d6886f9-7f56-4283-8976-5500b297e6aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990447281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.2990447281
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.3982172124
Short name T1831
Test name
Test status
Simulation time 99234989 ps
CPU time 0.86 seconds
Started Mar 17 03:15:46 PM PDT 24
Finished Mar 17 03:15:48 PM PDT 24
Peak memory 205424 kb
Host smart-9e73fbcd-0e65-4052-b348-0dde827159f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982172124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3982172124
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.3272286111
Short name T1072
Test name
Test status
Simulation time 18941165590 ps
CPU time 16.88 seconds
Started Mar 17 01:31:02 PM PDT 24
Finished Mar 17 01:31:19 PM PDT 24
Peak memory 234608 kb
Host smart-05ef2403-b971-48d8-ac58-92e3cd3d66d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272286111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.3272286111
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_upload.4158497963
Short name T1499
Test name
Test status
Simulation time 5919758235 ps
CPU time 14.95 seconds
Started Mar 17 03:15:50 PM PDT 24
Finished Mar 17 03:16:06 PM PDT 24
Peak memory 234852 kb
Host smart-cc171020-e811-4db6-a6fc-6522727e1970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158497963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.4158497963
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1189555491
Short name T944
Test name
Test status
Simulation time 13926032 ps
CPU time 0.69 seconds
Started Mar 17 03:15:53 PM PDT 24
Finished Mar 17 03:15:55 PM PDT 24
Peak memory 205032 kb
Host smart-80f3de94-4f49-4ea8-9876-661c234ec6c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189555491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1189555491
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.2067065491
Short name T1014
Test name
Test status
Simulation time 56840684 ps
CPU time 0.7 seconds
Started Mar 17 01:31:07 PM PDT 24
Finished Mar 17 01:31:08 PM PDT 24
Peak memory 204796 kb
Host smart-6e5879d1-f323-4969-a471-bd405061f186
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067065491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
2067065491
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1150809629
Short name T839
Test name
Test status
Simulation time 63077878 ps
CPU time 2.6 seconds
Started Mar 17 01:31:07 PM PDT 24
Finished Mar 17 01:31:10 PM PDT 24
Peak memory 233492 kb
Host smart-9e0359e4-e33a-4246-adf0-158722ee7c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1150809629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1150809629
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1346287703
Short name T380
Test name
Test status
Simulation time 5576010431 ps
CPU time 6.72 seconds
Started Mar 17 03:15:56 PM PDT 24
Finished Mar 17 03:16:03 PM PDT 24
Peak memory 234244 kb
Host smart-c42b74ce-2bca-49ff-aa61-c792affafc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346287703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1346287703
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1690354854
Short name T1559
Test name
Test status
Simulation time 47256520 ps
CPU time 0.76 seconds
Started Mar 17 01:31:05 PM PDT 24
Finished Mar 17 01:31:06 PM PDT 24
Peak memory 205956 kb
Host smart-c965590d-358e-46c5-90f1-5db334132909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690354854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1690354854
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.4026374554
Short name T514
Test name
Test status
Simulation time 33952369 ps
CPU time 0.8 seconds
Started Mar 17 03:15:52 PM PDT 24
Finished Mar 17 03:15:54 PM PDT 24
Peak memory 206516 kb
Host smart-9f2e08db-c47d-47d1-a03e-c40aea24d9fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026374554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.4026374554
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.1409975935
Short name T1146
Test name
Test status
Simulation time 91826528142 ps
CPU time 138.67 seconds
Started Mar 17 03:15:54 PM PDT 24
Finished Mar 17 03:18:13 PM PDT 24
Peak memory 256212 kb
Host smart-b8a15dad-0030-4b9f-90ab-a13e39ee8206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409975935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.1409975935
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2019175232
Short name T1032
Test name
Test status
Simulation time 44309893733 ps
CPU time 82.84 seconds
Started Mar 17 01:31:07 PM PDT 24
Finished Mar 17 01:32:30 PM PDT 24
Peak memory 253824 kb
Host smart-e29b7796-ab1e-4c31-b155-07f31aa93b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019175232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2019175232
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1819799790
Short name T320
Test name
Test status
Simulation time 5545920641 ps
CPU time 32.14 seconds
Started Mar 17 03:15:56 PM PDT 24
Finished Mar 17 03:16:28 PM PDT 24
Peak memory 239208 kb
Host smart-13f424d8-677a-4e33-b154-78878a7f889f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819799790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1819799790
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.829997749
Short name T1704
Test name
Test status
Simulation time 13051930433 ps
CPU time 45.28 seconds
Started Mar 17 01:31:06 PM PDT 24
Finished Mar 17 01:31:52 PM PDT 24
Peak memory 233324 kb
Host smart-27e85fbb-0b3e-4f54-b619-c04501d82cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829997749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.829997749
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3038859511
Short name T266
Test name
Test status
Simulation time 51834918437 ps
CPU time 321 seconds
Started Mar 17 03:15:56 PM PDT 24
Finished Mar 17 03:21:17 PM PDT 24
Peak memory 267200 kb
Host smart-32d4f750-270c-47bd-9fff-2c38d235d0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038859511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3038859511
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.428865758
Short name T1336
Test name
Test status
Simulation time 6625459009 ps
CPU time 55.24 seconds
Started Mar 17 01:31:06 PM PDT 24
Finished Mar 17 01:32:02 PM PDT 24
Peak memory 235372 kb
Host smart-ac6b2358-976a-4246-b55d-e63c431cbfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428865758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle
.428865758
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2090231469
Short name T816
Test name
Test status
Simulation time 6489258059 ps
CPU time 31.07 seconds
Started Mar 17 03:15:53 PM PDT 24
Finished Mar 17 03:16:25 PM PDT 24
Peak memory 233524 kb
Host smart-6407fe77-887a-44ae-a890-541bae6a7ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090231469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2090231469
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.700730711
Short name T574
Test name
Test status
Simulation time 1218691884 ps
CPU time 10.9 seconds
Started Mar 17 01:31:06 PM PDT 24
Finished Mar 17 01:31:17 PM PDT 24
Peak memory 247432 kb
Host smart-7f0e8f35-fc43-42b5-acb0-2086ccf6f344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700730711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.700730711
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1506802525
Short name T1483
Test name
Test status
Simulation time 145959577 ps
CPU time 3.04 seconds
Started Mar 17 03:15:53 PM PDT 24
Finished Mar 17 03:15:56 PM PDT 24
Peak memory 218164 kb
Host smart-8866c69e-62ce-4c27-a2e2-8abda1d96f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506802525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1506802525
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3391422825
Short name T1423
Test name
Test status
Simulation time 700456771 ps
CPU time 4.62 seconds
Started Mar 17 01:31:04 PM PDT 24
Finished Mar 17 01:31:09 PM PDT 24
Peak memory 217684 kb
Host smart-9ff4a268-e627-4be5-8ec0-942e3358ed14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391422825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3391422825
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.1953809744
Short name T1236
Test name
Test status
Simulation time 21081623359 ps
CPU time 57.76 seconds
Started Mar 17 03:15:54 PM PDT 24
Finished Mar 17 03:16:52 PM PDT 24
Peak memory 239976 kb
Host smart-cda378dc-866f-4d75-bc88-fbeded2239c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953809744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.1953809744
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.240979766
Short name T1436
Test name
Test status
Simulation time 23989803671 ps
CPU time 25.62 seconds
Started Mar 17 01:31:05 PM PDT 24
Finished Mar 17 01:31:31 PM PDT 24
Peak memory 230876 kb
Host smart-3a776586-2173-4ad8-a982-da83400c2838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240979766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.240979766
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.277659909
Short name T1432
Test name
Test status
Simulation time 13253487593 ps
CPU time 7.5 seconds
Started Mar 17 01:31:09 PM PDT 24
Finished Mar 17 01:31:16 PM PDT 24
Peak memory 224076 kb
Host smart-73ea60cd-8bd8-4011-ae2b-79406125c98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277659909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.277659909
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.4188292161
Short name T598
Test name
Test status
Simulation time 6026601883 ps
CPU time 12.25 seconds
Started Mar 17 03:15:53 PM PDT 24
Finished Mar 17 03:16:06 PM PDT 24
Peak memory 233812 kb
Host smart-1e622cdf-1e44-4dc6-af03-84393213ecb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188292161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.4188292161
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2248139710
Short name T221
Test name
Test status
Simulation time 5678654780 ps
CPU time 13.48 seconds
Started Mar 17 03:15:57 PM PDT 24
Finished Mar 17 03:16:10 PM PDT 24
Peak memory 237032 kb
Host smart-ac0d4a84-89c9-462a-a34b-6ff612fe796d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248139710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2248139710
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.462482207
Short name T1644
Test name
Test status
Simulation time 4103964492 ps
CPU time 17.55 seconds
Started Mar 17 01:31:05 PM PDT 24
Finished Mar 17 01:31:23 PM PDT 24
Peak memory 232960 kb
Host smart-80759603-d216-4c10-ac02-6906ed6ccaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462482207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.462482207
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1153105909
Short name T126
Test name
Test status
Simulation time 5785005105 ps
CPU time 5.79 seconds
Started Mar 17 03:15:56 PM PDT 24
Finished Mar 17 03:16:02 PM PDT 24
Peak memory 222748 kb
Host smart-16be3904-16eb-4464-87ae-907e4e805241
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1153105909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1153105909
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.3298850060
Short name T356
Test name
Test status
Simulation time 1465708099 ps
CPU time 6.98 seconds
Started Mar 17 01:31:08 PM PDT 24
Finished Mar 17 01:31:15 PM PDT 24
Peak memory 221176 kb
Host smart-f986d9aa-665c-4b94-ab6b-1b1dbaf3d1fd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3298850060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.3298850060
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2692715615
Short name T1103
Test name
Test status
Simulation time 83563176357 ps
CPU time 84.2 seconds
Started Mar 17 03:15:53 PM PDT 24
Finished Mar 17 03:17:17 PM PDT 24
Peak memory 273452 kb
Host smart-42c4da90-e447-4be1-8129-34960a058b1d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692715615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2692715615
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.271181066
Short name T39
Test name
Test status
Simulation time 271962621313 ps
CPU time 633.5 seconds
Started Mar 17 01:31:06 PM PDT 24
Finished Mar 17 01:41:40 PM PDT 24
Peak memory 283380 kb
Host smart-cf23adff-0583-4bcf-b10b-c21cfab138af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271181066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.271181066
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3679025992
Short name T1636
Test name
Test status
Simulation time 554623372 ps
CPU time 7.63 seconds
Started Mar 17 01:31:06 PM PDT 24
Finished Mar 17 01:31:13 PM PDT 24
Peak memory 215856 kb
Host smart-49cc8680-264a-46cc-9489-1e1f0299b368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3679025992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3679025992
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.53917986
Short name T1531
Test name
Test status
Simulation time 9529582694 ps
CPU time 35.13 seconds
Started Mar 17 03:15:50 PM PDT 24
Finished Mar 17 03:16:25 PM PDT 24
Peak memory 216336 kb
Host smart-c9cafebd-31d8-4ed7-a930-16a77f34ef29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53917986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.53917986
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.33732872
Short name T1819
Test name
Test status
Simulation time 5546789667 ps
CPU time 17.3 seconds
Started Mar 17 03:15:52 PM PDT 24
Finished Mar 17 03:16:10 PM PDT 24
Peak memory 216136 kb
Host smart-c4d32971-1b1e-4802-9c9c-2fea8befa557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33732872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.33732872
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.4191420135
Short name T802
Test name
Test status
Simulation time 617068799 ps
CPU time 3.43 seconds
Started Mar 17 01:31:04 PM PDT 24
Finished Mar 17 01:31:07 PM PDT 24
Peak memory 215772 kb
Host smart-17002c57-44be-422d-92cd-6f00dcc3fb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191420135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.4191420135
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2657327034
Short name T669
Test name
Test status
Simulation time 180690873 ps
CPU time 1.19 seconds
Started Mar 17 01:31:05 PM PDT 24
Finished Mar 17 01:31:06 PM PDT 24
Peak memory 207608 kb
Host smart-64e6a30b-d108-49b9-84e5-f2f80ea94c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657327034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2657327034
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.3478399336
Short name T879
Test name
Test status
Simulation time 112640694 ps
CPU time 3.87 seconds
Started Mar 17 03:15:52 PM PDT 24
Finished Mar 17 03:15:56 PM PDT 24
Peak memory 216120 kb
Host smart-c0fc6997-6ba1-4679-afb9-379d02598c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478399336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.3478399336
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1787612269
Short name T1617
Test name
Test status
Simulation time 231972331 ps
CPU time 0.88 seconds
Started Mar 17 03:16:03 PM PDT 24
Finished Mar 17 03:16:04 PM PDT 24
Peak memory 205448 kb
Host smart-d77010a9-06e7-475c-9082-11d62be53578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787612269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1787612269
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3124654973
Short name T1581
Test name
Test status
Simulation time 98575580 ps
CPU time 1.04 seconds
Started Mar 17 01:31:09 PM PDT 24
Finished Mar 17 01:31:10 PM PDT 24
Peak memory 206200 kb
Host smart-1f046e3a-b9f5-4f6b-8f5d-deed14a03ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124654973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3124654973
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1007519213
Short name T552
Test name
Test status
Simulation time 8773735301 ps
CPU time 14.76 seconds
Started Mar 17 03:15:53 PM PDT 24
Finished Mar 17 03:16:08 PM PDT 24
Peak memory 217596 kb
Host smart-039de1a7-fd87-4186-8640-eb6ec39f51a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007519213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1007519213
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_upload.1813288112
Short name T1304
Test name
Test status
Simulation time 794237266 ps
CPU time 5.33 seconds
Started Mar 17 01:31:07 PM PDT 24
Finished Mar 17 01:31:12 PM PDT 24
Peak memory 226192 kb
Host smart-e4c286f3-da0b-40fd-b56b-7284eb94de7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813288112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1813288112
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1014777039
Short name T1899
Test name
Test status
Simulation time 14820424 ps
CPU time 0.71 seconds
Started Mar 17 01:31:10 PM PDT 24
Finished Mar 17 01:31:12 PM PDT 24
Peak memory 204888 kb
Host smart-bebdb3dd-0181-47d7-ae52-fb167830da35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014777039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1014777039
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1870481748
Short name T1193
Test name
Test status
Simulation time 110870121 ps
CPU time 0.74 seconds
Started Mar 17 03:15:59 PM PDT 24
Finished Mar 17 03:16:00 PM PDT 24
Peak memory 205044 kb
Host smart-871837c4-b08e-4ed5-a2eb-f7d6f92cdd98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1870481748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1870481748
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.1382804357
Short name T1315
Test name
Test status
Simulation time 283330052 ps
CPU time 2.26 seconds
Started Mar 17 01:31:11 PM PDT 24
Finished Mar 17 01:31:14 PM PDT 24
Peak memory 218084 kb
Host smart-f3bb9a44-5e20-4008-b42b-ed860bb415ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382804357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.1382804357
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.633485693
Short name T479
Test name
Test status
Simulation time 1069945932 ps
CPU time 4.49 seconds
Started Mar 17 03:15:59 PM PDT 24
Finished Mar 17 03:16:04 PM PDT 24
Peak memory 233468 kb
Host smart-876a5e1c-a7e7-43e4-a49a-7ed1ad7366fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633485693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.633485693
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.1115080085
Short name T1125
Test name
Test status
Simulation time 21289787 ps
CPU time 0.79 seconds
Started Mar 17 01:31:08 PM PDT 24
Finished Mar 17 01:31:10 PM PDT 24
Peak memory 206048 kb
Host smart-b5efed0d-22a8-4f05-ac9a-15020ad55895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115080085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.1115080085
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2393784659
Short name T852
Test name
Test status
Simulation time 23997076 ps
CPU time 0.76 seconds
Started Mar 17 03:15:56 PM PDT 24
Finished Mar 17 03:15:57 PM PDT 24
Peak memory 206152 kb
Host smart-bbd198d0-37fb-43a6-8b42-d618aa7518ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393784659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2393784659
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2266912621
Short name T1204
Test name
Test status
Simulation time 122936442516 ps
CPU time 155.51 seconds
Started Mar 17 03:15:59 PM PDT 24
Finished Mar 17 03:18:34 PM PDT 24
Peak memory 252128 kb
Host smart-897eda7c-e071-4f14-9fcc-a98a71090324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2266912621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2266912621
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.2601884249
Short name T1803
Test name
Test status
Simulation time 226942904168 ps
CPU time 257.86 seconds
Started Mar 17 01:31:12 PM PDT 24
Finished Mar 17 01:35:30 PM PDT 24
Peak memory 265140 kb
Host smart-716427bc-e3da-4d84-ac07-5cdb884c3f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601884249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.2601884249
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2532708673
Short name T242
Test name
Test status
Simulation time 36930840533 ps
CPU time 231.46 seconds
Started Mar 17 01:31:11 PM PDT 24
Finished Mar 17 01:35:03 PM PDT 24
Peak memory 266768 kb
Host smart-6057a049-8062-4060-bbb4-ce1a61c1c34c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532708673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2532708673
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2100421017
Short name T597
Test name
Test status
Simulation time 5071980538 ps
CPU time 89.09 seconds
Started Mar 17 03:16:03 PM PDT 24
Finished Mar 17 03:17:32 PM PDT 24
Peak memory 249392 kb
Host smart-7e0745f9-6f38-40dc-8c2e-361841de470f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100421017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2100421017
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.2881157522
Short name T19
Test name
Test status
Simulation time 39751366523 ps
CPU time 279.17 seconds
Started Mar 17 01:31:11 PM PDT 24
Finished Mar 17 01:35:51 PM PDT 24
Peak memory 252864 kb
Host smart-9fcb3d5e-cd30-4479-a70c-7f1ffb04892f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881157522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.2881157522
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.1845317738
Short name T877
Test name
Test status
Simulation time 2208653349 ps
CPU time 15.71 seconds
Started Mar 17 01:31:10 PM PDT 24
Finished Mar 17 01:31:26 PM PDT 24
Peak memory 224100 kb
Host smart-a88c1786-51eb-4869-83e3-037bd3b5e01f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845317738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1845317738
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.3280788950
Short name T560
Test name
Test status
Simulation time 160247890 ps
CPU time 4.63 seconds
Started Mar 17 03:15:57 PM PDT 24
Finished Mar 17 03:16:02 PM PDT 24
Peak memory 233092 kb
Host smart-8fb8af27-4d35-44a4-afd8-f3ce9d43fb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3280788950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3280788950
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_intercept.375216718
Short name T1790
Test name
Test status
Simulation time 666688345 ps
CPU time 4.22 seconds
Started Mar 17 01:31:10 PM PDT 24
Finished Mar 17 01:31:15 PM PDT 24
Peak memory 233864 kb
Host smart-fbbede2d-7922-4974-bcc2-7538c19bca5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375216718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.375216718
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1750647291
Short name T1871
Test name
Test status
Simulation time 80727530 ps
CPU time 2.55 seconds
Started Mar 17 03:15:58 PM PDT 24
Finished Mar 17 03:16:01 PM PDT 24
Peak memory 218236 kb
Host smart-570bd9ea-9ba0-4804-81c0-40721b80b8c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750647291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1750647291
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1905192914
Short name T1368
Test name
Test status
Simulation time 146192007440 ps
CPU time 32.69 seconds
Started Mar 17 01:31:11 PM PDT 24
Finished Mar 17 01:31:44 PM PDT 24
Peak memory 246940 kb
Host smart-fb83267c-5b68-4b22-846e-586c0d91be5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905192914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1905192914
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.2610944763
Short name T1884
Test name
Test status
Simulation time 147814291 ps
CPU time 2.73 seconds
Started Mar 17 03:15:53 PM PDT 24
Finished Mar 17 03:15:57 PM PDT 24
Peak memory 218288 kb
Host smart-c78dc1f5-9ebe-4732-9916-f81beceb224b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610944763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.2610944763
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.4171673367
Short name T1626
Test name
Test status
Simulation time 2632282706 ps
CPU time 10.09 seconds
Started Mar 17 01:31:11 PM PDT 24
Finished Mar 17 01:31:22 PM PDT 24
Peak memory 239892 kb
Host smart-5e701141-7f02-4610-a21e-ab0bc6db4e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171673367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.4171673367
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.3734957010
Short name T759
Test name
Test status
Simulation time 20523887824 ps
CPU time 10.23 seconds
Started Mar 17 01:31:10 PM PDT 24
Finished Mar 17 01:31:21 PM PDT 24
Peak memory 224156 kb
Host smart-fcdc28c5-3479-4f88-9f4b-93d1b862b559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3734957010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3734957010
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.758025669
Short name T1722
Test name
Test status
Simulation time 2466423178 ps
CPU time 8.81 seconds
Started Mar 17 03:15:56 PM PDT 24
Finished Mar 17 03:16:05 PM PDT 24
Peak memory 224372 kb
Host smart-aab9a7b4-d44b-4fd8-816c-7f9868be11a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758025669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.758025669
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3740089246
Short name T1717
Test name
Test status
Simulation time 558453087 ps
CPU time 3.25 seconds
Started Mar 17 01:31:09 PM PDT 24
Finished Mar 17 01:31:13 PM PDT 24
Peak memory 218148 kb
Host smart-a4cf9764-3b06-4c80-bb3b-f34272568461
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3740089246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3740089246
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.4258203924
Short name T765
Test name
Test status
Simulation time 412985943 ps
CPU time 4.23 seconds
Started Mar 17 03:16:00 PM PDT 24
Finished Mar 17 03:16:05 PM PDT 24
Peak memory 218828 kb
Host smart-d2b365ec-cb86-42ef-a270-66cb4a1de6d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4258203924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.4258203924
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3217570832
Short name T1887
Test name
Test status
Simulation time 24010141166 ps
CPU time 184.39 seconds
Started Mar 17 03:16:00 PM PDT 24
Finished Mar 17 03:19:04 PM PDT 24
Peak memory 266568 kb
Host smart-b633d385-340f-4ad5-814e-332d163f71f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217570832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3217570832
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.365235098
Short name T1349
Test name
Test status
Simulation time 67924678 ps
CPU time 1.2 seconds
Started Mar 17 01:31:11 PM PDT 24
Finished Mar 17 01:31:13 PM PDT 24
Peak memory 206444 kb
Host smart-014931e6-37d0-4f58-bd18-a40f6f09da46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365235098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.365235098
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1425327413
Short name T535
Test name
Test status
Simulation time 7282101726 ps
CPU time 20.15 seconds
Started Mar 17 03:15:57 PM PDT 24
Finished Mar 17 03:16:17 PM PDT 24
Peak memory 216524 kb
Host smart-f708c7d6-bdf5-4194-9c28-08a0024bf6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425327413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1425327413
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.214974539
Short name T471
Test name
Test status
Simulation time 10629029331 ps
CPU time 31.44 seconds
Started Mar 17 01:31:12 PM PDT 24
Finished Mar 17 01:31:44 PM PDT 24
Peak memory 215816 kb
Host smart-ba63218a-cdf1-4360-b416-975354f2851d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214974539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.214974539
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1854991443
Short name T515
Test name
Test status
Simulation time 1941091205 ps
CPU time 4.76 seconds
Started Mar 17 01:31:11 PM PDT 24
Finished Mar 17 01:31:17 PM PDT 24
Peak memory 215884 kb
Host smart-a633e499-460c-4e5c-93f8-6572da081a47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854991443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1854991443
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3694825056
Short name T1833
Test name
Test status
Simulation time 1963813360 ps
CPU time 2.51 seconds
Started Mar 17 03:15:56 PM PDT 24
Finished Mar 17 03:15:58 PM PDT 24
Peak memory 207456 kb
Host smart-d8959d95-b024-47ae-9d47-1d0e9e9aabf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694825056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3694825056
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.233923496
Short name T1525
Test name
Test status
Simulation time 317991037 ps
CPU time 4.27 seconds
Started Mar 17 03:15:54 PM PDT 24
Finished Mar 17 03:15:58 PM PDT 24
Peak memory 216216 kb
Host smart-e90d082d-40e8-4405-b556-c6f7ddd50288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233923496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.233923496
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3072239683
Short name T1040
Test name
Test status
Simulation time 27588636 ps
CPU time 1.03 seconds
Started Mar 17 01:31:13 PM PDT 24
Finished Mar 17 01:31:14 PM PDT 24
Peak memory 206388 kb
Host smart-0eae6234-e7d7-41de-986b-b527797271f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072239683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3072239683
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.184102666
Short name T1874
Test name
Test status
Simulation time 90327965 ps
CPU time 0.96 seconds
Started Mar 17 03:15:55 PM PDT 24
Finished Mar 17 03:15:56 PM PDT 24
Peak memory 205452 kb
Host smart-d59e8874-3ad5-4f25-857f-9e8dd31976fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=184102666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.184102666
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2056270691
Short name T1742
Test name
Test status
Simulation time 231605197 ps
CPU time 0.87 seconds
Started Mar 17 01:31:11 PM PDT 24
Finished Mar 17 01:31:12 PM PDT 24
Peak memory 205164 kb
Host smart-562ed4ff-f13c-44d0-9785-7f0fb1e948f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056270691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2056270691
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1535332355
Short name T379
Test name
Test status
Simulation time 235959651 ps
CPU time 3.35 seconds
Started Mar 17 03:15:59 PM PDT 24
Finished Mar 17 03:16:02 PM PDT 24
Peak memory 217132 kb
Host smart-f4575348-35c4-4706-94e1-5baf4e0df07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535332355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1535332355
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1557995609
Short name T467
Test name
Test status
Simulation time 47974433 ps
CPU time 0.72 seconds
Started Mar 17 01:28:59 PM PDT 24
Finished Mar 17 01:28:59 PM PDT 24
Peak memory 204816 kb
Host smart-971f66d2-e580-4102-84c8-03904be89d87
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557995609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
557995609
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.2151778196
Short name T453
Test name
Test status
Simulation time 39369701 ps
CPU time 0.74 seconds
Started Mar 17 03:13:15 PM PDT 24
Finished Mar 17 03:13:17 PM PDT 24
Peak memory 205000 kb
Host smart-73b7e83a-8659-4f4b-be9c-921f9c41ba25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151778196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2
151778196
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3745270786
Short name T965
Test name
Test status
Simulation time 592476871 ps
CPU time 5.01 seconds
Started Mar 17 01:28:55 PM PDT 24
Finished Mar 17 01:29:00 PM PDT 24
Peak memory 232596 kb
Host smart-5300096d-4ac4-4a09-b71e-31fdf894f357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745270786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3745270786
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.610078871
Short name T731
Test name
Test status
Simulation time 622679919 ps
CPU time 3.75 seconds
Started Mar 17 03:13:13 PM PDT 24
Finished Mar 17 03:13:18 PM PDT 24
Peak memory 232980 kb
Host smart-f1374d60-305a-443e-a87c-8a5f1da562e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610078871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.610078871
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2030276401
Short name T707
Test name
Test status
Simulation time 21018690 ps
CPU time 0.83 seconds
Started Mar 17 03:13:08 PM PDT 24
Finished Mar 17 03:13:09 PM PDT 24
Peak memory 206204 kb
Host smart-270eaecd-4580-4bce-9d10-67ac7b812553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030276401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2030276401
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2116353899
Short name T1820
Test name
Test status
Simulation time 53907666 ps
CPU time 0.76 seconds
Started Mar 17 01:28:50 PM PDT 24
Finished Mar 17 01:28:51 PM PDT 24
Peak memory 205908 kb
Host smart-b84515b2-e96f-472f-9aac-fdb2c20667bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116353899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2116353899
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1324350744
Short name T1804
Test name
Test status
Simulation time 1424736953 ps
CPU time 9.34 seconds
Started Mar 17 03:13:15 PM PDT 24
Finished Mar 17 03:13:26 PM PDT 24
Peak memory 232532 kb
Host smart-5722acca-4720-4cda-a260-d086ab316a3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324350744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1324350744
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3649307637
Short name T358
Test name
Test status
Simulation time 621968974952 ps
CPU time 162.76 seconds
Started Mar 17 01:28:58 PM PDT 24
Finished Mar 17 01:31:41 PM PDT 24
Peak memory 256816 kb
Host smart-d52d9f1e-8443-4137-9a2e-7c637753e2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649307637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3649307637
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2016895703
Short name T251
Test name
Test status
Simulation time 10604130398 ps
CPU time 59.32 seconds
Started Mar 17 01:28:58 PM PDT 24
Finished Mar 17 01:29:57 PM PDT 24
Peak memory 256312 kb
Host smart-8518984e-ceb4-41cd-a1cf-253b39c9ae6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016895703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2016895703
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.711957816
Short name T249
Test name
Test status
Simulation time 5297494150 ps
CPU time 65.44 seconds
Started Mar 17 03:13:19 PM PDT 24
Finished Mar 17 03:14:25 PM PDT 24
Peak memory 234364 kb
Host smart-558d0dd4-e156-4340-bdd7-5a465538a571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711957816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.711957816
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.4042467020
Short name T446
Test name
Test status
Simulation time 89348700390 ps
CPU time 163.19 seconds
Started Mar 17 01:28:59 PM PDT 24
Finished Mar 17 01:31:42 PM PDT 24
Peak memory 272588 kb
Host smart-8bac7e5c-03d8-4d37-a4de-6666bc21d7cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4042467020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.4042467020
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3669545640
Short name T1479
Test name
Test status
Simulation time 8498516929 ps
CPU time 17.12 seconds
Started Mar 17 01:28:59 PM PDT 24
Finished Mar 17 01:29:17 PM PDT 24
Peak memory 236996 kb
Host smart-dc256b1e-6786-404a-b28e-903fe6a4a76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669545640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3669545640
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.668572227
Short name T905
Test name
Test status
Simulation time 4423761890 ps
CPU time 25 seconds
Started Mar 17 03:13:13 PM PDT 24
Finished Mar 17 03:13:39 PM PDT 24
Peak memory 233588 kb
Host smart-6f778538-c114-4855-a4ae-8e772c4bed3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668572227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.668572227
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3119149766
Short name T1784
Test name
Test status
Simulation time 547882004 ps
CPU time 2.73 seconds
Started Mar 17 03:13:11 PM PDT 24
Finished Mar 17 03:13:14 PM PDT 24
Peak memory 218444 kb
Host smart-cff33a94-f49c-419c-a1e9-3a275e5a1a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119149766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3119149766
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_intercept.3718734763
Short name T1783
Test name
Test status
Simulation time 881163133 ps
CPU time 3.03 seconds
Started Mar 17 01:28:53 PM PDT 24
Finished Mar 17 01:28:56 PM PDT 24
Peak memory 223928 kb
Host smart-314d6e84-16c9-4af4-87e2-60c1bb411afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718734763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.3718734763
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1473012709
Short name T459
Test name
Test status
Simulation time 15971062761 ps
CPU time 44.28 seconds
Started Mar 17 03:13:11 PM PDT 24
Finished Mar 17 03:13:57 PM PDT 24
Peak memory 240688 kb
Host smart-67f57b68-c9c1-41ae-baf0-aaa2cf0c5db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473012709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1473012709
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3901205577
Short name T849
Test name
Test status
Simulation time 13510683277 ps
CPU time 23.84 seconds
Started Mar 17 01:28:54 PM PDT 24
Finished Mar 17 01:29:18 PM PDT 24
Peak memory 246096 kb
Host smart-e6d14bf7-f75c-4d7f-88cd-e780ba3ec3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901205577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3901205577
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_mem_parity.391486699
Short name T22
Test name
Test status
Simulation time 29594099 ps
CPU time 1.04 seconds
Started Mar 17 01:28:49 PM PDT 24
Finished Mar 17 01:28:51 PM PDT 24
Peak memory 217640 kb
Host smart-1e81074d-3953-43e6-b7df-2817d0bbe8c3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391486699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
3.spi_device_mem_parity.391486699
Directory /workspace/3.spi_device_mem_parity/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3260945762
Short name T1759
Test name
Test status
Simulation time 8730578163 ps
CPU time 24.43 seconds
Started Mar 17 03:13:10 PM PDT 24
Finished Mar 17 03:13:35 PM PDT 24
Peak memory 219916 kb
Host smart-e084cff1-8c54-4607-b562-07436c14bd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260945762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3260945762
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3316073150
Short name T573
Test name
Test status
Simulation time 41704151168 ps
CPU time 27.13 seconds
Started Mar 17 01:28:55 PM PDT 24
Finished Mar 17 01:29:23 PM PDT 24
Peak memory 218008 kb
Host smart-c1022163-16c7-4a2a-8411-3ecf8d86aa42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316073150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3316073150
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2294375598
Short name T439
Test name
Test status
Simulation time 218507362 ps
CPU time 4.87 seconds
Started Mar 17 01:28:55 PM PDT 24
Finished Mar 17 01:29:00 PM PDT 24
Peak memory 236668 kb
Host smart-10a0ce64-a69d-4d3d-80eb-5c313c9811c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294375598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2294375598
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3783525565
Short name T987
Test name
Test status
Simulation time 8015087833 ps
CPU time 9.83 seconds
Started Mar 17 03:13:07 PM PDT 24
Finished Mar 17 03:13:17 PM PDT 24
Peak memory 218712 kb
Host smart-8e68d0fe-1988-441a-838e-f1abd2f35436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3783525565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3783525565
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.1449835690
Short name T421
Test name
Test status
Simulation time 100653650 ps
CPU time 0.74 seconds
Started Mar 17 03:13:08 PM PDT 24
Finished Mar 17 03:13:08 PM PDT 24
Peak memory 216000 kb
Host smart-88c069d7-669c-4c3d-8bfb-ca0069d0fdcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449835690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.1449835690
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_ram_cfg.3103906866
Short name T946
Test name
Test status
Simulation time 47111116 ps
CPU time 0.74 seconds
Started Mar 17 01:28:49 PM PDT 24
Finished Mar 17 01:28:49 PM PDT 24
Peak memory 215812 kb
Host smart-7451d5c1-11d8-45c4-a279-ae2c17a5e0c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103906866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_ram_cfg.3103906866
Directory /workspace/3.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1773125731
Short name T1895
Test name
Test status
Simulation time 960667934 ps
CPU time 5.12 seconds
Started Mar 17 01:28:58 PM PDT 24
Finished Mar 17 01:29:03 PM PDT 24
Peak memory 218224 kb
Host smart-f3a2a339-7a6f-4b3d-a2fe-a7adcf7151b9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1773125731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1773125731
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.4135826564
Short name T1138
Test name
Test status
Simulation time 208997459 ps
CPU time 3.49 seconds
Started Mar 17 03:13:11 PM PDT 24
Finished Mar 17 03:13:15 PM PDT 24
Peak memory 218932 kb
Host smart-ec75f2e4-ce7c-416a-81a4-0b34e2b2300f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4135826564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.4135826564
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1543432832
Short name T63
Test name
Test status
Simulation time 237388597 ps
CPU time 1.06 seconds
Started Mar 17 01:28:57 PM PDT 24
Finished Mar 17 01:28:58 PM PDT 24
Peak memory 235056 kb
Host smart-f46c1e33-5461-4f8c-ad90-a28762409c46
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543432832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1543432832
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.962376894
Short name T58
Test name
Test status
Simulation time 85805570 ps
CPU time 1.16 seconds
Started Mar 17 03:13:15 PM PDT 24
Finished Mar 17 03:13:17 PM PDT 24
Peak memory 234964 kb
Host smart-9c4ce8a9-49b4-4388-8f86-96a0b4e6adbf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=962376894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.962376894
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.1131988840
Short name T1795
Test name
Test status
Simulation time 109241621870 ps
CPU time 735.43 seconds
Started Mar 17 03:13:15 PM PDT 24
Finished Mar 17 03:25:32 PM PDT 24
Peak memory 273604 kb
Host smart-3fa870a7-f5fb-4b16-8e6b-ed5707f13e85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131988840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.1131988840
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2339503174
Short name T869
Test name
Test status
Simulation time 2733187236 ps
CPU time 14.92 seconds
Started Mar 17 01:28:57 PM PDT 24
Finished Mar 17 01:29:12 PM PDT 24
Peak memory 219540 kb
Host smart-e7d869cf-a5e4-4c50-a60e-19d4de9b813f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339503174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2339503174
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3231297663
Short name T1224
Test name
Test status
Simulation time 1355457288 ps
CPU time 7.9 seconds
Started Mar 17 03:13:07 PM PDT 24
Finished Mar 17 03:13:15 PM PDT 24
Peak memory 216060 kb
Host smart-a266ce68-5c98-46e6-bd8f-94ecdf151020
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231297663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3231297663
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2352552637
Short name T1779
Test name
Test status
Simulation time 3243714013 ps
CPU time 7.64 seconds
Started Mar 17 01:28:53 PM PDT 24
Finished Mar 17 01:29:01 PM PDT 24
Peak memory 215960 kb
Host smart-10ead172-b49f-43aa-8905-4fcc94a300c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352552637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2352552637
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4084915206
Short name T900
Test name
Test status
Simulation time 34767384222 ps
CPU time 24.04 seconds
Started Mar 17 03:13:08 PM PDT 24
Finished Mar 17 03:13:32 PM PDT 24
Peak memory 216124 kb
Host smart-1b94172c-262a-4cf0-8e10-2106683345e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084915206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4084915206
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3656222768
Short name T1033
Test name
Test status
Simulation time 252665492 ps
CPU time 5.93 seconds
Started Mar 17 01:28:54 PM PDT 24
Finished Mar 17 01:29:01 PM PDT 24
Peak memory 215912 kb
Host smart-e900dd86-ad29-4a88-a23f-536dbbc37288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656222768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3656222768
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.796815595
Short name T1247
Test name
Test status
Simulation time 80045442 ps
CPU time 1.54 seconds
Started Mar 17 03:13:07 PM PDT 24
Finished Mar 17 03:13:09 PM PDT 24
Peak memory 216128 kb
Host smart-3ebc2584-58fc-459f-9e2d-4ab7806c2ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796815595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.796815595
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2639608190
Short name T69
Test name
Test status
Simulation time 59130368 ps
CPU time 0.82 seconds
Started Mar 17 03:13:10 PM PDT 24
Finished Mar 17 03:13:12 PM PDT 24
Peak memory 205436 kb
Host smart-98ad3c6c-79f3-4660-80d7-7d14ed560c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639608190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2639608190
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.3961266400
Short name T1371
Test name
Test status
Simulation time 39405862 ps
CPU time 0.85 seconds
Started Mar 17 01:28:55 PM PDT 24
Finished Mar 17 01:28:57 PM PDT 24
Peak memory 205176 kb
Host smart-421545ea-45a6-401b-8b50-515f869cc8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961266400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.3961266400
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2042076132
Short name T1830
Test name
Test status
Simulation time 748380913 ps
CPU time 4.96 seconds
Started Mar 17 03:13:12 PM PDT 24
Finished Mar 17 03:13:18 PM PDT 24
Peak memory 217724 kb
Host smart-33e37b2d-8d0a-45ad-9073-cc598f27eeb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042076132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2042076132
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_upload.3138192573
Short name T396
Test name
Test status
Simulation time 14181221448 ps
CPU time 28.34 seconds
Started Mar 17 01:28:56 PM PDT 24
Finished Mar 17 01:29:25 PM PDT 24
Peak memory 238716 kb
Host smart-5e69d011-f049-46e4-a403-df0cc858c619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138192573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.3138192573
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2861941429
Short name T318
Test name
Test status
Simulation time 41272629 ps
CPU time 0.71 seconds
Started Mar 17 03:16:08 PM PDT 24
Finished Mar 17 03:16:09 PM PDT 24
Peak memory 205016 kb
Host smart-62f29868-64fd-4d58-8cf0-0785c6a03e28
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861941429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2861941429
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.741937542
Short name T1580
Test name
Test status
Simulation time 18688319 ps
CPU time 0.7 seconds
Started Mar 17 01:31:21 PM PDT 24
Finished Mar 17 01:31:22 PM PDT 24
Peak memory 204788 kb
Host smart-738c9316-9414-4720-8baa-ae8e20eefa03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741937542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.741937542
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1044285023
Short name T512
Test name
Test status
Simulation time 1104405999 ps
CPU time 4.89 seconds
Started Mar 17 03:16:07 PM PDT 24
Finished Mar 17 03:16:12 PM PDT 24
Peak memory 234060 kb
Host smart-b4b8e69e-5064-4d1f-8813-16f894a62f04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044285023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1044285023
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2922190739
Short name T1622
Test name
Test status
Simulation time 1230605851 ps
CPU time 6.44 seconds
Started Mar 17 01:31:23 PM PDT 24
Finished Mar 17 01:31:30 PM PDT 24
Peak memory 232940 kb
Host smart-55e96456-5811-4c6c-ab0d-1a9e9adb8c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922190739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2922190739
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1050087915
Short name T4
Test name
Test status
Simulation time 58459073 ps
CPU time 0.79 seconds
Started Mar 17 03:16:01 PM PDT 24
Finished Mar 17 03:16:02 PM PDT 24
Peak memory 206184 kb
Host smart-83698f19-a7bb-4606-b926-658860a271b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050087915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1050087915
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.1749766419
Short name T1303
Test name
Test status
Simulation time 47709408 ps
CPU time 0.84 seconds
Started Mar 17 01:31:24 PM PDT 24
Finished Mar 17 01:31:25 PM PDT 24
Peak memory 205972 kb
Host smart-0ce89e92-7621-4212-9b34-6c31822cca39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1749766419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.1749766419
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.16774017
Short name T309
Test name
Test status
Simulation time 11580299450 ps
CPU time 18.19 seconds
Started Mar 17 01:31:17 PM PDT 24
Finished Mar 17 01:31:36 PM PDT 24
Peak memory 235544 kb
Host smart-fac21f5f-fcc5-427c-8eb5-492215e928c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=16774017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.16774017
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2367005569
Short name T254
Test name
Test status
Simulation time 26342642256 ps
CPU time 117.98 seconds
Started Mar 17 03:16:05 PM PDT 24
Finished Mar 17 03:18:04 PM PDT 24
Peak memory 253500 kb
Host smart-2bdd719e-bf94-4ba5-a6d9-625b95e685dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2367005569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2367005569
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1174112006
Short name T1837
Test name
Test status
Simulation time 7366850434 ps
CPU time 22.22 seconds
Started Mar 17 01:31:24 PM PDT 24
Finished Mar 17 01:31:46 PM PDT 24
Peak memory 224144 kb
Host smart-52fef84c-f8d4-413c-a7a2-d55e28585432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174112006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1174112006
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.4164848931
Short name T716
Test name
Test status
Simulation time 37159271406 ps
CPU time 54.07 seconds
Started Mar 17 03:16:02 PM PDT 24
Finished Mar 17 03:16:57 PM PDT 24
Peak memory 254168 kb
Host smart-bdcb79fa-b531-40b4-9310-ef23135f984c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164848931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.4164848931
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3063757550
Short name T372
Test name
Test status
Simulation time 35213559149 ps
CPU time 76.08 seconds
Started Mar 17 01:31:16 PM PDT 24
Finished Mar 17 01:32:32 PM PDT 24
Peak memory 234524 kb
Host smart-70759bd1-4304-426e-a945-dc8b4433766e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3063757550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3063757550
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.3436976848
Short name T1684
Test name
Test status
Simulation time 88396744679 ps
CPU time 300.92 seconds
Started Mar 17 03:16:03 PM PDT 24
Finished Mar 17 03:21:04 PM PDT 24
Peak memory 251632 kb
Host smart-21e45d21-4c2d-4f7a-909c-5dc59f996f01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436976848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.3436976848
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1447949232
Short name T1909
Test name
Test status
Simulation time 18195417721 ps
CPU time 29.92 seconds
Started Mar 17 03:16:04 PM PDT 24
Finished Mar 17 03:16:34 PM PDT 24
Peak memory 240168 kb
Host smart-55cb80e4-202a-43f6-a9a6-3f618278d8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447949232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1447949232
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1525225257
Short name T1121
Test name
Test status
Simulation time 3601195875 ps
CPU time 17.81 seconds
Started Mar 17 01:31:20 PM PDT 24
Finished Mar 17 01:31:38 PM PDT 24
Peak memory 248136 kb
Host smart-75207199-1864-44e1-81c8-e49608ae5d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525225257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1525225257
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2144962885
Short name T620
Test name
Test status
Simulation time 520379518 ps
CPU time 5.49 seconds
Started Mar 17 03:16:03 PM PDT 24
Finished Mar 17 03:16:09 PM PDT 24
Peak memory 224340 kb
Host smart-2aa2a9f3-bdc1-4372-9bc2-f82ec28a1b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144962885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2144962885
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_intercept.3379425367
Short name T1619
Test name
Test status
Simulation time 1159187035 ps
CPU time 5.02 seconds
Started Mar 17 01:31:17 PM PDT 24
Finished Mar 17 01:31:22 PM PDT 24
Peak memory 234272 kb
Host smart-97d69f91-13a1-45b2-8675-bc754a8ddab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3379425367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3379425367
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1821129096
Short name T1864
Test name
Test status
Simulation time 497686738 ps
CPU time 7.5 seconds
Started Mar 17 01:31:17 PM PDT 24
Finished Mar 17 01:31:25 PM PDT 24
Peak memory 225696 kb
Host smart-4d68d3e9-8c97-4a1d-8c5f-db3a9d88d07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821129096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1821129096
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.389564876
Short name T1516
Test name
Test status
Simulation time 63386302075 ps
CPU time 36.96 seconds
Started Mar 17 03:16:04 PM PDT 24
Finished Mar 17 03:16:41 PM PDT 24
Peak memory 240752 kb
Host smart-6bf5c600-72ab-4ca1-b81b-dfdadced3af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389564876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.389564876
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1895827877
Short name T663
Test name
Test status
Simulation time 5804840080 ps
CPU time 9.34 seconds
Started Mar 17 03:16:03 PM PDT 24
Finished Mar 17 03:16:13 PM PDT 24
Peak memory 218536 kb
Host smart-96b306c8-7126-49d9-9d60-aba2141866b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895827877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1895827877
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.4113060830
Short name T1285
Test name
Test status
Simulation time 4485786775 ps
CPU time 15.71 seconds
Started Mar 17 01:31:17 PM PDT 24
Finished Mar 17 01:31:33 PM PDT 24
Peak memory 233364 kb
Host smart-47dffafe-f8b1-4844-9d45-17d0cd5c56f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113060830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.4113060830
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2501002227
Short name T949
Test name
Test status
Simulation time 1930292111 ps
CPU time 3.43 seconds
Started Mar 17 01:31:20 PM PDT 24
Finished Mar 17 01:31:24 PM PDT 24
Peak memory 224008 kb
Host smart-cf28b31f-a431-4605-aac6-ea3ce8a44bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501002227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2501002227
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.3460270718
Short name T1655
Test name
Test status
Simulation time 1231280596 ps
CPU time 10.03 seconds
Started Mar 17 03:16:04 PM PDT 24
Finished Mar 17 03:16:15 PM PDT 24
Peak memory 240408 kb
Host smart-9e635504-c433-4ddc-a917-62750db312cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460270718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3460270718
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2586253865
Short name T1178
Test name
Test status
Simulation time 386979722 ps
CPU time 4.08 seconds
Started Mar 17 03:16:03 PM PDT 24
Finished Mar 17 03:16:07 PM PDT 24
Peak memory 219000 kb
Host smart-b9f224c4-b8c9-4770-a10c-d74cc50812ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2586253865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2586253865
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.420057998
Short name T636
Test name
Test status
Simulation time 273990864 ps
CPU time 4.33 seconds
Started Mar 17 01:31:17 PM PDT 24
Finished Mar 17 01:31:21 PM PDT 24
Peak memory 221548 kb
Host smart-a7ddf342-ad4c-4778-85bf-f563f44ca7c0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=420057998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.420057998
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.310365370
Short name T1818
Test name
Test status
Simulation time 223320753 ps
CPU time 1.12 seconds
Started Mar 17 03:16:09 PM PDT 24
Finished Mar 17 03:16:11 PM PDT 24
Peak memory 207548 kb
Host smart-ac8549c9-8324-46ac-8613-d503145e9f07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310365370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.310365370
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.397693089
Short name T945
Test name
Test status
Simulation time 31515114836 ps
CPU time 128.49 seconds
Started Mar 17 01:31:17 PM PDT 24
Finished Mar 17 01:33:25 PM PDT 24
Peak memory 265148 kb
Host smart-4a5a6123-091b-46db-9ab5-e274c3c66b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397693089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.397693089
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1273850460
Short name T1279
Test name
Test status
Simulation time 2114325941 ps
CPU time 7.37 seconds
Started Mar 17 03:16:06 PM PDT 24
Finished Mar 17 03:16:13 PM PDT 24
Peak memory 216076 kb
Host smart-6d955bc3-8e86-492a-9610-613337f6fcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273850460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1273850460
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.4053873738
Short name T411
Test name
Test status
Simulation time 491418106 ps
CPU time 4.37 seconds
Started Mar 17 01:31:17 PM PDT 24
Finished Mar 17 01:31:21 PM PDT 24
Peak memory 215852 kb
Host smart-ec02f6f5-89ec-4db0-9d32-c5f2c83bb180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053873738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.4053873738
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2449960920
Short name T1287
Test name
Test status
Simulation time 4147105610 ps
CPU time 6.08 seconds
Started Mar 17 03:16:00 PM PDT 24
Finished Mar 17 03:16:07 PM PDT 24
Peak memory 216032 kb
Host smart-641bad98-b55d-44ee-87f4-372a6b781f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449960920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2449960920
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.807573723
Short name T1363
Test name
Test status
Simulation time 16989521335 ps
CPU time 11.82 seconds
Started Mar 17 01:31:17 PM PDT 24
Finished Mar 17 01:31:29 PM PDT 24
Peak memory 215884 kb
Host smart-787c4489-2482-48fe-b1fe-79b764cd7a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807573723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.807573723
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.3646684673
Short name T370
Test name
Test status
Simulation time 150299468 ps
CPU time 1.08 seconds
Started Mar 17 01:31:17 PM PDT 24
Finished Mar 17 01:31:19 PM PDT 24
Peak memory 207452 kb
Host smart-a15cb82b-3d13-4577-be66-55003e34573f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646684673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.3646684673
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.539996688
Short name T465
Test name
Test status
Simulation time 263871590 ps
CPU time 1.61 seconds
Started Mar 17 03:16:05 PM PDT 24
Finished Mar 17 03:16:06 PM PDT 24
Peak memory 216076 kb
Host smart-bb61236a-53f4-4827-a36e-d2e433296913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539996688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.539996688
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.3592142973
Short name T1191
Test name
Test status
Simulation time 26830109 ps
CPU time 0.76 seconds
Started Mar 17 03:16:04 PM PDT 24
Finished Mar 17 03:16:05 PM PDT 24
Peak memory 205396 kb
Host smart-5396c39f-978c-47a4-bf47-2f26988a5e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592142973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.3592142973
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.37988633
Short name T659
Test name
Test status
Simulation time 71372003 ps
CPU time 0.91 seconds
Started Mar 17 01:31:19 PM PDT 24
Finished Mar 17 01:31:20 PM PDT 24
Peak memory 206100 kb
Host smart-7c805c5e-6624-4b04-bc4b-3e03733c9987
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37988633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.37988633
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1934564277
Short name T706
Test name
Test status
Simulation time 3472457999 ps
CPU time 10.8 seconds
Started Mar 17 03:16:04 PM PDT 24
Finished Mar 17 03:16:15 PM PDT 24
Peak memory 224328 kb
Host smart-b79c4f6a-c7b8-4107-b7bb-f207f13352b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934564277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1934564277
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_upload.4142111933
Short name T1283
Test name
Test status
Simulation time 9140178155 ps
CPU time 12.8 seconds
Started Mar 17 01:31:23 PM PDT 24
Finished Mar 17 01:31:37 PM PDT 24
Peak memory 223248 kb
Host smart-c4820269-574c-4d19-b9e2-0e249cd73227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142111933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.4142111933
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.205176953
Short name T1155
Test name
Test status
Simulation time 28522961 ps
CPU time 0.75 seconds
Started Mar 17 03:16:08 PM PDT 24
Finished Mar 17 03:16:09 PM PDT 24
Peak memory 204996 kb
Host smart-825a4e7e-f5c6-4d62-b644-0d316ef2cc0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205176953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.205176953
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.3324755220
Short name T1037
Test name
Test status
Simulation time 46955410 ps
CPU time 0.72 seconds
Started Mar 17 01:31:28 PM PDT 24
Finished Mar 17 01:31:29 PM PDT 24
Peak memory 204828 kb
Host smart-8b104266-2d1a-457d-b17b-7b106f0d785a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324755220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
3324755220
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.415420563
Short name T1583
Test name
Test status
Simulation time 1948604462 ps
CPU time 4.29 seconds
Started Mar 17 01:31:21 PM PDT 24
Finished Mar 17 01:31:25 PM PDT 24
Peak memory 233336 kb
Host smart-3f4e3e72-f8ec-4843-a6a4-52728747a180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415420563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.415420563
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.996685351
Short name T481
Test name
Test status
Simulation time 634811903 ps
CPU time 4.2 seconds
Started Mar 17 03:16:07 PM PDT 24
Finished Mar 17 03:16:11 PM PDT 24
Peak memory 219640 kb
Host smart-74c3d6e6-d505-4f73-800b-533fd6d2c825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996685351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.996685351
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1012756460
Short name T315
Test name
Test status
Simulation time 20337348 ps
CPU time 0.79 seconds
Started Mar 17 01:31:22 PM PDT 24
Finished Mar 17 01:31:23 PM PDT 24
Peak memory 206284 kb
Host smart-cfa4b13f-668c-48d1-bb38-95ec5e2169dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012756460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1012756460
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2579238547
Short name T1535
Test name
Test status
Simulation time 64198376 ps
CPU time 0.79 seconds
Started Mar 17 03:16:10 PM PDT 24
Finished Mar 17 03:16:11 PM PDT 24
Peak memory 206656 kb
Host smart-e6335b2e-c3f6-4080-83b0-c0cc192ed47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579238547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2579238547
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.181487047
Short name T1681
Test name
Test status
Simulation time 5572966564 ps
CPU time 57.46 seconds
Started Mar 17 03:16:09 PM PDT 24
Finished Mar 17 03:17:06 PM PDT 24
Peak memory 240104 kb
Host smart-79563e7b-f5aa-48f8-95b5-844dac23918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181487047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.181487047
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.804102087
Short name T1181
Test name
Test status
Simulation time 51741328219 ps
CPU time 241.54 seconds
Started Mar 17 01:31:30 PM PDT 24
Finished Mar 17 01:35:32 PM PDT 24
Peak memory 256968 kb
Host smart-c98c3fa7-1b96-45d5-bd1e-44d60b30a558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804102087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.804102087
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.3924571738
Short name T257
Test name
Test status
Simulation time 137444789078 ps
CPU time 253.33 seconds
Started Mar 17 03:16:06 PM PDT 24
Finished Mar 17 03:20:19 PM PDT 24
Peak memory 248980 kb
Host smart-53f746c3-7e5e-41f4-afbc-59548e836491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924571738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.3924571738
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.942151857
Short name T1188
Test name
Test status
Simulation time 45296682499 ps
CPU time 107.55 seconds
Started Mar 17 01:31:29 PM PDT 24
Finished Mar 17 01:33:17 PM PDT 24
Peak memory 256576 kb
Host smart-c1888c40-b8a5-48f2-b302-c39263da0015
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942151857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.942151857
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4078685442
Short name T1872
Test name
Test status
Simulation time 80349942553 ps
CPU time 309.04 seconds
Started Mar 17 03:16:08 PM PDT 24
Finished Mar 17 03:21:18 PM PDT 24
Peak memory 250468 kb
Host smart-98263416-0228-4d08-a7f6-206d865dc263
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078685442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4078685442
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.4107521208
Short name T188
Test name
Test status
Simulation time 374974269424 ps
CPU time 233.04 seconds
Started Mar 17 01:31:29 PM PDT 24
Finished Mar 17 01:35:22 PM PDT 24
Peak memory 257028 kb
Host smart-bfbe87f6-30d4-4d1d-82c4-f1c35b87ff87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4107521208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.4107521208
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2421826933
Short name T283
Test name
Test status
Simulation time 5672133870 ps
CPU time 27.55 seconds
Started Mar 17 01:31:24 PM PDT 24
Finished Mar 17 01:31:52 PM PDT 24
Peak memory 234628 kb
Host smart-54607bb3-227e-4ba2-b54b-8282a26d7975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421826933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2421826933
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.4267811993
Short name T407
Test name
Test status
Simulation time 4349235042 ps
CPU time 23.84 seconds
Started Mar 17 03:16:05 PM PDT 24
Finished Mar 17 03:16:29 PM PDT 24
Peak memory 232576 kb
Host smart-9c527c6e-25ad-40a8-9944-402c37df8db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4267811993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.4267811993
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3084655123
Short name T371
Test name
Test status
Simulation time 544283838 ps
CPU time 4.17 seconds
Started Mar 17 01:31:21 PM PDT 24
Finished Mar 17 01:31:25 PM PDT 24
Peak memory 232968 kb
Host smart-89221bf5-7907-4840-a263-97c74e3ac3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084655123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3084655123
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_intercept.4041713742
Short name T1394
Test name
Test status
Simulation time 1080655940 ps
CPU time 4.36 seconds
Started Mar 17 03:16:10 PM PDT 24
Finished Mar 17 03:16:14 PM PDT 24
Peak memory 233208 kb
Host smart-b9f341b1-7397-4cf0-bff9-2a0e48ab5634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041713742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.4041713742
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1436851976
Short name T956
Test name
Test status
Simulation time 6591086145 ps
CPU time 11.17 seconds
Started Mar 17 01:31:23 PM PDT 24
Finished Mar 17 01:31:34 PM PDT 24
Peak memory 231908 kb
Host smart-98f7d25c-492d-4a47-b1e1-4c069b317128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436851976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1436851976
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1941305254
Short name T881
Test name
Test status
Simulation time 48429645898 ps
CPU time 33.3 seconds
Started Mar 17 03:16:07 PM PDT 24
Finished Mar 17 03:16:40 PM PDT 24
Peak memory 247148 kb
Host smart-fa505c1b-7169-4362-812e-8cdaba301c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941305254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1941305254
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.140153448
Short name T1725
Test name
Test status
Simulation time 20276334061 ps
CPU time 15.99 seconds
Started Mar 17 01:31:21 PM PDT 24
Finished Mar 17 01:31:37 PM PDT 24
Peak memory 233332 kb
Host smart-da032e3a-ee59-4e62-8aab-9d9744523ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=140153448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.140153448
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.751120970
Short name T1848
Test name
Test status
Simulation time 1099646085 ps
CPU time 5.03 seconds
Started Mar 17 03:16:12 PM PDT 24
Finished Mar 17 03:16:17 PM PDT 24
Peak memory 218164 kb
Host smart-5d404bc8-ecbd-4cd0-95c8-2536de4ec815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751120970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.751120970
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.1124767365
Short name T390
Test name
Test status
Simulation time 50007084431 ps
CPU time 36.97 seconds
Started Mar 17 01:31:23 PM PDT 24
Finished Mar 17 01:32:00 PM PDT 24
Peak memory 240136 kb
Host smart-afbb0dcf-6179-46ad-ba3a-962c26a2cd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124767365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.1124767365
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.804856668
Short name T1832
Test name
Test status
Simulation time 2012688889 ps
CPU time 11.85 seconds
Started Mar 17 03:16:12 PM PDT 24
Finished Mar 17 03:16:24 PM PDT 24
Peak memory 233444 kb
Host smart-dac55164-5e0a-4899-8104-e97d159b41a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=804856668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.804856668
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.210412120
Short name T1545
Test name
Test status
Simulation time 2102189895 ps
CPU time 4.02 seconds
Started Mar 17 03:16:07 PM PDT 24
Finished Mar 17 03:16:11 PM PDT 24
Peak memory 220460 kb
Host smart-6235b2bd-da18-4e82-b360-4d251c4aac70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=210412120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.210412120
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.4038093624
Short name T628
Test name
Test status
Simulation time 162832653 ps
CPU time 3.3 seconds
Started Mar 17 01:31:22 PM PDT 24
Finished Mar 17 01:31:26 PM PDT 24
Peak memory 219560 kb
Host smart-781eabc7-9398-484e-ba80-2f71fb6d71ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4038093624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.4038093624
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2230470483
Short name T143
Test name
Test status
Simulation time 311988488 ps
CPU time 1.15 seconds
Started Mar 17 01:31:27 PM PDT 24
Finished Mar 17 01:31:28 PM PDT 24
Peak memory 206472 kb
Host smart-daeba6ce-b13c-4ae3-b98f-bd80c2a2d635
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2230470483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2230470483
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.3881411297
Short name T53
Test name
Test status
Simulation time 63487084120 ps
CPU time 131.35 seconds
Started Mar 17 03:16:06 PM PDT 24
Finished Mar 17 03:18:17 PM PDT 24
Peak memory 249836 kb
Host smart-709af75a-8e76-47dc-801a-d1254066ed62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881411297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.3881411297
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2351448219
Short name T346
Test name
Test status
Simulation time 148330223613 ps
CPU time 38.99 seconds
Started Mar 17 03:16:07 PM PDT 24
Finished Mar 17 03:16:47 PM PDT 24
Peak memory 216176 kb
Host smart-ed82f2be-8d8e-4c3d-ae1f-944182072c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351448219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2351448219
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2487806679
Short name T935
Test name
Test status
Simulation time 273482347 ps
CPU time 2.88 seconds
Started Mar 17 01:31:22 PM PDT 24
Finished Mar 17 01:31:25 PM PDT 24
Peak memory 215816 kb
Host smart-458da464-e9f8-441e-98a2-e3655838d057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487806679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2487806679
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.2758764892
Short name T1587
Test name
Test status
Simulation time 1458932990 ps
CPU time 4.21 seconds
Started Mar 17 03:16:09 PM PDT 24
Finished Mar 17 03:16:13 PM PDT 24
Peak memory 216052 kb
Host smart-5fc35066-574d-45b8-8df9-c1f7c952c56e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758764892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2758764892
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.704755278
Short name T431
Test name
Test status
Simulation time 11091966382 ps
CPU time 27.92 seconds
Started Mar 17 01:31:23 PM PDT 24
Finished Mar 17 01:31:51 PM PDT 24
Peak memory 215868 kb
Host smart-4a01527c-c0cb-4f9d-a1fb-7edee9219421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704755278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.704755278
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2727661170
Short name T1691
Test name
Test status
Simulation time 367917369 ps
CPU time 1.75 seconds
Started Mar 17 03:16:06 PM PDT 24
Finished Mar 17 03:16:08 PM PDT 24
Peak memory 216048 kb
Host smart-62602470-3b18-4bbc-952c-882c0a4bb08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727661170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2727661170
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.634426070
Short name T980
Test name
Test status
Simulation time 753474553 ps
CPU time 9.56 seconds
Started Mar 17 01:31:22 PM PDT 24
Finished Mar 17 01:31:31 PM PDT 24
Peak memory 215960 kb
Host smart-18a1acfd-1515-41a8-ad64-d93d3f6f5989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634426070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.634426070
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.2184548344
Short name T310
Test name
Test status
Simulation time 113536914 ps
CPU time 1.04 seconds
Started Mar 17 03:16:08 PM PDT 24
Finished Mar 17 03:16:09 PM PDT 24
Peak memory 206500 kb
Host smart-c47d2d95-75e5-4aa9-a746-322ca316f53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184548344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2184548344
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.4175588866
Short name T761
Test name
Test status
Simulation time 177679587 ps
CPU time 0.99 seconds
Started Mar 17 01:31:22 PM PDT 24
Finished Mar 17 01:31:23 PM PDT 24
Peak memory 206232 kb
Host smart-435b1d08-b85e-4105-bcdb-a3bcd44a024b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175588866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.4175588866
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2701949635
Short name T1862
Test name
Test status
Simulation time 14704730199 ps
CPU time 24.12 seconds
Started Mar 17 01:31:21 PM PDT 24
Finished Mar 17 01:31:45 PM PDT 24
Peak memory 236896 kb
Host smart-b765ee53-0797-400c-b608-cfe1ffaf21bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701949635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2701949635
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_upload.825145047
Short name T332
Test name
Test status
Simulation time 4303860551 ps
CPU time 13.89 seconds
Started Mar 17 03:16:07 PM PDT 24
Finished Mar 17 03:16:22 PM PDT 24
Peak memory 220016 kb
Host smart-50633bf8-0b15-4edd-b026-bd3a1e3f801b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825145047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.825145047
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3505208653
Short name T1689
Test name
Test status
Simulation time 30399789 ps
CPU time 0.75 seconds
Started Mar 17 03:16:13 PM PDT 24
Finished Mar 17 03:16:14 PM PDT 24
Peak memory 204436 kb
Host smart-ddefc00d-9b9e-4e6f-984b-2bc7a62678be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505208653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3505208653
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.3869745816
Short name T532
Test name
Test status
Simulation time 24552374 ps
CPU time 0.71 seconds
Started Mar 17 01:31:36 PM PDT 24
Finished Mar 17 01:31:37 PM PDT 24
Peak memory 204288 kb
Host smart-34df87b4-5f57-4ea8-9e27-80ef096c9cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869745816 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
3869745816
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2648638886
Short name T1101
Test name
Test status
Simulation time 136371622 ps
CPU time 3.09 seconds
Started Mar 17 01:31:30 PM PDT 24
Finished Mar 17 01:31:34 PM PDT 24
Peak memory 216684 kb
Host smart-a715a6f8-b35d-493b-a05b-a85c6830c743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648638886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2648638886
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.590409614
Short name T848
Test name
Test status
Simulation time 2282083182 ps
CPU time 4.87 seconds
Started Mar 17 03:16:13 PM PDT 24
Finished Mar 17 03:16:18 PM PDT 24
Peak memory 219476 kb
Host smart-1c006801-c959-4fea-93e9-f77055788f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590409614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.590409614
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.2600296077
Short name T1620
Test name
Test status
Simulation time 41046726 ps
CPU time 0.82 seconds
Started Mar 17 03:16:12 PM PDT 24
Finished Mar 17 03:16:13 PM PDT 24
Peak memory 206204 kb
Host smart-bdc01d3b-a211-47b1-aafb-376b7d5e7ea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600296077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.2600296077
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.692235206
Short name T1288
Test name
Test status
Simulation time 24981241 ps
CPU time 0.8 seconds
Started Mar 17 01:31:29 PM PDT 24
Finished Mar 17 01:31:30 PM PDT 24
Peak memory 206340 kb
Host smart-5ec1e2a1-ca8c-45eb-bb95-2c6b5d9e3a2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692235206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.692235206
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2693048617
Short name T609
Test name
Test status
Simulation time 41886840823 ps
CPU time 79.67 seconds
Started Mar 17 03:16:14 PM PDT 24
Finished Mar 17 03:17:35 PM PDT 24
Peak memory 256648 kb
Host smart-1ec43733-aaf2-46bb-869b-5c6ea7ecf419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693048617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2693048617
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.3107632142
Short name T656
Test name
Test status
Simulation time 30917545139 ps
CPU time 56.35 seconds
Started Mar 17 01:31:29 PM PDT 24
Finished Mar 17 01:32:25 PM PDT 24
Peak memory 249696 kb
Host smart-bc1e3c67-13a2-4ff0-b629-ed5333f01499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107632142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3107632142
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.2167067681
Short name T1765
Test name
Test status
Simulation time 25516367019 ps
CPU time 101.32 seconds
Started Mar 17 03:16:15 PM PDT 24
Finished Mar 17 03:17:57 PM PDT 24
Peak memory 265396 kb
Host smart-668fa0dc-de8b-4a5a-8c89-754286f9705f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167067681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2167067681
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.535566064
Short name T1034
Test name
Test status
Simulation time 54325053987 ps
CPU time 86.68 seconds
Started Mar 17 01:31:35 PM PDT 24
Finished Mar 17 01:33:02 PM PDT 24
Peak memory 240720 kb
Host smart-0b2c192a-2f36-4cc6-a2e0-73e32f42dd0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535566064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.535566064
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.2700130648
Short name T964
Test name
Test status
Simulation time 19372295227 ps
CPU time 67.53 seconds
Started Mar 17 03:16:12 PM PDT 24
Finished Mar 17 03:17:20 PM PDT 24
Peak memory 232636 kb
Host smart-21b7a50e-5c73-4998-ba40-71ae56a73f2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700130648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.2700130648
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.858841020
Short name T1740
Test name
Test status
Simulation time 33231201690 ps
CPU time 208.44 seconds
Started Mar 17 01:31:33 PM PDT 24
Finished Mar 17 01:35:01 PM PDT 24
Peak memory 240908 kb
Host smart-f1013aba-f85a-4698-b9f9-7f7e0c34443e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858841020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle
.858841020
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3336160445
Short name T895
Test name
Test status
Simulation time 4882675421 ps
CPU time 29.41 seconds
Started Mar 17 01:31:27 PM PDT 24
Finished Mar 17 01:31:58 PM PDT 24
Peak memory 232356 kb
Host smart-8b7d5b53-f909-46ec-acdd-93c941e45ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336160445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3336160445
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.822797797
Short name T1815
Test name
Test status
Simulation time 24958194624 ps
CPU time 30.8 seconds
Started Mar 17 03:16:13 PM PDT 24
Finished Mar 17 03:16:44 PM PDT 24
Peak memory 235068 kb
Host smart-9e6a1030-6d52-4fae-b7e8-4d431febdf69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822797797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.822797797
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2085609117
Short name T1030
Test name
Test status
Simulation time 2659234282 ps
CPU time 4.23 seconds
Started Mar 17 01:31:30 PM PDT 24
Finished Mar 17 01:31:35 PM PDT 24
Peak memory 232128 kb
Host smart-80e6d21e-4189-4de0-bdb5-0f43fa43c6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085609117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2085609117
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_intercept.3867182771
Short name T1454
Test name
Test status
Simulation time 246157606 ps
CPU time 2.22 seconds
Started Mar 17 03:16:12 PM PDT 24
Finished Mar 17 03:16:15 PM PDT 24
Peak memory 218272 kb
Host smart-35e220f5-1cc1-46aa-8ee2-dde6c3dca222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867182771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3867182771
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.1770942439
Short name T897
Test name
Test status
Simulation time 16897578279 ps
CPU time 22.81 seconds
Started Mar 17 01:31:27 PM PDT 24
Finished Mar 17 01:31:50 PM PDT 24
Peak memory 230108 kb
Host smart-cd3c0a20-dfc6-40a6-a990-8f728dc1e4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770942439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.1770942439
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.58957714
Short name T585
Test name
Test status
Simulation time 16037113568 ps
CPU time 45.39 seconds
Started Mar 17 03:16:13 PM PDT 24
Finished Mar 17 03:16:59 PM PDT 24
Peak memory 240716 kb
Host smart-aee94aa4-4e76-47df-8c4d-c62100f7e6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58957714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.58957714
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.1005931636
Short name T912
Test name
Test status
Simulation time 5970833870 ps
CPU time 10.06 seconds
Started Mar 17 03:16:13 PM PDT 24
Finished Mar 17 03:16:24 PM PDT 24
Peak memory 218356 kb
Host smart-2733ed49-67b4-4563-a2c1-e28a27fc8b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1005931636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.1005931636
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.2513141471
Short name T1841
Test name
Test status
Simulation time 978646211 ps
CPU time 4.53 seconds
Started Mar 17 01:31:28 PM PDT 24
Finished Mar 17 01:31:33 PM PDT 24
Peak memory 228652 kb
Host smart-b1386ef2-ab12-41b9-9ec3-fa6ce4113f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513141471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.2513141471
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2524526547
Short name T1225
Test name
Test status
Simulation time 2318637525 ps
CPU time 4.34 seconds
Started Mar 17 01:31:30 PM PDT 24
Finished Mar 17 01:31:34 PM PDT 24
Peak memory 232876 kb
Host smart-68e28fae-95f7-49a5-ad09-5d77514310bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524526547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2524526547
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.3509629088
Short name T1639
Test name
Test status
Simulation time 1255769941 ps
CPU time 6.92 seconds
Started Mar 17 03:16:15 PM PDT 24
Finished Mar 17 03:16:23 PM PDT 24
Peak memory 233056 kb
Host smart-3e02c231-c1fb-4762-b41e-b56f39932265
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3509629088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.3509629088
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3070667863
Short name T1458
Test name
Test status
Simulation time 1630819271 ps
CPU time 4.14 seconds
Started Mar 17 01:31:29 PM PDT 24
Finished Mar 17 01:31:33 PM PDT 24
Peak memory 219292 kb
Host smart-e3773613-7dc5-4e1b-bfe9-34e877b25c1b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3070667863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3070667863
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.476218703
Short name T930
Test name
Test status
Simulation time 358937319 ps
CPU time 3.47 seconds
Started Mar 17 03:16:12 PM PDT 24
Finished Mar 17 03:16:16 PM PDT 24
Peak memory 220200 kb
Host smart-1b0d0f62-587b-4f9b-97c7-84761d0eaf0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=476218703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.476218703
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1007929466
Short name T138
Test name
Test status
Simulation time 70976070 ps
CPU time 0.88 seconds
Started Mar 17 01:31:33 PM PDT 24
Finished Mar 17 01:31:35 PM PDT 24
Peak memory 205276 kb
Host smart-bae81c38-9a7f-4a98-a8ea-896eadbdaf52
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007929466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1007929466
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2229558651
Short name T1467
Test name
Test status
Simulation time 10091664252 ps
CPU time 92.71 seconds
Started Mar 17 03:16:13 PM PDT 24
Finished Mar 17 03:17:47 PM PDT 24
Peak memory 251076 kb
Host smart-98244237-bc25-4021-a03c-be38fa96cfc6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229558651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2229558651
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1858108773
Short name T572
Test name
Test status
Simulation time 11300243619 ps
CPU time 32.64 seconds
Started Mar 17 01:31:29 PM PDT 24
Finished Mar 17 01:32:01 PM PDT 24
Peak memory 215900 kb
Host smart-7304de2d-46d6-4bb5-a14c-ee6aeb6b1d6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858108773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1858108773
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.255394946
Short name T426
Test name
Test status
Simulation time 7769430348 ps
CPU time 40.94 seconds
Started Mar 17 03:16:11 PM PDT 24
Finished Mar 17 03:16:52 PM PDT 24
Peak memory 216160 kb
Host smart-867250c8-3a81-4dd9-bcff-9868cfb7e8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255394946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.255394946
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2677992318
Short name T1613
Test name
Test status
Simulation time 7797648621 ps
CPU time 28.72 seconds
Started Mar 17 01:31:29 PM PDT 24
Finished Mar 17 01:31:57 PM PDT 24
Peak memory 215844 kb
Host smart-7641c0c0-35a8-46bc-b178-895867332b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677992318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2677992318
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.575242661
Short name T433
Test name
Test status
Simulation time 12638870754 ps
CPU time 6.43 seconds
Started Mar 17 03:16:07 PM PDT 24
Finished Mar 17 03:16:13 PM PDT 24
Peak memory 216112 kb
Host smart-1c4c7c95-a9c7-426d-8b2c-356cb2b6b97b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575242661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.575242661
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.2841483962
Short name T643
Test name
Test status
Simulation time 50464619 ps
CPU time 0.95 seconds
Started Mar 17 03:16:13 PM PDT 24
Finished Mar 17 03:16:15 PM PDT 24
Peak memory 206580 kb
Host smart-2699fa27-6c52-4f98-ace2-756b24b85c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841483962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.2841483962
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.3329417238
Short name T1393
Test name
Test status
Simulation time 39398185 ps
CPU time 1.46 seconds
Started Mar 17 01:31:30 PM PDT 24
Finished Mar 17 01:31:31 PM PDT 24
Peak memory 215896 kb
Host smart-04f1edd1-ab0e-4ceb-809b-35e396cf16e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329417238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3329417238
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.179191780
Short name T369
Test name
Test status
Simulation time 178389138 ps
CPU time 0.94 seconds
Started Mar 17 03:16:13 PM PDT 24
Finished Mar 17 03:16:15 PM PDT 24
Peak memory 205456 kb
Host smart-ee35efd0-c504-4ad6-8cc0-5eb8a0db1d18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179191780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.179191780
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.2001412063
Short name T1123
Test name
Test status
Simulation time 16825317 ps
CPU time 0.73 seconds
Started Mar 17 01:31:29 PM PDT 24
Finished Mar 17 01:31:30 PM PDT 24
Peak memory 205168 kb
Host smart-1a8a3a92-6520-4451-8704-402a0d80f90b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001412063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.2001412063
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.2638086357
Short name T722
Test name
Test status
Simulation time 352276363 ps
CPU time 3.26 seconds
Started Mar 17 01:31:29 PM PDT 24
Finished Mar 17 01:31:33 PM PDT 24
Peak memory 234100 kb
Host smart-cce1d5f4-5e5f-48c9-b4e5-2b25b897702b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638086357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.2638086357
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_upload.588966144
Short name T772
Test name
Test status
Simulation time 1462707801 ps
CPU time 6.8 seconds
Started Mar 17 03:16:13 PM PDT 24
Finished Mar 17 03:16:20 PM PDT 24
Peak memory 240536 kb
Host smart-a4f8bd41-d0a2-4c97-9028-f4488c063164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588966144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.588966144
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1047650857
Short name T718
Test name
Test status
Simulation time 46619283 ps
CPU time 0.71 seconds
Started Mar 17 01:31:34 PM PDT 24
Finished Mar 17 01:31:35 PM PDT 24
Peak memory 204876 kb
Host smart-5f57dda4-6b11-496a-9792-48842a5c2c03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047650857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1047650857
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2419552638
Short name T417
Test name
Test status
Simulation time 12883677 ps
CPU time 0.73 seconds
Started Mar 17 03:16:24 PM PDT 24
Finished Mar 17 03:16:25 PM PDT 24
Peak memory 205052 kb
Host smart-50506b00-ca05-4a3c-a388-a5731d5d3ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419552638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2419552638
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1784918878
Short name T1415
Test name
Test status
Simulation time 264811882 ps
CPU time 3.36 seconds
Started Mar 17 03:16:18 PM PDT 24
Finished Mar 17 03:16:22 PM PDT 24
Peak memory 233368 kb
Host smart-bb6a7a00-415f-4783-acbf-672c68d8ad7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784918878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1784918878
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2924318970
Short name T1437
Test name
Test status
Simulation time 280949753 ps
CPU time 3.18 seconds
Started Mar 17 01:31:33 PM PDT 24
Finished Mar 17 01:31:37 PM PDT 24
Peak memory 217356 kb
Host smart-6874bf75-4d57-4741-9069-f5b42f7c025a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2924318970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2924318970
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1976606302
Short name T1008
Test name
Test status
Simulation time 19533060 ps
CPU time 0.76 seconds
Started Mar 17 03:16:18 PM PDT 24
Finished Mar 17 03:16:20 PM PDT 24
Peak memory 205484 kb
Host smart-05f5a102-0b0c-4cc5-b1b5-34b24a1f771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976606302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1976606302
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3665332714
Short name T786
Test name
Test status
Simulation time 61933317 ps
CPU time 0.77 seconds
Started Mar 17 01:31:35 PM PDT 24
Finished Mar 17 01:31:36 PM PDT 24
Peak memory 206284 kb
Host smart-30dbdf24-6f27-42c9-9d30-f6ae858e4d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665332714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3665332714
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2216102433
Short name T1741
Test name
Test status
Simulation time 3502890048 ps
CPU time 5.28 seconds
Started Mar 17 03:16:15 PM PDT 24
Finished Mar 17 03:16:21 PM PDT 24
Peak memory 232612 kb
Host smart-af021e2a-f05c-4e6a-8fd9-cf30f988599c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216102433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2216102433
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2542934198
Short name T1370
Test name
Test status
Simulation time 5736124930 ps
CPU time 31.44 seconds
Started Mar 17 01:31:40 PM PDT 24
Finished Mar 17 01:32:12 PM PDT 24
Peak memory 248676 kb
Host smart-bdb1bffe-762c-4e2e-baa0-3e85858c2c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542934198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2542934198
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3177829097
Short name T1329
Test name
Test status
Simulation time 40830139502 ps
CPU time 187.31 seconds
Started Mar 17 03:16:19 PM PDT 24
Finished Mar 17 03:19:28 PM PDT 24
Peak memory 238036 kb
Host smart-a32eca2a-60ea-4b8c-8852-c397fee86c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177829097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3177829097
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.545169083
Short name T529
Test name
Test status
Simulation time 98250264589 ps
CPU time 122.68 seconds
Started Mar 17 01:31:34 PM PDT 24
Finished Mar 17 01:33:37 PM PDT 24
Peak memory 256540 kb
Host smart-403d5621-4c4b-45f2-a92c-dc23fba8258e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545169083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.545169083
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.1224291424
Short name T398
Test name
Test status
Simulation time 28224854143 ps
CPU time 116.35 seconds
Started Mar 17 01:31:40 PM PDT 24
Finished Mar 17 01:33:37 PM PDT 24
Peak memory 265144 kb
Host smart-589e96dd-86d2-4f37-89b1-6c2522bdcb95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224291424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.1224291424
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.3750643160
Short name T256
Test name
Test status
Simulation time 10062079910 ps
CPU time 90.86 seconds
Started Mar 17 03:16:16 PM PDT 24
Finished Mar 17 03:17:48 PM PDT 24
Peak memory 249028 kb
Host smart-349d9cca-894e-43e2-a82f-e93b6c4c359d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750643160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.3750643160
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1013427705
Short name T197
Test name
Test status
Simulation time 8520500544 ps
CPU time 39.06 seconds
Started Mar 17 01:31:36 PM PDT 24
Finished Mar 17 01:32:15 PM PDT 24
Peak memory 237340 kb
Host smart-e6233782-4d73-4ae6-bafb-e02869cb1536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013427705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1013427705
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.126295907
Short name T198
Test name
Test status
Simulation time 10815086052 ps
CPU time 15.48 seconds
Started Mar 17 03:16:20 PM PDT 24
Finished Mar 17 03:16:36 PM PDT 24
Peak memory 247384 kb
Host smart-4c119bd2-6949-4b6f-a098-7d13cab1b5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=126295907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.126295907
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2989606677
Short name T721
Test name
Test status
Simulation time 1017077229 ps
CPU time 5.58 seconds
Started Mar 17 01:31:34 PM PDT 24
Finished Mar 17 01:31:40 PM PDT 24
Peak memory 237712 kb
Host smart-64590ce5-89a6-4828-872d-d4b9d2f1583c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989606677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2989606677
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_intercept.3672260461
Short name T1821
Test name
Test status
Simulation time 6421854850 ps
CPU time 10.34 seconds
Started Mar 17 03:16:16 PM PDT 24
Finished Mar 17 03:16:26 PM PDT 24
Peak memory 219540 kb
Host smart-bad4afee-91d4-4bd4-bda8-f0ba2151d439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672260461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.3672260461
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1759935376
Short name T767
Test name
Test status
Simulation time 17025330261 ps
CPU time 40.16 seconds
Started Mar 17 01:31:33 PM PDT 24
Finished Mar 17 01:32:13 PM PDT 24
Peak memory 234320 kb
Host smart-a78a3022-c1f0-4cd3-ae33-1bb37b617831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759935376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1759935376
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.884747648
Short name T779
Test name
Test status
Simulation time 8213333006 ps
CPU time 12.98 seconds
Started Mar 17 03:16:18 PM PDT 24
Finished Mar 17 03:16:31 PM PDT 24
Peak memory 234768 kb
Host smart-97e9658d-15ee-4c24-ad3c-f4786232ad17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884747648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.884747648
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2600181852
Short name T1638
Test name
Test status
Simulation time 6556071843 ps
CPU time 17.58 seconds
Started Mar 17 03:16:18 PM PDT 24
Finished Mar 17 03:16:36 PM PDT 24
Peak memory 233540 kb
Host smart-1dd16cb4-1114-42e7-a11f-f5f45f2ae635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600181852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2600181852
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.2975689903
Short name T1319
Test name
Test status
Simulation time 23921912767 ps
CPU time 7.24 seconds
Started Mar 17 01:31:40 PM PDT 24
Finished Mar 17 01:31:48 PM PDT 24
Peak memory 224036 kb
Host smart-666c85e2-6190-470c-a508-1c3fe3f4e3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975689903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.2975689903
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.2170593348
Short name T393
Test name
Test status
Simulation time 6234200509 ps
CPU time 8.94 seconds
Started Mar 17 03:16:17 PM PDT 24
Finished Mar 17 03:16:27 PM PDT 24
Peak memory 229008 kb
Host smart-dabd607f-9a6e-4489-8d55-0874b5b5c69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170593348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.2170593348
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4004090874
Short name T228
Test name
Test status
Simulation time 526617176 ps
CPU time 3.77 seconds
Started Mar 17 01:31:33 PM PDT 24
Finished Mar 17 01:31:37 PM PDT 24
Peak memory 233048 kb
Host smart-c733d82e-7b54-460c-8328-99bc06ffd05d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004090874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4004090874
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3046904072
Short name T1397
Test name
Test status
Simulation time 1108884981 ps
CPU time 3.43 seconds
Started Mar 17 03:16:18 PM PDT 24
Finished Mar 17 03:16:23 PM PDT 24
Peak memory 219264 kb
Host smart-39c64082-5dad-44c9-b04e-0f5b4f614165
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3046904072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3046904072
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.3397343191
Short name T129
Test name
Test status
Simulation time 1319600424 ps
CPU time 6.05 seconds
Started Mar 17 01:31:32 PM PDT 24
Finished Mar 17 01:31:39 PM PDT 24
Peak memory 222396 kb
Host smart-67833eb6-5395-4a5a-870d-3e16ad00e491
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3397343191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.3397343191
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.1170456315
Short name T1105
Test name
Test status
Simulation time 81771038248 ps
CPU time 652.15 seconds
Started Mar 17 01:31:33 PM PDT 24
Finished Mar 17 01:42:25 PM PDT 24
Peak memory 268800 kb
Host smart-284d0a9c-917d-4c4a-978f-aea10bd113d8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170456315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.1170456315
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.2257605624
Short name T1068
Test name
Test status
Simulation time 216688085731 ps
CPU time 361.29 seconds
Started Mar 17 03:16:19 PM PDT 24
Finished Mar 17 03:22:21 PM PDT 24
Peak memory 249040 kb
Host smart-76ae68e3-fd92-42a8-ac27-84aae421fb46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257605624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.2257605624
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2383102414
Short name T1342
Test name
Test status
Simulation time 2092151542 ps
CPU time 27.43 seconds
Started Mar 17 03:16:17 PM PDT 24
Finished Mar 17 03:16:46 PM PDT 24
Peak memory 216248 kb
Host smart-32c7c5af-4736-4ee3-b05d-cc2ae856b18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383102414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2383102414
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.2915684952
Short name T285
Test name
Test status
Simulation time 41671941873 ps
CPU time 36.58 seconds
Started Mar 17 01:31:34 PM PDT 24
Finished Mar 17 01:32:11 PM PDT 24
Peak memory 215872 kb
Host smart-820677d1-1a83-409c-a88d-798c552922dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915684952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.2915684952
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.281138653
Short name T1278
Test name
Test status
Simulation time 944355635 ps
CPU time 3.2 seconds
Started Mar 17 03:16:15 PM PDT 24
Finished Mar 17 03:16:19 PM PDT 24
Peak memory 215824 kb
Host smart-5ec6b371-895b-4a5c-a351-240a5772308f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281138653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.281138653
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2877912263
Short name T316
Test name
Test status
Simulation time 415809014 ps
CPU time 3.47 seconds
Started Mar 17 01:31:35 PM PDT 24
Finished Mar 17 01:31:39 PM PDT 24
Peak memory 215888 kb
Host smart-a24e30ad-2c35-49c1-aba9-5bf8439d60ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877912263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2877912263
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3276103915
Short name T1417
Test name
Test status
Simulation time 87563410 ps
CPU time 1.96 seconds
Started Mar 17 01:31:35 PM PDT 24
Finished Mar 17 01:31:37 PM PDT 24
Peak memory 216112 kb
Host smart-e69c6822-6842-47d6-bde6-f84b9ad3df85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276103915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3276103915
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3772307460
Short name T418
Test name
Test status
Simulation time 169158654 ps
CPU time 1.41 seconds
Started Mar 17 03:16:16 PM PDT 24
Finished Mar 17 03:16:18 PM PDT 24
Peak memory 216088 kb
Host smart-04f379da-6f97-4acd-b3e1-eca6a4257332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772307460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3772307460
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.1174118907
Short name T1661
Test name
Test status
Simulation time 203212130 ps
CPU time 0.87 seconds
Started Mar 17 03:16:18 PM PDT 24
Finished Mar 17 03:16:19 PM PDT 24
Peak memory 206428 kb
Host smart-9214ca36-127e-4964-a99f-ff233d5b25f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174118907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.1174118907
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2707837907
Short name T694
Test name
Test status
Simulation time 415516523 ps
CPU time 0.93 seconds
Started Mar 17 01:31:34 PM PDT 24
Finished Mar 17 01:31:35 PM PDT 24
Peak memory 206208 kb
Host smart-dcbb87db-2b85-4469-9fe6-ac1ee58d438a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2707837907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2707837907
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2016966281
Short name T1798
Test name
Test status
Simulation time 11515123013 ps
CPU time 38.02 seconds
Started Mar 17 03:16:20 PM PDT 24
Finished Mar 17 03:16:59 PM PDT 24
Peak memory 235852 kb
Host smart-20ec133b-1aba-4865-9bf3-66fcb9d08175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016966281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2016966281
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_upload.224158396
Short name T1656
Test name
Test status
Simulation time 9011507018 ps
CPU time 14.72 seconds
Started Mar 17 01:31:33 PM PDT 24
Finished Mar 17 01:31:48 PM PDT 24
Peak memory 219132 kb
Host smart-3652aa11-c407-4f8b-ac77-028e99807f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224158396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.224158396
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1147445824
Short name T1398
Test name
Test status
Simulation time 14574254 ps
CPU time 0.75 seconds
Started Mar 17 03:16:27 PM PDT 24
Finished Mar 17 03:16:28 PM PDT 24
Peak memory 205336 kb
Host smart-c0313274-1774-4a6a-8e12-3f235e9fdff6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147445824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1147445824
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2750127973
Short name T937
Test name
Test status
Simulation time 41292305 ps
CPU time 0.73 seconds
Started Mar 17 01:31:41 PM PDT 24
Finished Mar 17 01:31:42 PM PDT 24
Peak memory 204276 kb
Host smart-4a39a148-6f97-4f86-ba4e-eb652f353edf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750127973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2750127973
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1948359355
Short name T1056
Test name
Test status
Simulation time 4438415330 ps
CPU time 4.93 seconds
Started Mar 17 01:31:41 PM PDT 24
Finished Mar 17 01:31:46 PM PDT 24
Peak memory 219352 kb
Host smart-0ac91a8a-f03a-4898-9ad2-72177e08c103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948359355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1948359355
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.226156659
Short name T1855
Test name
Test status
Simulation time 41533013 ps
CPU time 2.6 seconds
Started Mar 17 03:16:21 PM PDT 24
Finished Mar 17 03:16:24 PM PDT 24
Peak memory 233900 kb
Host smart-dd3b931e-88bd-40b7-b575-9ccccd47f12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226156659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.226156659
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1667597378
Short name T1219
Test name
Test status
Simulation time 28455466 ps
CPU time 0.79 seconds
Started Mar 17 03:16:21 PM PDT 24
Finished Mar 17 03:16:22 PM PDT 24
Peak memory 205184 kb
Host smart-fe2d6a4a-a09d-43ba-a302-d299253f88fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667597378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1667597378
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.630418332
Short name T385
Test name
Test status
Simulation time 23188903 ps
CPU time 0.78 seconds
Started Mar 17 01:31:34 PM PDT 24
Finished Mar 17 01:31:35 PM PDT 24
Peak memory 204896 kb
Host smart-957dc494-ae47-4c17-8d6f-fe0929b6016c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630418332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.630418332
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2102884309
Short name T1286
Test name
Test status
Simulation time 110838394539 ps
CPU time 116.24 seconds
Started Mar 17 01:31:42 PM PDT 24
Finished Mar 17 01:33:39 PM PDT 24
Peak memory 256612 kb
Host smart-12611dfc-f02b-40a6-a62f-a0ddf5ba48e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102884309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2102884309
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3733188034
Short name T1431
Test name
Test status
Simulation time 30884065638 ps
CPU time 138.43 seconds
Started Mar 17 03:16:24 PM PDT 24
Finished Mar 17 03:18:43 PM PDT 24
Peak memory 248964 kb
Host smart-be41772d-e140-4459-8c1f-d168ef2dc261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733188034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3733188034
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.1305536344
Short name T81
Test name
Test status
Simulation time 7045731150 ps
CPU time 88.72 seconds
Started Mar 17 01:31:41 PM PDT 24
Finished Mar 17 01:33:09 PM PDT 24
Peak memory 256376 kb
Host smart-893b3b33-9f16-4b59-807c-202f1b8b9898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305536344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.1305536344
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2344443085
Short name T207
Test name
Test status
Simulation time 9683171250 ps
CPU time 48.2 seconds
Started Mar 17 03:16:27 PM PDT 24
Finished Mar 17 03:17:15 PM PDT 24
Peak memory 233404 kb
Host smart-5643c803-4b4a-41f2-81d5-c1514ad7aa7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344443085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2344443085
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2751106865
Short name T842
Test name
Test status
Simulation time 17155160549 ps
CPU time 175.55 seconds
Started Mar 17 01:31:40 PM PDT 24
Finished Mar 17 01:34:35 PM PDT 24
Peak memory 249932 kb
Host smart-a83ee1c6-19f0-444a-852a-e43b67786128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751106865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2751106865
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3123417162
Short name T122
Test name
Test status
Simulation time 27972833991 ps
CPU time 118.5 seconds
Started Mar 17 03:16:25 PM PDT 24
Finished Mar 17 03:18:24 PM PDT 24
Peak memory 249012 kb
Host smart-bc4d4ae9-19c4-4329-8da7-25fd487939a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123417162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3123417162
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.2137421710
Short name T1079
Test name
Test status
Simulation time 1368617562 ps
CPU time 10.7 seconds
Started Mar 17 03:16:20 PM PDT 24
Finished Mar 17 03:16:32 PM PDT 24
Peak memory 238492 kb
Host smart-e8889b4c-48b2-4174-9d4d-9d04407c38f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137421710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.2137421710
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3557343988
Short name T1251
Test name
Test status
Simulation time 12178329988 ps
CPU time 19.56 seconds
Started Mar 17 01:31:43 PM PDT 24
Finished Mar 17 01:32:02 PM PDT 24
Peak memory 238504 kb
Host smart-f12ca954-1196-45c1-88b3-765c6058001e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557343988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3557343988
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2767075838
Short name T1654
Test name
Test status
Simulation time 2303715251 ps
CPU time 5.58 seconds
Started Mar 17 03:16:21 PM PDT 24
Finished Mar 17 03:16:27 PM PDT 24
Peak memory 218664 kb
Host smart-554feb52-8d48-4376-a4f3-97318ebf7e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767075838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2767075838
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_intercept.631754204
Short name T1629
Test name
Test status
Simulation time 443366923 ps
CPU time 4.72 seconds
Started Mar 17 01:31:40 PM PDT 24
Finished Mar 17 01:31:44 PM PDT 24
Peak memory 237680 kb
Host smart-68181c93-7601-49ed-9275-1a6c71a6c566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631754204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.631754204
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.1886521387
Short name T1144
Test name
Test status
Simulation time 10119003088 ps
CPU time 9.4 seconds
Started Mar 17 01:31:38 PM PDT 24
Finished Mar 17 01:31:48 PM PDT 24
Peak memory 223700 kb
Host smart-285f2bd1-ff43-4165-8c42-cbe4f89d26d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886521387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.1886521387
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2870436951
Short name T740
Test name
Test status
Simulation time 5297423249 ps
CPU time 18.28 seconds
Started Mar 17 03:16:19 PM PDT 24
Finished Mar 17 03:16:38 PM PDT 24
Peak memory 247796 kb
Host smart-525a1b2c-669e-4b1f-9805-7d6620d5d4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870436951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2870436951
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1130271056
Short name T364
Test name
Test status
Simulation time 637013348 ps
CPU time 5.53 seconds
Started Mar 17 01:31:43 PM PDT 24
Finished Mar 17 01:31:48 PM PDT 24
Peak memory 235132 kb
Host smart-71bcc83d-bd8a-4f01-a2e9-0e993a5d6d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130271056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1130271056
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.3331198725
Short name T447
Test name
Test status
Simulation time 3992011237 ps
CPU time 12.42 seconds
Started Mar 17 03:16:21 PM PDT 24
Finished Mar 17 03:16:34 PM PDT 24
Peak memory 224364 kb
Host smart-c40a71a6-87bb-41da-b18e-238f3f266d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331198725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.3331198725
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.2670341501
Short name T1667
Test name
Test status
Simulation time 14383427167 ps
CPU time 17.42 seconds
Started Mar 17 03:16:27 PM PDT 24
Finished Mar 17 03:16:44 PM PDT 24
Peak memory 236592 kb
Host smart-494b83d5-52dd-4ca6-917b-bb57ebaede47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670341501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.2670341501
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.511688038
Short name T1001
Test name
Test status
Simulation time 1975752693 ps
CPU time 7.42 seconds
Started Mar 17 01:31:41 PM PDT 24
Finished Mar 17 01:31:49 PM PDT 24
Peak memory 233492 kb
Host smart-2e54bb50-16f3-4c98-b0b0-60b7e4f0dcd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511688038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.511688038
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2031221175
Short name T125
Test name
Test status
Simulation time 788740596 ps
CPU time 4.83 seconds
Started Mar 17 01:31:42 PM PDT 24
Finished Mar 17 01:31:47 PM PDT 24
Peak memory 219624 kb
Host smart-8b09b4e3-eb77-4478-bd70-2fa028391136
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2031221175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2031221175
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.4203740533
Short name T1628
Test name
Test status
Simulation time 852566665 ps
CPU time 3.32 seconds
Started Mar 17 03:16:32 PM PDT 24
Finished Mar 17 03:16:35 PM PDT 24
Peak memory 218520 kb
Host smart-bc7a2eeb-16aa-4174-b6af-a5c1612d77f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4203740533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.4203740533
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1698749852
Short name T1861
Test name
Test status
Simulation time 297689241 ps
CPU time 1.16 seconds
Started Mar 17 01:31:42 PM PDT 24
Finished Mar 17 01:31:43 PM PDT 24
Peak memory 207328 kb
Host smart-2d4cc1d1-ae29-497d-9300-69c4562d1e5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698749852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1698749852
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.2412609883
Short name T70
Test name
Test status
Simulation time 28491986253 ps
CPU time 251.58 seconds
Started Mar 17 03:16:24 PM PDT 24
Finished Mar 17 03:20:36 PM PDT 24
Peak memory 279928 kb
Host smart-6eb4fbff-e749-4be7-aef3-609a54139640
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412609883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.2412609883
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.2234841693
Short name T1517
Test name
Test status
Simulation time 3278957369 ps
CPU time 11.29 seconds
Started Mar 17 01:31:42 PM PDT 24
Finished Mar 17 01:31:54 PM PDT 24
Peak memory 215940 kb
Host smart-e12528d1-8348-4843-987c-8d555b6d0ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234841693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2234841693
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3618797905
Short name T293
Test name
Test status
Simulation time 26814269756 ps
CPU time 30.83 seconds
Started Mar 17 03:16:22 PM PDT 24
Finished Mar 17 03:16:53 PM PDT 24
Peak memory 216196 kb
Host smart-6ca1e510-ef4b-45c3-9c4e-b020f7271363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618797905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3618797905
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.35423885
Short name T865
Test name
Test status
Simulation time 3981550847 ps
CPU time 7.52 seconds
Started Mar 17 03:16:24 PM PDT 24
Finished Mar 17 03:16:32 PM PDT 24
Peak memory 216124 kb
Host smart-5164d069-7173-4436-b702-1f384cd90fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35423885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.35423885
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.664426923
Short name T1107
Test name
Test status
Simulation time 9216530384 ps
CPU time 13.9 seconds
Started Mar 17 01:31:42 PM PDT 24
Finished Mar 17 01:31:56 PM PDT 24
Peak memory 215876 kb
Host smart-91777cb0-fd56-42fa-84ab-b3cc403dafd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664426923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.664426923
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.1907512803
Short name T741
Test name
Test status
Simulation time 27985888 ps
CPU time 0.79 seconds
Started Mar 17 03:16:22 PM PDT 24
Finished Mar 17 03:16:23 PM PDT 24
Peak memory 205500 kb
Host smart-a2f3517e-db38-419c-880c-2c20d47ec1c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907512803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.1907512803
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2571799713
Short name T1145
Test name
Test status
Simulation time 54653103 ps
CPU time 1.18 seconds
Started Mar 17 01:31:38 PM PDT 24
Finished Mar 17 01:31:40 PM PDT 24
Peak memory 207248 kb
Host smart-025b8580-0214-4b87-b166-9b741fc18953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571799713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2571799713
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.3163383063
Short name T771
Test name
Test status
Simulation time 46920098 ps
CPU time 0.72 seconds
Started Mar 17 01:31:39 PM PDT 24
Finished Mar 17 01:31:40 PM PDT 24
Peak memory 205196 kb
Host smart-2fc0704f-29c2-4f91-b500-dfcb117825bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163383063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3163383063
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.506976235
Short name T1018
Test name
Test status
Simulation time 217804826 ps
CPU time 0.93 seconds
Started Mar 17 03:16:18 PM PDT 24
Finished Mar 17 03:16:20 PM PDT 24
Peak memory 206396 kb
Host smart-6dbec887-e38c-4173-92f0-8e03e934f067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506976235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.506976235
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1204549318
Short name T468
Test name
Test status
Simulation time 28252709244 ps
CPU time 38.41 seconds
Started Mar 17 03:16:20 PM PDT 24
Finished Mar 17 03:17:00 PM PDT 24
Peak memory 226840 kb
Host smart-35342d42-1aa1-41c7-86e8-d4bd43b0ae92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204549318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1204549318
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_upload.738880995
Short name T1413
Test name
Test status
Simulation time 3385526594 ps
CPU time 16.72 seconds
Started Mar 17 01:31:38 PM PDT 24
Finished Mar 17 01:31:55 PM PDT 24
Peak memory 234580 kb
Host smart-37ce3c5b-fbe2-450f-914f-a0af07119845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=738880995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.738880995
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3527461709
Short name T571
Test name
Test status
Simulation time 29785678 ps
CPU time 0.73 seconds
Started Mar 17 03:16:31 PM PDT 24
Finished Mar 17 03:16:32 PM PDT 24
Peak memory 205036 kb
Host smart-a2eccc3c-f7dc-405b-a5a8-3100eb4fccd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527461709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3527461709
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.582809757
Short name T305
Test name
Test status
Simulation time 12719394 ps
CPU time 0.77 seconds
Started Mar 17 01:31:45 PM PDT 24
Finished Mar 17 01:31:46 PM PDT 24
Peak memory 204820 kb
Host smart-b9b097a7-339f-42df-b723-8105ddf014d8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582809757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.582809757
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3715076885
Short name T1568
Test name
Test status
Simulation time 1252081777 ps
CPU time 5.5 seconds
Started Mar 17 01:31:43 PM PDT 24
Finished Mar 17 01:31:48 PM PDT 24
Peak memory 233820 kb
Host smart-06cb55dc-95e6-47f5-8fe3-3af1fe73a0bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715076885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3715076885
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.632626987
Short name T1520
Test name
Test status
Simulation time 969605964 ps
CPU time 6.66 seconds
Started Mar 17 03:16:25 PM PDT 24
Finished Mar 17 03:16:32 PM PDT 24
Peak memory 233624 kb
Host smart-ec9c8fb4-53de-4ade-83b0-0cdb56e7f4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632626987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.632626987
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3179275090
Short name T910
Test name
Test status
Simulation time 16696056 ps
CPU time 0.76 seconds
Started Mar 17 03:16:24 PM PDT 24
Finished Mar 17 03:16:25 PM PDT 24
Peak memory 205456 kb
Host smart-84d57c9a-dd16-4f04-8452-a863d7015249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179275090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3179275090
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.740032941
Short name T1518
Test name
Test status
Simulation time 21589939 ps
CPU time 0.82 seconds
Started Mar 17 01:31:38 PM PDT 24
Finished Mar 17 01:31:39 PM PDT 24
Peak memory 206036 kb
Host smart-aecdad0b-9d3a-46dc-b56c-3057c633cc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740032941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.740032941
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3887599339
Short name T174
Test name
Test status
Simulation time 317699929766 ps
CPU time 384.54 seconds
Started Mar 17 01:31:45 PM PDT 24
Finished Mar 17 01:38:10 PM PDT 24
Peak memory 256476 kb
Host smart-4c98eece-7c4b-401c-b534-cb04c45b5eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887599339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3887599339
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.525610911
Short name T1605
Test name
Test status
Simulation time 19420332208 ps
CPU time 49.47 seconds
Started Mar 17 03:16:36 PM PDT 24
Finished Mar 17 03:17:25 PM PDT 24
Peak memory 248472 kb
Host smart-35885270-8471-4b0d-b6e0-91f8549ead8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525610911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.525610911
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.3934214668
Short name T1307
Test name
Test status
Simulation time 43634888360 ps
CPU time 142.7 seconds
Started Mar 17 03:16:30 PM PDT 24
Finished Mar 17 03:18:53 PM PDT 24
Peak memory 257084 kb
Host smart-86f8ea0f-cb04-49d3-bb9a-58e174633607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934214668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.3934214668
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1181312049
Short name T32
Test name
Test status
Simulation time 54462001611 ps
CPU time 176.87 seconds
Started Mar 17 03:16:29 PM PDT 24
Finished Mar 17 03:19:27 PM PDT 24
Peak memory 249000 kb
Host smart-d4ffea86-0762-41e0-b491-51a57ae93705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181312049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1181312049
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.4189282558
Short name T1356
Test name
Test status
Simulation time 23469676191 ps
CPU time 207.07 seconds
Started Mar 17 01:31:44 PM PDT 24
Finished Mar 17 01:35:11 PM PDT 24
Peak memory 255980 kb
Host smart-d490904f-ce51-4bb9-85c8-f2943207a64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189282558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.4189282558
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1081774263
Short name T1051
Test name
Test status
Simulation time 9742364779 ps
CPU time 25.42 seconds
Started Mar 17 03:16:35 PM PDT 24
Finished Mar 17 03:17:01 PM PDT 24
Peak memory 233208 kb
Host smart-68ad4e90-ed8f-46a8-b5b3-dc73070d237e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081774263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1081774263
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.957369269
Short name T784
Test name
Test status
Simulation time 2350697711 ps
CPU time 11.27 seconds
Started Mar 17 01:31:46 PM PDT 24
Finished Mar 17 01:31:57 PM PDT 24
Peak memory 240344 kb
Host smart-f5effd5c-3f01-49ec-a0df-efe641c69fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957369269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.957369269
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2011803587
Short name T1235
Test name
Test status
Simulation time 464441322 ps
CPU time 3.15 seconds
Started Mar 17 01:31:45 PM PDT 24
Finished Mar 17 01:31:48 PM PDT 24
Peak memory 223872 kb
Host smart-e05e8040-322e-4093-81b4-286c3de0dcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2011803587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2011803587
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_intercept.692692708
Short name T756
Test name
Test status
Simulation time 909430126 ps
CPU time 5.87 seconds
Started Mar 17 03:16:24 PM PDT 24
Finished Mar 17 03:16:30 PM PDT 24
Peak memory 219708 kb
Host smart-5141096e-259a-43e2-9f8e-4c428b6c4694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692692708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.692692708
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.1029894174
Short name T1266
Test name
Test status
Simulation time 9959028065 ps
CPU time 21.32 seconds
Started Mar 17 01:31:45 PM PDT 24
Finished Mar 17 01:32:06 PM PDT 24
Peak memory 239096 kb
Host smart-447860fe-3d6e-4ac1-aa02-7099408d9923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029894174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.1029894174
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.4264467039
Short name T1586
Test name
Test status
Simulation time 15262648056 ps
CPU time 6.31 seconds
Started Mar 17 03:16:26 PM PDT 24
Finished Mar 17 03:16:32 PM PDT 24
Peak memory 225628 kb
Host smart-5fac785a-8e2d-4bae-9306-5070ea57aa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264467039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4264467039
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2180579974
Short name T1011
Test name
Test status
Simulation time 3372400479 ps
CPU time 11.78 seconds
Started Mar 17 03:16:26 PM PDT 24
Finished Mar 17 03:16:38 PM PDT 24
Peak memory 238820 kb
Host smart-22b97219-1569-4264-bd5c-f3b787710ea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180579974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2180579974
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2479751
Short name T261
Test name
Test status
Simulation time 6814114215 ps
CPU time 12.1 seconds
Started Mar 17 01:31:44 PM PDT 24
Finished Mar 17 01:31:56 PM PDT 24
Peak memory 240368 kb
Host smart-2addd3b2-68df-45bf-8855-6a25b2a4332d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.2479751
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1226291396
Short name T218
Test name
Test status
Simulation time 854485861 ps
CPU time 3.64 seconds
Started Mar 17 03:16:32 PM PDT 24
Finished Mar 17 03:16:36 PM PDT 24
Peak memory 233496 kb
Host smart-297b50f7-c6c1-4103-90e5-c7131b2e9ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226291396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1226291396
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.3918422212
Short name T612
Test name
Test status
Simulation time 3876556406 ps
CPU time 9.83 seconds
Started Mar 17 01:31:39 PM PDT 24
Finished Mar 17 01:31:48 PM PDT 24
Peak memory 228116 kb
Host smart-86f8c7af-2de9-4db7-bb6d-a0b8252592b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918422212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3918422212
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.4066081567
Short name T758
Test name
Test status
Simulation time 900797652 ps
CPU time 4.98 seconds
Started Mar 17 03:16:33 PM PDT 24
Finished Mar 17 03:16:38 PM PDT 24
Peak memory 218600 kb
Host smart-ab264403-1779-404a-b9fb-dbc38330487b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4066081567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.4066081567
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.671733834
Short name T543
Test name
Test status
Simulation time 2428038674 ps
CPU time 5.94 seconds
Started Mar 17 01:31:45 PM PDT 24
Finished Mar 17 01:31:51 PM PDT 24
Peak memory 221872 kb
Host smart-050e42f0-5143-4db2-a1c7-dd84d891c9bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=671733834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.671733834
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2806081126
Short name T1169
Test name
Test status
Simulation time 201909562570 ps
CPU time 381.26 seconds
Started Mar 17 03:16:31 PM PDT 24
Finished Mar 17 03:22:53 PM PDT 24
Peak memory 249048 kb
Host smart-199d0f5d-3332-465b-9caa-e7c420564427
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806081126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2806081126
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.4149388213
Short name T1904
Test name
Test status
Simulation time 111707349 ps
CPU time 1.1 seconds
Started Mar 17 01:31:44 PM PDT 24
Finished Mar 17 01:31:45 PM PDT 24
Peak memory 206428 kb
Host smart-ed04df05-bc34-4c07-b8c0-fade530fd8e6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149388213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.4149388213
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.2293187107
Short name T1478
Test name
Test status
Simulation time 8562577141 ps
CPU time 42.87 seconds
Started Mar 17 01:31:42 PM PDT 24
Finished Mar 17 01:32:25 PM PDT 24
Peak memory 215964 kb
Host smart-5cc5fabd-dd0e-4f31-8881-24cced85b880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293187107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.2293187107
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3917725635
Short name T780
Test name
Test status
Simulation time 3144230346 ps
CPU time 34.49 seconds
Started Mar 17 03:16:24 PM PDT 24
Finished Mar 17 03:16:59 PM PDT 24
Peak memory 220628 kb
Host smart-8a852d12-e1e5-42e7-8d52-1ebc46cfd414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917725635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3917725635
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2055626433
Short name T328
Test name
Test status
Simulation time 27080174606 ps
CPU time 18.24 seconds
Started Mar 17 01:31:41 PM PDT 24
Finished Mar 17 01:32:00 PM PDT 24
Peak memory 215920 kb
Host smart-8901c219-4ffc-4feb-8fc3-f415de165322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055626433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2055626433
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2544089555
Short name T638
Test name
Test status
Simulation time 847714873 ps
CPU time 2.27 seconds
Started Mar 17 03:16:32 PM PDT 24
Finished Mar 17 03:16:34 PM PDT 24
Peak memory 215788 kb
Host smart-9eef9b72-5556-4374-9ad9-e3be066ccc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544089555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2544089555
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.1565898290
Short name T449
Test name
Test status
Simulation time 269591237 ps
CPU time 3.73 seconds
Started Mar 17 03:16:24 PM PDT 24
Finished Mar 17 03:16:29 PM PDT 24
Peak memory 216132 kb
Host smart-ef41e2db-7401-4cc0-a3ce-b9664f1fd492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565898290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.1565898290
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2843165684
Short name T926
Test name
Test status
Simulation time 200957834 ps
CPU time 2.62 seconds
Started Mar 17 01:31:39 PM PDT 24
Finished Mar 17 01:31:42 PM PDT 24
Peak memory 207352 kb
Host smart-0ec6e22e-69d9-47a3-bafa-df0e6a6ca559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843165684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2843165684
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2170318990
Short name T492
Test name
Test status
Simulation time 97479420 ps
CPU time 0.8 seconds
Started Mar 17 01:31:38 PM PDT 24
Finished Mar 17 01:31:39 PM PDT 24
Peak memory 205204 kb
Host smart-61568187-15ad-45d7-89f0-16771ce87ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170318990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2170318990
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.52144550
Short name T1544
Test name
Test status
Simulation time 83038476 ps
CPU time 0.96 seconds
Started Mar 17 03:16:27 PM PDT 24
Finished Mar 17 03:16:28 PM PDT 24
Peak memory 205364 kb
Host smart-d7a33601-1041-430c-9df5-afa5e9b6eb22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=52144550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.52144550
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1133493844
Short name T183
Test name
Test status
Simulation time 21565676537 ps
CPU time 21.34 seconds
Started Mar 17 01:31:44 PM PDT 24
Finished Mar 17 01:32:06 PM PDT 24
Peak memory 238268 kb
Host smart-694d19b2-61df-4911-831e-cde37c7ffce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133493844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1133493844
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_upload.3117150556
Short name T581
Test name
Test status
Simulation time 8845109143 ps
CPU time 30.82 seconds
Started Mar 17 03:16:27 PM PDT 24
Finished Mar 17 03:16:58 PM PDT 24
Peak memory 240500 kb
Host smart-a9d45924-b5de-411d-84f5-d619d3fc26b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117150556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3117150556
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.1456484200
Short name T1642
Test name
Test status
Simulation time 20416329 ps
CPU time 0.76 seconds
Started Mar 17 03:16:37 PM PDT 24
Finished Mar 17 03:16:38 PM PDT 24
Peak memory 204448 kb
Host smart-f5a1bf4f-ff1e-4d85-a4a6-7bfdaadf9e78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456484200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
1456484200
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3345918568
Short name T695
Test name
Test status
Simulation time 12590971 ps
CPU time 0.72 seconds
Started Mar 17 01:31:54 PM PDT 24
Finished Mar 17 01:31:55 PM PDT 24
Peak memory 204840 kb
Host smart-d18034f5-efe3-4368-8b13-cba0025ca4af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3345918568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3345918568
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3525378364
Short name T698
Test name
Test status
Simulation time 263623082 ps
CPU time 2.67 seconds
Started Mar 17 03:16:29 PM PDT 24
Finished Mar 17 03:16:32 PM PDT 24
Peak memory 218580 kb
Host smart-c2515322-bf2f-49c3-84fe-c3b0d3aa5126
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525378364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3525378364
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3995436486
Short name T1071
Test name
Test status
Simulation time 24151502687 ps
CPU time 12.62 seconds
Started Mar 17 01:31:50 PM PDT 24
Finished Mar 17 01:32:03 PM PDT 24
Peak memory 232720 kb
Host smart-f7720339-9680-47bd-ba91-ea133b856ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995436486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3995436486
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3064582082
Short name T1615
Test name
Test status
Simulation time 22472022 ps
CPU time 0.75 seconds
Started Mar 17 03:16:35 PM PDT 24
Finished Mar 17 03:16:36 PM PDT 24
Peak memory 205132 kb
Host smart-927c9d60-76b1-477a-b4f1-0e4bb664a758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064582082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3064582082
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3399872887
Short name T1416
Test name
Test status
Simulation time 132332900 ps
CPU time 0.81 seconds
Started Mar 17 01:31:44 PM PDT 24
Finished Mar 17 01:31:45 PM PDT 24
Peak memory 206232 kb
Host smart-6e081826-2025-4927-8c1d-ddc9d041d07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3399872887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3399872887
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3558950103
Short name T25
Test name
Test status
Simulation time 26286574525 ps
CPU time 63.24 seconds
Started Mar 17 03:16:29 PM PDT 24
Finished Mar 17 03:17:33 PM PDT 24
Peak memory 240744 kb
Host smart-fbbbf891-a4d2-4701-b2b7-79b61954efb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558950103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3558950103
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.1121506308
Short name T994
Test name
Test status
Simulation time 8624926534 ps
CPU time 41.92 seconds
Started Mar 17 03:16:34 PM PDT 24
Finished Mar 17 03:17:16 PM PDT 24
Peak memory 232928 kb
Host smart-5378c678-1d81-4a58-8baa-6f6ce4fc9e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121506308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1121506308
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.2798047690
Short name T1500
Test name
Test status
Simulation time 43797667180 ps
CPU time 83.39 seconds
Started Mar 17 01:31:52 PM PDT 24
Finished Mar 17 01:33:16 PM PDT 24
Peak memory 236856 kb
Host smart-b22a10c0-5338-41d2-9067-dda367597737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798047690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2798047690
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.1822669688
Short name T1576
Test name
Test status
Simulation time 51496861687 ps
CPU time 299.13 seconds
Started Mar 17 01:31:50 PM PDT 24
Finished Mar 17 01:36:49 PM PDT 24
Peak memory 267872 kb
Host smart-6e17a60a-12d4-4f27-ab37-6f1f53656c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822669688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.1822669688
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.3952663926
Short name T1409
Test name
Test status
Simulation time 153519655010 ps
CPU time 355.6 seconds
Started Mar 17 03:16:33 PM PDT 24
Finished Mar 17 03:22:29 PM PDT 24
Peak memory 251496 kb
Host smart-fcd7c0b0-248a-4bb9-88a2-c5106af24bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952663926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.3952663926
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1525964892
Short name T425
Test name
Test status
Simulation time 21456979395 ps
CPU time 41.28 seconds
Started Mar 17 01:31:53 PM PDT 24
Finished Mar 17 01:32:34 PM PDT 24
Peak memory 234468 kb
Host smart-23c67805-6878-4a58-9aae-304522a607bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525964892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1525964892
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2320637345
Short name T1807
Test name
Test status
Simulation time 235273578 ps
CPU time 7.7 seconds
Started Mar 17 03:16:31 PM PDT 24
Finished Mar 17 03:16:39 PM PDT 24
Peak memory 238372 kb
Host smart-f318986c-221b-4955-acc7-9f068a7b2734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320637345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2320637345
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1223652904
Short name T1808
Test name
Test status
Simulation time 1025436881 ps
CPU time 4.5 seconds
Started Mar 17 03:16:33 PM PDT 24
Finished Mar 17 03:16:38 PM PDT 24
Peak memory 224252 kb
Host smart-c271e5c7-afed-464a-b53c-510899f41899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223652904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1223652904
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_intercept.635360794
Short name T1220
Test name
Test status
Simulation time 3243027700 ps
CPU time 5.46 seconds
Started Mar 17 01:31:54 PM PDT 24
Finished Mar 17 01:31:59 PM PDT 24
Peak memory 218040 kb
Host smart-df892270-e1f1-4449-ae38-d0974b25a1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635360794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.635360794
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2142752538
Short name T936
Test name
Test status
Simulation time 35535874638 ps
CPU time 31.42 seconds
Started Mar 17 03:16:28 PM PDT 24
Finished Mar 17 03:16:59 PM PDT 24
Peak memory 230012 kb
Host smart-9b99e935-001a-45b5-86bc-660feae440f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142752538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2142752538
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3990291242
Short name T1466
Test name
Test status
Simulation time 4482257912 ps
CPU time 13.67 seconds
Started Mar 17 01:31:50 PM PDT 24
Finished Mar 17 01:32:04 PM PDT 24
Peak memory 218004 kb
Host smart-b4ac60e6-7b08-4ea8-9744-0c4ace15f85c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990291242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3990291242
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3042807545
Short name T1809
Test name
Test status
Simulation time 11591147930 ps
CPU time 30.95 seconds
Started Mar 17 01:31:50 PM PDT 24
Finished Mar 17 01:32:22 PM PDT 24
Peak memory 234332 kb
Host smart-3384921f-2b29-4c06-bb4b-04a38a0a0e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042807545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3042807545
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3788412713
Short name T476
Test name
Test status
Simulation time 1310970027 ps
CPU time 8.46 seconds
Started Mar 17 03:16:35 PM PDT 24
Finished Mar 17 03:16:44 PM PDT 24
Peak memory 233364 kb
Host smart-2c26318f-2b8b-471f-81d2-2bd3aa00a1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788412713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3788412713
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3767711319
Short name T1739
Test name
Test status
Simulation time 8883431786 ps
CPU time 25.69 seconds
Started Mar 17 03:16:34 PM PDT 24
Finished Mar 17 03:17:00 PM PDT 24
Peak memory 235900 kb
Host smart-d4b50f82-1aa4-4bd1-8322-b554bb4672c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3767711319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3767711319
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.4121347245
Short name T569
Test name
Test status
Simulation time 6573185834 ps
CPU time 21.22 seconds
Started Mar 17 01:31:51 PM PDT 24
Finished Mar 17 01:32:13 PM PDT 24
Peak memory 232340 kb
Host smart-197f7671-c5fe-4f07-af87-75e9b53947b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121347245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.4121347245
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2851954992
Short name T1402
Test name
Test status
Simulation time 1084979149 ps
CPU time 5.01 seconds
Started Mar 17 01:31:51 PM PDT 24
Finished Mar 17 01:31:57 PM PDT 24
Peak memory 220000 kb
Host smart-ef3bf322-6b3d-4caf-9317-514bab593289
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2851954992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2851954992
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.813575159
Short name T627
Test name
Test status
Simulation time 61505767 ps
CPU time 3.42 seconds
Started Mar 17 03:16:38 PM PDT 24
Finished Mar 17 03:16:42 PM PDT 24
Peak memory 221940 kb
Host smart-0273dadd-e7fd-423e-a52e-fd0851cbffe1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=813575159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.813575159
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.1738829502
Short name T1476
Test name
Test status
Simulation time 11872438208 ps
CPU time 136.5 seconds
Started Mar 17 01:31:50 PM PDT 24
Finished Mar 17 01:34:07 PM PDT 24
Peak memory 255608 kb
Host smart-c1cde221-0414-44ea-9357-bb6c15ba1791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1738829502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.1738829502
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.275675683
Short name T743
Test name
Test status
Simulation time 27366672350 ps
CPU time 188.06 seconds
Started Mar 17 03:16:36 PM PDT 24
Finished Mar 17 03:19:44 PM PDT 24
Peak memory 257028 kb
Host smart-25580846-df72-46e2-8f50-fbfe58aeb50b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=275675683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.275675683
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2313113268
Short name T1716
Test name
Test status
Simulation time 1445873159 ps
CPU time 12.87 seconds
Started Mar 17 01:31:44 PM PDT 24
Finished Mar 17 01:31:57 PM PDT 24
Peak memory 215916 kb
Host smart-af2f43b4-e62b-4e35-bc10-6ab3ff68159a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313113268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2313113268
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.4241062199
Short name T1577
Test name
Test status
Simulation time 9683513601 ps
CPU time 35.57 seconds
Started Mar 17 03:16:35 PM PDT 24
Finished Mar 17 03:17:11 PM PDT 24
Peak memory 216168 kb
Host smart-2b0be9ef-00ab-4148-904d-222f0d1b4de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241062199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.4241062199
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2794821330
Short name T1484
Test name
Test status
Simulation time 843880668 ps
CPU time 3.49 seconds
Started Mar 17 03:16:38 PM PDT 24
Finished Mar 17 03:16:41 PM PDT 24
Peak memory 215768 kb
Host smart-95a889ba-f64d-4bdf-bb52-177cbdfbd95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794821330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2794821330
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.3459638591
Short name T1881
Test name
Test status
Simulation time 1609018899 ps
CPU time 4.54 seconds
Started Mar 17 01:31:45 PM PDT 24
Finished Mar 17 01:31:50 PM PDT 24
Peak memory 215820 kb
Host smart-5ec9a520-a408-4176-b56c-d6fc64d8fc82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459638591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3459638591
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3390728033
Short name T892
Test name
Test status
Simulation time 81233719 ps
CPU time 1.43 seconds
Started Mar 17 01:31:50 PM PDT 24
Finished Mar 17 01:31:52 PM PDT 24
Peak memory 215820 kb
Host smart-98e60f39-fa38-4c4c-9779-44c1f7408595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390728033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3390728033
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.353325732
Short name T587
Test name
Test status
Simulation time 102987822 ps
CPU time 2.31 seconds
Started Mar 17 03:16:28 PM PDT 24
Finished Mar 17 03:16:31 PM PDT 24
Peak memory 216040 kb
Host smart-79c593ba-dbe1-4a6b-9ad7-219d313e73c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353325732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.353325732
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1390708611
Short name T1301
Test name
Test status
Simulation time 73463675 ps
CPU time 0.83 seconds
Started Mar 17 03:16:38 PM PDT 24
Finished Mar 17 03:16:39 PM PDT 24
Peak memory 205436 kb
Host smart-6e457890-e4fa-4014-a86f-4590c7e6fdd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390708611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1390708611
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.4144965336
Short name T1404
Test name
Test status
Simulation time 58091398 ps
CPU time 0.89 seconds
Started Mar 17 01:31:46 PM PDT 24
Finished Mar 17 01:31:47 PM PDT 24
Peak memory 205164 kb
Host smart-76c08126-0294-4ef6-a5a1-4c00bafe9245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144965336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.4144965336
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.1321701521
Short name T821
Test name
Test status
Simulation time 984279488 ps
CPU time 7.25 seconds
Started Mar 17 03:16:40 PM PDT 24
Finished Mar 17 03:16:47 PM PDT 24
Peak memory 234192 kb
Host smart-82ea18fa-f925-4bcf-901c-0eda8ab8bd30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321701521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.1321701521
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2390133678
Short name T947
Test name
Test status
Simulation time 40465546 ps
CPU time 0.71 seconds
Started Mar 17 03:16:37 PM PDT 24
Finished Mar 17 03:16:38 PM PDT 24
Peak memory 204452 kb
Host smart-8bae2fc5-285a-42e3-9da3-140112879479
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390133678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2390133678
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.2583458463
Short name T466
Test name
Test status
Simulation time 15147035 ps
CPU time 0.74 seconds
Started Mar 17 01:31:56 PM PDT 24
Finished Mar 17 01:31:57 PM PDT 24
Peak memory 204852 kb
Host smart-282b6d85-bfeb-41aa-b534-a29d8d6e7334
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583458463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
2583458463
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.1612977419
Short name T606
Test name
Test status
Simulation time 1063920328 ps
CPU time 3.78 seconds
Started Mar 17 01:31:51 PM PDT 24
Finished Mar 17 01:31:55 PM PDT 24
Peak memory 219340 kb
Host smart-cf3e1f09-81f5-4c23-a0c6-eaa526afad5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612977419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.1612977419
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3965518943
Short name T1405
Test name
Test status
Simulation time 24172056939 ps
CPU time 11.47 seconds
Started Mar 17 03:16:38 PM PDT 24
Finished Mar 17 03:16:50 PM PDT 24
Peak memory 234604 kb
Host smart-e018621e-07d7-4cc3-aede-db2da9fca5b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965518943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3965518943
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3579042615
Short name T1069
Test name
Test status
Simulation time 15073451 ps
CPU time 0.76 seconds
Started Mar 17 03:16:37 PM PDT 24
Finished Mar 17 03:16:38 PM PDT 24
Peak memory 205100 kb
Host smart-63caf009-577b-4cee-a254-8bc52ca93cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579042615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3579042615
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3861620185
Short name T1491
Test name
Test status
Simulation time 48811012 ps
CPU time 0.75 seconds
Started Mar 17 01:31:50 PM PDT 24
Finished Mar 17 01:31:51 PM PDT 24
Peak memory 206048 kb
Host smart-16cd7f88-01de-4491-885b-49f1a94533df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861620185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3861620185
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.2080046257
Short name T1551
Test name
Test status
Simulation time 12609574376 ps
CPU time 39.71 seconds
Started Mar 17 03:16:41 PM PDT 24
Finished Mar 17 03:17:20 PM PDT 24
Peak memory 248916 kb
Host smart-e0120b2b-7c9d-455c-8756-7cba09287f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080046257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.2080046257
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.300895010
Short name T182
Test name
Test status
Simulation time 5549557409 ps
CPU time 27.62 seconds
Started Mar 17 01:31:52 PM PDT 24
Finished Mar 17 01:32:20 PM PDT 24
Peak memory 240424 kb
Host smart-231c0c2b-2836-49cc-ad80-3ad5e1ab07bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300895010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.300895010
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1261754154
Short name T1147
Test name
Test status
Simulation time 26881234902 ps
CPU time 105.23 seconds
Started Mar 17 03:16:41 PM PDT 24
Finished Mar 17 03:18:27 PM PDT 24
Peak memory 249048 kb
Host smart-d2140034-3cbd-467a-a4c7-90b1bc6e445f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261754154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1261754154
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.844814693
Short name T209
Test name
Test status
Simulation time 267147127703 ps
CPU time 428.05 seconds
Started Mar 17 01:31:50 PM PDT 24
Finished Mar 17 01:38:59 PM PDT 24
Peak memory 255184 kb
Host smart-f6b8d7c3-f11f-4652-a107-56e819696424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844814693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.844814693
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.1127249930
Short name T1084
Test name
Test status
Simulation time 33405947483 ps
CPU time 43.89 seconds
Started Mar 17 01:31:50 PM PDT 24
Finished Mar 17 01:32:35 PM PDT 24
Peak memory 232408 kb
Host smart-eda8306c-6c27-4bb6-829c-ac7f53c19b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127249930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.1127249930
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.3546370635
Short name T1699
Test name
Test status
Simulation time 4867003666 ps
CPU time 58.2 seconds
Started Mar 17 03:16:38 PM PDT 24
Finished Mar 17 03:17:37 PM PDT 24
Peak memory 249060 kb
Host smart-f87b1301-1334-46e5-85ef-2958335b0949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546370635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.3546370635
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3660499702
Short name T473
Test name
Test status
Simulation time 6606080034 ps
CPU time 46.72 seconds
Started Mar 17 03:16:37 PM PDT 24
Finished Mar 17 03:17:24 PM PDT 24
Peak memory 235744 kb
Host smart-50a9adbc-88d2-46e3-8ceb-60e453218c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660499702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3660499702
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.371395041
Short name T1547
Test name
Test status
Simulation time 23756973828 ps
CPU time 25.77 seconds
Started Mar 17 01:31:54 PM PDT 24
Finished Mar 17 01:32:20 PM PDT 24
Peak memory 232268 kb
Host smart-2485e98e-0eab-489d-b0fb-56273028c4f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371395041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.371395041
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1321780006
Short name T827
Test name
Test status
Simulation time 1943285628 ps
CPU time 7.55 seconds
Started Mar 17 01:31:55 PM PDT 24
Finished Mar 17 01:32:03 PM PDT 24
Peak memory 234940 kb
Host smart-971c7a61-1ef0-467b-a73f-a146637517f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321780006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1321780006
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_intercept.1509002282
Short name T1373
Test name
Test status
Simulation time 10071645739 ps
CPU time 6.54 seconds
Started Mar 17 03:16:37 PM PDT 24
Finished Mar 17 03:16:44 PM PDT 24
Peak memory 236184 kb
Host smart-56a1bd56-7a21-4694-a726-933016bc16b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509002282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1509002282
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1228098035
Short name T582
Test name
Test status
Simulation time 5282192734 ps
CPU time 6.43 seconds
Started Mar 17 01:31:50 PM PDT 24
Finished Mar 17 01:31:56 PM PDT 24
Peak memory 233188 kb
Host smart-38e96329-eb89-42c2-9fae-4a6ac7d8b481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228098035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1228098035
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.673478669
Short name T857
Test name
Test status
Simulation time 117159369 ps
CPU time 3.09 seconds
Started Mar 17 03:16:37 PM PDT 24
Finished Mar 17 03:16:41 PM PDT 24
Peak memory 222524 kb
Host smart-fc5f40c3-33ff-470d-b201-dddacc435171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673478669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.673478669
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.300500571
Short name T1338
Test name
Test status
Simulation time 7373923964 ps
CPU time 21.5 seconds
Started Mar 17 01:31:51 PM PDT 24
Finished Mar 17 01:32:12 PM PDT 24
Peak memory 233244 kb
Host smart-d9169cef-6251-40bd-ad0c-a9c7b3e6a895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300500571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.300500571
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.3842830441
Short name T1445
Test name
Test status
Simulation time 1189565695 ps
CPU time 12.98 seconds
Started Mar 17 03:16:39 PM PDT 24
Finished Mar 17 03:16:53 PM PDT 24
Peak memory 240544 kb
Host smart-73aaf2dd-75b8-4b3e-a38f-3ab13bb0c9bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842830441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.3842830441
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.1718157501
Short name T1497
Test name
Test status
Simulation time 2790140357 ps
CPU time 10.16 seconds
Started Mar 17 03:16:38 PM PDT 24
Finished Mar 17 03:16:49 PM PDT 24
Peak memory 217228 kb
Host smart-2dc5c57c-c0f4-4813-a9b0-503b0658f336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718157501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.1718157501
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3111172945
Short name T1316
Test name
Test status
Simulation time 6871005691 ps
CPU time 3.07 seconds
Started Mar 17 01:31:51 PM PDT 24
Finished Mar 17 01:31:55 PM PDT 24
Peak memory 224084 kb
Host smart-53805ed4-e6e8-4fa5-a70e-fb840f1f25b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111172945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3111172945
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.2270205372
Short name T1427
Test name
Test status
Simulation time 2159063999 ps
CPU time 4.66 seconds
Started Mar 17 03:16:39 PM PDT 24
Finished Mar 17 03:16:44 PM PDT 24
Peak memory 218616 kb
Host smart-fd07d177-9449-4866-9d23-cba1e2ed82a4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2270205372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.2270205372
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.4001271804
Short name T1745
Test name
Test status
Simulation time 68504950 ps
CPU time 3.19 seconds
Started Mar 17 01:31:50 PM PDT 24
Finished Mar 17 01:31:54 PM PDT 24
Peak memory 218272 kb
Host smart-4977fa04-d716-4c94-a116-c5ad7882fee3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4001271804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.4001271804
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1776951390
Short name T258
Test name
Test status
Simulation time 42088988857 ps
CPU time 117.87 seconds
Started Mar 17 01:31:58 PM PDT 24
Finished Mar 17 01:33:56 PM PDT 24
Peak memory 271232 kb
Host smart-49e86602-597b-4769-a843-d3bd487249c7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776951390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1776951390
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4065003981
Short name T1850
Test name
Test status
Simulation time 232137802 ps
CPU time 1.06 seconds
Started Mar 17 03:16:38 PM PDT 24
Finished Mar 17 03:16:40 PM PDT 24
Peak memory 206856 kb
Host smart-bf952c3f-6840-4ffb-af25-ba530a83f9b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065003981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4065003981
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1171328126
Short name T295
Test name
Test status
Simulation time 18875935279 ps
CPU time 29.87 seconds
Started Mar 17 01:31:51 PM PDT 24
Finished Mar 17 01:32:21 PM PDT 24
Peak memory 216008 kb
Host smart-1847a894-e8e2-46bf-aaca-2dc239b96725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171328126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1171328126
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.4135706809
Short name T1212
Test name
Test status
Simulation time 933251659 ps
CPU time 2.72 seconds
Started Mar 17 03:16:37 PM PDT 24
Finished Mar 17 03:16:40 PM PDT 24
Peak memory 216044 kb
Host smart-ae4690c3-28c5-4da7-b272-d03ac8cf9f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135706809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.4135706809
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4054699922
Short name T1645
Test name
Test status
Simulation time 547308156 ps
CPU time 2.09 seconds
Started Mar 17 01:31:52 PM PDT 24
Finished Mar 17 01:31:54 PM PDT 24
Peak memory 215652 kb
Host smart-33024fc5-a36d-44ae-a298-61b7fabaf10b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054699922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4054699922
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.4123412085
Short name T1355
Test name
Test status
Simulation time 55943295030 ps
CPU time 26.79 seconds
Started Mar 17 03:16:33 PM PDT 24
Finished Mar 17 03:17:00 PM PDT 24
Peak memory 216104 kb
Host smart-947581a2-afbc-4319-9e21-ded1a7162b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123412085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.4123412085
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3460243646
Short name T1127
Test name
Test status
Simulation time 616628276 ps
CPU time 8.93 seconds
Started Mar 17 01:31:53 PM PDT 24
Finished Mar 17 01:32:03 PM PDT 24
Peak memory 216064 kb
Host smart-b741e0ae-6fcc-4ad5-ab96-35e62884f909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460243646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3460243646
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.690929116
Short name T934
Test name
Test status
Simulation time 264717781 ps
CPU time 1.95 seconds
Started Mar 17 03:16:39 PM PDT 24
Finished Mar 17 03:16:41 PM PDT 24
Peak memory 216096 kb
Host smart-8a5cbb81-2286-4769-9d18-3e50b17c387c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690929116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.690929116
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2752731756
Short name T1771
Test name
Test status
Simulation time 53081038 ps
CPU time 0.84 seconds
Started Mar 17 01:31:51 PM PDT 24
Finished Mar 17 01:31:52 PM PDT 24
Peak memory 205176 kb
Host smart-49a90894-dc1f-46f3-a105-99748148b5af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2752731756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2752731756
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.806620573
Short name T800
Test name
Test status
Simulation time 31831467 ps
CPU time 0.76 seconds
Started Mar 17 03:16:40 PM PDT 24
Finished Mar 17 03:16:41 PM PDT 24
Peak memory 205412 kb
Host smart-72506bef-538c-414d-a288-0cf9c7131495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806620573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.806620573
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.149374742
Short name T145
Test name
Test status
Simulation time 182087514 ps
CPU time 3.6 seconds
Started Mar 17 03:16:41 PM PDT 24
Finished Mar 17 03:16:44 PM PDT 24
Peak memory 218504 kb
Host smart-57b20145-4be4-42a0-8c18-f7a44271b13b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149374742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.149374742
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_upload.630636851
Short name T1434
Test name
Test status
Simulation time 6268222760 ps
CPU time 12.67 seconds
Started Mar 17 01:31:50 PM PDT 24
Finished Mar 17 01:32:03 PM PDT 24
Peak memory 229756 kb
Host smart-5418ae6c-7b8b-41a4-bbdb-5a87a4f3004b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630636851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.630636851
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.1416154261
Short name T667
Test name
Test status
Simulation time 40313218 ps
CPU time 0.68 seconds
Started Mar 17 03:16:44 PM PDT 24
Finished Mar 17 03:16:45 PM PDT 24
Peak memory 204984 kb
Host smart-9556613d-a100-4b11-a579-be75f2d77050
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416154261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
1416154261
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.529113656
Short name T1866
Test name
Test status
Simulation time 30507849 ps
CPU time 0.71 seconds
Started Mar 17 01:31:55 PM PDT 24
Finished Mar 17 01:31:56 PM PDT 24
Peak memory 204852 kb
Host smart-bbc0a122-dee7-4129-b396-2f743bc35b6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529113656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.529113656
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1466274245
Short name T927
Test name
Test status
Simulation time 525569351 ps
CPU time 2.95 seconds
Started Mar 17 01:31:57 PM PDT 24
Finished Mar 17 01:32:00 PM PDT 24
Peak memory 217908 kb
Host smart-84b6e95f-7cd5-4d20-9572-76df3fe2d33e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466274245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1466274245
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2423764199
Short name T1609
Test name
Test status
Simulation time 1096695649 ps
CPU time 5.73 seconds
Started Mar 17 03:16:38 PM PDT 24
Finished Mar 17 03:16:44 PM PDT 24
Peak memory 219220 kb
Host smart-bb8909e8-7851-4425-9d35-37f6c16dfbc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423764199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2423764199
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.3831293771
Short name T763
Test name
Test status
Simulation time 60024683 ps
CPU time 0.8 seconds
Started Mar 17 03:16:39 PM PDT 24
Finished Mar 17 03:16:41 PM PDT 24
Peak memory 205132 kb
Host smart-d0890d0d-09b9-4abc-8f26-4f1b6c066c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831293771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3831293771
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.571047686
Short name T576
Test name
Test status
Simulation time 17762029 ps
CPU time 0.8 seconds
Started Mar 17 01:31:56 PM PDT 24
Finished Mar 17 01:31:57 PM PDT 24
Peak memory 206244 kb
Host smart-95da765b-180b-4dde-bf19-a966629f6f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571047686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.571047686
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.1017554801
Short name T151
Test name
Test status
Simulation time 168999459812 ps
CPU time 267.48 seconds
Started Mar 17 01:31:57 PM PDT 24
Finished Mar 17 01:36:25 PM PDT 24
Peak memory 256840 kb
Host smart-47f8b616-c7c2-409b-afb1-9f99b7081e92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017554801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.1017554801
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.867230947
Short name T923
Test name
Test status
Simulation time 3290161881 ps
CPU time 43.68 seconds
Started Mar 17 03:16:43 PM PDT 24
Finished Mar 17 03:17:27 PM PDT 24
Peak memory 253312 kb
Host smart-ba9c7ce7-3e90-42ec-8129-e98e37b20bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867230947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.867230947
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3145387150
Short name T395
Test name
Test status
Simulation time 985783681 ps
CPU time 22.16 seconds
Started Mar 17 03:16:45 PM PDT 24
Finished Mar 17 03:17:07 PM PDT 24
Peak memory 253144 kb
Host smart-4646e38e-9ec4-42ea-8bcc-b954d6676310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145387150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3145387150
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3542774695
Short name T570
Test name
Test status
Simulation time 8570238483 ps
CPU time 68.69 seconds
Started Mar 17 01:31:58 PM PDT 24
Finished Mar 17 01:33:07 PM PDT 24
Peak memory 233440 kb
Host smart-85477d63-9db9-4123-8265-c3f5b2ba9807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542774695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3542774695
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3846907966
Short name T275
Test name
Test status
Simulation time 3844746331 ps
CPU time 62.57 seconds
Started Mar 17 01:31:55 PM PDT 24
Finished Mar 17 01:32:58 PM PDT 24
Peak memory 252868 kb
Host smart-f45a4919-d10f-4327-9151-070b3def4990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846907966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3846907966
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.834314812
Short name T1110
Test name
Test status
Simulation time 4328888799 ps
CPU time 79.69 seconds
Started Mar 17 03:16:47 PM PDT 24
Finished Mar 17 03:18:06 PM PDT 24
Peak memory 249368 kb
Host smart-5782e503-59f4-4db9-aa44-116e06469816
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834314812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.834314812
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1044172155
Short name T284
Test name
Test status
Simulation time 13343806417 ps
CPU time 56.7 seconds
Started Mar 17 01:31:57 PM PDT 24
Finished Mar 17 01:32:54 PM PDT 24
Peak memory 240456 kb
Host smart-b1fa67af-829c-4b91-90bd-e78430602a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044172155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1044172155
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3674326999
Short name T828
Test name
Test status
Simulation time 10437970269 ps
CPU time 36.74 seconds
Started Mar 17 03:16:42 PM PDT 24
Finished Mar 17 03:17:18 PM PDT 24
Peak memory 236380 kb
Host smart-856884f3-5dc0-4f3a-9f23-5795b83473ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674326999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3674326999
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1251615049
Short name T1564
Test name
Test status
Simulation time 3359007018 ps
CPU time 4.68 seconds
Started Mar 17 01:31:56 PM PDT 24
Finished Mar 17 01:32:01 PM PDT 24
Peak memory 233324 kb
Host smart-8465de5d-e2ac-4a8e-a020-645e9132ca1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251615049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1251615049
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1377051518
Short name T1162
Test name
Test status
Simulation time 1880872990 ps
CPU time 7.68 seconds
Started Mar 17 03:16:37 PM PDT 24
Finished Mar 17 03:16:45 PM PDT 24
Peak memory 233076 kb
Host smart-460f6f1a-7cc4-4606-8cb3-1e54f87de3d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377051518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1377051518
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3775283622
Short name T1159
Test name
Test status
Simulation time 861205779 ps
CPU time 11.6 seconds
Started Mar 17 03:16:38 PM PDT 24
Finished Mar 17 03:16:50 PM PDT 24
Peak memory 236940 kb
Host smart-9ca3e70d-133f-4b3e-b54f-39f06178eef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775283622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3775283622
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.400443625
Short name T488
Test name
Test status
Simulation time 189652765 ps
CPU time 4.33 seconds
Started Mar 17 01:31:57 PM PDT 24
Finished Mar 17 01:32:02 PM PDT 24
Peak memory 233304 kb
Host smart-85df35d8-a126-4f10-a95d-26ee15f66232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400443625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.400443625
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2109789548
Short name T1735
Test name
Test status
Simulation time 284742658 ps
CPU time 3.19 seconds
Started Mar 17 03:16:40 PM PDT 24
Finished Mar 17 03:16:43 PM PDT 24
Peak memory 224256 kb
Host smart-593bad95-43ea-4838-8502-86d97312d832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109789548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2109789548
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2963405789
Short name T1690
Test name
Test status
Simulation time 30509531912 ps
CPU time 21.31 seconds
Started Mar 17 01:31:55 PM PDT 24
Finished Mar 17 01:32:17 PM PDT 24
Peak memory 232988 kb
Host smart-5ac5783a-6e46-4d60-a498-6980f75fd609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963405789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2963405789
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3996419877
Short name T898
Test name
Test status
Simulation time 16123764265 ps
CPU time 25.2 seconds
Started Mar 17 03:16:40 PM PDT 24
Finished Mar 17 03:17:06 PM PDT 24
Peak memory 227912 kb
Host smart-d0eeebe2-ff87-426c-adc7-dbda001bede8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996419877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3996419877
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.501694945
Short name T1905
Test name
Test status
Simulation time 4121511970 ps
CPU time 8.23 seconds
Started Mar 17 01:31:57 PM PDT 24
Finished Mar 17 01:32:06 PM PDT 24
Peak memory 240324 kb
Host smart-9117d3b3-b656-4c7c-89d7-379f31daaa5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501694945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.501694945
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2284844471
Short name T739
Test name
Test status
Simulation time 119730519 ps
CPU time 2.97 seconds
Started Mar 17 01:31:57 PM PDT 24
Finished Mar 17 01:32:00 PM PDT 24
Peak memory 220152 kb
Host smart-a4c91bc0-8471-472e-8936-bf5bad93c0d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2284844471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2284844471
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.638293642
Short name T124
Test name
Test status
Simulation time 742832027 ps
CPU time 3.79 seconds
Started Mar 17 03:16:41 PM PDT 24
Finished Mar 17 03:16:45 PM PDT 24
Peak memory 222780 kb
Host smart-e8ac4ccf-0139-46d4-948a-12de240f4980
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=638293642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.638293642
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1049902929
Short name T1697
Test name
Test status
Simulation time 42742531051 ps
CPU time 122.32 seconds
Started Mar 17 03:16:47 PM PDT 24
Finished Mar 17 03:18:49 PM PDT 24
Peak memory 248968 kb
Host smart-cdd0444b-f155-45c0-b6fa-c42ebd97e1af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049902929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1049902929
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4243333263
Short name T1439
Test name
Test status
Simulation time 5286432661 ps
CPU time 30.56 seconds
Started Mar 17 03:16:40 PM PDT 24
Finished Mar 17 03:17:11 PM PDT 24
Peak memory 220168 kb
Host smart-01d3a1f9-800a-47c1-8332-e38f75b8f258
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243333263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4243333263
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.9249754
Short name T1522
Test name
Test status
Simulation time 52318295124 ps
CPU time 30.4 seconds
Started Mar 17 01:31:58 PM PDT 24
Finished Mar 17 01:32:29 PM PDT 24
Peak memory 215832 kb
Host smart-7e9df10b-e762-4f69-8d47-8f05f51201da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9249754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.9249754
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.4145492791
Short name T1443
Test name
Test status
Simulation time 49806228256 ps
CPU time 10.76 seconds
Started Mar 17 03:16:41 PM PDT 24
Finished Mar 17 03:16:51 PM PDT 24
Peak memory 216076 kb
Host smart-bbe7d978-7cf5-4039-9795-9db4396cc7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145492791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.4145492791
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.721173954
Short name T73
Test name
Test status
Simulation time 5033609374 ps
CPU time 6.43 seconds
Started Mar 17 01:31:57 PM PDT 24
Finished Mar 17 01:32:04 PM PDT 24
Peak memory 215908 kb
Host smart-cb9fd646-26e0-4627-9615-e4ba03cee949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721173954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.721173954
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1016072875
Short name T409
Test name
Test status
Simulation time 125201250 ps
CPU time 1.16 seconds
Started Mar 17 01:31:55 PM PDT 24
Finished Mar 17 01:31:57 PM PDT 24
Peak memory 215456 kb
Host smart-cdab210d-ef09-40d0-9304-9e658256176b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016072875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1016072875
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2613124733
Short name T1005
Test name
Test status
Simulation time 283807064 ps
CPU time 8.05 seconds
Started Mar 17 03:16:37 PM PDT 24
Finished Mar 17 03:16:45 PM PDT 24
Peak memory 216312 kb
Host smart-6ca52c2c-52af-4537-8a45-0959d096ddeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613124733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2613124733
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2939448397
Short name T596
Test name
Test status
Simulation time 25831497 ps
CPU time 0.73 seconds
Started Mar 17 01:31:54 PM PDT 24
Finished Mar 17 01:31:55 PM PDT 24
Peak memory 205220 kb
Host smart-7f87ee97-bbca-44dd-a733-19edc6acf668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939448397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2939448397
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3808388758
Short name T568
Test name
Test status
Simulation time 187343479 ps
CPU time 1.18 seconds
Started Mar 17 03:16:39 PM PDT 24
Finished Mar 17 03:16:40 PM PDT 24
Peak memory 206436 kb
Host smart-fac7e5a9-5c68-4213-9d9a-25b9b04eae78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808388758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3808388758
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2445768344
Short name T649
Test name
Test status
Simulation time 734305158 ps
CPU time 4.35 seconds
Started Mar 17 03:16:42 PM PDT 24
Finished Mar 17 03:16:47 PM PDT 24
Peak memory 235648 kb
Host smart-d51a41f9-4b92-4100-b11b-e9df771bd5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445768344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2445768344
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_upload.3706201504
Short name T383
Test name
Test status
Simulation time 3571884959 ps
CPU time 7.36 seconds
Started Mar 17 01:31:58 PM PDT 24
Finished Mar 17 01:32:05 PM PDT 24
Peak memory 233688 kb
Host smart-8234af4f-3384-4097-ae99-77d4d17b4910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706201504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3706201504
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2167219148
Short name T1238
Test name
Test status
Simulation time 42318323 ps
CPU time 0.71 seconds
Started Mar 17 03:16:42 PM PDT 24
Finished Mar 17 03:16:42 PM PDT 24
Peak memory 205040 kb
Host smart-16801809-88fa-4dc4-ab0f-d1fab68640eb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167219148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2167219148
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3888401145
Short name T68
Test name
Test status
Simulation time 27997780 ps
CPU time 0.72 seconds
Started Mar 17 01:32:01 PM PDT 24
Finished Mar 17 01:32:02 PM PDT 24
Peak memory 205228 kb
Host smart-60ac5fc7-c8c1-4cb8-8457-d233cf3ff7b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888401145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3888401145
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.4060482108
Short name T217
Test name
Test status
Simulation time 454346111 ps
CPU time 3.38 seconds
Started Mar 17 03:16:44 PM PDT 24
Finished Mar 17 03:16:47 PM PDT 24
Peak memory 233832 kb
Host smart-c27c2300-956f-4216-a3c9-5002072d083e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060482108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.4060482108
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.766864590
Short name T1320
Test name
Test status
Simulation time 124513084 ps
CPU time 3.12 seconds
Started Mar 17 01:32:00 PM PDT 24
Finished Mar 17 01:32:03 PM PDT 24
Peak memory 218044 kb
Host smart-f08ebb69-fd09-4ec5-9f3e-2f9e0dc889da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766864590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.766864590
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3167210492
Short name T1376
Test name
Test status
Simulation time 29215487 ps
CPU time 0.77 seconds
Started Mar 17 03:16:45 PM PDT 24
Finished Mar 17 03:16:45 PM PDT 24
Peak memory 205116 kb
Host smart-af00827e-2e43-4793-8d58-9c673d0040c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167210492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3167210492
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3310566813
Short name T903
Test name
Test status
Simulation time 48411915 ps
CPU time 0.77 seconds
Started Mar 17 01:31:59 PM PDT 24
Finished Mar 17 01:32:00 PM PDT 24
Peak memory 205984 kb
Host smart-013edbd5-bab0-497f-87af-01ad36d5f9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310566813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3310566813
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.27258407
Short name T974
Test name
Test status
Simulation time 410544369214 ps
CPU time 492.98 seconds
Started Mar 17 01:32:01 PM PDT 24
Finished Mar 17 01:40:15 PM PDT 24
Peak memory 280572 kb
Host smart-b6bf82a3-6796-4926-91a5-ca8dc4b195ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27258407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.27258407
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3283706263
Short name T260
Test name
Test status
Simulation time 161008685197 ps
CPU time 220.34 seconds
Started Mar 17 03:16:42 PM PDT 24
Finished Mar 17 03:20:22 PM PDT 24
Peak memory 240752 kb
Host smart-eab54c98-1e33-44c3-84d7-327c5c8306ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283706263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3283706263
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.162164625
Short name T1333
Test name
Test status
Simulation time 8295567856 ps
CPU time 91.6 seconds
Started Mar 17 03:16:42 PM PDT 24
Finished Mar 17 03:18:14 PM PDT 24
Peak memory 257172 kb
Host smart-bf4dd007-a6b8-4764-842c-e33f38f2149b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162164625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.162164625
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3012613623
Short name T1894
Test name
Test status
Simulation time 32323392680 ps
CPU time 35.54 seconds
Started Mar 17 01:32:01 PM PDT 24
Finished Mar 17 01:32:37 PM PDT 24
Peak memory 221892 kb
Host smart-801fbea0-4f3e-421e-b8e8-23c2077df1bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3012613623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3012613623
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1219652617
Short name T1890
Test name
Test status
Simulation time 375972373001 ps
CPU time 651.52 seconds
Started Mar 17 03:16:46 PM PDT 24
Finished Mar 17 03:27:38 PM PDT 24
Peak memory 249200 kb
Host smart-1f0f7a55-a9da-41a8-a38c-8f1f36ed625a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219652617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1219652617
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1524220106
Short name T1763
Test name
Test status
Simulation time 36448264971 ps
CPU time 250.95 seconds
Started Mar 17 01:32:00 PM PDT 24
Finished Mar 17 01:36:11 PM PDT 24
Peak memory 266544 kb
Host smart-361b51b4-8841-4234-95b0-013d7d7ece09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524220106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1524220106
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3630754129
Short name T1116
Test name
Test status
Simulation time 2296425179 ps
CPU time 21.38 seconds
Started Mar 17 03:16:43 PM PDT 24
Finished Mar 17 03:17:05 PM PDT 24
Peak memory 233708 kb
Host smart-d9dd23e6-346d-42e6-920f-73073096abc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630754129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3630754129
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.577043365
Short name T782
Test name
Test status
Simulation time 14858326031 ps
CPU time 21.51 seconds
Started Mar 17 01:32:00 PM PDT 24
Finished Mar 17 01:32:22 PM PDT 24
Peak memory 239432 kb
Host smart-2154dd00-bb72-431a-954c-84808f1c69ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577043365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.577043365
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3615708282
Short name T540
Test name
Test status
Simulation time 426184795 ps
CPU time 3.13 seconds
Started Mar 17 03:16:42 PM PDT 24
Finished Mar 17 03:16:45 PM PDT 24
Peak memory 216696 kb
Host smart-f0aae788-d2ae-4d8a-bd01-87aa621b38bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615708282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3615708282
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3852400662
Short name T755
Test name
Test status
Simulation time 107688146 ps
CPU time 2.36 seconds
Started Mar 17 01:31:59 PM PDT 24
Finished Mar 17 01:32:02 PM PDT 24
Peak memory 216424 kb
Host smart-dc13ffd2-7f67-4df9-9824-8063b6de8c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852400662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3852400662
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1208852324
Short name T195
Test name
Test status
Simulation time 588581951 ps
CPU time 5.35 seconds
Started Mar 17 01:31:59 PM PDT 24
Finished Mar 17 01:32:04 PM PDT 24
Peak memory 218808 kb
Host smart-7c8ae7d5-ab21-4b55-9dd2-ae090d073c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208852324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1208852324
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.264317596
Short name T1226
Test name
Test status
Simulation time 3108063185 ps
CPU time 14.89 seconds
Started Mar 17 03:16:46 PM PDT 24
Finished Mar 17 03:17:01 PM PDT 24
Peak memory 248948 kb
Host smart-bfaa409d-187d-40de-a0dc-222d841a29eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264317596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.264317596
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2159498680
Short name T536
Test name
Test status
Simulation time 1028714069 ps
CPU time 3.25 seconds
Started Mar 17 03:16:42 PM PDT 24
Finished Mar 17 03:16:46 PM PDT 24
Peak memory 218272 kb
Host smart-fecb0c18-9390-482f-af0a-bc6f637b5818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159498680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2159498680
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2916325709
Short name T728
Test name
Test status
Simulation time 15108033084 ps
CPU time 41.76 seconds
Started Mar 17 01:32:02 PM PDT 24
Finished Mar 17 01:32:43 PM PDT 24
Peak memory 246076 kb
Host smart-2d706186-e393-40a8-b317-4d4bb03ca6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916325709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2916325709
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.1925975759
Short name T1237
Test name
Test status
Simulation time 364883012 ps
CPU time 2.47 seconds
Started Mar 17 01:32:01 PM PDT 24
Finished Mar 17 01:32:03 PM PDT 24
Peak memory 223792 kb
Host smart-20583e31-fdad-4ce6-868c-25ad47708dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925975759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.1925975759
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3697404473
Short name T1380
Test name
Test status
Simulation time 2059494238 ps
CPU time 13.22 seconds
Started Mar 17 03:16:42 PM PDT 24
Finished Mar 17 03:16:55 PM PDT 24
Peak memory 233828 kb
Host smart-1c151c7c-0d44-433e-8ab7-e30e6cbed5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697404473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3697404473
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1491002393
Short name T929
Test name
Test status
Simulation time 4219726268 ps
CPU time 5.86 seconds
Started Mar 17 01:32:01 PM PDT 24
Finished Mar 17 01:32:08 PM PDT 24
Peak memory 222496 kb
Host smart-144bdf7e-235b-47e8-a436-d30fee797049
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1491002393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1491002393
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.24645618
Short name T329
Test name
Test status
Simulation time 1820748837 ps
CPU time 5.84 seconds
Started Mar 17 03:16:43 PM PDT 24
Finished Mar 17 03:16:49 PM PDT 24
Peak memory 219020 kb
Host smart-a249afe1-c82c-4aee-a077-053deef7a3d8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=24645618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direc
t.24645618
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.1689735426
Short name T838
Test name
Test status
Simulation time 5157178733 ps
CPU time 100.76 seconds
Started Mar 17 01:32:01 PM PDT 24
Finished Mar 17 01:33:42 PM PDT 24
Peak memory 254208 kb
Host smart-b543c48e-833f-42a7-864c-51ec764909a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689735426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.1689735426
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3564741875
Short name T1352
Test name
Test status
Simulation time 55458878369 ps
CPU time 396.23 seconds
Started Mar 17 03:16:42 PM PDT 24
Finished Mar 17 03:23:18 PM PDT 24
Peak memory 267272 kb
Host smart-bca20c5a-c5dc-4278-9930-4132b1657787
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564741875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3564741875
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2179460689
Short name T1239
Test name
Test status
Simulation time 35129425809 ps
CPU time 89.77 seconds
Started Mar 17 03:16:44 PM PDT 24
Finished Mar 17 03:18:14 PM PDT 24
Peak memory 216196 kb
Host smart-abde2b76-7b76-4605-9b22-ee9393607c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179460689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2179460689
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.2482960154
Short name T388
Test name
Test status
Simulation time 1668692094 ps
CPU time 25.81 seconds
Started Mar 17 01:32:01 PM PDT 24
Finished Mar 17 01:32:27 PM PDT 24
Peak memory 215812 kb
Host smart-68e82972-a211-4e4b-a915-e6123b868343
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482960154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.2482960154
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1018471657
Short name T953
Test name
Test status
Simulation time 893033247 ps
CPU time 2.21 seconds
Started Mar 17 01:31:59 PM PDT 24
Finished Mar 17 01:32:02 PM PDT 24
Peak memory 215648 kb
Host smart-28c033d4-51b8-4dce-8056-fc172596d2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018471657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1018471657
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3372848547
Short name T366
Test name
Test status
Simulation time 9631540227 ps
CPU time 13.65 seconds
Started Mar 17 03:16:40 PM PDT 24
Finished Mar 17 03:16:54 PM PDT 24
Peak memory 216128 kb
Host smart-3a571cf2-97bf-4084-960e-3e2e83e89715
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372848547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3372848547
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3739859475
Short name T729
Test name
Test status
Simulation time 25051930 ps
CPU time 0.85 seconds
Started Mar 17 03:16:43 PM PDT 24
Finished Mar 17 03:16:44 PM PDT 24
Peak memory 206196 kb
Host smart-062284cf-8f7f-4820-9b47-6f0d0c2121f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739859475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3739859475
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.550850931
Short name T1488
Test name
Test status
Simulation time 530035517 ps
CPU time 2.94 seconds
Started Mar 17 01:32:02 PM PDT 24
Finished Mar 17 01:32:05 PM PDT 24
Peak memory 215932 kb
Host smart-4f9b0fd2-5441-4f25-92cb-4e0c35a106e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550850931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.550850931
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1291282364
Short name T938
Test name
Test status
Simulation time 129093956 ps
CPU time 1.07 seconds
Started Mar 17 03:16:42 PM PDT 24
Finished Mar 17 03:16:43 PM PDT 24
Peak memory 206460 kb
Host smart-1e676530-4d3b-4da2-9e81-f0f3aefe0c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291282364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1291282364
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3850396290
Short name T1671
Test name
Test status
Simulation time 363034905 ps
CPU time 0.96 seconds
Started Mar 17 01:32:01 PM PDT 24
Finished Mar 17 01:32:02 PM PDT 24
Peak memory 206184 kb
Host smart-66643c07-32da-4c6b-a8b1-c3c15b9f30d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850396290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3850396290
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.1110492800
Short name T622
Test name
Test status
Simulation time 2111854889 ps
CPU time 6.01 seconds
Started Mar 17 03:16:44 PM PDT 24
Finished Mar 17 03:16:50 PM PDT 24
Peak memory 233968 kb
Host smart-d324badc-0185-42aa-922a-8472e341a5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110492800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1110492800
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_upload.11212907
Short name T1173
Test name
Test status
Simulation time 853737464 ps
CPU time 4.55 seconds
Started Mar 17 01:32:00 PM PDT 24
Finished Mar 17 01:32:04 PM PDT 24
Peak memory 234488 kb
Host smart-a5572931-8e97-43fb-9a95-04d1ef1b358e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11212907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.11212907
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1760646675
Short name T1632
Test name
Test status
Simulation time 41231112 ps
CPU time 0.69 seconds
Started Mar 17 03:13:23 PM PDT 24
Finished Mar 17 03:13:24 PM PDT 24
Peak memory 204444 kb
Host smart-e8c84294-9d35-4bba-8588-2f9eb512f3c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760646675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
760646675
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2299351985
Short name T1688
Test name
Test status
Simulation time 13698812 ps
CPU time 0.69 seconds
Started Mar 17 01:29:04 PM PDT 24
Finished Mar 17 01:29:05 PM PDT 24
Peak memory 204856 kb
Host smart-5492d1f4-031f-402d-9e49-13d37d8dba65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299351985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
299351985
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1436208338
Short name T677
Test name
Test status
Simulation time 2734393497 ps
CPU time 8.26 seconds
Started Mar 17 03:13:25 PM PDT 24
Finished Mar 17 03:13:34 PM PDT 24
Peak memory 219348 kb
Host smart-8b24fe40-bd41-46ba-9e23-ca25587f4544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436208338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1436208338
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.2364481062
Short name T222
Test name
Test status
Simulation time 3432533524 ps
CPU time 7.97 seconds
Started Mar 17 01:29:03 PM PDT 24
Finished Mar 17 01:29:11 PM PDT 24
Peak memory 224104 kb
Host smart-cbd146b1-834b-4dd0-abe4-e5336b290b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364481062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2364481062
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2646267723
Short name T1039
Test name
Test status
Simulation time 41722562 ps
CPU time 0.8 seconds
Started Mar 17 01:28:59 PM PDT 24
Finished Mar 17 01:29:00 PM PDT 24
Peak memory 206064 kb
Host smart-4d5ddad7-c63f-4991-aca5-152d95655583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646267723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2646267723
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.2996551524
Short name T311
Test name
Test status
Simulation time 125560488 ps
CPU time 0.82 seconds
Started Mar 17 03:13:15 PM PDT 24
Finished Mar 17 03:13:17 PM PDT 24
Peak memory 206192 kb
Host smart-59c7094f-192a-4b04-a53c-590d05692267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996551524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.2996551524
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3025486495
Short name T1276
Test name
Test status
Simulation time 35009466559 ps
CPU time 110.51 seconds
Started Mar 17 01:29:04 PM PDT 24
Finished Mar 17 01:30:56 PM PDT 24
Peak memory 232140 kb
Host smart-9948abee-0cf9-43c8-8b00-226476f91575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025486495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3025486495
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.4274947814
Short name T1549
Test name
Test status
Simulation time 19785826355 ps
CPU time 46.4 seconds
Started Mar 17 03:13:25 PM PDT 24
Finished Mar 17 03:14:12 PM PDT 24
Peak memory 237600 kb
Host smart-dcca2a76-81a2-41ca-a879-e05a062ef22d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274947814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.4274947814
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2874825747
Short name T273
Test name
Test status
Simulation time 7449397391 ps
CPU time 140.01 seconds
Started Mar 17 01:29:06 PM PDT 24
Finished Mar 17 01:31:27 PM PDT 24
Peak memory 268444 kb
Host smart-50e73619-de76-4e60-9a02-4cd70ec07277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874825747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2874825747
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3370696288
Short name T351
Test name
Test status
Simulation time 12823172099 ps
CPU time 40.59 seconds
Started Mar 17 03:13:23 PM PDT 24
Finished Mar 17 03:14:04 PM PDT 24
Peak memory 240788 kb
Host smart-38f383cb-bb6c-4406-ae7e-3127366c3e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370696288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3370696288
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1209408536
Short name T1566
Test name
Test status
Simulation time 421796654953 ps
CPU time 598.05 seconds
Started Mar 17 03:13:26 PM PDT 24
Finished Mar 17 03:23:25 PM PDT 24
Peak memory 273524 kb
Host smart-32d323ee-2b58-46d3-b6bf-5200b81cbdc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209408536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1209408536
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1535779772
Short name T1047
Test name
Test status
Simulation time 17207389161 ps
CPU time 91.66 seconds
Started Mar 17 01:29:04 PM PDT 24
Finished Mar 17 01:30:36 PM PDT 24
Peak memory 268752 kb
Host smart-ebc93e0b-f9e8-4229-aea0-494d40b6503f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535779772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1535779772
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.397752250
Short name T916
Test name
Test status
Simulation time 2536754525 ps
CPU time 15.61 seconds
Started Mar 17 01:29:10 PM PDT 24
Finished Mar 17 01:29:27 PM PDT 24
Peak memory 235012 kb
Host smart-e03988c6-b65a-4a4e-a13e-b96dd40c8f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397752250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.397752250
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.569963981
Short name T1885
Test name
Test status
Simulation time 9793275061 ps
CPU time 53.28 seconds
Started Mar 17 03:13:27 PM PDT 24
Finished Mar 17 03:14:20 PM PDT 24
Peak memory 240736 kb
Host smart-31ec0f19-31e2-46e7-83ac-5c19d1077595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569963981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.569963981
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1639680741
Short name T1382
Test name
Test status
Simulation time 5775744625 ps
CPU time 5.72 seconds
Started Mar 17 03:13:24 PM PDT 24
Finished Mar 17 03:13:30 PM PDT 24
Peak memory 218260 kb
Host smart-a49a6b13-a3ee-4eb4-b880-13d5c489824c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639680741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1639680741
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_intercept.2281163805
Short name T891
Test name
Test status
Simulation time 7198154590 ps
CPU time 11.64 seconds
Started Mar 17 01:29:04 PM PDT 24
Finished Mar 17 01:29:16 PM PDT 24
Peak memory 233404 kb
Host smart-29e24ff1-9448-42bb-a900-a59a2da63af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281163805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2281163805
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.2610493829
Short name T1464
Test name
Test status
Simulation time 16097315631 ps
CPU time 12.81 seconds
Started Mar 17 01:29:04 PM PDT 24
Finished Mar 17 01:29:18 PM PDT 24
Peak memory 237440 kb
Host smart-0927b9bc-5962-4afb-81d5-7c931f93a416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610493829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.2610493829
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.3142791300
Short name T1873
Test name
Test status
Simulation time 547714054 ps
CPU time 13.95 seconds
Started Mar 17 03:13:27 PM PDT 24
Finished Mar 17 03:13:41 PM PDT 24
Peak memory 236236 kb
Host smart-69bd1862-21a1-48ea-a14b-56403cba6f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142791300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3142791300
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_mem_parity.906500291
Short name T1210
Test name
Test status
Simulation time 98743563 ps
CPU time 1.11 seconds
Started Mar 17 01:28:57 PM PDT 24
Finished Mar 17 01:28:59 PM PDT 24
Peak memory 216420 kb
Host smart-4b71b59d-c072-482b-84b8-f50ec2b8c735
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906500291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
4.spi_device_mem_parity.906500291
Directory /workspace/4.spi_device_mem_parity/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2610981550
Short name T1108
Test name
Test status
Simulation time 206559425 ps
CPU time 3.28 seconds
Started Mar 17 03:13:25 PM PDT 24
Finished Mar 17 03:13:29 PM PDT 24
Peak memory 217744 kb
Host smart-9a163ea6-1be7-4722-b046-e87258249356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610981550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2610981550
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2705966675
Short name T1558
Test name
Test status
Simulation time 9236621364 ps
CPU time 7.75 seconds
Started Mar 17 01:29:04 PM PDT 24
Finished Mar 17 01:29:12 PM PDT 24
Peak memory 217992 kb
Host smart-19ccf487-7d46-4483-a3ff-2abefc349022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2705966675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2705966675
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3313302348
Short name T452
Test name
Test status
Simulation time 4206451856 ps
CPU time 5.92 seconds
Started Mar 17 03:13:25 PM PDT 24
Finished Mar 17 03:13:31 PM PDT 24
Peak memory 233016 kb
Host smart-88ddbeda-97b0-48d2-8b47-d9f2f3191449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313302348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3313302348
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.3676519416
Short name T1711
Test name
Test status
Simulation time 58695148348 ps
CPU time 28.97 seconds
Started Mar 17 01:29:04 PM PDT 24
Finished Mar 17 01:29:35 PM PDT 24
Peak memory 245680 kb
Host smart-dbd51bef-6e15-4059-8af8-e4a96a332daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676519416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3676519416
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.1279772181
Short name T54
Test name
Test status
Simulation time 17326732 ps
CPU time 0.74 seconds
Started Mar 17 01:28:58 PM PDT 24
Finished Mar 17 01:28:59 PM PDT 24
Peak memory 215768 kb
Host smart-1a7c8cfe-ea20-42da-bfba-25fbed50cea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279772181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.1279772181
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_ram_cfg.2446927440
Short name T968
Test name
Test status
Simulation time 36669368 ps
CPU time 0.75 seconds
Started Mar 17 03:13:20 PM PDT 24
Finished Mar 17 03:13:21 PM PDT 24
Peak memory 216020 kb
Host smart-967f2b72-d58a-4086-bae2-b35e8361ed2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446927440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_ram_cfg.2446927440
Directory /workspace/4.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2398658216
Short name T1459
Test name
Test status
Simulation time 181818986 ps
CPU time 3.58 seconds
Started Mar 17 03:13:26 PM PDT 24
Finished Mar 17 03:13:30 PM PDT 24
Peak memory 218856 kb
Host smart-6b5f7e05-906f-4f7c-9901-948025e55273
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2398658216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2398658216
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.4152836056
Short name T831
Test name
Test status
Simulation time 15059406955 ps
CPU time 5.51 seconds
Started Mar 17 01:29:10 PM PDT 24
Finished Mar 17 01:29:17 PM PDT 24
Peak memory 221828 kb
Host smart-7c81aed9-a495-4f7c-830b-481f8ab91c1a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4152836056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.4152836056
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1091907646
Short name T62
Test name
Test status
Simulation time 236652161 ps
CPU time 1.04 seconds
Started Mar 17 01:29:05 PM PDT 24
Finished Mar 17 01:29:08 PM PDT 24
Peak memory 235016 kb
Host smart-89c69d40-43eb-46ff-9887-77a7a6286cfa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091907646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1091907646
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1787899255
Short name T60
Test name
Test status
Simulation time 119609255 ps
CPU time 0.98 seconds
Started Mar 17 03:13:26 PM PDT 24
Finished Mar 17 03:13:27 PM PDT 24
Peak memory 234848 kb
Host smart-fc23df9c-6353-47d0-b49d-939ba3655bb9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787899255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1787899255
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1706888821
Short name T154
Test name
Test status
Simulation time 461363453 ps
CPU time 0.95 seconds
Started Mar 17 01:29:03 PM PDT 24
Finished Mar 17 01:29:04 PM PDT 24
Peak memory 206440 kb
Host smart-f25f54f9-753b-40eb-a14f-254b863da8bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706888821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1706888821
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2442583968
Short name T1053
Test name
Test status
Simulation time 105412686731 ps
CPU time 597.48 seconds
Started Mar 17 03:13:26 PM PDT 24
Finished Mar 17 03:23:23 PM PDT 24
Peak memory 269580 kb
Host smart-dc0ec732-4e16-4c45-b787-02a52b9e2713
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442583968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2442583968
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.1917757318
Short name T1585
Test name
Test status
Simulation time 2270773287 ps
CPU time 24.14 seconds
Started Mar 17 01:29:06 PM PDT 24
Finished Mar 17 01:29:31 PM PDT 24
Peak memory 216012 kb
Host smart-c72bdf7f-bfca-40b0-a697-04406581c210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917757318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.1917757318
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2231902933
Short name T1908
Test name
Test status
Simulation time 7167123350 ps
CPU time 34.55 seconds
Started Mar 17 03:13:20 PM PDT 24
Finished Mar 17 03:13:55 PM PDT 24
Peak memory 216160 kb
Host smart-ecce5f3c-a828-4e32-843c-25b9e55dc3a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231902933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2231902933
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2008868923
Short name T1648
Test name
Test status
Simulation time 4679341575 ps
CPU time 8.98 seconds
Started Mar 17 01:29:05 PM PDT 24
Finished Mar 17 01:29:16 PM PDT 24
Peak memory 215936 kb
Host smart-1cd07e10-6f0a-4c22-a40a-9b0f3a8c03d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008868923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2008868923
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.352270493
Short name T487
Test name
Test status
Simulation time 579443045 ps
CPU time 1.6 seconds
Started Mar 17 03:13:20 PM PDT 24
Finished Mar 17 03:13:22 PM PDT 24
Peak memory 207428 kb
Host smart-0633849e-2a5a-4c8c-81b6-51daf36328ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352270493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.352270493
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.247439233
Short name T670
Test name
Test status
Simulation time 265817113 ps
CPU time 1.59 seconds
Started Mar 17 01:29:03 PM PDT 24
Finished Mar 17 01:29:05 PM PDT 24
Peak memory 207552 kb
Host smart-c370309d-85a0-4469-aa52-ea58d64d2d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247439233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.247439233
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.3992580108
Short name T871
Test name
Test status
Simulation time 59941019 ps
CPU time 0.88 seconds
Started Mar 17 03:13:19 PM PDT 24
Finished Mar 17 03:13:21 PM PDT 24
Peak memory 206512 kb
Host smart-ab11fc82-45f4-4289-a879-54a0a81d30c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992580108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3992580108
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.3666617388
Short name T843
Test name
Test status
Simulation time 75581031 ps
CPU time 0.78 seconds
Started Mar 17 01:29:03 PM PDT 24
Finished Mar 17 01:29:04 PM PDT 24
Peak memory 205184 kb
Host smart-1101bc2d-c9ac-4d30-82e9-a099d1c3b2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666617388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3666617388
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4220492768
Short name T796
Test name
Test status
Simulation time 496537489 ps
CPU time 0.97 seconds
Started Mar 17 03:13:22 PM PDT 24
Finished Mar 17 03:13:23 PM PDT 24
Peak memory 205452 kb
Host smart-c2495eac-a530-47b1-9497-7652c1c8c696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220492768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4220492768
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.125815011
Short name T1430
Test name
Test status
Simulation time 24858735156 ps
CPU time 23.1 seconds
Started Mar 17 01:29:04 PM PDT 24
Finished Mar 17 01:29:29 PM PDT 24
Peak memory 232312 kb
Host smart-ac69c243-a46a-401d-a176-383e2ceaffb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125815011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.125815011
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_upload.3264434726
Short name T1260
Test name
Test status
Simulation time 65103610799 ps
CPU time 39.77 seconds
Started Mar 17 03:13:25 PM PDT 24
Finished Mar 17 03:14:05 PM PDT 24
Peak memory 226744 kb
Host smart-75bcf5fa-5a9f-4f69-8271-44e237b06df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264434726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3264434726
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.2047500594
Short name T992
Test name
Test status
Simulation time 27566408 ps
CPU time 0.73 seconds
Started Mar 17 01:32:12 PM PDT 24
Finished Mar 17 01:32:12 PM PDT 24
Peak memory 204828 kb
Host smart-0a4cba64-4075-4ac1-9838-b8c7d02cf187
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047500594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
2047500594
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3834722829
Short name T394
Test name
Test status
Simulation time 48116057 ps
CPU time 0.67 seconds
Started Mar 17 03:16:51 PM PDT 24
Finished Mar 17 03:16:52 PM PDT 24
Peak memory 205388 kb
Host smart-f0ef700e-c366-48c1-b6ac-eaa69d2ad4c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834722829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3834722829
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1937062717
Short name T376
Test name
Test status
Simulation time 441430792 ps
CPU time 3.67 seconds
Started Mar 17 01:32:06 PM PDT 24
Finished Mar 17 01:32:09 PM PDT 24
Peak memory 220328 kb
Host smart-dc8c70d1-6f9d-4f50-899e-d6d7c42855ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937062717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1937062717
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.3715959811
Short name T752
Test name
Test status
Simulation time 545580607 ps
CPU time 3.49 seconds
Started Mar 17 03:16:45 PM PDT 24
Finished Mar 17 03:16:49 PM PDT 24
Peak memory 218428 kb
Host smart-0bea4170-834c-4dde-8ed4-acd27ef14793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3715959811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.3715959811
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2985842673
Short name T1481
Test name
Test status
Simulation time 150206481 ps
CPU time 0.72 seconds
Started Mar 17 03:16:46 PM PDT 24
Finished Mar 17 03:16:47 PM PDT 24
Peak memory 205164 kb
Host smart-59db7eed-716f-40fe-b762-94028f9a1f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985842673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2985842673
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3688870642
Short name T1271
Test name
Test status
Simulation time 18575044 ps
CPU time 0.76 seconds
Started Mar 17 01:32:01 PM PDT 24
Finished Mar 17 01:32:02 PM PDT 24
Peak memory 205272 kb
Host smart-8d89601f-8acf-4b4b-968d-b3e39351881c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688870642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3688870642
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1039255283
Short name T1195
Test name
Test status
Simulation time 61690312773 ps
CPU time 263.6 seconds
Started Mar 17 03:16:46 PM PDT 24
Finished Mar 17 03:21:10 PM PDT 24
Peak memory 253924 kb
Host smart-122b5d51-c70c-4099-b48a-eb19eb085103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039255283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1039255283
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.3861771544
Short name T1293
Test name
Test status
Simulation time 9045476546 ps
CPU time 92.11 seconds
Started Mar 17 01:32:06 PM PDT 24
Finished Mar 17 01:33:39 PM PDT 24
Peak memory 249988 kb
Host smart-c65c3f9c-4aff-4238-b9f4-70bf7b29cd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861771544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3861771544
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3443954617
Short name T477
Test name
Test status
Simulation time 20792928653 ps
CPU time 33.46 seconds
Started Mar 17 03:16:53 PM PDT 24
Finished Mar 17 03:17:27 PM PDT 24
Peak memory 221192 kb
Host smart-ef38d7b1-f3d8-4c59-bcce-df112389d148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443954617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3443954617
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.782585951
Short name T1258
Test name
Test status
Simulation time 19004494196 ps
CPU time 76.37 seconds
Started Mar 17 01:32:16 PM PDT 24
Finished Mar 17 01:33:33 PM PDT 24
Peak memory 253824 kb
Host smart-8b63452e-b29d-45d0-a3f2-37c7cf4ff81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782585951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.782585951
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1798741254
Short name T1167
Test name
Test status
Simulation time 2089853785 ps
CPU time 39.23 seconds
Started Mar 17 01:32:17 PM PDT 24
Finished Mar 17 01:32:56 PM PDT 24
Peak memory 249616 kb
Host smart-63bb5e9f-83c4-4719-9451-d0aee5056974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798741254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1798741254
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.319277584
Short name T280
Test name
Test status
Simulation time 7095633302 ps
CPU time 23.58 seconds
Started Mar 17 01:32:06 PM PDT 24
Finished Mar 17 01:32:29 PM PDT 24
Peak memory 244620 kb
Host smart-c85c1713-b109-4e76-a7a0-0f53bb0c5ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319277584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.319277584
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.670665149
Short name T1452
Test name
Test status
Simulation time 4096800757 ps
CPU time 17.54 seconds
Started Mar 17 03:16:47 PM PDT 24
Finished Mar 17 03:17:05 PM PDT 24
Peak memory 247460 kb
Host smart-7dea31c2-803c-4906-835e-d109ed061913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670665149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.670665149
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_intercept.2421946118
Short name T1505
Test name
Test status
Simulation time 1821472647 ps
CPU time 4.48 seconds
Started Mar 17 03:16:47 PM PDT 24
Finished Mar 17 03:16:52 PM PDT 24
Peak memory 218696 kb
Host smart-042c3371-b068-4992-9eca-b5e988d727c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421946118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.2421946118
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_intercept.3515915530
Short name T1282
Test name
Test status
Simulation time 435985196 ps
CPU time 4.43 seconds
Started Mar 17 01:32:06 PM PDT 24
Finished Mar 17 01:32:10 PM PDT 24
Peak memory 233356 kb
Host smart-de77273b-4c00-4324-b9a5-2aa61381a83a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515915530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3515915530
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4052030758
Short name T1109
Test name
Test status
Simulation time 1653008823 ps
CPU time 7.26 seconds
Started Mar 17 01:32:07 PM PDT 24
Finished Mar 17 01:32:14 PM PDT 24
Peak memory 245204 kb
Host smart-a7bf01b6-7ab7-4d5e-a608-e1cd461ea93b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052030758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4052030758
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.907989719
Short name T1197
Test name
Test status
Simulation time 575756286 ps
CPU time 8.55 seconds
Started Mar 17 03:16:45 PM PDT 24
Finished Mar 17 03:16:54 PM PDT 24
Peak memory 234884 kb
Host smart-d079a47a-935c-472c-b7c2-d4784cea756e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907989719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.907989719
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.1123558039
Short name T1840
Test name
Test status
Simulation time 1354685192 ps
CPU time 4.14 seconds
Started Mar 17 01:32:05 PM PDT 24
Finished Mar 17 01:32:10 PM PDT 24
Peak memory 224024 kb
Host smart-2186e057-8f4a-4602-89fa-088981112713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123558039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.1123558039
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3646013792
Short name T1461
Test name
Test status
Simulation time 9190532585 ps
CPU time 21.2 seconds
Started Mar 17 03:16:46 PM PDT 24
Finished Mar 17 03:17:07 PM PDT 24
Peak memory 220868 kb
Host smart-e4062b2b-b026-4fc6-a4ee-3a03ae25284e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646013792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3646013792
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3302361369
Short name T12
Test name
Test status
Simulation time 1370556455 ps
CPU time 8.1 seconds
Started Mar 17 01:32:06 PM PDT 24
Finished Mar 17 01:32:15 PM PDT 24
Peak memory 224036 kb
Host smart-8650e2a7-8e95-4c6b-aabf-4418fce33ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302361369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3302361369
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.343865630
Short name T776
Test name
Test status
Simulation time 2954576826 ps
CPU time 5.1 seconds
Started Mar 17 03:16:45 PM PDT 24
Finished Mar 17 03:16:50 PM PDT 24
Peak memory 235640 kb
Host smart-1530588a-9285-485a-8b62-5c8eb2d3016e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343865630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.343865630
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.2411739421
Short name T1493
Test name
Test status
Simulation time 664990319 ps
CPU time 4.22 seconds
Started Mar 17 03:16:46 PM PDT 24
Finished Mar 17 03:16:50 PM PDT 24
Peak memory 218968 kb
Host smart-8a225719-cff5-4fe8-a778-4be15ca0618b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2411739421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.2411739421
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3241959271
Short name T1489
Test name
Test status
Simulation time 151200057 ps
CPU time 3.58 seconds
Started Mar 17 01:32:07 PM PDT 24
Finished Mar 17 01:32:11 PM PDT 24
Peak memory 222424 kb
Host smart-613b7b9e-3a82-49b4-8bf1-63a5909c2eb0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3241959271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3241959271
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1871121814
Short name T1441
Test name
Test status
Simulation time 36884106100 ps
CPU time 78.36 seconds
Started Mar 17 03:16:51 PM PDT 24
Finished Mar 17 03:18:09 PM PDT 24
Peak memory 238776 kb
Host smart-9e8794b5-98bd-42df-8148-c8ed138f4b08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871121814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1871121814
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.2580880768
Short name T144
Test name
Test status
Simulation time 60372075 ps
CPU time 1.01 seconds
Started Mar 17 01:32:11 PM PDT 24
Finished Mar 17 01:32:12 PM PDT 24
Peak memory 206260 kb
Host smart-a9c4a0dd-15ab-491d-b2f5-5b5ddd67a9b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580880768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.2580880768
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2166397554
Short name T368
Test name
Test status
Simulation time 25032581408 ps
CPU time 8.3 seconds
Started Mar 17 03:16:46 PM PDT 24
Finished Mar 17 03:16:54 PM PDT 24
Peak memory 216088 kb
Host smart-f4e4117f-f671-4ca0-a76c-413e35124291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166397554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2166397554
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.407419888
Short name T1860
Test name
Test status
Simulation time 7623235321 ps
CPU time 40.21 seconds
Started Mar 17 01:32:06 PM PDT 24
Finished Mar 17 01:32:46 PM PDT 24
Peak memory 215992 kb
Host smart-c9c83ccb-414a-44e4-b2dc-eb56509102b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407419888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.407419888
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.1110609022
Short name T809
Test name
Test status
Simulation time 5759176654 ps
CPU time 9.01 seconds
Started Mar 17 01:31:59 PM PDT 24
Finished Mar 17 01:32:08 PM PDT 24
Peak memory 215912 kb
Host smart-f834a6ff-95fb-41b7-be6f-bf9d4d17831c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110609022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.1110609022
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2325906379
Short name T1789
Test name
Test status
Simulation time 10700583771 ps
CPU time 26.18 seconds
Started Mar 17 03:16:46 PM PDT 24
Finished Mar 17 03:17:12 PM PDT 24
Peak memory 216128 kb
Host smart-ed3b09dd-62de-4955-8fbb-fe9c4665d219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325906379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2325906379
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.3658392139
Short name T646
Test name
Test status
Simulation time 28475166 ps
CPU time 1.01 seconds
Started Mar 17 01:32:07 PM PDT 24
Finished Mar 17 01:32:08 PM PDT 24
Peak memory 206216 kb
Host smart-a3c44bd4-1115-43ce-9f42-a8476c97512b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658392139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3658392139
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.549439175
Short name T1856
Test name
Test status
Simulation time 110000565 ps
CPU time 1 seconds
Started Mar 17 03:16:47 PM PDT 24
Finished Mar 17 03:16:48 PM PDT 24
Peak memory 206928 kb
Host smart-1e771e91-76f5-4be6-bf8e-5105a5ff90d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549439175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.549439175
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1393851915
Short name T1245
Test name
Test status
Simulation time 254813824 ps
CPU time 1.12 seconds
Started Mar 17 03:16:47 PM PDT 24
Finished Mar 17 03:16:49 PM PDT 24
Peak memory 206480 kb
Host smart-486f167d-19e7-4e17-bfe0-d1d5cb21d73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393851915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1393851915
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.909544550
Short name T819
Test name
Test status
Simulation time 1041723282 ps
CPU time 1.04 seconds
Started Mar 17 01:32:06 PM PDT 24
Finished Mar 17 01:32:08 PM PDT 24
Peak memory 206228 kb
Host smart-b686e66c-a5cc-4f1f-814b-d2ca4b869927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909544550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.909544550
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1985860702
Short name T1252
Test name
Test status
Simulation time 10719403395 ps
CPU time 15.05 seconds
Started Mar 17 01:32:05 PM PDT 24
Finished Mar 17 01:32:20 PM PDT 24
Peak memory 218492 kb
Host smart-aa4bf49e-d252-4b25-a60f-7392f815eb8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985860702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1985860702
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_upload.3251365184
Short name T913
Test name
Test status
Simulation time 5820999608 ps
CPU time 6.46 seconds
Started Mar 17 03:16:45 PM PDT 24
Finished Mar 17 03:16:51 PM PDT 24
Peak memory 218396 kb
Host smart-0d3fd64e-4bd5-4fef-ae70-379ef6bb3c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251365184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3251365184
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2281578131
Short name T51
Test name
Test status
Simulation time 56373004 ps
CPU time 0.74 seconds
Started Mar 17 01:32:29 PM PDT 24
Finished Mar 17 01:32:30 PM PDT 24
Peak memory 204752 kb
Host smart-7ebf0765-982f-4b1b-8e52-3b8c337e0cbe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281578131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2281578131
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3297545065
Short name T1367
Test name
Test status
Simulation time 32418242 ps
CPU time 0.72 seconds
Started Mar 17 03:16:56 PM PDT 24
Finished Mar 17 03:16:57 PM PDT 24
Peak memory 205316 kb
Host smart-bb883888-34ad-4deb-9e24-e35bcfb592c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297545065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3297545065
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1556810894
Short name T792
Test name
Test status
Simulation time 2091497068 ps
CPU time 5.87 seconds
Started Mar 17 03:16:54 PM PDT 24
Finished Mar 17 03:17:00 PM PDT 24
Peak memory 233632 kb
Host smart-68317dc5-5c2c-486d-a3c5-f07621f7480f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556810894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1556810894
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.4119542993
Short name T558
Test name
Test status
Simulation time 240154742 ps
CPU time 3.44 seconds
Started Mar 17 01:32:29 PM PDT 24
Finished Mar 17 01:32:33 PM PDT 24
Peak memory 232800 kb
Host smart-59292595-2267-47db-b5fb-3a0111d5bc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119542993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.4119542993
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3198969655
Short name T557
Test name
Test status
Simulation time 29135930 ps
CPU time 0.76 seconds
Started Mar 17 01:32:11 PM PDT 24
Finished Mar 17 01:32:12 PM PDT 24
Peak memory 205312 kb
Host smart-9df79fcf-8966-4e45-8f75-2e99a2aea142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198969655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3198969655
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.3251819259
Short name T312
Test name
Test status
Simulation time 14614285 ps
CPU time 0.75 seconds
Started Mar 17 03:16:51 PM PDT 24
Finished Mar 17 03:16:52 PM PDT 24
Peak memory 205484 kb
Host smart-2298617e-dfd8-4597-af9d-d390459b963a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251819259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3251819259
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4009789292
Short name T835
Test name
Test status
Simulation time 10427150581 ps
CPU time 25 seconds
Started Mar 17 01:32:18 PM PDT 24
Finished Mar 17 01:32:43 PM PDT 24
Peak memory 250628 kb
Host smart-b6a4d97a-26c3-4a03-92b7-705b17fe4e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009789292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4009789292
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.531809121
Short name T1050
Test name
Test status
Simulation time 4461804171 ps
CPU time 53.05 seconds
Started Mar 17 03:16:53 PM PDT 24
Finished Mar 17 03:17:46 PM PDT 24
Peak memory 252744 kb
Host smart-c1acbfde-458b-4c46-b069-4364f996a099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531809121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.531809121
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.1778385355
Short name T502
Test name
Test status
Simulation time 8665038520 ps
CPU time 52.67 seconds
Started Mar 17 01:32:11 PM PDT 24
Finished Mar 17 01:33:04 PM PDT 24
Peak memory 222960 kb
Host smart-a9d25e3d-17d8-4e55-a6a3-d0ace165a3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778385355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.1778385355
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.827232486
Short name T121
Test name
Test status
Simulation time 25149080890 ps
CPU time 195.67 seconds
Started Mar 17 03:16:56 PM PDT 24
Finished Mar 17 03:20:12 PM PDT 24
Peak memory 249000 kb
Host smart-54d0b63a-96b9-402d-93d0-63f1a72efe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827232486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.827232486
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2601177612
Short name T834
Test name
Test status
Simulation time 70083116346 ps
CPU time 143.73 seconds
Started Mar 17 03:16:54 PM PDT 24
Finished Mar 17 03:19:18 PM PDT 24
Peak memory 256784 kb
Host smart-e085eaaf-d4c4-413a-bbca-e6bc7aa3afb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601177612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2601177612
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.67488954
Short name T400
Test name
Test status
Simulation time 68575302874 ps
CPU time 99.56 seconds
Started Mar 17 01:32:29 PM PDT 24
Finished Mar 17 01:34:09 PM PDT 24
Peak memory 236056 kb
Host smart-7cf25eb2-eed3-433f-ad9c-9b2146c0428b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67488954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.67488954
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.23190709
Short name T1284
Test name
Test status
Simulation time 35161170936 ps
CPU time 26.33 seconds
Started Mar 17 03:16:56 PM PDT 24
Finished Mar 17 03:17:23 PM PDT 24
Peak memory 238244 kb
Host smart-0f96ebfb-6332-40b2-abe9-eb191ce36e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23190709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.23190709
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.844084176
Short name T1451
Test name
Test status
Simulation time 5054869207 ps
CPU time 27 seconds
Started Mar 17 01:32:29 PM PDT 24
Finished Mar 17 01:32:56 PM PDT 24
Peak memory 233292 kb
Host smart-29b4cc5b-b4b1-4588-829a-5f6f2d2fdf8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844084176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.844084176
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2257056246
Short name T147
Test name
Test status
Simulation time 725953213 ps
CPU time 5.23 seconds
Started Mar 17 03:16:52 PM PDT 24
Finished Mar 17 03:16:57 PM PDT 24
Peak memory 233728 kb
Host smart-7a342967-b1b7-408e-b5d4-adbe4e07b098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257056246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2257056246
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_intercept.2953935269
Short name T1265
Test name
Test status
Simulation time 3143657789 ps
CPU time 5.11 seconds
Started Mar 17 01:32:29 PM PDT 24
Finished Mar 17 01:32:34 PM PDT 24
Peak memory 235796 kb
Host smart-1b332726-6665-4198-b358-29fbc705afb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953935269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.2953935269
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2562328078
Short name T381
Test name
Test status
Simulation time 2106421051 ps
CPU time 11.33 seconds
Started Mar 17 03:16:52 PM PDT 24
Finished Mar 17 03:17:03 PM PDT 24
Peak memory 232024 kb
Host smart-8d94e79e-acb6-454f-80d0-d8fd522bf1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2562328078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2562328078
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3039773753
Short name T1262
Test name
Test status
Simulation time 11729608372 ps
CPU time 40.74 seconds
Started Mar 17 01:32:29 PM PDT 24
Finished Mar 17 01:33:10 PM PDT 24
Peak memory 248604 kb
Host smart-a9fcf13e-1ef4-44c5-b31f-f0c52003f8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039773753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3039773753
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.3384292274
Short name T1020
Test name
Test status
Simulation time 12072945723 ps
CPU time 7.46 seconds
Started Mar 17 01:32:13 PM PDT 24
Finished Mar 17 01:32:21 PM PDT 24
Peak memory 232628 kb
Host smart-8e0d6a3e-99a6-481f-a4b8-bf09b56c5d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384292274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.3384292274
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.813123948
Short name T1364
Test name
Test status
Simulation time 1428240153 ps
CPU time 3.69 seconds
Started Mar 17 03:16:51 PM PDT 24
Finished Mar 17 03:16:55 PM PDT 24
Peak memory 216616 kb
Host smart-c8b860b6-a629-4606-b872-12dd06c004e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813123948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.813123948
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.266521695
Short name T742
Test name
Test status
Simulation time 12693569357 ps
CPU time 10.06 seconds
Started Mar 17 03:16:50 PM PDT 24
Finished Mar 17 03:17:00 PM PDT 24
Peak memory 218604 kb
Host smart-73366640-7e1b-4bfd-b568-9a6d26e1c16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266521695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.266521695
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.767086131
Short name T1552
Test name
Test status
Simulation time 23735188586 ps
CPU time 16.32 seconds
Started Mar 17 01:32:16 PM PDT 24
Finished Mar 17 01:32:33 PM PDT 24
Peak memory 232344 kb
Host smart-849a7c62-c378-480d-a60f-8a23465e1bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767086131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.767086131
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1138722977
Short name T872
Test name
Test status
Simulation time 1521070046 ps
CPU time 3.4 seconds
Started Mar 17 01:32:11 PM PDT 24
Finished Mar 17 01:32:15 PM PDT 24
Peak memory 222360 kb
Host smart-43795ab6-076a-4093-ab5f-54b827a6e1b2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1138722977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1138722977
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.1788860756
Short name T127
Test name
Test status
Simulation time 498008111 ps
CPU time 4.05 seconds
Started Mar 17 03:16:51 PM PDT 24
Finished Mar 17 03:16:55 PM PDT 24
Peak memory 219628 kb
Host smart-f4382432-9d70-4439-9072-06564758f0e0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1788860756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.1788860756
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.405654964
Short name T1229
Test name
Test status
Simulation time 35964813134 ps
CPU time 207.46 seconds
Started Mar 17 01:32:10 PM PDT 24
Finished Mar 17 01:35:38 PM PDT 24
Peak memory 255992 kb
Host smart-ecc225fa-9ee5-473e-b2b2-2a8cd1dc0f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405654964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.405654964
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.889075182
Short name T1598
Test name
Test status
Simulation time 497510473 ps
CPU time 1.1 seconds
Started Mar 17 03:17:01 PM PDT 24
Finished Mar 17 03:17:02 PM PDT 24
Peak memory 206928 kb
Host smart-def60ec7-8f48-4603-8153-bdbdd99fe6dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889075182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.889075182
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2712765063
Short name T373
Test name
Test status
Simulation time 10572859150 ps
CPU time 50.8 seconds
Started Mar 17 03:16:54 PM PDT 24
Finished Mar 17 03:17:45 PM PDT 24
Peak memory 216152 kb
Host smart-9b0ff5e6-108c-4cdb-82cc-13a3ab21b938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712765063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2712765063
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.3520410915
Short name T401
Test name
Test status
Simulation time 2346715923 ps
CPU time 31.73 seconds
Started Mar 17 01:32:12 PM PDT 24
Finished Mar 17 01:32:44 PM PDT 24
Peak memory 215940 kb
Host smart-b1ef7e68-96f0-4d3f-adde-3e7f33897521
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520410915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.3520410915
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3295542999
Short name T561
Test name
Test status
Simulation time 3263490414 ps
CPU time 7.94 seconds
Started Mar 17 01:32:12 PM PDT 24
Finished Mar 17 01:32:20 PM PDT 24
Peak memory 215868 kb
Host smart-5123386b-ba51-48f9-a61b-005633771ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295542999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3295542999
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.477881942
Short name T399
Test name
Test status
Simulation time 8864392576 ps
CPU time 16.04 seconds
Started Mar 17 03:16:53 PM PDT 24
Finished Mar 17 03:17:09 PM PDT 24
Peak memory 216100 kb
Host smart-abfd4cc9-7200-4176-8218-11a8feca5033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477881942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.477881942
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.2417970355
Short name T338
Test name
Test status
Simulation time 71397291 ps
CPU time 1.46 seconds
Started Mar 17 03:16:52 PM PDT 24
Finished Mar 17 03:16:53 PM PDT 24
Peak memory 216136 kb
Host smart-6f0aa483-5930-4f7d-a6f4-8dd3530dc585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417970355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.2417970355
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3780504336
Short name T1420
Test name
Test status
Simulation time 533867214 ps
CPU time 4.93 seconds
Started Mar 17 01:32:10 PM PDT 24
Finished Mar 17 01:32:15 PM PDT 24
Peak memory 215952 kb
Host smart-a8eea17d-1f1b-4161-a16a-1f8af52811cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3780504336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3780504336
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.1515767407
Short name T83
Test name
Test status
Simulation time 66288621 ps
CPU time 0.89 seconds
Started Mar 17 01:32:10 PM PDT 24
Finished Mar 17 01:32:11 PM PDT 24
Peak memory 205164 kb
Host smart-b2355d5d-de25-4c7e-8911-8a8a5bf02d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515767407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1515767407
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.38428626
Short name T1163
Test name
Test status
Simulation time 43776711 ps
CPU time 0.92 seconds
Started Mar 17 03:16:54 PM PDT 24
Finished Mar 17 03:16:55 PM PDT 24
Peak memory 205664 kb
Host smart-e552adb5-4747-414d-9276-6425909d37e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=38428626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.38428626
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.3422070452
Short name T1718
Test name
Test status
Simulation time 22772814247 ps
CPU time 18.78 seconds
Started Mar 17 03:16:56 PM PDT 24
Finished Mar 17 03:17:15 PM PDT 24
Peak memory 234928 kb
Host smart-38799f15-ab7f-4df5-b55d-6ff69a7c5938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422070452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.3422070452
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_upload.390088271
Short name T1274
Test name
Test status
Simulation time 54853954850 ps
CPU time 32.8 seconds
Started Mar 17 01:32:13 PM PDT 24
Finished Mar 17 01:32:46 PM PDT 24
Peak memory 246736 kb
Host smart-bf9d6a60-62e4-4265-b629-4705c11a1d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390088271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.390088271
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1466611649
Short name T505
Test name
Test status
Simulation time 14385950 ps
CPU time 0.75 seconds
Started Mar 17 03:17:01 PM PDT 24
Finished Mar 17 03:17:02 PM PDT 24
Peak memory 205040 kb
Host smart-263a40f9-1b0c-413d-ba0f-e40dd8220838
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466611649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1466611649
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1691265209
Short name T1023
Test name
Test status
Simulation time 12914700 ps
CPU time 0.73 seconds
Started Mar 17 01:32:16 PM PDT 24
Finished Mar 17 01:32:17 PM PDT 24
Peak memory 204776 kb
Host smart-e597445c-3160-4e72-a4c4-0cbecf74bb50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691265209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1691265209
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.117373821
Short name T648
Test name
Test status
Simulation time 2629142802 ps
CPU time 5.53 seconds
Started Mar 17 01:32:16 PM PDT 24
Finished Mar 17 01:32:22 PM PDT 24
Peak memory 219528 kb
Host smart-cf8a89a5-8e31-4bba-b2dd-84f22aec22b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117373821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.117373821
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.3481099014
Short name T1604
Test name
Test status
Simulation time 1488458704 ps
CPU time 4.76 seconds
Started Mar 17 03:16:58 PM PDT 24
Finished Mar 17 03:17:03 PM PDT 24
Peak memory 238448 kb
Host smart-41b1ffcd-473f-435c-a900-860e5d3da67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481099014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3481099014
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2618361826
Short name T340
Test name
Test status
Simulation time 36858385 ps
CPU time 0.74 seconds
Started Mar 17 03:16:56 PM PDT 24
Finished Mar 17 03:16:57 PM PDT 24
Peak memory 205484 kb
Host smart-8d352f19-3053-42c6-9bfd-1d9e26bc7878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618361826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2618361826
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3605520537
Short name T1834
Test name
Test status
Simulation time 15208113 ps
CPU time 0.76 seconds
Started Mar 17 01:32:12 PM PDT 24
Finished Mar 17 01:32:13 PM PDT 24
Peak memory 204952 kb
Host smart-232b47f6-7dcf-446d-9cbf-e4a10ea7211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605520537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3605520537
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.2795940406
Short name T1314
Test name
Test status
Simulation time 4498084895 ps
CPU time 71.73 seconds
Started Mar 17 03:17:00 PM PDT 24
Finished Mar 17 03:18:11 PM PDT 24
Peak memory 249140 kb
Host smart-330ef669-2073-4583-a528-c9b3e025f643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795940406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.2795940406
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3802397764
Short name T672
Test name
Test status
Simulation time 19398609168 ps
CPU time 60.57 seconds
Started Mar 17 01:32:16 PM PDT 24
Finished Mar 17 01:33:17 PM PDT 24
Peak memory 256400 kb
Host smart-df730f50-1526-49d7-aa0d-46ded0380310
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3802397764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3802397764
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3183572446
Short name T1570
Test name
Test status
Simulation time 3512018707 ps
CPU time 46.31 seconds
Started Mar 17 03:16:58 PM PDT 24
Finished Mar 17 03:17:45 PM PDT 24
Peak memory 254572 kb
Host smart-09114817-d1a1-4b51-b204-f82e46644198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183572446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3183572446
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.367740607
Short name T578
Test name
Test status
Simulation time 34760336133 ps
CPU time 261.9 seconds
Started Mar 17 01:32:17 PM PDT 24
Finished Mar 17 01:36:39 PM PDT 24
Peak memory 253568 kb
Host smart-33e60214-1db3-4874-a907-c57f0e5da566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367740607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.367740607
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3169860312
Short name T1327
Test name
Test status
Simulation time 109744595789 ps
CPU time 706.67 seconds
Started Mar 17 01:32:16 PM PDT 24
Finished Mar 17 01:44:03 PM PDT 24
Peak memory 267496 kb
Host smart-d0387b10-cbe6-4d84-8f3d-db9ec85034a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169860312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3169860312
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.3635565113
Short name T1143
Test name
Test status
Simulation time 47070609948 ps
CPU time 162.65 seconds
Started Mar 17 03:16:58 PM PDT 24
Finished Mar 17 03:19:41 PM PDT 24
Peak memory 256572 kb
Host smart-f03e22d5-170b-4dc9-804c-e18cf5c053a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635565113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.3635565113
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1166530143
Short name T693
Test name
Test status
Simulation time 5357820489 ps
CPU time 27.33 seconds
Started Mar 17 01:32:18 PM PDT 24
Finished Mar 17 01:32:46 PM PDT 24
Peak memory 231940 kb
Host smart-7aaf7129-26bb-4ca3-b45d-4d82ebdd6f03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166530143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1166530143
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3090144041
Short name T1670
Test name
Test status
Simulation time 337958170 ps
CPU time 5.13 seconds
Started Mar 17 03:16:58 PM PDT 24
Finished Mar 17 03:17:03 PM PDT 24
Peak memory 233308 kb
Host smart-973b72d3-4d67-4120-b120-cb94cde86ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090144041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3090144041
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_intercept.449186292
Short name T1302
Test name
Test status
Simulation time 1523430945 ps
CPU time 7.22 seconds
Started Mar 17 03:16:58 PM PDT 24
Finished Mar 17 03:17:06 PM PDT 24
Peak memory 234228 kb
Host smart-63c42b67-b84f-4082-82b5-ba3186c68e9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449186292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.449186292
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_intercept.711525016
Short name T1447
Test name
Test status
Simulation time 463093548 ps
CPU time 5.29 seconds
Started Mar 17 01:32:15 PM PDT 24
Finished Mar 17 01:32:21 PM PDT 24
Peak memory 232724 kb
Host smart-e28b16ed-2e28-46c2-a572-38bd48ff995f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=711525016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.711525016
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1485035545
Short name T813
Test name
Test status
Simulation time 21767104104 ps
CPU time 23.66 seconds
Started Mar 17 01:32:17 PM PDT 24
Finished Mar 17 01:32:41 PM PDT 24
Peak memory 231548 kb
Host smart-e8a76210-8544-481a-a360-83bf8780e74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485035545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1485035545
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.817256130
Short name T1896
Test name
Test status
Simulation time 2145819200 ps
CPU time 16.48 seconds
Started Mar 17 03:16:56 PM PDT 24
Finished Mar 17 03:17:13 PM PDT 24
Peak memory 227020 kb
Host smart-9446ecc4-16e9-41d0-9164-1435ce07b8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817256130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.817256130
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.290574185
Short name T438
Test name
Test status
Simulation time 1318654107 ps
CPU time 4.48 seconds
Started Mar 17 03:17:01 PM PDT 24
Finished Mar 17 03:17:05 PM PDT 24
Peak memory 233348 kb
Host smart-216d8e9e-9371-4d84-bfd8-e7f5044700ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290574185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap
.290574185
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3387652301
Short name T475
Test name
Test status
Simulation time 1894893648 ps
CPU time 8.36 seconds
Started Mar 17 01:32:17 PM PDT 24
Finished Mar 17 01:32:26 PM PDT 24
Peak memory 248992 kb
Host smart-9ff74bbe-e0db-48d8-8b42-f379dd1d6099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387652301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3387652301
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1209132510
Short name T640
Test name
Test status
Simulation time 7977275925 ps
CPU time 22.92 seconds
Started Mar 17 03:16:56 PM PDT 24
Finished Mar 17 03:17:19 PM PDT 24
Peak memory 236956 kb
Host smart-47e798e5-decc-4e8a-a425-18fb88514902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209132510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1209132510
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1930654226
Short name T1713
Test name
Test status
Simulation time 10606496396 ps
CPU time 27.74 seconds
Started Mar 17 01:32:15 PM PDT 24
Finished Mar 17 01:32:43 PM PDT 24
Peak memory 233084 kb
Host smart-6966134e-37a2-494b-a79c-16723214ce54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930654226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1930654226
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.1376782620
Short name T1403
Test name
Test status
Simulation time 994499618 ps
CPU time 5.66 seconds
Started Mar 17 03:16:56 PM PDT 24
Finished Mar 17 03:17:01 PM PDT 24
Peak memory 221620 kb
Host smart-1bb4ebb6-6e9c-45b1-9bb9-17639e15d90d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1376782620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.1376782620
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3705832276
Short name T1
Test name
Test status
Simulation time 7915367316 ps
CPU time 6.92 seconds
Started Mar 17 01:32:16 PM PDT 24
Finished Mar 17 01:32:23 PM PDT 24
Peak memory 222364 kb
Host smart-35f93b0d-fe02-45b6-b421-519f41cc1669
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3705832276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3705832276
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1675840636
Short name T817
Test name
Test status
Simulation time 27275867361 ps
CPU time 149.72 seconds
Started Mar 17 01:32:16 PM PDT 24
Finished Mar 17 01:34:46 PM PDT 24
Peak memory 248636 kb
Host smart-85030c86-9a7a-4468-9596-64ff3c0391ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675840636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1675840636
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2563082098
Short name T28
Test name
Test status
Simulation time 60492212376 ps
CPU time 231.41 seconds
Started Mar 17 03:17:00 PM PDT 24
Finished Mar 17 03:20:51 PM PDT 24
Peak memory 265364 kb
Host smart-470c798a-858c-4d48-9ca1-0b3c88c80e64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563082098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2563082098
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2081833967
Short name T1027
Test name
Test status
Simulation time 4176075547 ps
CPU time 21.95 seconds
Started Mar 17 01:32:13 PM PDT 24
Finished Mar 17 01:32:35 PM PDT 24
Peak memory 215844 kb
Host smart-9311c577-aaf7-4f1b-8461-55b8fb81f961
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081833967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2081833967
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.4265882583
Short name T353
Test name
Test status
Simulation time 11435111937 ps
CPU time 55.09 seconds
Started Mar 17 03:16:57 PM PDT 24
Finished Mar 17 03:17:52 PM PDT 24
Peak memory 216128 kb
Host smart-40ee10c7-390a-4674-8eb0-f1dbe925b751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265882583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.4265882583
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3256739494
Short name T1231
Test name
Test status
Simulation time 719450601 ps
CPU time 4.71 seconds
Started Mar 17 03:16:56 PM PDT 24
Finished Mar 17 03:17:01 PM PDT 24
Peak memory 216096 kb
Host smart-4ad1ac1c-04e3-4137-835d-baada81bcd57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256739494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3256739494
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.4040487864
Short name T1152
Test name
Test status
Simulation time 9754043023 ps
CPU time 25.24 seconds
Started Mar 17 01:32:29 PM PDT 24
Finished Mar 17 01:32:55 PM PDT 24
Peak memory 215816 kb
Host smart-82c1ba47-cdca-41aa-8da0-c3e988676e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040487864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.4040487864
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1687976101
Short name T988
Test name
Test status
Simulation time 17734481 ps
CPU time 0.9 seconds
Started Mar 17 01:32:13 PM PDT 24
Finished Mar 17 01:32:14 PM PDT 24
Peak memory 206180 kb
Host smart-9480f730-51d2-424d-b190-99bc63410cec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687976101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1687976101
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2771119741
Short name T1248
Test name
Test status
Simulation time 113869398 ps
CPU time 1.83 seconds
Started Mar 17 03:17:01 PM PDT 24
Finished Mar 17 03:17:03 PM PDT 24
Peak memory 216120 kb
Host smart-10c6b011-fafb-4691-962e-b472316d714b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771119741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2771119741
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3203457165
Short name T1046
Test name
Test status
Simulation time 152575344 ps
CPU time 1.03 seconds
Started Mar 17 01:32:13 PM PDT 24
Finished Mar 17 01:32:14 PM PDT 24
Peak memory 205096 kb
Host smart-f00a21de-e56f-4534-8b79-02474bfa41e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203457165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3203457165
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.3386892215
Short name T419
Test name
Test status
Simulation time 395425828 ps
CPU time 0.99 seconds
Started Mar 17 03:16:59 PM PDT 24
Finished Mar 17 03:17:00 PM PDT 24
Peak memory 205416 kb
Host smart-ca03bccb-0819-4b59-9d7a-dbe6de1e9456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386892215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3386892215
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.414682518
Short name T210
Test name
Test status
Simulation time 2895775101 ps
CPU time 8.77 seconds
Started Mar 17 03:16:56 PM PDT 24
Finished Mar 17 03:17:05 PM PDT 24
Peak memory 248904 kb
Host smart-b73d6c73-7bd5-4925-b0c6-13d5e417b3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=414682518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.414682518
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_upload.991729487
Short name T1161
Test name
Test status
Simulation time 6296767478 ps
CPU time 11.16 seconds
Started Mar 17 01:32:17 PM PDT 24
Finished Mar 17 01:32:29 PM PDT 24
Peak memory 233872 kb
Host smart-fe8d1e8c-0cc4-4f53-9123-170b85aaafef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991729487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.991729487
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2455647303
Short name T1647
Test name
Test status
Simulation time 11100182 ps
CPU time 0.7 seconds
Started Mar 17 01:32:23 PM PDT 24
Finished Mar 17 01:32:24 PM PDT 24
Peak memory 204808 kb
Host smart-8a666136-a90b-488b-bc36-bf29fe9fa5ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455647303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2455647303
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.416471299
Short name T778
Test name
Test status
Simulation time 27254696 ps
CPU time 0.77 seconds
Started Mar 17 03:17:11 PM PDT 24
Finished Mar 17 03:17:12 PM PDT 24
Peak memory 204404 kb
Host smart-3f79c617-4664-4e1f-9574-4a7542a2645c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416471299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.416471299
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1931101282
Short name T1772
Test name
Test status
Simulation time 159894137 ps
CPU time 2.64 seconds
Started Mar 17 03:16:59 PM PDT 24
Finished Mar 17 03:17:02 PM PDT 24
Peak memory 218308 kb
Host smart-d619d4b6-bb9b-4bb6-a54e-7a47afe0d843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931101282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1931101282
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.675202717
Short name T229
Test name
Test status
Simulation time 381577658 ps
CPU time 2.63 seconds
Started Mar 17 01:32:23 PM PDT 24
Finished Mar 17 01:32:26 PM PDT 24
Peak memory 216212 kb
Host smart-761718c5-fb3f-4b02-8a16-ddc4b0624e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=675202717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.675202717
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3485990042
Short name T673
Test name
Test status
Simulation time 19221372 ps
CPU time 0.77 seconds
Started Mar 17 01:32:15 PM PDT 24
Finished Mar 17 01:32:16 PM PDT 24
Peak memory 204952 kb
Host smart-af4b1fcf-f631-4a21-8916-2cc91448e697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485990042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3485990042
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3924343390
Short name T1410
Test name
Test status
Simulation time 17259317 ps
CPU time 0.8 seconds
Started Mar 17 03:16:59 PM PDT 24
Finished Mar 17 03:17:00 PM PDT 24
Peak memory 206176 kb
Host smart-18ee59be-cc62-47f7-8e8a-e9aad72c6af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924343390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3924343390
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1985858706
Short name T1680
Test name
Test status
Simulation time 12233350090 ps
CPU time 56.56 seconds
Started Mar 17 03:17:02 PM PDT 24
Finished Mar 17 03:17:59 PM PDT 24
Peak memory 252436 kb
Host smart-8e40099a-5cb9-4eb1-9f04-21fb7f8c81fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985858706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1985858706
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2209722738
Short name T1218
Test name
Test status
Simulation time 247862695589 ps
CPU time 105.54 seconds
Started Mar 17 01:32:23 PM PDT 24
Finished Mar 17 01:34:09 PM PDT 24
Peak memory 238464 kb
Host smart-3e6f7e7c-fd6f-4255-bb4e-14cd038ca6f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2209722738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2209722738
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1514060932
Short name T1796
Test name
Test status
Simulation time 3944293915 ps
CPU time 61.04 seconds
Started Mar 17 01:32:26 PM PDT 24
Finished Mar 17 01:33:27 PM PDT 24
Peak memory 256624 kb
Host smart-e2438e61-6d92-419d-af74-894ce144ad27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514060932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1514060932
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.4199783717
Short name T1457
Test name
Test status
Simulation time 143089425351 ps
CPU time 937.02 seconds
Started Mar 17 03:17:09 PM PDT 24
Finished Mar 17 03:32:46 PM PDT 24
Peak memory 266508 kb
Host smart-c8c568d2-7589-4e87-9424-c4c727d5bbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199783717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.4199783717
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1528885087
Short name T1185
Test name
Test status
Simulation time 33058611324 ps
CPU time 206.38 seconds
Started Mar 17 01:32:22 PM PDT 24
Finished Mar 17 01:35:49 PM PDT 24
Peak memory 264280 kb
Host smart-1b38b3c7-a777-4620-bfd5-0d54e9253b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528885087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1528885087
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1634647165
Short name T1776
Test name
Test status
Simulation time 2838547896 ps
CPU time 47.44 seconds
Started Mar 17 03:17:10 PM PDT 24
Finished Mar 17 03:17:57 PM PDT 24
Peak memory 255732 kb
Host smart-0d28eec6-8a10-4fd3-80ca-a9eeba4ef08d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634647165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1634647165
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1257425597
Short name T699
Test name
Test status
Simulation time 26949954091 ps
CPU time 37.74 seconds
Started Mar 17 03:17:01 PM PDT 24
Finished Mar 17 03:17:38 PM PDT 24
Peak memory 239788 kb
Host smart-4e6aebea-0bab-4f37-b8e8-fd33b931917c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257425597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1257425597
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.3215659942
Short name T1343
Test name
Test status
Simulation time 1437921331 ps
CPU time 16.83 seconds
Started Mar 17 01:32:20 PM PDT 24
Finished Mar 17 01:32:37 PM PDT 24
Peak memory 234352 kb
Host smart-947f44ec-643e-4243-bb95-5cd18768b608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3215659942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.3215659942
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2831330691
Short name T542
Test name
Test status
Simulation time 4659742504 ps
CPU time 9.12 seconds
Started Mar 17 01:32:26 PM PDT 24
Finished Mar 17 01:32:35 PM PDT 24
Peak memory 233824 kb
Host smart-a2544476-d387-474a-9e26-efde29901c60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831330691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2831330691
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3232520902
Short name T985
Test name
Test status
Simulation time 6936226999 ps
CPU time 9.07 seconds
Started Mar 17 03:16:59 PM PDT 24
Finished Mar 17 03:17:08 PM PDT 24
Peak memory 233616 kb
Host smart-1212e5f8-362f-42d6-81d2-2b62e6bee6a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232520902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3232520902
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.1578495561
Short name T493
Test name
Test status
Simulation time 5537320892 ps
CPU time 5.88 seconds
Started Mar 17 01:32:23 PM PDT 24
Finished Mar 17 01:32:29 PM PDT 24
Peak memory 232316 kb
Host smart-67e35e50-a6f4-434a-9367-01374acc32d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578495561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.1578495561
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2801321795
Short name T547
Test name
Test status
Simulation time 6533379725 ps
CPU time 22.71 seconds
Started Mar 17 03:17:01 PM PDT 24
Finished Mar 17 03:17:24 PM PDT 24
Peak memory 240700 kb
Host smart-941fd74e-0d65-4a78-8bd3-aa3fe0d5df42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801321795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2801321795
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2934200054
Short name T13
Test name
Test status
Simulation time 1367812010 ps
CPU time 10.27 seconds
Started Mar 17 03:17:00 PM PDT 24
Finished Mar 17 03:17:11 PM PDT 24
Peak memory 240272 kb
Host smart-ce8c3a21-ac9c-4807-acc9-335919482296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934200054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2934200054
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.3120297508
Short name T31
Test name
Test status
Simulation time 5671705474 ps
CPU time 18.14 seconds
Started Mar 17 01:32:29 PM PDT 24
Finished Mar 17 01:32:47 PM PDT 24
Peak memory 251600 kb
Host smart-6b6795c2-6c1e-4f8e-b868-114faf464cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120297508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.3120297508
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.829260173
Short name T1695
Test name
Test status
Simulation time 619603853 ps
CPU time 2.89 seconds
Started Mar 17 01:32:26 PM PDT 24
Finished Mar 17 01:32:29 PM PDT 24
Peak memory 233416 kb
Host smart-cc91e9b6-34f7-450d-8f4e-bdc28d58025d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829260173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.829260173
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.836607124
Short name T1128
Test name
Test status
Simulation time 8905110773 ps
CPU time 15.04 seconds
Started Mar 17 03:17:00 PM PDT 24
Finished Mar 17 03:17:15 PM PDT 24
Peak memory 234148 kb
Host smart-d2c3e15b-9f12-4e37-bba9-005644ff8858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836607124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.836607124
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1597370375
Short name T1061
Test name
Test status
Simulation time 2711303535 ps
CPU time 4.15 seconds
Started Mar 17 03:16:58 PM PDT 24
Finished Mar 17 03:17:02 PM PDT 24
Peak memory 218620 kb
Host smart-c7eac010-1e28-42bf-acb1-601ed7c32a46
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1597370375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1597370375
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1788203442
Short name T847
Test name
Test status
Simulation time 1109441612 ps
CPU time 4.32 seconds
Started Mar 17 01:32:23 PM PDT 24
Finished Mar 17 01:32:27 PM PDT 24
Peak memory 218220 kb
Host smart-ddf2ebce-7baa-4359-bb3c-53e1b7be9262
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1788203442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1788203442
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.17181689
Short name T1649
Test name
Test status
Simulation time 4532708154 ps
CPU time 70.05 seconds
Started Mar 17 03:17:09 PM PDT 24
Finished Mar 17 03:18:19 PM PDT 24
Peak memory 262304 kb
Host smart-5c6a8ceb-a06b-44ab-bfcc-4000c67078a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17181689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress
_all.17181689
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1545038523
Short name T808
Test name
Test status
Simulation time 1600387098 ps
CPU time 25.28 seconds
Started Mar 17 03:17:02 PM PDT 24
Finished Mar 17 03:17:27 PM PDT 24
Peak memory 216300 kb
Host smart-d13a67fb-828f-49ca-be0c-99bf8c6d6415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545038523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1545038523
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1906742427
Short name T1096
Test name
Test status
Simulation time 3181922980 ps
CPU time 43.86 seconds
Started Mar 17 01:32:15 PM PDT 24
Finished Mar 17 01:32:59 PM PDT 24
Peak memory 215888 kb
Host smart-bce5c77a-4be2-4997-827e-db3c36f92ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906742427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1906742427
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2047984500
Short name T650
Test name
Test status
Simulation time 4254517950 ps
CPU time 7.4 seconds
Started Mar 17 03:17:01 PM PDT 24
Finished Mar 17 03:17:08 PM PDT 24
Peak memory 216096 kb
Host smart-6cc1854f-9897-440d-b89a-b5e865ea6a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047984500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2047984500
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.552235844
Short name T1077
Test name
Test status
Simulation time 275641718 ps
CPU time 2.15 seconds
Started Mar 17 01:32:17 PM PDT 24
Finished Mar 17 01:32:19 PM PDT 24
Peak memory 207516 kb
Host smart-f5d2f3c5-e3ee-44d5-a6ea-265cfce31180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=552235844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.552235844
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1614645132
Short name T1541
Test name
Test status
Simulation time 176342422 ps
CPU time 2.22 seconds
Started Mar 17 01:32:21 PM PDT 24
Finished Mar 17 01:32:24 PM PDT 24
Peak memory 215920 kb
Host smart-fac30b1f-3a3f-4865-85ff-ac1111032111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614645132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1614645132
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.4022466564
Short name T803
Test name
Test status
Simulation time 99743344 ps
CPU time 1.13 seconds
Started Mar 17 03:17:00 PM PDT 24
Finished Mar 17 03:17:01 PM PDT 24
Peak memory 207016 kb
Host smart-383a9876-a1ae-458c-aba5-da3912e522cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022466564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.4022466564
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3196290758
Short name T764
Test name
Test status
Simulation time 26506540 ps
CPU time 0.81 seconds
Started Mar 17 01:32:16 PM PDT 24
Finished Mar 17 01:32:17 PM PDT 24
Peak memory 205160 kb
Host smart-35a94d7f-8273-4c80-85e2-3edbe3428919
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196290758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3196290758
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3724294702
Short name T1428
Test name
Test status
Simulation time 212841670 ps
CPU time 0.93 seconds
Started Mar 17 03:17:01 PM PDT 24
Finished Mar 17 03:17:02 PM PDT 24
Peak memory 206452 kb
Host smart-81a68877-e6e1-459b-810c-c3e3c36c3beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724294702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3724294702
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.2621444157
Short name T993
Test name
Test status
Simulation time 35712138135 ps
CPU time 34.98 seconds
Started Mar 17 01:32:21 PM PDT 24
Finished Mar 17 01:32:57 PM PDT 24
Peak memory 228612 kb
Host smart-39f7e78b-ca5d-4718-a1b4-158cd0803079
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621444157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.2621444157
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_upload.3888812230
Short name T1223
Test name
Test status
Simulation time 10002101735 ps
CPU time 19.94 seconds
Started Mar 17 03:17:00 PM PDT 24
Finished Mar 17 03:17:20 PM PDT 24
Peak memory 233784 kb
Host smart-68a14fb0-494d-4ca1-b635-bb408e8f1b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888812230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3888812230
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1622794300
Short name T415
Test name
Test status
Simulation time 11780459 ps
CPU time 0.69 seconds
Started Mar 17 03:17:12 PM PDT 24
Finished Mar 17 03:17:13 PM PDT 24
Peak memory 205024 kb
Host smart-b502d465-29a8-44e9-9cf1-3f476992c74b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622794300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1622794300
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2820912067
Short name T642
Test name
Test status
Simulation time 22130118 ps
CPU time 0.72 seconds
Started Mar 17 01:32:27 PM PDT 24
Finished Mar 17 01:32:28 PM PDT 24
Peak memory 204260 kb
Host smart-f02593a7-8fb8-4a2d-aa02-2e3e43243c8f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820912067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2820912067
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1152327311
Short name T339
Test name
Test status
Simulation time 652739184 ps
CPU time 4.42 seconds
Started Mar 17 01:32:28 PM PDT 24
Finished Mar 17 01:32:33 PM PDT 24
Peak memory 237292 kb
Host smart-700bb7a0-1eb9-43e9-9df2-837544014059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152327311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1152327311
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.438288530
Short name T1542
Test name
Test status
Simulation time 3599397766 ps
CPU time 4.3 seconds
Started Mar 17 03:17:09 PM PDT 24
Finished Mar 17 03:17:14 PM PDT 24
Peak memory 234228 kb
Host smart-d341ccc2-8175-4878-ae3a-dda1f1dc9975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438288530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.438288530
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2331566419
Short name T1623
Test name
Test status
Simulation time 28043830 ps
CPU time 0.76 seconds
Started Mar 17 03:17:10 PM PDT 24
Finished Mar 17 03:17:12 PM PDT 24
Peak memory 205136 kb
Host smart-512278eb-5a42-49a1-86a7-749a9c90cbcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331566419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2331566419
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3590450341
Short name T1817
Test name
Test status
Simulation time 17156919 ps
CPU time 0.76 seconds
Started Mar 17 01:32:27 PM PDT 24
Finished Mar 17 01:32:28 PM PDT 24
Peak memory 206312 kb
Host smart-e2f327ff-81c0-4e09-ab7f-09394e19c49a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590450341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3590450341
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1067088906
Short name T27
Test name
Test status
Simulation time 9549632470 ps
CPU time 25.4 seconds
Started Mar 17 01:32:27 PM PDT 24
Finished Mar 17 01:32:53 PM PDT 24
Peak memory 250028 kb
Host smart-dd1a3523-930a-492f-a8c8-9f826baf166d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067088906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1067088906
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2565666233
Short name T181
Test name
Test status
Simulation time 126686756309 ps
CPU time 180.47 seconds
Started Mar 17 03:17:09 PM PDT 24
Finished Mar 17 03:20:10 PM PDT 24
Peak memory 256240 kb
Host smart-f7ee8a5f-0b06-44f5-905d-df39257060d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565666233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2565666233
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1596903158
Short name T211
Test name
Test status
Simulation time 41168825833 ps
CPU time 250.96 seconds
Started Mar 17 03:17:13 PM PDT 24
Finished Mar 17 03:21:25 PM PDT 24
Peak memory 265404 kb
Host smart-37e97df7-cfa3-43b7-ad5b-e13e957b60e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596903158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1596903158
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3524596902
Short name T517
Test name
Test status
Simulation time 45026156438 ps
CPU time 280.73 seconds
Started Mar 17 01:32:30 PM PDT 24
Finished Mar 17 01:37:11 PM PDT 24
Peak memory 263456 kb
Host smart-a774898c-c190-42d5-b892-6f34c5d6a085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524596902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3524596902
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1685218069
Short name T564
Test name
Test status
Simulation time 227232808556 ps
CPU time 331.55 seconds
Started Mar 17 01:32:30 PM PDT 24
Finished Mar 17 01:38:02 PM PDT 24
Peak memory 257032 kb
Host smart-3b230f56-47f9-4bdb-a664-5e32487c218e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685218069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1685218069
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.1425996064
Short name T1013
Test name
Test status
Simulation time 3155997643 ps
CPU time 21.41 seconds
Started Mar 17 03:17:13 PM PDT 24
Finished Mar 17 03:17:35 PM PDT 24
Peak memory 250988 kb
Host smart-a76e551b-7cd9-4a7a-8494-feee0822c1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425996064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.1425996064
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2329750458
Short name T499
Test name
Test status
Simulation time 3707157769 ps
CPU time 12.07 seconds
Started Mar 17 01:32:30 PM PDT 24
Finished Mar 17 01:32:42 PM PDT 24
Peak memory 236812 kb
Host smart-cb3c978b-988f-4b94-b34e-9ac7f1732821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329750458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2329750458
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_intercept.559600831
Short name T422
Test name
Test status
Simulation time 312930475 ps
CPU time 4.45 seconds
Started Mar 17 03:17:11 PM PDT 24
Finished Mar 17 03:17:16 PM PDT 24
Peak memory 234148 kb
Host smart-4a1e2921-d8ee-43cd-8901-c896c9903edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559600831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.559600831
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_intercept.584002436
Short name T1190
Test name
Test status
Simulation time 476072300 ps
CPU time 5.93 seconds
Started Mar 17 01:32:23 PM PDT 24
Finished Mar 17 01:32:29 PM PDT 24
Peak memory 218076 kb
Host smart-349eb902-6a2d-4aa7-b4d5-f6e2cab3c25a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584002436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.584002436
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3148163083
Short name T1126
Test name
Test status
Simulation time 547528032 ps
CPU time 4.5 seconds
Started Mar 17 01:32:30 PM PDT 24
Finished Mar 17 01:32:34 PM PDT 24
Peak memory 223992 kb
Host smart-0ee2dcc7-8db3-4cf7-8705-bcd975160271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148163083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3148163083
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3493703409
Short name T600
Test name
Test status
Simulation time 212744572 ps
CPU time 5.58 seconds
Started Mar 17 03:17:10 PM PDT 24
Finished Mar 17 03:17:16 PM PDT 24
Peak memory 224236 kb
Host smart-24fad624-8875-4f5b-a56b-369ad558661f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493703409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3493703409
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2148826512
Short name T862
Test name
Test status
Simulation time 8728541389 ps
CPU time 26.75 seconds
Started Mar 17 01:32:29 PM PDT 24
Finished Mar 17 01:32:56 PM PDT 24
Peak memory 232212 kb
Host smart-0162fd42-accc-45d5-a8eb-debfb0ffeea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148826512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2148826512
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.861426346
Short name T248
Test name
Test status
Simulation time 1271853886 ps
CPU time 6.46 seconds
Started Mar 17 03:17:10 PM PDT 24
Finished Mar 17 03:17:16 PM PDT 24
Peak memory 221128 kb
Host smart-51b05983-96f2-4c18-9502-ed184fa75f1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861426346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap
.861426346
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.1695676315
Short name T621
Test name
Test status
Simulation time 2314705991 ps
CPU time 6.04 seconds
Started Mar 17 01:32:22 PM PDT 24
Finished Mar 17 01:32:29 PM PDT 24
Peak memory 240468 kb
Host smart-af00ce5d-95bd-4f5e-8439-da9eabd773c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695676315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.1695676315
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.435050781
Short name T307
Test name
Test status
Simulation time 2297427662 ps
CPU time 3.06 seconds
Started Mar 17 03:17:09 PM PDT 24
Finished Mar 17 03:17:12 PM PDT 24
Peak memory 232588 kb
Host smart-81e3255e-fd85-4e25-b041-49b7c556ffcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435050781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.435050781
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1471875164
Short name T1669
Test name
Test status
Simulation time 655671974 ps
CPU time 3.77 seconds
Started Mar 17 03:17:11 PM PDT 24
Finished Mar 17 03:17:15 PM PDT 24
Peak memory 222172 kb
Host smart-77aa9b4c-4f72-42d0-981c-02f71e538bd0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1471875164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1471875164
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.2928948704
Short name T1019
Test name
Test status
Simulation time 641966392 ps
CPU time 4.96 seconds
Started Mar 17 01:32:28 PM PDT 24
Finished Mar 17 01:32:33 PM PDT 24
Peak memory 222376 kb
Host smart-f45781d6-68e6-4f9f-aeef-f35e1d473420
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2928948704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.2928948704
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.1189220987
Short name T931
Test name
Test status
Simulation time 271555579760 ps
CPU time 332.4 seconds
Started Mar 17 03:17:12 PM PDT 24
Finished Mar 17 03:22:45 PM PDT 24
Peak memory 269304 kb
Host smart-022f7519-c801-47c2-a2b2-0f252f384044
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189220987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.1189220987
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.249136920
Short name T1657
Test name
Test status
Simulation time 48964308 ps
CPU time 1.01 seconds
Started Mar 17 01:32:28 PM PDT 24
Finished Mar 17 01:32:29 PM PDT 24
Peak memory 206316 kb
Host smart-02672447-e867-4d86-a092-27d26cbc4588
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249136920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stres
s_all.249136920
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2948535928
Short name T1673
Test name
Test status
Simulation time 9502218262 ps
CPU time 18.25 seconds
Started Mar 17 03:17:10 PM PDT 24
Finished Mar 17 03:17:28 PM PDT 24
Peak memory 216148 kb
Host smart-1fb82c7d-30cb-41d7-9552-8fcdd900c7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948535928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2948535928
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.796927592
Short name T322
Test name
Test status
Simulation time 1041925610 ps
CPU time 12.04 seconds
Started Mar 17 01:32:21 PM PDT 24
Finished Mar 17 01:32:33 PM PDT 24
Peak memory 215832 kb
Host smart-487b5be8-cd04-4f27-b7bc-f9ba1af9082c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796927592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.796927592
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.1468502761
Short name T1244
Test name
Test status
Simulation time 1884414007 ps
CPU time 12 seconds
Started Mar 17 03:17:15 PM PDT 24
Finished Mar 17 03:17:28 PM PDT 24
Peak memory 216080 kb
Host smart-722c0ff3-ce66-4000-9120-b5928786bb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468502761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.1468502761
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2283589694
Short name T1377
Test name
Test status
Simulation time 6069865519 ps
CPU time 16.15 seconds
Started Mar 17 01:32:23 PM PDT 24
Finished Mar 17 01:32:39 PM PDT 24
Peak memory 215968 kb
Host smart-6b1ca00e-7427-4c67-b880-e3ff18149d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2283589694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2283589694
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.3333278235
Short name T1233
Test name
Test status
Simulation time 193267288 ps
CPU time 7.34 seconds
Started Mar 17 03:17:11 PM PDT 24
Finished Mar 17 03:17:19 PM PDT 24
Peak memory 216120 kb
Host smart-152ed198-c4e9-4aa0-bd31-e45828512afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333278235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.3333278235
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.362927150
Short name T1693
Test name
Test status
Simulation time 442042604 ps
CPU time 5 seconds
Started Mar 17 01:32:21 PM PDT 24
Finished Mar 17 01:32:26 PM PDT 24
Peak memory 216080 kb
Host smart-faacecb2-eecd-4c13-897d-76b72a2806ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362927150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.362927150
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3637776526
Short name T1300
Test name
Test status
Simulation time 260045037 ps
CPU time 0.88 seconds
Started Mar 17 01:32:23 PM PDT 24
Finished Mar 17 01:32:24 PM PDT 24
Peak memory 205168 kb
Host smart-b12174d4-9ec0-486a-b11c-adbf31320e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637776526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3637776526
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.4156389913
Short name T1387
Test name
Test status
Simulation time 105179222 ps
CPU time 1 seconds
Started Mar 17 03:17:10 PM PDT 24
Finished Mar 17 03:17:12 PM PDT 24
Peak memory 205932 kb
Host smart-f26d583a-0525-4ca9-8f85-1ce0a7e3eeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4156389913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4156389913
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3290588426
Short name T1149
Test name
Test status
Simulation time 5174193737 ps
CPU time 8.65 seconds
Started Mar 17 03:17:10 PM PDT 24
Finished Mar 17 03:17:19 PM PDT 24
Peak memory 233804 kb
Host smart-e3f9a1cf-bcf1-41c2-8326-f0746fcc8620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290588426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3290588426
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_upload.3952725412
Short name T1732
Test name
Test status
Simulation time 202541843 ps
CPU time 2.36 seconds
Started Mar 17 01:32:27 PM PDT 24
Finished Mar 17 01:32:30 PM PDT 24
Peak memory 217084 kb
Host smart-a91838a9-adbb-43b6-bb2f-db35bfad0813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952725412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3952725412
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1009394240
Short name T423
Test name
Test status
Simulation time 12607578 ps
CPU time 0.73 seconds
Started Mar 17 01:32:34 PM PDT 24
Finished Mar 17 01:32:35 PM PDT 24
Peak memory 204900 kb
Host smart-5574d7ec-e001-4135-acd5-99b3b8315656
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009394240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1009394240
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3948278260
Short name T1337
Test name
Test status
Simulation time 16132792 ps
CPU time 0.7 seconds
Started Mar 17 03:17:13 PM PDT 24
Finished Mar 17 03:17:14 PM PDT 24
Peak memory 204460 kb
Host smart-f2e5564e-8e9c-4c8e-bd60-3f35151bd496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948278260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3948278260
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1525973181
Short name T1346
Test name
Test status
Simulation time 155112484 ps
CPU time 2.58 seconds
Started Mar 17 01:32:36 PM PDT 24
Finished Mar 17 01:32:39 PM PDT 24
Peak memory 233304 kb
Host smart-15a94b36-1237-4687-ab0f-79cda903490e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525973181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1525973181
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3225563035
Short name T1444
Test name
Test status
Simulation time 947243885 ps
CPU time 4.59 seconds
Started Mar 17 03:17:10 PM PDT 24
Finished Mar 17 03:17:15 PM PDT 24
Peak memory 233472 kb
Host smart-7ba24507-69d4-4add-8d05-2812b12364c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225563035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3225563035
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2139058289
Short name T412
Test name
Test status
Simulation time 45981716 ps
CPU time 0.77 seconds
Started Mar 17 03:17:11 PM PDT 24
Finished Mar 17 03:17:12 PM PDT 24
Peak memory 205120 kb
Host smart-83ed2d9e-1c9a-4f89-9fad-43110a289f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139058289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2139058289
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2173257394
Short name T1261
Test name
Test status
Simulation time 25926072 ps
CPU time 0.76 seconds
Started Mar 17 01:32:29 PM PDT 24
Finished Mar 17 01:32:29 PM PDT 24
Peak memory 204968 kb
Host smart-2384afbd-01f5-4e9a-9a20-62729a5688ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173257394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2173257394
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.1246410433
Short name T1049
Test name
Test status
Simulation time 2306715555 ps
CPU time 32.68 seconds
Started Mar 17 01:32:33 PM PDT 24
Finished Mar 17 01:33:06 PM PDT 24
Peak memory 252596 kb
Host smart-8c4fb993-ccef-442b-8379-c6c2046e85d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1246410433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.1246410433
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.2223509751
Short name T668
Test name
Test status
Simulation time 11135940752 ps
CPU time 66.08 seconds
Started Mar 17 03:17:14 PM PDT 24
Finished Mar 17 03:18:20 PM PDT 24
Peak memory 240716 kb
Host smart-c2f6353b-c718-4cba-8341-dce5432e0b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223509751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2223509751
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.19525358
Short name T943
Test name
Test status
Simulation time 13791368973 ps
CPU time 59.48 seconds
Started Mar 17 01:32:35 PM PDT 24
Finished Mar 17 01:33:35 PM PDT 24
Peak memory 238356 kb
Host smart-26a3ee4d-a71c-4356-8d30-584346b35fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=19525358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.19525358
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.3393089817
Short name T1672
Test name
Test status
Simulation time 4754962101 ps
CPU time 86.37 seconds
Started Mar 17 03:17:16 PM PDT 24
Finished Mar 17 03:18:43 PM PDT 24
Peak memory 251068 kb
Host smart-050fe76c-e020-48f2-8ff4-445e23e7385d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393089817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.3393089817
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.665387945
Short name T1822
Test name
Test status
Simulation time 7608114717 ps
CPU time 82.2 seconds
Started Mar 17 01:32:35 PM PDT 24
Finished Mar 17 01:33:57 PM PDT 24
Peak memory 260100 kb
Host smart-53f59e89-dec6-448c-9d1d-8176080b25c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665387945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.665387945
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.199979156
Short name T1438
Test name
Test status
Simulation time 81731686373 ps
CPU time 36.41 seconds
Started Mar 17 01:32:34 PM PDT 24
Finished Mar 17 01:33:11 PM PDT 24
Peak memory 239736 kb
Host smart-f8883c7b-83ef-4bed-afb8-47f665b8e8c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199979156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.199979156
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2982364769
Short name T982
Test name
Test status
Simulation time 16983936489 ps
CPU time 34.82 seconds
Started Mar 17 03:17:13 PM PDT 24
Finished Mar 17 03:17:48 PM PDT 24
Peak memory 249924 kb
Host smart-a6f75d4f-0e5f-4c62-88f5-3fc1babad983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982364769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2982364769
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_intercept.3230616283
Short name T584
Test name
Test status
Simulation time 7870364704 ps
CPU time 8.02 seconds
Started Mar 17 03:17:09 PM PDT 24
Finished Mar 17 03:17:18 PM PDT 24
Peak memory 234696 kb
Host smart-13576985-1db0-439e-af34-df8eb3f475e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230616283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.3230616283
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_intercept.519251308
Short name T171
Test name
Test status
Simulation time 392597640 ps
CPU time 3.74 seconds
Started Mar 17 01:32:29 PM PDT 24
Finished Mar 17 01:32:33 PM PDT 24
Peak memory 233028 kb
Host smart-1d997edd-85f0-497c-b34c-477abb7bf7a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519251308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.519251308
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.1211332298
Short name T1762
Test name
Test status
Simulation time 3046052292 ps
CPU time 12.96 seconds
Started Mar 17 01:32:27 PM PDT 24
Finished Mar 17 01:32:40 PM PDT 24
Peak memory 240392 kb
Host smart-54c474cd-3bcd-427a-8f68-ef01ba700d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211332298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1211332298
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2299697525
Short name T766
Test name
Test status
Simulation time 282844157 ps
CPU time 3.05 seconds
Started Mar 17 03:17:10 PM PDT 24
Finished Mar 17 03:17:14 PM PDT 24
Peak memory 232472 kb
Host smart-ba63d97b-d605-4d59-ad09-bec277418d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299697525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2299697525
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.1990867947
Short name T1134
Test name
Test status
Simulation time 10768357013 ps
CPU time 19.14 seconds
Started Mar 17 01:32:28 PM PDT 24
Finished Mar 17 01:32:47 PM PDT 24
Peak memory 234168 kb
Host smart-2fae83b8-beb6-46e8-8adb-9bcb1c867162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990867947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.1990867947
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.3342826806
Short name T186
Test name
Test status
Simulation time 3601599328 ps
CPU time 11.87 seconds
Started Mar 17 03:17:10 PM PDT 24
Finished Mar 17 03:17:22 PM PDT 24
Peak memory 232840 kb
Host smart-45198fcf-b794-4e39-9cc2-08ccfa8a3df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3342826806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.3342826806
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2083903364
Short name T674
Test name
Test status
Simulation time 8153104011 ps
CPU time 14.73 seconds
Started Mar 17 01:32:30 PM PDT 24
Finished Mar 17 01:32:45 PM PDT 24
Peak memory 244296 kb
Host smart-fc5ee03d-ea38-46e8-a6f6-8a4218e5b322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083903364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2083903364
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.3531723647
Short name T1537
Test name
Test status
Simulation time 6125457330 ps
CPU time 18.67 seconds
Started Mar 17 03:17:10 PM PDT 24
Finished Mar 17 03:17:29 PM PDT 24
Peak memory 224288 kb
Host smart-695f924f-bee3-4356-ba37-4d64b4290d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531723647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3531723647
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.2504119666
Short name T10
Test name
Test status
Simulation time 446321874 ps
CPU time 4.36 seconds
Started Mar 17 03:17:12 PM PDT 24
Finished Mar 17 03:17:16 PM PDT 24
Peak memory 222508 kb
Host smart-96e54cde-429c-4e43-91a7-1cf5648580e7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2504119666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.2504119666
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.4168929699
Short name T1270
Test name
Test status
Simulation time 1976486297 ps
CPU time 4.56 seconds
Started Mar 17 01:32:36 PM PDT 24
Finished Mar 17 01:32:41 PM PDT 24
Peak memory 222436 kb
Host smart-0d18216a-af7b-4a79-84a8-dceb3c8acad3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4168929699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.4168929699
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.4265367755
Short name T1533
Test name
Test status
Simulation time 106878309699 ps
CPU time 483.44 seconds
Started Mar 17 01:32:34 PM PDT 24
Finished Mar 17 01:40:37 PM PDT 24
Peak memory 282572 kb
Host smart-9a71d09b-a107-41ad-8dce-9cabf4652f1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265367755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.4265367755
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.1293088916
Short name T701
Test name
Test status
Simulation time 7541340675 ps
CPU time 36.45 seconds
Started Mar 17 03:17:11 PM PDT 24
Finished Mar 17 03:17:48 PM PDT 24
Peak memory 216204 kb
Host smart-cf046556-4e41-4e6b-8b5a-ff6e3982676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293088916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1293088916
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.353432509
Short name T1242
Test name
Test status
Simulation time 24525623532 ps
CPU time 59.97 seconds
Started Mar 17 01:32:29 PM PDT 24
Finished Mar 17 01:33:29 PM PDT 24
Peak memory 215916 kb
Host smart-88541a0d-8bfe-42a5-aeaf-dbd520afb2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353432509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.353432509
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2321821863
Short name T531
Test name
Test status
Simulation time 6507844467 ps
CPU time 5.06 seconds
Started Mar 17 03:17:08 PM PDT 24
Finished Mar 17 03:17:13 PM PDT 24
Peak memory 216068 kb
Host smart-90a59d47-1909-4693-b8f1-81ce6940ad93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321821863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2321821863
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.3124705684
Short name T749
Test name
Test status
Simulation time 40172652475 ps
CPU time 26.33 seconds
Started Mar 17 01:32:26 PM PDT 24
Finished Mar 17 01:32:53 PM PDT 24
Peak memory 215924 kb
Host smart-64cba3cb-c391-4594-88a1-4a6dc3e47837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124705684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.3124705684
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2261203311
Short name T1029
Test name
Test status
Simulation time 296171165 ps
CPU time 0.89 seconds
Started Mar 17 03:17:09 PM PDT 24
Finished Mar 17 03:17:10 PM PDT 24
Peak memory 206268 kb
Host smart-99c60a0e-423d-4f1b-b106-9df09e55f088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261203311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2261203311
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.2463147589
Short name T768
Test name
Test status
Simulation time 46413362 ps
CPU time 1.12 seconds
Started Mar 17 01:32:30 PM PDT 24
Finished Mar 17 01:32:31 PM PDT 24
Peak memory 206688 kb
Host smart-a1dbaf8d-bf38-4074-b260-28dd318bc398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463147589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.2463147589
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1519550062
Short name T504
Test name
Test status
Simulation time 355361777 ps
CPU time 0.81 seconds
Started Mar 17 03:17:10 PM PDT 24
Finished Mar 17 03:17:11 PM PDT 24
Peak memory 205380 kb
Host smart-a4807c1a-0210-43ff-8602-15de76f45b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1519550062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1519550062
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.2664174216
Short name T1540
Test name
Test status
Simulation time 267340635 ps
CPU time 0.98 seconds
Started Mar 17 01:32:30 PM PDT 24
Finished Mar 17 01:32:31 PM PDT 24
Peak memory 205220 kb
Host smart-4a055d81-5523-4559-8dfe-7e96bebcfe46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664174216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2664174216
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1334761442
Short name T1297
Test name
Test status
Simulation time 16562917773 ps
CPU time 16.1 seconds
Started Mar 17 01:32:35 PM PDT 24
Finished Mar 17 01:32:51 PM PDT 24
Peak memory 237104 kb
Host smart-46ecd7ba-81ae-4e4c-b969-1c4093b8e20f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334761442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1334761442
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_upload.2802482351
Short name T238
Test name
Test status
Simulation time 4868467922 ps
CPU time 15.76 seconds
Started Mar 17 03:17:10 PM PDT 24
Finished Mar 17 03:17:27 PM PDT 24
Peak memory 218852 kb
Host smart-de42ab54-812a-4462-b942-0d6f94e1fd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802482351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2802482351
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.1461054049
Short name T1296
Test name
Test status
Simulation time 37198172 ps
CPU time 0.76 seconds
Started Mar 17 01:32:36 PM PDT 24
Finished Mar 17 01:32:37 PM PDT 24
Peak memory 205156 kb
Host smart-0a263571-619f-425c-8e11-a9e924020b1c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461054049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
1461054049
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2226212479
Short name T810
Test name
Test status
Simulation time 20951838 ps
CPU time 0.71 seconds
Started Mar 17 03:17:19 PM PDT 24
Finished Mar 17 03:17:20 PM PDT 24
Peak memory 204416 kb
Host smart-3dc3fc16-ff65-446d-b18a-c15acc2e4361
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226212479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2226212479
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1572138929
Short name T1098
Test name
Test status
Simulation time 212851431 ps
CPU time 2.43 seconds
Started Mar 17 03:17:16 PM PDT 24
Finished Mar 17 03:17:19 PM PDT 24
Peak memory 218384 kb
Host smart-1bfe4f90-a038-4be3-8a56-5e639f8665d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572138929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1572138929
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.4141707144
Short name T1746
Test name
Test status
Simulation time 140242978 ps
CPU time 2.94 seconds
Started Mar 17 01:32:37 PM PDT 24
Finished Mar 17 01:32:40 PM PDT 24
Peak memory 219052 kb
Host smart-60130242-4c2c-436c-955d-9241e8727b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141707144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.4141707144
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1342792803
Short name T681
Test name
Test status
Simulation time 90337718 ps
CPU time 0.73 seconds
Started Mar 17 01:32:35 PM PDT 24
Finished Mar 17 01:32:36 PM PDT 24
Peak memory 204848 kb
Host smart-63c24d86-d2e0-48a4-92ab-909a7c94d38c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342792803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1342792803
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3513730878
Short name T856
Test name
Test status
Simulation time 45828162 ps
CPU time 0.79 seconds
Started Mar 17 03:17:15 PM PDT 24
Finished Mar 17 03:17:15 PM PDT 24
Peak memory 206184 kb
Host smart-61e9414f-e5f2-4832-9b9e-d9cbd01a67e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513730878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3513730878
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.4065948488
Short name T966
Test name
Test status
Simulation time 21704854776 ps
CPU time 140.98 seconds
Started Mar 17 01:32:34 PM PDT 24
Finished Mar 17 01:34:55 PM PDT 24
Peak memory 254012 kb
Host smart-989489de-9e96-4729-86f6-ce9159f61312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065948488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.4065948488
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.929465546
Short name T234
Test name
Test status
Simulation time 13028355156 ps
CPU time 69.08 seconds
Started Mar 17 03:17:13 PM PDT 24
Finished Mar 17 03:18:23 PM PDT 24
Peak memory 242432 kb
Host smart-a6eefd7e-663a-4b61-9c61-6e3c6fdf17b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929465546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.929465546
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1259659146
Short name T1341
Test name
Test status
Simulation time 27470868393 ps
CPU time 201.71 seconds
Started Mar 17 03:17:17 PM PDT 24
Finished Mar 17 03:20:39 PM PDT 24
Peak memory 249028 kb
Host smart-4c23b1c4-bb3f-4207-b5ee-f29db935950d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259659146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1259659146
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.4010049646
Short name T1827
Test name
Test status
Simulation time 64139239475 ps
CPU time 128.07 seconds
Started Mar 17 01:32:37 PM PDT 24
Finished Mar 17 01:34:46 PM PDT 24
Peak memory 248104 kb
Host smart-7a3ee32a-42e9-4bdd-b301-f4233f1e718a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010049646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.4010049646
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1152384122
Short name T1823
Test name
Test status
Simulation time 36697219988 ps
CPU time 156.43 seconds
Started Mar 17 03:17:18 PM PDT 24
Finished Mar 17 03:19:54 PM PDT 24
Peak memory 256360 kb
Host smart-50141c23-4b42-4e1b-a7f4-7a6a6d6b7807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152384122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1152384122
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.1576284205
Short name T904
Test name
Test status
Simulation time 207108891668 ps
CPU time 641.77 seconds
Started Mar 17 01:32:34 PM PDT 24
Finished Mar 17 01:43:16 PM PDT 24
Peak memory 263564 kb
Host smart-c6130d09-cb17-4581-a495-bb04557dfbc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576284205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.1576284205
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.221679264
Short name T1207
Test name
Test status
Simulation time 9239712301 ps
CPU time 14.42 seconds
Started Mar 17 01:32:39 PM PDT 24
Finished Mar 17 01:32:53 PM PDT 24
Peak memory 232240 kb
Host smart-da24c2e0-5d67-4292-8d9e-be38a1f30c1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221679264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.221679264
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3723934635
Short name T281
Test name
Test status
Simulation time 10491247301 ps
CPU time 34.09 seconds
Started Mar 17 03:17:16 PM PDT 24
Finished Mar 17 03:17:51 PM PDT 24
Peak memory 235848 kb
Host smart-f7391e33-22ad-4208-b50b-eed35b009de2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723934635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3723934635
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_intercept.1115768343
Short name T1573
Test name
Test status
Simulation time 473294119 ps
CPU time 4.05 seconds
Started Mar 17 01:32:35 PM PDT 24
Finished Mar 17 01:32:39 PM PDT 24
Peak memory 224004 kb
Host smart-356c4797-8f9e-47a3-bcbc-209f018b9c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115768343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.1115768343
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2261005800
Short name T491
Test name
Test status
Simulation time 285880892 ps
CPU time 2.6 seconds
Started Mar 17 03:17:16 PM PDT 24
Finished Mar 17 03:17:19 PM PDT 24
Peak memory 233224 kb
Host smart-bab2df5c-dcbc-4a11-9f38-3b2ac9356ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261005800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2261005800
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2535322774
Short name T704
Test name
Test status
Simulation time 13166102631 ps
CPU time 15.05 seconds
Started Mar 17 03:17:16 PM PDT 24
Finished Mar 17 03:17:31 PM PDT 24
Peak memory 219292 kb
Host smart-66d37bff-2b9e-4af4-b152-2db9f6f1623e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535322774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2535322774
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2905711594
Short name T235
Test name
Test status
Simulation time 101465654165 ps
CPU time 41.17 seconds
Started Mar 17 01:32:34 PM PDT 24
Finished Mar 17 01:33:15 PM PDT 24
Peak memory 232244 kb
Host smart-58a2f49e-0041-4637-a44f-f3caa549fe5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905711594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2905711594
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2674821182
Short name T1563
Test name
Test status
Simulation time 7007951774 ps
CPU time 17.53 seconds
Started Mar 17 03:17:12 PM PDT 24
Finished Mar 17 03:17:30 PM PDT 24
Peak memory 224348 kb
Host smart-bb0b7f5f-3769-4102-bb2a-ce0239fec58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2674821182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2674821182
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.452695636
Short name T1091
Test name
Test status
Simulation time 2926459413 ps
CPU time 2.53 seconds
Started Mar 17 01:32:39 PM PDT 24
Finished Mar 17 01:32:42 PM PDT 24
Peak memory 218028 kb
Host smart-d47b34b7-ab01-4b25-aa15-f65d61e08219
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452695636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap
.452695636
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1824591591
Short name T657
Test name
Test status
Simulation time 10149617783 ps
CPU time 31.16 seconds
Started Mar 17 01:32:34 PM PDT 24
Finished Mar 17 01:33:06 PM PDT 24
Peak memory 233316 kb
Host smart-9ff9746a-085a-41cf-9d52-5d02a6cef545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824591591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1824591591
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.1885093181
Short name T575
Test name
Test status
Simulation time 8905097951 ps
CPU time 22.04 seconds
Started Mar 17 03:17:13 PM PDT 24
Finished Mar 17 03:17:36 PM PDT 24
Peak memory 233604 kb
Host smart-dc87d7fb-5c9b-4f17-ae7d-8090fbee48ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885093181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.1885093181
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2097049263
Short name T1357
Test name
Test status
Simulation time 889784863 ps
CPU time 5.06 seconds
Started Mar 17 03:17:15 PM PDT 24
Finished Mar 17 03:17:21 PM PDT 24
Peak memory 222320 kb
Host smart-3a47875d-b030-4d6f-82ea-a4e6208321ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2097049263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2097049263
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3996672824
Short name T1408
Test name
Test status
Simulation time 202952039 ps
CPU time 3.5 seconds
Started Mar 17 01:32:34 PM PDT 24
Finished Mar 17 01:32:38 PM PDT 24
Peak memory 222228 kb
Host smart-a0c4cebd-5306-4932-a9f8-076d9f921f37
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3996672824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3996672824
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.109862023
Short name T489
Test name
Test status
Simulation time 19409439658 ps
CPU time 87.57 seconds
Started Mar 17 03:17:18 PM PDT 24
Finished Mar 17 03:18:46 PM PDT 24
Peak memory 253760 kb
Host smart-0aee4dc1-4a80-475a-af64-9d5e8c8888d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109862023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.109862023
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2777447077
Short name T287
Test name
Test status
Simulation time 1486608229 ps
CPU time 20.49 seconds
Started Mar 17 01:32:34 PM PDT 24
Finished Mar 17 01:32:55 PM PDT 24
Peak memory 215872 kb
Host smart-95c425ca-6906-434c-af5c-a8d0be072862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777447077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2777447077
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3337542369
Short name T1196
Test name
Test status
Simulation time 2497538664 ps
CPU time 14.86 seconds
Started Mar 17 03:17:16 PM PDT 24
Finished Mar 17 03:17:31 PM PDT 24
Peak memory 216212 kb
Host smart-964edbab-a3a4-4be9-8013-56b412c37491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337542369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3337542369
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.229369155
Short name T1892
Test name
Test status
Simulation time 2760611659 ps
CPU time 9.97 seconds
Started Mar 17 01:32:44 PM PDT 24
Finished Mar 17 01:32:54 PM PDT 24
Peak memory 215892 kb
Host smart-73dbae1e-983a-4c58-a1e0-b53247563db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229369155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.229369155
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.3854592066
Short name T1676
Test name
Test status
Simulation time 954786593 ps
CPU time 1.97 seconds
Started Mar 17 03:17:15 PM PDT 24
Finished Mar 17 03:17:17 PM PDT 24
Peak memory 207484 kb
Host smart-f2abf427-3044-4bb5-ace8-af3b002d0041
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854592066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.3854592066
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1944302550
Short name T1715
Test name
Test status
Simulation time 294621056 ps
CPU time 3.69 seconds
Started Mar 17 01:32:39 PM PDT 24
Finished Mar 17 01:32:43 PM PDT 24
Peak memory 207692 kb
Host smart-989a7b10-cf6c-40d4-80ff-88e24da74946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944302550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1944302550
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.4048777148
Short name T1785
Test name
Test status
Simulation time 19209699 ps
CPU time 0.87 seconds
Started Mar 17 03:17:14 PM PDT 24
Finished Mar 17 03:17:15 PM PDT 24
Peak memory 206136 kb
Host smart-a39ba827-1a3c-4c9b-96a2-589d68661492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048777148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.4048777148
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2790689240
Short name T500
Test name
Test status
Simulation time 454688874 ps
CPU time 0.82 seconds
Started Mar 17 01:32:35 PM PDT 24
Finished Mar 17 01:32:36 PM PDT 24
Peak memory 205200 kb
Host smart-67c659c5-d848-445d-9bec-1310a451081f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790689240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2790689240
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.537809045
Short name T1792
Test name
Test status
Simulation time 351217477 ps
CPU time 1.09 seconds
Started Mar 17 03:17:13 PM PDT 24
Finished Mar 17 03:17:15 PM PDT 24
Peak memory 206444 kb
Host smart-41160cd0-1fcb-4f2e-8fe5-10beab77d77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537809045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.537809045
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3667406439
Short name T1743
Test name
Test status
Simulation time 1111771583 ps
CPU time 5.22 seconds
Started Mar 17 03:17:17 PM PDT 24
Finished Mar 17 03:17:22 PM PDT 24
Peak memory 235576 kb
Host smart-fdbe76b6-8c1a-46c2-b5d2-72905a6dd0b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667406439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3667406439
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_upload.41925968
Short name T1194
Test name
Test status
Simulation time 1154437521 ps
CPU time 6.44 seconds
Started Mar 17 01:32:35 PM PDT 24
Finished Mar 17 01:32:42 PM PDT 24
Peak memory 217064 kb
Host smart-76c3bda7-0ade-4d5e-9521-e5a1c0218846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41925968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.41925968
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2522912217
Short name T635
Test name
Test status
Simulation time 14198590 ps
CPU time 0.72 seconds
Started Mar 17 03:17:23 PM PDT 24
Finished Mar 17 03:17:24 PM PDT 24
Peak memory 204992 kb
Host smart-6339c767-1e72-4db1-9b03-b841c51fd038
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522912217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2522912217
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.755322608
Short name T825
Test name
Test status
Simulation time 13351652 ps
CPU time 0.73 seconds
Started Mar 17 01:32:45 PM PDT 24
Finished Mar 17 01:32:47 PM PDT 24
Peak memory 204664 kb
Host smart-72f0e5c4-5d2a-4209-b45d-ff681d37f587
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755322608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.755322608
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2238618577
Short name T1060
Test name
Test status
Simulation time 198676986 ps
CPU time 2.35 seconds
Started Mar 17 03:17:20 PM PDT 24
Finished Mar 17 03:17:23 PM PDT 24
Peak memory 234244 kb
Host smart-850ed36f-575c-4c72-80b7-52db064db5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238618577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2238618577
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3427517671
Short name T474
Test name
Test status
Simulation time 182690657 ps
CPU time 2.8 seconds
Started Mar 17 01:32:46 PM PDT 24
Finished Mar 17 01:32:49 PM PDT 24
Peak memory 218276 kb
Host smart-5d9c5d04-de1c-4dca-b4b3-d5a02439805b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427517671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3427517671
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2124559223
Short name T1130
Test name
Test status
Simulation time 14320298 ps
CPU time 0.78 seconds
Started Mar 17 03:17:19 PM PDT 24
Finished Mar 17 03:17:20 PM PDT 24
Peak memory 206200 kb
Host smart-4b40ca3b-284f-41a0-b331-296a774ad43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124559223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2124559223
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.3836080991
Short name T1852
Test name
Test status
Simulation time 31693427 ps
CPU time 0.75 seconds
Started Mar 17 01:32:33 PM PDT 24
Finished Mar 17 01:32:34 PM PDT 24
Peak memory 205272 kb
Host smart-36e13215-342e-4f42-ad1d-32d66b9f729a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836080991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3836080991
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.3163180762
Short name T1532
Test name
Test status
Simulation time 3147997098 ps
CPU time 30.83 seconds
Started Mar 17 03:17:18 PM PDT 24
Finished Mar 17 03:17:50 PM PDT 24
Peak memory 240732 kb
Host smart-a0c3e833-8c34-4476-be17-2f9f2dea90e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163180762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.3163180762
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.947433211
Short name T1754
Test name
Test status
Simulation time 51365474708 ps
CPU time 127.79 seconds
Started Mar 17 01:32:44 PM PDT 24
Finished Mar 17 01:34:52 PM PDT 24
Peak memory 265304 kb
Host smart-3790f391-dc38-46f7-b104-c31d8a54f67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947433211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.947433211
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.2090312828
Short name T1299
Test name
Test status
Simulation time 10396571920 ps
CPU time 117.97 seconds
Started Mar 17 03:17:18 PM PDT 24
Finished Mar 17 03:19:16 PM PDT 24
Peak memory 264768 kb
Host smart-aed199f6-afd2-4bb5-97fd-0de24da4821a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090312828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2090312828
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3920376146
Short name T199
Test name
Test status
Simulation time 5129789755 ps
CPU time 59.27 seconds
Started Mar 17 01:32:44 PM PDT 24
Finished Mar 17 01:33:44 PM PDT 24
Peak memory 259172 kb
Host smart-08be5dff-e91e-4385-bd1a-b1d118433746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920376146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3920376146
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.657520697
Short name T1325
Test name
Test status
Simulation time 9552132609 ps
CPU time 104.37 seconds
Started Mar 17 03:17:25 PM PDT 24
Finished Mar 17 03:19:10 PM PDT 24
Peak memory 260536 kb
Host smart-e909fcfe-9719-47cb-bf11-b38fa6774c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=657520697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.657520697
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.811964350
Short name T1156
Test name
Test status
Simulation time 28123619933 ps
CPU time 66.82 seconds
Started Mar 17 01:32:43 PM PDT 24
Finished Mar 17 01:33:50 PM PDT 24
Peak memory 252644 kb
Host smart-89a7b65f-230e-4303-ac53-8e4569ad9b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811964350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle
.811964350
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3155815231
Short name T1386
Test name
Test status
Simulation time 22841807612 ps
CPU time 28.15 seconds
Started Mar 17 01:32:43 PM PDT 24
Finished Mar 17 01:33:11 PM PDT 24
Peak memory 232252 kb
Host smart-378d3bc8-c56e-4a1a-a65f-25e5e392cbfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155815231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3155815231
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1618019774
Short name T205
Test name
Test status
Simulation time 3347370501 ps
CPU time 7.86 seconds
Started Mar 17 03:17:18 PM PDT 24
Finished Mar 17 03:17:26 PM PDT 24
Peak memory 218032 kb
Host smart-fc47a45d-e1e6-4eb6-8cf3-89963758be2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618019774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1618019774
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_intercept.1956066985
Short name T1730
Test name
Test status
Simulation time 168491982 ps
CPU time 2.87 seconds
Started Mar 17 01:32:45 PM PDT 24
Finished Mar 17 01:32:49 PM PDT 24
Peak memory 234444 kb
Host smart-692e2a3c-6dc4-498d-b953-48465be427fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956066985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.1956066985
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.1013464459
Short name T1635
Test name
Test status
Simulation time 920847263 ps
CPU time 5.74 seconds
Started Mar 17 01:32:43 PM PDT 24
Finished Mar 17 01:32:49 PM PDT 24
Peak memory 233596 kb
Host smart-fbc38b57-30fe-40dc-a975-cb0ddca9e8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013464459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.1013464459
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.268785990
Short name T1721
Test name
Test status
Simulation time 2175445266 ps
CPU time 12.8 seconds
Started Mar 17 03:17:18 PM PDT 24
Finished Mar 17 03:17:31 PM PDT 24
Peak memory 240728 kb
Host smart-2f3d8f3a-2cbb-4276-ab99-d7bbed41f93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268785990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.268785990
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.209404886
Short name T1829
Test name
Test status
Simulation time 1016916405 ps
CPU time 7.32 seconds
Started Mar 17 01:32:43 PM PDT 24
Finished Mar 17 01:32:51 PM PDT 24
Peak memory 218112 kb
Host smart-52267004-bc64-477d-82b9-c3001a0152bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209404886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.209404886
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.2641087649
Short name T551
Test name
Test status
Simulation time 4469960461 ps
CPU time 18.57 seconds
Started Mar 17 03:17:18 PM PDT 24
Finished Mar 17 03:17:37 PM PDT 24
Peak memory 240672 kb
Host smart-f26cac68-0ec8-4319-be72-ae94309283a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641087649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.2641087649
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1405233667
Short name T1614
Test name
Test status
Simulation time 8175383722 ps
CPU time 12.92 seconds
Started Mar 17 03:17:20 PM PDT 24
Finished Mar 17 03:17:34 PM PDT 24
Peak memory 234816 kb
Host smart-aed8d941-1829-44ce-93f8-60c47a3d4fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405233667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1405233667
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1655521350
Short name T8
Test name
Test status
Simulation time 14058190672 ps
CPU time 18.39 seconds
Started Mar 17 01:32:43 PM PDT 24
Finished Mar 17 01:33:02 PM PDT 24
Peak memory 240392 kb
Host smart-bf55580e-9ed9-4557-8090-0fb2917c846e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655521350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1655521350
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1734389949
Short name T1228
Test name
Test status
Simulation time 1160181602 ps
CPU time 4.41 seconds
Started Mar 17 01:32:44 PM PDT 24
Finished Mar 17 01:32:48 PM PDT 24
Peak memory 220152 kb
Host smart-c547f585-2976-4c89-9fc0-e0cc8e0c1a6e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1734389949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1734389949
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1734703190
Short name T1810
Test name
Test status
Simulation time 6831982654 ps
CPU time 5.55 seconds
Started Mar 17 03:17:19 PM PDT 24
Finished Mar 17 03:17:25 PM PDT 24
Peak memory 222232 kb
Host smart-abd309cb-4a7a-42dd-a75b-919061a4fe31
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1734703190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1734703190
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1227985045
Short name T136
Test name
Test status
Simulation time 147607943958 ps
CPU time 202.44 seconds
Started Mar 17 01:32:41 PM PDT 24
Finished Mar 17 01:36:04 PM PDT 24
Peak memory 248864 kb
Host smart-50101b42-2f63-4c07-828b-8e28fc5b0c95
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227985045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1227985045
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3220494615
Short name T864
Test name
Test status
Simulation time 472887974870 ps
CPU time 895.55 seconds
Started Mar 17 03:17:24 PM PDT 24
Finished Mar 17 03:32:20 PM PDT 24
Peak memory 302332 kb
Host smart-3e0dd951-02bf-4e38-846f-4e7b1dd19bd6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220494615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3220494615
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2219695127
Short name T815
Test name
Test status
Simulation time 2071789926 ps
CPU time 12.24 seconds
Started Mar 17 01:32:44 PM PDT 24
Finished Mar 17 01:32:56 PM PDT 24
Peak memory 216000 kb
Host smart-53fed52e-1b8b-4fcd-9498-ac9f226b16be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219695127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2219695127
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3796596144
Short name T294
Test name
Test status
Simulation time 20684175717 ps
CPU time 33.38 seconds
Started Mar 17 03:17:19 PM PDT 24
Finished Mar 17 03:17:53 PM PDT 24
Peak memory 216244 kb
Host smart-8a965b21-ec8d-47ea-9bc4-7fdb4263b2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796596144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3796596144
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1500171016
Short name T837
Test name
Test status
Simulation time 40156142081 ps
CPU time 34 seconds
Started Mar 17 03:17:19 PM PDT 24
Finished Mar 17 03:17:53 PM PDT 24
Peak memory 216096 kb
Host smart-9236681e-02e0-4766-985d-1d7147cef878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500171016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1500171016
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4088739826
Short name T1331
Test name
Test status
Simulation time 1313189089 ps
CPU time 9.81 seconds
Started Mar 17 01:32:35 PM PDT 24
Finished Mar 17 01:32:45 PM PDT 24
Peak memory 215856 kb
Host smart-6b35e2a4-c590-4a88-aed3-a9b61501ed21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088739826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4088739826
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2323402546
Short name T1806
Test name
Test status
Simulation time 83275261 ps
CPU time 2.07 seconds
Started Mar 17 01:32:43 PM PDT 24
Finished Mar 17 01:32:46 PM PDT 24
Peak memory 215808 kb
Host smart-a13a4574-0a6c-401b-964e-015182a810dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323402546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2323402546
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.635432852
Short name T1616
Test name
Test status
Simulation time 297514575 ps
CPU time 1.69 seconds
Started Mar 17 03:17:20 PM PDT 24
Finished Mar 17 03:17:22 PM PDT 24
Peak memory 216148 kb
Host smart-b3a18de6-8d0b-45ec-a730-e54eb850b72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635432852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.635432852
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.3681011081
Short name T3
Test name
Test status
Simulation time 151463943 ps
CPU time 0.98 seconds
Started Mar 17 03:17:18 PM PDT 24
Finished Mar 17 03:17:20 PM PDT 24
Peak memory 206444 kb
Host smart-4270b270-192f-4209-932a-909e94d8866f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681011081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3681011081
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.759100366
Short name T770
Test name
Test status
Simulation time 35409113 ps
CPU time 0.72 seconds
Started Mar 17 01:32:42 PM PDT 24
Finished Mar 17 01:32:43 PM PDT 24
Peak memory 205180 kb
Host smart-38acd987-431c-4fe6-9c89-578bcf399ba5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759100366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.759100366
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2186008377
Short name T227
Test name
Test status
Simulation time 43861545 ps
CPU time 2.16 seconds
Started Mar 17 01:32:42 PM PDT 24
Finished Mar 17 01:32:44 PM PDT 24
Peak memory 218540 kb
Host smart-68d56326-5caa-4e1a-9fec-2390b6e329af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186008377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2186008377
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_upload.4058308106
Short name T1550
Test name
Test status
Simulation time 445406677 ps
CPU time 3.17 seconds
Started Mar 17 03:17:21 PM PDT 24
Finished Mar 17 03:17:24 PM PDT 24
Peak memory 224284 kb
Host smart-688b6787-a814-4248-98a1-2889cd65f4ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058308106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4058308106
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2387043002
Short name T454
Test name
Test status
Simulation time 71204229 ps
CPU time 0.7 seconds
Started Mar 17 01:32:50 PM PDT 24
Finished Mar 17 01:32:51 PM PDT 24
Peak memory 204316 kb
Host smart-2128e65b-ecb9-4265-a69d-6dde84b09463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2387043002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2387043002
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.903856918
Short name T321
Test name
Test status
Simulation time 50928872 ps
CPU time 0.72 seconds
Started Mar 17 03:17:23 PM PDT 24
Finished Mar 17 03:17:25 PM PDT 24
Peak memory 205068 kb
Host smart-0b2e7b72-2c06-48b7-aa2e-54218e83cf5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903856918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.903856918
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.2400596307
Short name T744
Test name
Test status
Simulation time 2806151713 ps
CPU time 3.6 seconds
Started Mar 17 01:32:45 PM PDT 24
Finished Mar 17 01:32:48 PM PDT 24
Peak memory 218236 kb
Host smart-e9aacc07-6010-4e25-b40d-37797e8b6631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400596307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2400596307
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.430743500
Short name T717
Test name
Test status
Simulation time 680280445 ps
CPU time 3.49 seconds
Started Mar 17 03:17:27 PM PDT 24
Finished Mar 17 03:17:30 PM PDT 24
Peak memory 234308 kb
Host smart-37c0c5be-cac9-4f5c-bddf-5be145471920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430743500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.430743500
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.2983785576
Short name T67
Test name
Test status
Simulation time 22947187 ps
CPU time 0.85 seconds
Started Mar 17 03:17:23 PM PDT 24
Finished Mar 17 03:17:24 PM PDT 24
Peak memory 206172 kb
Host smart-99f14d2b-532c-4070-ad3d-f4ebaf3b795d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983785576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.2983785576
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.991372346
Short name T1768
Test name
Test status
Simulation time 49285549 ps
CPU time 0.78 seconds
Started Mar 17 01:32:43 PM PDT 24
Finished Mar 17 01:32:44 PM PDT 24
Peak memory 204956 kb
Host smart-c6f8466c-4ed8-4b73-9586-ae244eea7bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991372346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.991372346
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1529893579
Short name T1512
Test name
Test status
Simulation time 187744349087 ps
CPU time 230.57 seconds
Started Mar 17 01:32:45 PM PDT 24
Finished Mar 17 01:36:36 PM PDT 24
Peak memory 249748 kb
Host smart-35d07248-78d7-4d7a-aea5-fb6fbc269277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529893579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1529893579
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.2346771193
Short name T899
Test name
Test status
Simulation time 300558824331 ps
CPU time 322.68 seconds
Started Mar 17 03:17:21 PM PDT 24
Finished Mar 17 03:22:44 PM PDT 24
Peak memory 252688 kb
Host smart-54db6342-fbe2-47e9-9761-cb6271ba9f97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346771193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2346771193
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3851966401
Short name T960
Test name
Test status
Simulation time 4316270692 ps
CPU time 37.57 seconds
Started Mar 17 03:17:24 PM PDT 24
Finished Mar 17 03:18:02 PM PDT 24
Peak memory 249196 kb
Host smart-c7ac2943-8470-499d-b40f-375c3bb0bc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851966401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3851966401
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.424077466
Short name T1524
Test name
Test status
Simulation time 74634993784 ps
CPU time 171.61 seconds
Started Mar 17 01:32:48 PM PDT 24
Finished Mar 17 01:35:40 PM PDT 24
Peak memory 251640 kb
Host smart-273e40eb-9b55-468c-8310-b176027d65fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=424077466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.424077466
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.3336219231
Short name T1595
Test name
Test status
Simulation time 2538388847 ps
CPU time 21 seconds
Started Mar 17 01:32:47 PM PDT 24
Finished Mar 17 01:33:08 PM PDT 24
Peak memory 236048 kb
Host smart-3e964f0a-fdab-4a0e-a32d-f5d13a3880ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336219231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.3336219231
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.482210844
Short name T1578
Test name
Test status
Simulation time 30056258250 ps
CPU time 259.74 seconds
Started Mar 17 03:17:23 PM PDT 24
Finished Mar 17 03:21:44 PM PDT 24
Peak memory 273588 kb
Host smart-249df2de-d75d-419f-a68c-52cc9b6e67b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482210844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle
.482210844
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1937659342
Short name T413
Test name
Test status
Simulation time 3296864538 ps
CPU time 35.06 seconds
Started Mar 17 01:32:43 PM PDT 24
Finished Mar 17 01:33:18 PM PDT 24
Peak memory 236296 kb
Host smart-4e225100-5f96-4b83-9490-5584312059b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937659342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1937659342
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_intercept.279436161
Short name T1490
Test name
Test status
Simulation time 192309672 ps
CPU time 4.46 seconds
Started Mar 17 03:17:24 PM PDT 24
Finished Mar 17 03:17:29 PM PDT 24
Peak memory 233276 kb
Host smart-d663fc58-55f9-4c5b-973b-cf2af1a340fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279436161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.279436161
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3346388677
Short name T583
Test name
Test status
Simulation time 235326932 ps
CPU time 4.19 seconds
Started Mar 17 01:32:45 PM PDT 24
Finished Mar 17 01:32:50 PM PDT 24
Peak memory 224144 kb
Host smart-4984cf66-0db3-44d3-8849-2837829dfddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3346388677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3346388677
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1497105882
Short name T1035
Test name
Test status
Simulation time 1002250223 ps
CPU time 5.25 seconds
Started Mar 17 01:32:42 PM PDT 24
Finished Mar 17 01:32:47 PM PDT 24
Peak memory 235812 kb
Host smart-1822be91-b6e9-413f-adc9-e6942a92ae03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497105882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1497105882
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.981449902
Short name T384
Test name
Test status
Simulation time 8177700783 ps
CPU time 9.07 seconds
Started Mar 17 03:17:21 PM PDT 24
Finished Mar 17 03:17:30 PM PDT 24
Peak memory 240732 kb
Host smart-0c5c0b99-fa51-40a7-8c28-f9aaa22d0f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981449902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.981449902
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2858434356
Short name T247
Test name
Test status
Simulation time 34612027030 ps
CPU time 17.83 seconds
Started Mar 17 03:17:23 PM PDT 24
Finished Mar 17 03:17:41 PM PDT 24
Peak memory 234480 kb
Host smart-8efed440-c610-4265-aeac-68ac3ed01461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858434356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2858434356
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.4233313804
Short name T427
Test name
Test status
Simulation time 4218063877 ps
CPU time 10.21 seconds
Started Mar 17 01:32:43 PM PDT 24
Finished Mar 17 01:32:54 PM PDT 24
Peak memory 224108 kb
Host smart-e14d7be9-83fb-4a63-9c8c-bef04b1a1e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233313804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.4233313804
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.1957532456
Short name T1687
Test name
Test status
Simulation time 62226912534 ps
CPU time 42.01 seconds
Started Mar 17 03:17:23 PM PDT 24
Finished Mar 17 03:18:05 PM PDT 24
Peak memory 246812 kb
Host smart-6252ccab-e909-439e-8718-3b370a6b3664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957532456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.1957532456
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.832727439
Short name T1213
Test name
Test status
Simulation time 425639582 ps
CPU time 3.46 seconds
Started Mar 17 01:32:45 PM PDT 24
Finished Mar 17 01:32:49 PM PDT 24
Peak memory 224080 kb
Host smart-42f6713d-c238-4a35-be44-4171ae3b4b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832727439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.832727439
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.114896413
Short name T1083
Test name
Test status
Simulation time 233264655 ps
CPU time 3.6 seconds
Started Mar 17 03:17:23 PM PDT 24
Finished Mar 17 03:17:27 PM PDT 24
Peak memory 218956 kb
Host smart-b9c0bcd9-628e-42e0-9621-0a0287037d3b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=114896413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dire
ct.114896413
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2453185560
Short name T130
Test name
Test status
Simulation time 1362207796 ps
CPU time 6.54 seconds
Started Mar 17 01:32:43 PM PDT 24
Finished Mar 17 01:32:50 PM PDT 24
Peak memory 221700 kb
Host smart-d344deba-14bc-4733-9a52-d200b63f8cc7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2453185560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2453185560
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2772351423
Short name T1700
Test name
Test status
Simulation time 161333475700 ps
CPU time 141.29 seconds
Started Mar 17 03:17:24 PM PDT 24
Finished Mar 17 03:19:45 PM PDT 24
Peak memory 252464 kb
Host smart-013c1efd-f3ad-49e4-9c89-5aab2ec23462
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772351423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2772351423
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2107173419
Short name T34
Test name
Test status
Simulation time 14909422725 ps
CPU time 26.47 seconds
Started Mar 17 03:17:22 PM PDT 24
Finished Mar 17 03:17:49 PM PDT 24
Peak memory 220136 kb
Host smart-6b07a219-e138-4bce-be9c-53a609258a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107173419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2107173419
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.971267103
Short name T1095
Test name
Test status
Simulation time 6063147257 ps
CPU time 18.38 seconds
Started Mar 17 01:32:48 PM PDT 24
Finished Mar 17 01:33:07 PM PDT 24
Peak memory 215968 kb
Host smart-e04ccb07-b39d-41e5-a907-2abfe3daf5dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971267103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.971267103
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.176517838
Short name T812
Test name
Test status
Simulation time 138621472 ps
CPU time 1.61 seconds
Started Mar 17 01:32:43 PM PDT 24
Finished Mar 17 01:32:45 PM PDT 24
Peak memory 207240 kb
Host smart-3a2aa31a-81e5-47a0-b915-dae15e435030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176517838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.176517838
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2398859474
Short name T1322
Test name
Test status
Simulation time 3872916102 ps
CPU time 5.2 seconds
Started Mar 17 03:17:24 PM PDT 24
Finished Mar 17 03:17:29 PM PDT 24
Peak memory 216016 kb
Host smart-13b2b9a9-b272-4d60-8212-b81cabb21d6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398859474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2398859474
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.737883677
Short name T302
Test name
Test status
Simulation time 163428320 ps
CPU time 1.45 seconds
Started Mar 17 01:32:43 PM PDT 24
Finished Mar 17 01:32:44 PM PDT 24
Peak memory 215824 kb
Host smart-bc9b3561-ec3a-43ca-9565-e5db2e41ab95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737883677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.737883677
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.857120516
Short name T595
Test name
Test status
Simulation time 241329407 ps
CPU time 3.92 seconds
Started Mar 17 03:17:23 PM PDT 24
Finished Mar 17 03:17:27 PM PDT 24
Peak memory 216132 kb
Host smart-6efbd6a6-8c95-49d5-837f-b29c67e6a965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857120516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.857120516
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.172695600
Short name T660
Test name
Test status
Simulation time 36300531 ps
CPU time 0.75 seconds
Started Mar 17 03:17:21 PM PDT 24
Finished Mar 17 03:17:22 PM PDT 24
Peak memory 205360 kb
Host smart-2d3adcb1-a803-4646-8e19-1c1ca7acc51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172695600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.172695600
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.62042492
Short name T1099
Test name
Test status
Simulation time 633166439 ps
CPU time 1.12 seconds
Started Mar 17 01:32:48 PM PDT 24
Finished Mar 17 01:32:50 PM PDT 24
Peak memory 206184 kb
Host smart-5f41ebce-0c5d-47ec-a8e8-cafb1fed5053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62042492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.62042492
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1296670045
Short name T678
Test name
Test status
Simulation time 708371431 ps
CPU time 6.86 seconds
Started Mar 17 01:32:43 PM PDT 24
Finished Mar 17 01:32:51 PM PDT 24
Peak memory 222640 kb
Host smart-f9e12e59-664b-4796-bfe3-2c9be5a171a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296670045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1296670045
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_upload.2251450595
Short name T1042
Test name
Test status
Simulation time 29404394207 ps
CPU time 14.36 seconds
Started Mar 17 03:17:24 PM PDT 24
Finished Mar 17 03:17:39 PM PDT 24
Peak memory 240652 kb
Host smart-66749488-0985-4fe6-b62a-e7f09a53479a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251450595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.2251450595
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.3826797417
Short name T788
Test name
Test status
Simulation time 52957897 ps
CPU time 0.69 seconds
Started Mar 17 03:17:31 PM PDT 24
Finished Mar 17 03:17:32 PM PDT 24
Peak memory 204996 kb
Host smart-a7c9570d-8187-46c4-a08b-aaf5628e651a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826797417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
3826797417
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.571119574
Short name T653
Test name
Test status
Simulation time 29357102 ps
CPU time 0.75 seconds
Started Mar 17 01:32:50 PM PDT 24
Finished Mar 17 01:32:51 PM PDT 24
Peak memory 205152 kb
Host smart-bfb78b6d-1a5d-4578-b30f-cb4a01268c8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571119574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.571119574
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.1731448762
Short name T397
Test name
Test status
Simulation time 133859322 ps
CPU time 2.51 seconds
Started Mar 17 01:32:48 PM PDT 24
Finished Mar 17 01:32:51 PM PDT 24
Peak memory 218036 kb
Host smart-96411db2-9d08-4ca0-9a39-6d46104cc3e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731448762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.1731448762
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.4275333594
Short name T959
Test name
Test status
Simulation time 938680424 ps
CPU time 3.23 seconds
Started Mar 17 03:17:27 PM PDT 24
Finished Mar 17 03:17:31 PM PDT 24
Peak memory 234636 kb
Host smart-934f7035-1950-4a47-a546-2c13a490fda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275333594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.4275333594
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.3718959567
Short name T1263
Test name
Test status
Simulation time 60472990 ps
CPU time 0.79 seconds
Started Mar 17 01:32:51 PM PDT 24
Finished Mar 17 01:32:53 PM PDT 24
Peak memory 205288 kb
Host smart-3fa3fa88-d907-4226-903c-fc28ab7097dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718959567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3718959567
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.51066227
Short name T911
Test name
Test status
Simulation time 22452079 ps
CPU time 0.78 seconds
Started Mar 17 03:17:24 PM PDT 24
Finished Mar 17 03:17:25 PM PDT 24
Peak memory 206212 kb
Host smart-b09744e7-effa-45c7-972d-595d8906b0c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51066227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.51066227
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1104177315
Short name T1507
Test name
Test status
Simulation time 130791142299 ps
CPU time 218.36 seconds
Started Mar 17 03:17:30 PM PDT 24
Finished Mar 17 03:21:09 PM PDT 24
Peak memory 268888 kb
Host smart-0f3c2a4e-1984-4339-af27-0694dbfceac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1104177315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1104177315
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1105163817
Short name T654
Test name
Test status
Simulation time 19658515885 ps
CPU time 88.84 seconds
Started Mar 17 01:32:47 PM PDT 24
Finished Mar 17 01:34:16 PM PDT 24
Peak memory 268736 kb
Host smart-cf98d924-002c-447c-a088-135b91f54916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105163817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1105163817
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.631549312
Short name T1675
Test name
Test status
Simulation time 10373084311 ps
CPU time 54.84 seconds
Started Mar 17 03:17:27 PM PDT 24
Finished Mar 17 03:18:22 PM PDT 24
Peak memory 240780 kb
Host smart-e62a3349-e60f-42d2-bf26-35f807e6b560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631549312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.631549312
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.858656187
Short name T533
Test name
Test status
Simulation time 50723075154 ps
CPU time 207.5 seconds
Started Mar 17 01:32:48 PM PDT 24
Finished Mar 17 01:36:16 PM PDT 24
Peak memory 248772 kb
Host smart-13334e26-a13b-4b81-8054-369f58887d1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858656187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.858656187
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.1414507658
Short name T799
Test name
Test status
Simulation time 38746837824 ps
CPU time 135.93 seconds
Started Mar 17 03:17:26 PM PDT 24
Finished Mar 17 03:19:43 PM PDT 24
Peak memory 256428 kb
Host smart-e1bc617e-fff4-46f9-93fd-b2d57adcc977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414507658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.1414507658
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.526120477
Short name T1627
Test name
Test status
Simulation time 30154117801 ps
CPU time 210.56 seconds
Started Mar 17 01:32:47 PM PDT 24
Finished Mar 17 01:36:18 PM PDT 24
Peak memory 250040 kb
Host smart-14840b12-1733-4fb2-9ada-928196fb793b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526120477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.526120477
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.1931602429
Short name T196
Test name
Test status
Simulation time 1457684893 ps
CPU time 8.17 seconds
Started Mar 17 03:17:28 PM PDT 24
Finished Mar 17 03:17:36 PM PDT 24
Peak memory 220376 kb
Host smart-d9ce98a0-93e6-4f76-a415-5c06d3c6c529
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931602429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1931602429
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.3698867456
Short name T1733
Test name
Test status
Simulation time 1302254843 ps
CPU time 10.11 seconds
Started Mar 17 01:32:48 PM PDT 24
Finished Mar 17 01:32:58 PM PDT 24
Peak memory 224080 kb
Host smart-f79b8e1a-b01d-42b9-8e95-df72505dd446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698867456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.3698867456
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.3285414189
Short name T1295
Test name
Test status
Simulation time 729918274 ps
CPU time 4.15 seconds
Started Mar 17 01:32:50 PM PDT 24
Finished Mar 17 01:32:55 PM PDT 24
Peak memory 217980 kb
Host smart-134d72f1-3dd4-4fda-ad0c-af146f40f5e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285414189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3285414189
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_intercept.459678065
Short name T1720
Test name
Test status
Simulation time 946179003 ps
CPU time 5.83 seconds
Started Mar 17 03:17:27 PM PDT 24
Finished Mar 17 03:17:33 PM PDT 24
Peak memory 219432 kb
Host smart-db33db12-440c-4f2b-8243-d5a9c4a979a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459678065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.459678065
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1566817075
Short name T683
Test name
Test status
Simulation time 2064120010 ps
CPU time 7.37 seconds
Started Mar 17 01:32:47 PM PDT 24
Finished Mar 17 01:32:55 PM PDT 24
Peak memory 232244 kb
Host smart-a611ba6e-5a94-4d21-b50d-dc4d46a17b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1566817075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1566817075
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.2643597709
Short name T1897
Test name
Test status
Simulation time 881038983 ps
CPU time 6.55 seconds
Started Mar 17 03:17:30 PM PDT 24
Finished Mar 17 03:17:37 PM PDT 24
Peak memory 235824 kb
Host smart-7f71a08f-5494-47c9-8992-4d4f794f4240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643597709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.2643597709
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1490396400
Short name T1359
Test name
Test status
Simulation time 20579138542 ps
CPU time 20.02 seconds
Started Mar 17 03:17:27 PM PDT 24
Finished Mar 17 03:17:47 PM PDT 24
Peak memory 240716 kb
Host smart-dc0cb8e4-96ca-435b-9cde-1c4f1d127168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490396400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1490396400
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1506002806
Short name T352
Test name
Test status
Simulation time 613425751 ps
CPU time 3.06 seconds
Started Mar 17 01:32:48 PM PDT 24
Finished Mar 17 01:32:52 PM PDT 24
Peak memory 216312 kb
Host smart-601d42b7-d28a-4ba2-900c-093cd8a44ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506002806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1506002806
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2365874216
Short name T697
Test name
Test status
Simulation time 972522182 ps
CPU time 2.57 seconds
Started Mar 17 01:32:51 PM PDT 24
Finished Mar 17 01:32:55 PM PDT 24
Peak memory 223976 kb
Host smart-f806e7df-3e6f-4332-9c5c-93438285b241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365874216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2365874216
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2504095372
Short name T675
Test name
Test status
Simulation time 30358889787 ps
CPU time 9.65 seconds
Started Mar 17 03:17:28 PM PDT 24
Finished Mar 17 03:17:38 PM PDT 24
Peak memory 233604 kb
Host smart-1df4c495-739f-42f9-af09-c783546fb23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504095372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2504095372
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.3847422756
Short name T854
Test name
Test status
Simulation time 1127101700 ps
CPU time 5.58 seconds
Started Mar 17 03:17:28 PM PDT 24
Finished Mar 17 03:17:34 PM PDT 24
Peak memory 218928 kb
Host smart-c18c9b63-9382-4a36-ad18-885e631b8939
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3847422756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.3847422756
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.530056933
Short name T814
Test name
Test status
Simulation time 81027078 ps
CPU time 3.39 seconds
Started Mar 17 01:32:53 PM PDT 24
Finished Mar 17 01:32:57 PM PDT 24
Peak memory 222380 kb
Host smart-c06c14bc-f1a2-4640-b018-67a82630e0d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=530056933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dire
ct.530056933
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2696281425
Short name T562
Test name
Test status
Simulation time 195966162 ps
CPU time 1.12 seconds
Started Mar 17 03:17:28 PM PDT 24
Finished Mar 17 03:17:29 PM PDT 24
Peak memory 206816 kb
Host smart-6733838f-4988-4c4e-9cfb-4f96a423b9d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696281425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2696281425
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.95028383
Short name T1249
Test name
Test status
Simulation time 40116165860 ps
CPU time 272.42 seconds
Started Mar 17 01:32:50 PM PDT 24
Finished Mar 17 01:37:23 PM PDT 24
Peak memory 259700 kb
Host smart-35d183df-71de-4c12-8b7b-68e967d3ad37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95028383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_str
ess_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress
_all.95028383
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3130223481
Short name T456
Test name
Test status
Simulation time 578753518 ps
CPU time 9.9 seconds
Started Mar 17 01:32:48 PM PDT 24
Finished Mar 17 01:32:58 PM PDT 24
Peak memory 215812 kb
Host smart-e7893f96-a6d6-4bfe-82f0-92ff678c82ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3130223481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3130223481
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.4021940372
Short name T1183
Test name
Test status
Simulation time 10278175149 ps
CPU time 5.76 seconds
Started Mar 17 03:17:26 PM PDT 24
Finished Mar 17 03:17:32 PM PDT 24
Peak memory 216144 kb
Host smart-299a63e7-08f7-4907-8020-0c908e7d9328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021940372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4021940372
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.1680126924
Short name T1114
Test name
Test status
Simulation time 2531547084 ps
CPU time 13.53 seconds
Started Mar 17 03:17:21 PM PDT 24
Finished Mar 17 03:17:34 PM PDT 24
Peak memory 216124 kb
Host smart-ae3e5071-9ecd-482a-958d-58042da74c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680126924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.1680126924
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3451711785
Short name T914
Test name
Test status
Simulation time 15354467406 ps
CPU time 13.23 seconds
Started Mar 17 01:32:50 PM PDT 24
Finished Mar 17 01:33:04 PM PDT 24
Peak memory 215964 kb
Host smart-bce73794-0468-4143-8929-84b1381c0639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451711785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3451711785
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1509339461
Short name T1674
Test name
Test status
Simulation time 41532646 ps
CPU time 0.86 seconds
Started Mar 17 01:32:50 PM PDT 24
Finished Mar 17 01:32:51 PM PDT 24
Peak memory 205788 kb
Host smart-ed713572-3f11-4407-a0a3-3b19d42dc92f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509339461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1509339461
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.3295735273
Short name T365
Test name
Test status
Simulation time 171852429 ps
CPU time 1.45 seconds
Started Mar 17 03:17:28 PM PDT 24
Finished Mar 17 03:17:30 PM PDT 24
Peak memory 216256 kb
Host smart-63d2756e-a036-4f86-88b2-b9b5facbd806
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3295735273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.3295735273
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3611920833
Short name T1214
Test name
Test status
Simulation time 178289496 ps
CPU time 0.82 seconds
Started Mar 17 03:17:27 PM PDT 24
Finished Mar 17 03:17:28 PM PDT 24
Peak memory 205440 kb
Host smart-28b49b3a-c4c0-4616-b701-e1a907d358b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611920833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3611920833
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.612329845
Short name T754
Test name
Test status
Simulation time 80456354 ps
CPU time 1 seconds
Started Mar 17 01:32:53 PM PDT 24
Finished Mar 17 01:32:55 PM PDT 24
Peak memory 205180 kb
Host smart-07ff9356-c44f-4096-adef-36b0f6d9c52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612329845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.612329845
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.4090496089
Short name T1838
Test name
Test status
Simulation time 553621161 ps
CPU time 8.33 seconds
Started Mar 17 01:32:48 PM PDT 24
Finished Mar 17 01:32:56 PM PDT 24
Peak memory 241752 kb
Host smart-8f7a8e96-0d8b-41d7-9132-ad406367b23b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090496089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.4090496089
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_upload.708277312
Short name T216
Test name
Test status
Simulation time 55650403385 ps
CPU time 31.49 seconds
Started Mar 17 03:17:28 PM PDT 24
Finished Mar 17 03:18:00 PM PDT 24
Peak memory 243392 kb
Host smart-6d87ac21-3131-4921-8813-5994b0141ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708277312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.708277312
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2032217428
Short name T962
Test name
Test status
Simulation time 37777814 ps
CPU time 0.69 seconds
Started Mar 17 01:29:18 PM PDT 24
Finished Mar 17 01:29:18 PM PDT 24
Peak memory 204916 kb
Host smart-8ddb987f-4ab2-457c-b02c-462e4a8f9a32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032217428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
032217428
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2302906251
Short name T1004
Test name
Test status
Simulation time 224571203 ps
CPU time 0.73 seconds
Started Mar 17 03:13:32 PM PDT 24
Finished Mar 17 03:13:33 PM PDT 24
Peak memory 204984 kb
Host smart-6f4ab48b-9c7d-4174-ba6d-bcb2e402bc6b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302906251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
302906251
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1173633674
Short name T942
Test name
Test status
Simulation time 191975128 ps
CPU time 2.8 seconds
Started Mar 17 01:29:09 PM PDT 24
Finished Mar 17 01:29:13 PM PDT 24
Peak memory 233080 kb
Host smart-a10aaf68-285a-424c-ab52-f9d1696f799a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1173633674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1173633674
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.1310389656
Short name T522
Test name
Test status
Simulation time 783293660 ps
CPU time 4.06 seconds
Started Mar 17 03:13:35 PM PDT 24
Finished Mar 17 03:13:39 PM PDT 24
Peak memory 233656 kb
Host smart-31d2f99a-4caa-43d4-a478-b016cb653f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310389656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1310389656
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.1341317651
Short name T1707
Test name
Test status
Simulation time 55133831 ps
CPU time 0.77 seconds
Started Mar 17 01:29:06 PM PDT 24
Finished Mar 17 01:29:08 PM PDT 24
Peak memory 205960 kb
Host smart-a2983390-7353-4226-ba45-2b125f6ef6f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341317651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.1341317651
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3589912226
Short name T1135
Test name
Test status
Simulation time 15894731 ps
CPU time 0.74 seconds
Started Mar 17 03:13:25 PM PDT 24
Finished Mar 17 03:13:26 PM PDT 24
Peak memory 205448 kb
Host smart-dde4eae9-2158-425a-bd66-6ad971361df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589912226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3589912226
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1155455709
Short name T149
Test name
Test status
Simulation time 47307003730 ps
CPU time 135.99 seconds
Started Mar 17 01:29:09 PM PDT 24
Finished Mar 17 01:31:27 PM PDT 24
Peak memory 266024 kb
Host smart-42faa98c-53b0-4b4c-b49b-4fdd759a467c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155455709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1155455709
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.1684305102
Short name T1749
Test name
Test status
Simulation time 4558379074 ps
CPU time 31.33 seconds
Started Mar 17 03:13:33 PM PDT 24
Finished Mar 17 03:14:05 PM PDT 24
Peak memory 240568 kb
Host smart-8611dd4d-5b8e-4d28-9c35-be42f52e8796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1684305102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.1684305102
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.2732888610
Short name T1468
Test name
Test status
Simulation time 16442777256 ps
CPU time 82.59 seconds
Started Mar 17 01:29:10 PM PDT 24
Finished Mar 17 01:30:34 PM PDT 24
Peak memory 240308 kb
Host smart-0cf36f58-9a96-4f6c-8991-0c1a43c84fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2732888610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.2732888610
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.3804935173
Short name T1240
Test name
Test status
Simulation time 94156464166 ps
CPU time 180.21 seconds
Started Mar 17 03:13:40 PM PDT 24
Finished Mar 17 03:16:40 PM PDT 24
Peak memory 248940 kb
Host smart-87312115-9961-4641-acf8-730c0b843f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804935173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.3804935173
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.1900069138
Short name T1621
Test name
Test status
Simulation time 16083206353 ps
CPU time 178.92 seconds
Started Mar 17 01:29:23 PM PDT 24
Finished Mar 17 01:32:22 PM PDT 24
Peak memory 252616 kb
Host smart-bba7e6d0-eaad-4587-a88f-3144087521ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900069138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.1900069138
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.281434431
Short name T1313
Test name
Test status
Simulation time 37989566086 ps
CPU time 177.59 seconds
Started Mar 17 03:13:35 PM PDT 24
Finished Mar 17 03:16:33 PM PDT 24
Peak memory 265600 kb
Host smart-3abef2a2-62ab-433f-99c6-cc559ec50cc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281434431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
281434431
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.4150263546
Short name T998
Test name
Test status
Simulation time 377198780 ps
CPU time 12.91 seconds
Started Mar 17 03:13:35 PM PDT 24
Finished Mar 17 03:13:48 PM PDT 24
Peak memory 232504 kb
Host smart-b1d8da7c-a2b5-4d5e-aa20-6e0c606c1c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150263546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.4150263546
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_intercept.213692002
Short name T1425
Test name
Test status
Simulation time 844896577 ps
CPU time 3.33 seconds
Started Mar 17 03:13:34 PM PDT 24
Finished Mar 17 03:13:38 PM PDT 24
Peak memory 218612 kb
Host smart-c2b8ff2a-1c19-483d-82f3-9ddccfd93f52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213692002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.213692002
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2416554584
Short name T342
Test name
Test status
Simulation time 391245981 ps
CPU time 3.04 seconds
Started Mar 17 01:29:09 PM PDT 24
Finished Mar 17 01:29:13 PM PDT 24
Peak memory 218124 kb
Host smart-52ff322a-294c-4714-a7fa-eca4d09cc51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416554584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2416554584
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.2622528335
Short name T185
Test name
Test status
Simulation time 2258256061 ps
CPU time 7.21 seconds
Started Mar 17 03:13:35 PM PDT 24
Finished Mar 17 03:13:43 PM PDT 24
Peak memory 226884 kb
Host smart-7556c896-f505-4b02-8b63-69c01104281f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622528335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2622528335
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.573636874
Short name T1686
Test name
Test status
Simulation time 23670963206 ps
CPU time 10.06 seconds
Started Mar 17 01:29:09 PM PDT 24
Finished Mar 17 01:29:21 PM PDT 24
Peak memory 218096 kb
Host smart-4651dd3d-ad32-4522-afab-6e6322390400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573636874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.573636874
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_mem_parity.3491498882
Short name T21
Test name
Test status
Simulation time 46764063 ps
CPU time 1.08 seconds
Started Mar 17 01:29:04 PM PDT 24
Finished Mar 17 01:29:06 PM PDT 24
Peak memory 216404 kb
Host smart-51183432-5608-4b9d-90d4-cb05c5880f2d
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491498882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 5.spi_device_mem_parity.3491498882
Directory /workspace/5.spi_device_mem_parity/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.1248566265
Short name T1486
Test name
Test status
Simulation time 96287725 ps
CPU time 2.42 seconds
Started Mar 17 01:29:09 PM PDT 24
Finished Mar 17 01:29:13 PM PDT 24
Peak memory 216480 kb
Host smart-814443ee-cbb7-4626-b4fe-ad759a50274c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248566265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.1248566265
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.687933196
Short name T462
Test name
Test status
Simulation time 1449138225 ps
CPU time 4.47 seconds
Started Mar 17 03:13:34 PM PDT 24
Finished Mar 17 03:13:39 PM PDT 24
Peak memory 227292 kb
Host smart-35c0634d-c682-4e39-9e7b-4cbddf40d01e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687933196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
687933196
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1139519915
Short name T1731
Test name
Test status
Simulation time 720623910 ps
CPU time 7.51 seconds
Started Mar 17 03:13:40 PM PDT 24
Finished Mar 17 03:13:47 PM PDT 24
Peak memory 219272 kb
Host smart-a07867e0-bc4a-4ee9-99c7-99c5be6c8c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139519915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1139519915
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.979253000
Short name T1253
Test name
Test status
Simulation time 730160950 ps
CPU time 4.08 seconds
Started Mar 17 01:29:09 PM PDT 24
Finished Mar 17 01:29:14 PM PDT 24
Peak memory 223940 kb
Host smart-b60b8948-9ecd-4af7-b4ba-20afb3d39ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979253000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.979253000
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.3069580770
Short name T1264
Test name
Test status
Simulation time 49626408 ps
CPU time 0.76 seconds
Started Mar 17 03:13:29 PM PDT 24
Finished Mar 17 03:13:30 PM PDT 24
Peak memory 216000 kb
Host smart-89ae5468-1cb8-413d-9b4b-f2fbaaedb3ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069580770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.3069580770
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_ram_cfg.369434462
Short name T623
Test name
Test status
Simulation time 63206472 ps
CPU time 0.73 seconds
Started Mar 17 01:29:05 PM PDT 24
Finished Mar 17 01:29:06 PM PDT 24
Peak memory 215816 kb
Host smart-3c8a1a36-f7cc-47f2-b928-cfbc0584e6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369434462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_ram_cfg.369434462
Directory /workspace/5.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.1957574502
Short name T363
Test name
Test status
Simulation time 291532078 ps
CPU time 3.88 seconds
Started Mar 17 03:13:35 PM PDT 24
Finished Mar 17 03:13:39 PM PDT 24
Peak memory 222772 kb
Host smart-43209263-2d10-4156-8c48-14e80d2705a6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1957574502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.1957574502
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.49007587
Short name T1854
Test name
Test status
Simulation time 392709966 ps
CPU time 3.2 seconds
Started Mar 17 01:29:09 PM PDT 24
Finished Mar 17 01:29:13 PM PDT 24
Peak memory 219712 kb
Host smart-bcc47dbb-a36b-4ed1-b849-9fb7bb79b019
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=49007587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct
.49007587
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.4029470750
Short name T797
Test name
Test status
Simulation time 53776690 ps
CPU time 1.07 seconds
Started Mar 17 03:13:39 PM PDT 24
Finished Mar 17 03:13:41 PM PDT 24
Peak memory 206824 kb
Host smart-38ac0d0b-c2fa-4dbb-9e37-61356b0827cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029470750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.4029470750
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.704378356
Short name T925
Test name
Test status
Simulation time 18723084978 ps
CPU time 71.53 seconds
Started Mar 17 01:29:16 PM PDT 24
Finished Mar 17 01:30:27 PM PDT 24
Peak memory 251948 kb
Host smart-7cf44765-c4da-412d-baca-d231a32fa631
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704378356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress
_all.704378356
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.342811726
Short name T1085
Test name
Test status
Simulation time 1881337501 ps
CPU time 18.63 seconds
Started Mar 17 01:29:10 PM PDT 24
Finished Mar 17 01:29:30 PM PDT 24
Peak memory 215804 kb
Host smart-66297a79-542e-4902-ac29-5fec7344856c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342811726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.342811726
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.355189974
Short name T1773
Test name
Test status
Simulation time 2765423260 ps
CPU time 25.58 seconds
Started Mar 17 03:13:27 PM PDT 24
Finished Mar 17 03:13:53 PM PDT 24
Peak memory 219980 kb
Host smart-0721e035-08d7-4178-b219-ec0322376bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355189974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.355189974
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2280924529
Short name T986
Test name
Test status
Simulation time 170450332 ps
CPU time 1.64 seconds
Started Mar 17 01:29:10 PM PDT 24
Finished Mar 17 01:29:14 PM PDT 24
Peak memory 206552 kb
Host smart-671e22da-128b-42d5-89a5-bfbb7be2d2be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280924529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2280924529
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3848614254
Short name T1893
Test name
Test status
Simulation time 8281164174 ps
CPU time 14.44 seconds
Started Mar 17 03:13:29 PM PDT 24
Finished Mar 17 03:13:43 PM PDT 24
Peak memory 216124 kb
Host smart-e98d5b52-21f6-4c3a-9e56-361381560962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848614254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3848614254
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1109653582
Short name T753
Test name
Test status
Simulation time 1562083180 ps
CPU time 2.1 seconds
Started Mar 17 01:29:10 PM PDT 24
Finished Mar 17 01:29:13 PM PDT 24
Peak memory 215848 kb
Host smart-0354baab-5f1d-4ba6-97be-8d587c787a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109653582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1109653582
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.2075755499
Short name T24
Test name
Test status
Simulation time 152720409 ps
CPU time 1.84 seconds
Started Mar 17 03:13:34 PM PDT 24
Finished Mar 17 03:13:36 PM PDT 24
Peak memory 216092 kb
Host smart-a2fb77fa-832d-4408-a791-f43babf57a93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075755499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.2075755499
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.3798702248
Short name T1813
Test name
Test status
Simulation time 25871418 ps
CPU time 0.73 seconds
Started Mar 17 03:13:29 PM PDT 24
Finished Mar 17 03:13:30 PM PDT 24
Peak memory 205420 kb
Host smart-12a2dc40-2f9f-4f7a-959b-111c8cac7b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798702248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.3798702248
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.860016743
Short name T1392
Test name
Test status
Simulation time 108730448 ps
CPU time 0.85 seconds
Started Mar 17 01:29:09 PM PDT 24
Finished Mar 17 01:29:11 PM PDT 24
Peak memory 205196 kb
Host smart-c0cbc0bc-5a4d-47c7-8b2f-3031432c7978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860016743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.860016743
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3459021348
Short name T664
Test name
Test status
Simulation time 2620982837 ps
CPU time 11.71 seconds
Started Mar 17 01:29:09 PM PDT 24
Finished Mar 17 01:29:24 PM PDT 24
Peak memory 225072 kb
Host smart-938b447d-3bde-4a3a-b5f2-e6d20ba2828f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459021348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3459021348
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_upload.4143637842
Short name T933
Test name
Test status
Simulation time 8546407875 ps
CPU time 13.06 seconds
Started Mar 17 03:13:35 PM PDT 24
Finished Mar 17 03:13:48 PM PDT 24
Peak memory 229676 kb
Host smart-8e3587f4-149f-4610-867a-8086f539f3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143637842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.4143637842
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3134431052
Short name T1419
Test name
Test status
Simulation time 39787048 ps
CPU time 0.73 seconds
Started Mar 17 01:29:22 PM PDT 24
Finished Mar 17 01:29:23 PM PDT 24
Peak memory 204836 kb
Host smart-96fc3cbd-ac9d-402e-8639-9db3cab59d69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134431052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
134431052
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.3527432696
Short name T878
Test name
Test status
Simulation time 27495113 ps
CPU time 0.73 seconds
Started Mar 17 03:13:46 PM PDT 24
Finished Mar 17 03:13:47 PM PDT 24
Peak memory 205060 kb
Host smart-a097a059-226d-4fa4-bb29-b2f463fdb2fe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527432696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3
527432696
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.280027501
Short name T1396
Test name
Test status
Simulation time 1695616118 ps
CPU time 3.51 seconds
Started Mar 17 01:29:19 PM PDT 24
Finished Mar 17 01:29:23 PM PDT 24
Peak memory 233320 kb
Host smart-a1e1b76c-4e49-4ebc-bc13-5e383857dfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280027501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.280027501
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.4069162190
Short name T967
Test name
Test status
Simulation time 46021586 ps
CPU time 2.78 seconds
Started Mar 17 03:13:44 PM PDT 24
Finished Mar 17 03:13:47 PM PDT 24
Peak memory 233616 kb
Host smart-151f4aeb-6f9f-4891-864b-6a235a7affb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069162190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.4069162190
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.1516159089
Short name T516
Test name
Test status
Simulation time 25548786 ps
CPU time 0.74 seconds
Started Mar 17 01:29:17 PM PDT 24
Finished Mar 17 01:29:18 PM PDT 24
Peak memory 206288 kb
Host smart-920e5bc5-d053-4537-a2d1-c6b1a0afa443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516159089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1516159089
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2126977963
Short name T805
Test name
Test status
Simulation time 32403770 ps
CPU time 0.76 seconds
Started Mar 17 03:13:34 PM PDT 24
Finished Mar 17 03:13:35 PM PDT 24
Peak memory 206164 kb
Host smart-9ac4ce9c-d388-44a5-8e73-91d5bfacec93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126977963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2126977963
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1669941803
Short name T811
Test name
Test status
Simulation time 20398782051 ps
CPU time 76.91 seconds
Started Mar 17 01:29:18 PM PDT 24
Finished Mar 17 01:30:35 PM PDT 24
Peak memory 264412 kb
Host smart-ddacf20a-f34c-462b-9422-690aaabcdce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669941803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1669941803
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.434274939
Short name T1179
Test name
Test status
Simulation time 2940750089 ps
CPU time 40 seconds
Started Mar 17 03:13:43 PM PDT 24
Finished Mar 17 03:14:23 PM PDT 24
Peak memory 250824 kb
Host smart-5dc16dfc-6cbd-40a4-b1fe-631304af56cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434274939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.434274939
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1725769770
Short name T712
Test name
Test status
Simulation time 4982901905 ps
CPU time 34.72 seconds
Started Mar 17 01:29:15 PM PDT 24
Finished Mar 17 01:29:50 PM PDT 24
Peak memory 220316 kb
Host smart-e485f189-b56f-4b6b-a7d3-904281261a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725769770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1725769770
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3246321190
Short name T1509
Test name
Test status
Simulation time 24827814603 ps
CPU time 86.54 seconds
Started Mar 17 03:13:44 PM PDT 24
Finished Mar 17 03:15:11 PM PDT 24
Peak memory 247352 kb
Host smart-97ef3803-d7f2-49cb-b839-c8426ab116e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246321190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3246321190
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.67107872
Short name T9
Test name
Test status
Simulation time 53001933748 ps
CPU time 92.92 seconds
Started Mar 17 01:29:32 PM PDT 24
Finished Mar 17 01:31:05 PM PDT 24
Peak memory 240492 kb
Host smart-e3adc3e1-0ef4-4141-a5f1-f3b906032ed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67107872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.67107872
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1936579207
Short name T618
Test name
Test status
Simulation time 4742067153 ps
CPU time 13.19 seconds
Started Mar 17 03:13:44 PM PDT 24
Finished Mar 17 03:13:58 PM PDT 24
Peak memory 233548 kb
Host smart-66409b09-333b-4334-a183-c101dbc729c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936579207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1936579207
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1969522795
Short name T589
Test name
Test status
Simulation time 2352244646 ps
CPU time 10.29 seconds
Started Mar 17 01:29:15 PM PDT 24
Finished Mar 17 01:29:26 PM PDT 24
Peak memory 233356 kb
Host smart-3732ba3e-e8c7-4b54-ab2b-ce5b5764c714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969522795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1969522795
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2070057212
Short name T1727
Test name
Test status
Simulation time 160645627 ps
CPU time 2.62 seconds
Started Mar 17 03:13:39 PM PDT 24
Finished Mar 17 03:13:42 PM PDT 24
Peak memory 233236 kb
Host smart-1eb0f5a1-3268-4569-8128-a3e0e981b8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2070057212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2070057212
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_intercept.4211317229
Short name T1366
Test name
Test status
Simulation time 2048275554 ps
CPU time 9.52 seconds
Started Mar 17 01:29:24 PM PDT 24
Finished Mar 17 01:29:34 PM PDT 24
Peak memory 234244 kb
Host smart-511b3e59-6161-4d5b-9651-038826342d1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211317229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.4211317229
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.4188276179
Short name T1201
Test name
Test status
Simulation time 2610279780 ps
CPU time 7.76 seconds
Started Mar 17 03:13:40 PM PDT 24
Finished Mar 17 03:13:48 PM PDT 24
Peak memory 218536 kb
Host smart-4f1fc629-f50c-43ec-bc0f-b3d64478e1c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188276179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.4188276179
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.692526763
Short name T662
Test name
Test status
Simulation time 4192281892 ps
CPU time 18.87 seconds
Started Mar 17 01:29:23 PM PDT 24
Finished Mar 17 01:29:42 PM PDT 24
Peak memory 238652 kb
Host smart-8e61e1e2-9509-4a3b-b227-49df6d5d3465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692526763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.692526763
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_mem_parity.3406170891
Short name T894
Test name
Test status
Simulation time 33333159 ps
CPU time 1.08 seconds
Started Mar 17 01:29:16 PM PDT 24
Finished Mar 17 01:29:17 PM PDT 24
Peak memory 216432 kb
Host smart-018ad63a-e1b1-464d-851a-4e330fbc5749
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406170891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 6.spi_device_mem_parity.3406170891
Directory /workspace/6.spi_device_mem_parity/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.2635418531
Short name T176
Test name
Test status
Simulation time 2714629760 ps
CPU time 8.26 seconds
Started Mar 17 03:13:39 PM PDT 24
Finished Mar 17 03:13:47 PM PDT 24
Peak memory 233516 kb
Host smart-f9d905a9-8ca6-44ae-9cee-d7472edcf923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635418531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.2635418531
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.489063654
Short name T972
Test name
Test status
Simulation time 15226455036 ps
CPU time 41.29 seconds
Started Mar 17 01:29:17 PM PDT 24
Finished Mar 17 01:29:59 PM PDT 24
Peak memory 251544 kb
Host smart-1a404696-66ac-432c-ab69-7ed1fa3f7b97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489063654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
489063654
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1195738305
Short name T1243
Test name
Test status
Simulation time 602652480 ps
CPU time 6.3 seconds
Started Mar 17 03:13:39 PM PDT 24
Finished Mar 17 03:13:45 PM PDT 24
Peak memory 234908 kb
Host smart-d4130ee2-3f3a-4474-9b9c-fc165f720d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195738305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1195738305
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1885407317
Short name T853
Test name
Test status
Simulation time 21254218684 ps
CPU time 18.82 seconds
Started Mar 17 01:29:16 PM PDT 24
Finished Mar 17 01:29:35 PM PDT 24
Peak memory 237776 kb
Host smart-6627677b-7645-4db5-9d84-8daf80cb6423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885407317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1885407317
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.3769603772
Short name T461
Test name
Test status
Simulation time 17933966 ps
CPU time 0.76 seconds
Started Mar 17 01:29:16 PM PDT 24
Finished Mar 17 01:29:17 PM PDT 24
Peak memory 215780 kb
Host smart-34bb9b08-86a5-481f-81ee-88fbb254c060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3769603772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.3769603772
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_ram_cfg.4081156651
Short name T845
Test name
Test status
Simulation time 25653322 ps
CPU time 0.72 seconds
Started Mar 17 03:13:40 PM PDT 24
Finished Mar 17 03:13:41 PM PDT 24
Peak memory 216056 kb
Host smart-1e7423d6-b785-4f05-b951-745a03a01be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081156651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_ram_cfg.4081156651
Directory /workspace/6.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2150596842
Short name T1202
Test name
Test status
Simulation time 2764309034 ps
CPU time 3.93 seconds
Started Mar 17 01:29:23 PM PDT 24
Finished Mar 17 01:29:27 PM PDT 24
Peak memory 222448 kb
Host smart-3e279389-4b67-472e-bd13-ae2301edb878
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2150596842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2150596842
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.31736319
Short name T1089
Test name
Test status
Simulation time 1278995170 ps
CPU time 4.28 seconds
Started Mar 17 03:13:45 PM PDT 24
Finished Mar 17 03:13:49 PM PDT 24
Peak memory 219120 kb
Host smart-2da7a062-d891-4c79-8f54-18bdaad9de0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=31736319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct
.31736319
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3420427502
Short name T513
Test name
Test status
Simulation time 33057596 ps
CPU time 0.95 seconds
Started Mar 17 01:29:23 PM PDT 24
Finished Mar 17 01:29:24 PM PDT 24
Peak memory 206048 kb
Host smart-54d07bb7-ce3a-409d-a768-eae06900cc33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420427502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3420427502
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3609540665
Short name T1679
Test name
Test status
Simulation time 836101861 ps
CPU time 1.13 seconds
Started Mar 17 03:13:43 PM PDT 24
Finished Mar 17 03:13:45 PM PDT 24
Peak memory 206624 kb
Host smart-3bbc828b-ab8f-43b5-b2e3-6521d45b8546
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609540665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3609540665
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.4129365916
Short name T1791
Test name
Test status
Simulation time 20195329961 ps
CPU time 59.56 seconds
Started Mar 17 03:13:39 PM PDT 24
Finished Mar 17 03:14:39 PM PDT 24
Peak memory 216172 kb
Host smart-e9f4811d-988b-4e40-b1c7-852b51c5e18e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4129365916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.4129365916
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.884230254
Short name T527
Test name
Test status
Simulation time 1716232174 ps
CPU time 5.01 seconds
Started Mar 17 01:29:17 PM PDT 24
Finished Mar 17 01:29:22 PM PDT 24
Peak memory 215820 kb
Host smart-20b37d4c-2d1f-4e35-b020-549cb6aee710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884230254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.884230254
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3056315385
Short name T1706
Test name
Test status
Simulation time 20976516814 ps
CPU time 18.12 seconds
Started Mar 17 03:13:39 PM PDT 24
Finished Mar 17 03:13:57 PM PDT 24
Peak memory 216152 kb
Host smart-23a23a87-9ed8-413c-a939-9baeb5f13b26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056315385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3056315385
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.4030671328
Short name T855
Test name
Test status
Simulation time 29806299692 ps
CPU time 6.24 seconds
Started Mar 17 01:29:15 PM PDT 24
Finished Mar 17 01:29:22 PM PDT 24
Peak memory 215940 kb
Host smart-a72e5ccf-cab6-43b0-b64a-adb2985b0034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030671328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.4030671328
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1770299722
Short name T478
Test name
Test status
Simulation time 847420885 ps
CPU time 2.89 seconds
Started Mar 17 03:13:38 PM PDT 24
Finished Mar 17 03:13:41 PM PDT 24
Peak memory 216104 kb
Host smart-18d7bad3-589c-44d7-8094-6f7944e6d5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1770299722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1770299722
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.564819552
Short name T1767
Test name
Test status
Simulation time 174644675 ps
CPU time 1.32 seconds
Started Mar 17 01:29:19 PM PDT 24
Finished Mar 17 01:29:21 PM PDT 24
Peak memory 215780 kb
Host smart-cf92f3f4-3b8c-4fc8-922e-fc250758f808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564819552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.564819552
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2017537839
Short name T1787
Test name
Test status
Simulation time 45127651 ps
CPU time 0.93 seconds
Started Mar 17 01:29:16 PM PDT 24
Finished Mar 17 01:29:17 PM PDT 24
Peak memory 206160 kb
Host smart-71ea7c49-d520-4b33-928d-e8922aae3b75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017537839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2017537839
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.280280886
Short name T1269
Test name
Test status
Simulation time 171979084 ps
CPU time 0.93 seconds
Started Mar 17 03:13:38 PM PDT 24
Finished Mar 17 03:13:39 PM PDT 24
Peak memory 206496 kb
Host smart-f3e3c47b-344f-4866-8a0d-a7425c0053db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280280886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.280280886
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2680557993
Short name T1708
Test name
Test status
Simulation time 434855822 ps
CPU time 7.33 seconds
Started Mar 17 01:29:16 PM PDT 24
Finished Mar 17 01:29:24 PM PDT 24
Peak memory 245920 kb
Host smart-20124347-f8fc-4973-beda-24ba5844bc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680557993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2680557993
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_upload.4160475268
Short name T746
Test name
Test status
Simulation time 508464945 ps
CPU time 3.01 seconds
Started Mar 17 03:13:46 PM PDT 24
Finished Mar 17 03:13:49 PM PDT 24
Peak memory 233444 kb
Host smart-9371f240-9872-4aa0-9ba9-82f8c951f314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160475268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.4160475268
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.2670601254
Short name T1090
Test name
Test status
Simulation time 47220309 ps
CPU time 0.74 seconds
Started Mar 17 01:29:26 PM PDT 24
Finished Mar 17 01:29:27 PM PDT 24
Peak memory 205344 kb
Host smart-181dd6e9-02bf-46af-afd7-3d2cf751fb1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670601254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2
670601254
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.467538808
Short name T336
Test name
Test status
Simulation time 16511032 ps
CPU time 0.74 seconds
Started Mar 17 03:13:45 PM PDT 24
Finished Mar 17 03:13:46 PM PDT 24
Peak memory 205060 kb
Host smart-83ec42ab-c161-424c-9df9-525ed6dad5a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467538808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.467538808
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.370766430
Short name T1139
Test name
Test status
Simulation time 2852147804 ps
CPU time 9.77 seconds
Started Mar 17 03:13:48 PM PDT 24
Finished Mar 17 03:13:58 PM PDT 24
Peak memory 220420 kb
Host smart-13a6f955-96b1-48b4-99b2-0204ef723c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370766430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.370766430
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.3898873717
Short name T719
Test name
Test status
Simulation time 116365312 ps
CPU time 2.98 seconds
Started Mar 17 01:29:22 PM PDT 24
Finished Mar 17 01:29:25 PM PDT 24
Peak memory 232912 kb
Host smart-893a68d1-7f12-4937-97a9-ff333d64e739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898873717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3898873717
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.27856574
Short name T1273
Test name
Test status
Simulation time 49290558 ps
CPU time 0.87 seconds
Started Mar 17 01:29:32 PM PDT 24
Finished Mar 17 01:29:33 PM PDT 24
Peak memory 204940 kb
Host smart-2e0dbab1-07ae-48f1-b5e7-501a732b9b10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27856574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.27856574
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.857829787
Short name T359
Test name
Test status
Simulation time 20267454 ps
CPU time 0.8 seconds
Started Mar 17 03:13:43 PM PDT 24
Finished Mar 17 03:13:44 PM PDT 24
Peak memory 206532 kb
Host smart-8e564a90-22e2-4657-8230-cdc285bf7522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857829787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.857829787
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.629860966
Short name T633
Test name
Test status
Simulation time 28737833260 ps
CPU time 134.97 seconds
Started Mar 17 03:13:48 PM PDT 24
Finished Mar 17 03:16:03 PM PDT 24
Peak memory 256984 kb
Host smart-86336737-5f77-4578-82fc-d04bf990ff0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629860966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.629860966
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.6511110
Short name T696
Test name
Test status
Simulation time 8824166370 ps
CPU time 87.87 seconds
Started Mar 17 01:29:23 PM PDT 24
Finished Mar 17 01:30:51 PM PDT 24
Peak memory 256032 kb
Host smart-c0084e64-1e7e-40e3-b385-7b7d70d6c07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6511110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.6511110
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3164160355
Short name T268
Test name
Test status
Simulation time 12599614781 ps
CPU time 76.05 seconds
Started Mar 17 03:13:49 PM PDT 24
Finished Mar 17 03:15:05 PM PDT 24
Peak memory 252896 kb
Host smart-1fdb1d8d-f6eb-4431-bb83-57da4cb2434d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164160355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3164160355
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3315702429
Short name T1426
Test name
Test status
Simulation time 6048324399 ps
CPU time 66.79 seconds
Started Mar 17 01:29:27 PM PDT 24
Finished Mar 17 01:30:34 PM PDT 24
Peak memory 249828 kb
Host smart-e69dc1e9-1ba1-480d-8714-3a92b39ba788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315702429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3315702429
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.1777392525
Short name T2
Test name
Test status
Simulation time 2168501157 ps
CPU time 13.73 seconds
Started Mar 17 01:29:22 PM PDT 24
Finished Mar 17 01:29:36 PM PDT 24
Peak memory 236632 kb
Host smart-8d9a59a5-3b51-4d7e-8bd3-26c194a7238f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777392525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.1777392525
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3779951669
Short name T408
Test name
Test status
Simulation time 1236558406 ps
CPU time 15.73 seconds
Started Mar 17 03:13:51 PM PDT 24
Finished Mar 17 03:14:07 PM PDT 24
Peak memory 232480 kb
Host smart-98f100d4-d4d6-4644-80cf-0a59b4dd4e63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779951669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3779951669
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_intercept.2429612057
Short name T374
Test name
Test status
Simulation time 982076275 ps
CPU time 4.62 seconds
Started Mar 17 03:13:46 PM PDT 24
Finished Mar 17 03:13:51 PM PDT 24
Peak memory 218620 kb
Host smart-7d3c376b-6ba7-47bd-8b20-9e84c977038c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429612057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.2429612057
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4008215243
Short name T1312
Test name
Test status
Simulation time 818751692 ps
CPU time 5.34 seconds
Started Mar 17 01:29:23 PM PDT 24
Finished Mar 17 01:29:28 PM PDT 24
Peak memory 233168 kb
Host smart-d033e005-d99e-481d-9f85-fc851d2c0c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008215243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4008215243
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3236535173
Short name T212
Test name
Test status
Simulation time 2175971217 ps
CPU time 11.24 seconds
Started Mar 17 03:13:45 PM PDT 24
Finished Mar 17 03:13:56 PM PDT 24
Peak memory 226748 kb
Host smart-b362506b-b077-4fcb-bd68-e20a0a58e60a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236535173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3236535173
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3814366102
Short name T334
Test name
Test status
Simulation time 502174322 ps
CPU time 3.77 seconds
Started Mar 17 01:29:32 PM PDT 24
Finished Mar 17 01:29:36 PM PDT 24
Peak memory 217560 kb
Host smart-71e19285-c79c-4944-8bb0-68928d2f9933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814366102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3814366102
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_mem_parity.176864811
Short name T1508
Test name
Test status
Simulation time 57358218 ps
CPU time 1.12 seconds
Started Mar 17 01:29:22 PM PDT 24
Finished Mar 17 01:29:24 PM PDT 24
Peak memory 216412 kb
Host smart-930d2c7a-fbbc-4c15-b056-d76c9772a9c3
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176864811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TE
ST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name
7.spi_device_mem_parity.176864811
Directory /workspace/7.spi_device_mem_parity/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.2806343731
Short name T679
Test name
Test status
Simulation time 7409449980 ps
CPU time 21.11 seconds
Started Mar 17 03:13:43 PM PDT 24
Finished Mar 17 03:14:05 PM PDT 24
Peak memory 238156 kb
Host smart-df50803f-bd0e-497e-9db1-e0145df00c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806343731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.2806343731
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3386489302
Short name T1607
Test name
Test status
Simulation time 5053045707 ps
CPU time 8.17 seconds
Started Mar 17 01:29:21 PM PDT 24
Finished Mar 17 01:29:29 PM PDT 24
Peak memory 217628 kb
Host smart-d0602d6a-839c-498b-8378-63d59af371de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386489302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3386489302
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.1629036471
Short name T559
Test name
Test status
Simulation time 5394283886 ps
CPU time 10.26 seconds
Started Mar 17 01:29:20 PM PDT 24
Finished Mar 17 01:29:31 PM PDT 24
Peak memory 247700 kb
Host smart-a5022dba-6f42-4730-a8d2-9f624b635c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629036471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1629036471
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.3742257338
Short name T747
Test name
Test status
Simulation time 1307150489 ps
CPU time 5.72 seconds
Started Mar 17 03:13:43 PM PDT 24
Finished Mar 17 03:13:49 PM PDT 24
Peak memory 221156 kb
Host smart-0fe6948c-82c7-4bc9-86cc-5e169b048e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742257338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.3742257338
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.2720537879
Short name T1216
Test name
Test status
Simulation time 17049988 ps
CPU time 0.76 seconds
Started Mar 17 03:13:44 PM PDT 24
Finished Mar 17 03:13:45 PM PDT 24
Peak memory 216040 kb
Host smart-e4734607-406b-4ee0-9a7e-33298c1c940c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720537879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.2720537879
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_ram_cfg.3378643730
Short name T1372
Test name
Test status
Simulation time 45566841 ps
CPU time 0.74 seconds
Started Mar 17 01:29:22 PM PDT 24
Finished Mar 17 01:29:23 PM PDT 24
Peak memory 215752 kb
Host smart-3f02d0a3-85ca-4142-9ced-cfff0f85caad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378643730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_ram_cfg.3378643730
Directory /workspace/7.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1005365104
Short name T1883
Test name
Test status
Simulation time 1443712577 ps
CPU time 6.25 seconds
Started Mar 17 03:13:47 PM PDT 24
Finished Mar 17 03:13:53 PM PDT 24
Peak memory 222716 kb
Host smart-b211ab72-03b2-4ba2-b249-a6c25ac92c92
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1005365104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1005365104
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.173952990
Short name T1668
Test name
Test status
Simulation time 4471475022 ps
CPU time 4.87 seconds
Started Mar 17 01:29:32 PM PDT 24
Finished Mar 17 01:29:37 PM PDT 24
Peak memory 221852 kb
Host smart-388cd04d-3ba6-44f5-9c8d-a8f4ff63d4ab
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=173952990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.173952990
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3178943675
Short name T867
Test name
Test status
Simulation time 317072215886 ps
CPU time 1077.76 seconds
Started Mar 17 03:13:47 PM PDT 24
Finished Mar 17 03:31:45 PM PDT 24
Peak memory 286028 kb
Host smart-2556aace-98b9-4339-a8b9-69297349a7bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178943675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3178943675
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.768541695
Short name T274
Test name
Test status
Simulation time 324207677825 ps
CPU time 1153.18 seconds
Started Mar 17 01:29:25 PM PDT 24
Finished Mar 17 01:48:38 PM PDT 24
Peak memory 283564 kb
Host smart-b056fd1b-84c1-46ce-b621-e3e2c482a7cd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768541695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.768541695
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.1524808308
Short name T1844
Test name
Test status
Simulation time 2144149651 ps
CPU time 37.63 seconds
Started Mar 17 01:29:21 PM PDT 24
Finished Mar 17 01:29:59 PM PDT 24
Peak memory 215876 kb
Host smart-cee1bda2-9fb4-400a-8bcb-77334ea98b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524808308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.1524808308
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.825597560
Short name T1902
Test name
Test status
Simulation time 19566124954 ps
CPU time 30.99 seconds
Started Mar 17 03:13:46 PM PDT 24
Finished Mar 17 03:14:17 PM PDT 24
Peak memory 216284 kb
Host smart-d8091344-dbfa-41a5-8cba-bad9de7bb93e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825597560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.825597560
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.275976903
Short name T1630
Test name
Test status
Simulation time 5233981208 ps
CPU time 8.68 seconds
Started Mar 17 03:13:43 PM PDT 24
Finished Mar 17 03:13:52 PM PDT 24
Peak memory 216108 kb
Host smart-ba191485-bcf6-4363-a208-3dcb0d0bb0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275976903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.275976903
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.69586528
Short name T705
Test name
Test status
Simulation time 2870331501 ps
CPU time 7.75 seconds
Started Mar 17 01:29:21 PM PDT 24
Finished Mar 17 01:29:28 PM PDT 24
Peak memory 215864 kb
Host smart-99f68bd8-fb76-4780-85be-bb56d18fa0e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69586528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.69586528
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1937731356
Short name T1571
Test name
Test status
Simulation time 190651982 ps
CPU time 2.53 seconds
Started Mar 17 03:13:43 PM PDT 24
Finished Mar 17 03:13:46 PM PDT 24
Peak memory 207840 kb
Host smart-65f91516-8941-42e5-875b-42c143958426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937731356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1937731356
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.4214642856
Short name T1839
Test name
Test status
Simulation time 75403611 ps
CPU time 2.63 seconds
Started Mar 17 01:29:23 PM PDT 24
Finished Mar 17 01:29:25 PM PDT 24
Peak memory 215836 kb
Host smart-5ce47319-38c6-4e0f-b06a-be3b582557bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214642856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.4214642856
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1383496280
Short name T940
Test name
Test status
Simulation time 154334594 ps
CPU time 0.83 seconds
Started Mar 17 01:29:23 PM PDT 24
Finished Mar 17 01:29:23 PM PDT 24
Peak memory 205216 kb
Host smart-17ba55c8-b94a-46e8-bf9e-fbb61ed6541e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383496280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1383496280
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.213424395
Short name T1878
Test name
Test status
Simulation time 21755694 ps
CPU time 0.72 seconds
Started Mar 17 03:13:44 PM PDT 24
Finished Mar 17 03:13:45 PM PDT 24
Peak memory 205416 kb
Host smart-ecaf8623-5034-4de7-9a74-48651241b6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=213424395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.213424395
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.667216006
Short name T429
Test name
Test status
Simulation time 8057362175 ps
CPU time 26.88 seconds
Started Mar 17 03:13:48 PM PDT 24
Finished Mar 17 03:14:14 PM PDT 24
Peak memory 233644 kb
Host smart-0ade787a-d640-461e-bd66-b6a76b88467d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667216006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.667216006
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_upload.899330610
Short name T1124
Test name
Test status
Simulation time 3298643179 ps
CPU time 9.2 seconds
Started Mar 17 01:29:24 PM PDT 24
Finished Mar 17 01:29:33 PM PDT 24
Peak memory 226504 kb
Host smart-6110a507-f18d-4d20-8d77-4f8b6ae1d753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899330610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.899330610
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.1196148164
Short name T341
Test name
Test status
Simulation time 13994059 ps
CPU time 0.71 seconds
Started Mar 17 03:14:03 PM PDT 24
Finished Mar 17 03:14:03 PM PDT 24
Peak memory 205044 kb
Host smart-bc1bd29b-4e89-4c53-8a77-4631fd7ef7dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196148164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.1
196148164
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2418310400
Short name T617
Test name
Test status
Simulation time 36468814 ps
CPU time 0.74 seconds
Started Mar 17 01:29:33 PM PDT 24
Finished Mar 17 01:29:34 PM PDT 24
Peak memory 204796 kb
Host smart-fd854bcc-50db-4532-8827-b0cb7ad365f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418310400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
418310400
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1888794365
Short name T1761
Test name
Test status
Simulation time 99057493 ps
CPU time 2.66 seconds
Started Mar 17 03:13:57 PM PDT 24
Finished Mar 17 03:14:00 PM PDT 24
Peak memory 233612 kb
Host smart-f043e893-ebea-4788-972a-0e1736902dbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888794365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1888794365
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.33333418
Short name T641
Test name
Test status
Simulation time 2345907124 ps
CPU time 2.53 seconds
Started Mar 17 01:29:27 PM PDT 24
Finished Mar 17 01:29:30 PM PDT 24
Peak memory 218364 kb
Host smart-c7d7c80a-e243-4182-bd39-5448ca6be8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33333418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.33333418
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1214787083
Short name T950
Test name
Test status
Simulation time 45154355 ps
CPU time 0.73 seconds
Started Mar 17 01:29:26 PM PDT 24
Finished Mar 17 01:29:27 PM PDT 24
Peak memory 205188 kb
Host smart-cb580e51-4a4e-4c13-9094-49f93873fa60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214787083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1214787083
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.743857146
Short name T977
Test name
Test status
Simulation time 36534427 ps
CPU time 0.83 seconds
Started Mar 17 03:13:53 PM PDT 24
Finished Mar 17 03:13:54 PM PDT 24
Peak memory 206140 kb
Host smart-f4149d83-26e9-431a-b3aa-7fd10788ef46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743857146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.743857146
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3539851572
Short name T775
Test name
Test status
Simulation time 75220150892 ps
CPU time 77.04 seconds
Started Mar 17 01:29:26 PM PDT 24
Finished Mar 17 01:30:43 PM PDT 24
Peak memory 235768 kb
Host smart-ffb606fa-8a03-413a-93b6-a55cd04da49d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539851572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3539851572
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.868635560
Short name T655
Test name
Test status
Simulation time 44313825509 ps
CPU time 152.54 seconds
Started Mar 17 03:13:57 PM PDT 24
Finished Mar 17 03:16:30 PM PDT 24
Peak memory 249000 kb
Host smart-a65bd925-d3e2-4966-9089-10c0b2a2bf10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868635560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.868635560
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1764322497
Short name T1025
Test name
Test status
Simulation time 18838214766 ps
CPU time 145.22 seconds
Started Mar 17 03:13:56 PM PDT 24
Finished Mar 17 03:16:21 PM PDT 24
Peak memory 249148 kb
Host smart-ea8bf9f9-86de-4fd0-bec2-18a3b6daa115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764322497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1764322497
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.1777288379
Short name T250
Test name
Test status
Simulation time 89462622241 ps
CPU time 219 seconds
Started Mar 17 01:29:27 PM PDT 24
Finished Mar 17 01:33:06 PM PDT 24
Peak memory 256536 kb
Host smart-68966ee1-a55e-46a1-a8b6-ed59ee961682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777288379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1777288379
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.3310493035
Short name T270
Test name
Test status
Simulation time 99723877474 ps
CPU time 328.83 seconds
Started Mar 17 03:13:57 PM PDT 24
Finished Mar 17 03:19:26 PM PDT 24
Peak memory 249032 kb
Host smart-28b8a8e0-5ee4-45d6-b496-8724266f2c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310493035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.3310493035
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.71116263
Short name T1816
Test name
Test status
Simulation time 108439727437 ps
CPU time 192.07 seconds
Started Mar 17 01:29:28 PM PDT 24
Finished Mar 17 01:32:40 PM PDT 24
Peak memory 256260 kb
Host smart-24b12282-7817-4f77-ac5b-5a932b3457f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71116263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.71116263
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1402948842
Short name T1330
Test name
Test status
Simulation time 7309480409 ps
CPU time 26.71 seconds
Started Mar 17 01:29:30 PM PDT 24
Finished Mar 17 01:29:57 PM PDT 24
Peak memory 237748 kb
Host smart-38824d82-67b1-44cb-87ee-b754a74a77d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402948842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1402948842
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3904881968
Short name T1294
Test name
Test status
Simulation time 2168375750 ps
CPU time 15.28 seconds
Started Mar 17 03:13:55 PM PDT 24
Finished Mar 17 03:14:10 PM PDT 24
Peak memory 252000 kb
Host smart-b3bb19d5-158d-4ca7-bd09-8f71e3e9006d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904881968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3904881968
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1504743833
Short name T1055
Test name
Test status
Simulation time 465174755 ps
CPU time 5.36 seconds
Started Mar 17 01:29:29 PM PDT 24
Finished Mar 17 01:29:34 PM PDT 24
Peak memory 234228 kb
Host smart-c2ee5751-96df-43be-aaf8-379180ec6578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504743833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1504743833
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_intercept.761922675
Short name T521
Test name
Test status
Simulation time 2587372648 ps
CPU time 5.7 seconds
Started Mar 17 03:13:52 PM PDT 24
Finished Mar 17 03:13:58 PM PDT 24
Peak memory 218692 kb
Host smart-c81a8163-61d3-4e4a-a25c-8b409af0a23f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761922675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.761922675
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.1091547027
Short name T1389
Test name
Test status
Simulation time 3093506197 ps
CPU time 12.09 seconds
Started Mar 17 03:13:53 PM PDT 24
Finished Mar 17 03:14:05 PM PDT 24
Peak memory 234476 kb
Host smart-43c17c84-80de-4cd4-b5fe-3cdf4d45daa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091547027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.1091547027
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3252108199
Short name T1900
Test name
Test status
Simulation time 5523231454 ps
CPU time 18.54 seconds
Started Mar 17 01:29:28 PM PDT 24
Finished Mar 17 01:29:47 PM PDT 24
Peak memory 233924 kb
Host smart-ecc20249-85ee-40f5-a075-d91cda873999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252108199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3252108199
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_mem_parity.1035544063
Short name T1390
Test name
Test status
Simulation time 94385131 ps
CPU time 1.01 seconds
Started Mar 17 01:29:28 PM PDT 24
Finished Mar 17 01:29:29 PM PDT 24
Peak memory 216500 kb
Host smart-92727534-816c-4c78-b58d-8ffd12a5e41b
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035544063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 8.spi_device_mem_parity.1035544063
Directory /workspace/8.spi_device_mem_parity/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2007039520
Short name T625
Test name
Test status
Simulation time 5905379972 ps
CPU time 8.6 seconds
Started Mar 17 03:13:52 PM PDT 24
Finished Mar 17 03:14:01 PM PDT 24
Peak memory 240728 kb
Host smart-189966fc-bd7e-4e19-8bee-f5c30bc5439f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007039520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2007039520
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2431358083
Short name T976
Test name
Test status
Simulation time 1969937364 ps
CPU time 9.96 seconds
Started Mar 17 01:29:27 PM PDT 24
Finished Mar 17 01:29:37 PM PDT 24
Peak memory 237704 kb
Host smart-b92b0ee7-29a3-4f1c-814d-40884c066fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431358083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2431358083
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1977076227
Short name T1206
Test name
Test status
Simulation time 1122385532 ps
CPU time 7.49 seconds
Started Mar 17 01:29:26 PM PDT 24
Finished Mar 17 01:29:34 PM PDT 24
Peak memory 233340 kb
Host smart-b267da4a-4020-4e74-9838-3c8f08432200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977076227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1977076227
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.4184456857
Short name T1378
Test name
Test status
Simulation time 188343049 ps
CPU time 2.87 seconds
Started Mar 17 03:13:52 PM PDT 24
Finished Mar 17 03:13:55 PM PDT 24
Peak memory 218468 kb
Host smart-8b676061-e2e7-4248-b1a9-fd54b2871e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184456857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.4184456857
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.474770648
Short name T603
Test name
Test status
Simulation time 26886853 ps
CPU time 0.75 seconds
Started Mar 17 03:13:53 PM PDT 24
Finished Mar 17 03:13:54 PM PDT 24
Peak memory 216056 kb
Host smart-3042c335-408f-4627-a91c-cf1c2e1398d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474770648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.474770648
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_ram_cfg.924617359
Short name T922
Test name
Test status
Simulation time 17900121 ps
CPU time 0.74 seconds
Started Mar 17 01:29:28 PM PDT 24
Finished Mar 17 01:29:29 PM PDT 24
Peak memory 215768 kb
Host smart-1dcc7f03-f5bc-4913-a188-79db3dd5c4c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924617359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_ram_cfg.924617359
Directory /workspace/8.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.2411336104
Short name T72
Test name
Test status
Simulation time 97710797 ps
CPU time 3.2 seconds
Started Mar 17 01:29:27 PM PDT 24
Finished Mar 17 01:29:30 PM PDT 24
Peak memory 222396 kb
Host smart-371d799d-8c32-43d6-a145-12d1a001167b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2411336104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.2411336104
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3896966342
Short name T482
Test name
Test status
Simulation time 689798213 ps
CPU time 4.93 seconds
Started Mar 17 03:13:55 PM PDT 24
Finished Mar 17 03:14:00 PM PDT 24
Peak memory 222588 kb
Host smart-b3dbb822-2ef1-477b-8308-e9a436bd3c32
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3896966342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3896966342
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2898892949
Short name T1351
Test name
Test status
Simulation time 173322355498 ps
CPU time 294.68 seconds
Started Mar 17 01:29:28 PM PDT 24
Finished Mar 17 01:34:23 PM PDT 24
Peak memory 251080 kb
Host smart-17608518-f811-4591-a6d1-2237471ec249
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898892949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2898892949
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2900567400
Short name T1574
Test name
Test status
Simulation time 295072034325 ps
CPU time 625.59 seconds
Started Mar 17 03:14:01 PM PDT 24
Finished Mar 17 03:24:27 PM PDT 24
Peak memory 289764 kb
Host smart-fc99c30c-f7e9-4a26-a8e4-904521f6d8a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900567400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2900567400
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.2884104736
Short name T292
Test name
Test status
Simulation time 2929155811 ps
CPU time 8.65 seconds
Started Mar 17 01:29:26 PM PDT 24
Finished Mar 17 01:29:35 PM PDT 24
Peak memory 215924 kb
Host smart-8f2f9e2e-61ac-4d4b-b725-ce875d07c95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884104736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2884104736
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.4002646691
Short name T1562
Test name
Test status
Simulation time 11481899775 ps
CPU time 64.42 seconds
Started Mar 17 03:13:54 PM PDT 24
Finished Mar 17 03:14:58 PM PDT 24
Peak memory 216104 kb
Host smart-e29c9e8b-3573-476b-8ce7-8d27ae845ca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002646691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.4002646691
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2456709347
Short name T497
Test name
Test status
Simulation time 491976795 ps
CPU time 1.8 seconds
Started Mar 17 03:13:54 PM PDT 24
Finished Mar 17 03:13:56 PM PDT 24
Peak memory 207492 kb
Host smart-81a3dab6-7cb7-42f5-8d93-c4af45f27ec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456709347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2456709347
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3683019132
Short name T858
Test name
Test status
Simulation time 1475830230 ps
CPU time 7.95 seconds
Started Mar 17 01:29:27 PM PDT 24
Finished Mar 17 01:29:35 PM PDT 24
Peak memory 215772 kb
Host smart-1f78bb08-f3bb-4c32-af6b-85f828fe0ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683019132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3683019132
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2553150416
Short name T1528
Test name
Test status
Simulation time 240917938 ps
CPU time 3.09 seconds
Started Mar 17 03:13:53 PM PDT 24
Finished Mar 17 03:13:56 PM PDT 24
Peak memory 216192 kb
Host smart-d79a87dd-e0ae-4d44-a313-f761d099de8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553150416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2553150416
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3650708588
Short name T1058
Test name
Test status
Simulation time 42043113 ps
CPU time 0.93 seconds
Started Mar 17 01:29:27 PM PDT 24
Finished Mar 17 01:29:28 PM PDT 24
Peak memory 206184 kb
Host smart-808ee6c5-836a-42c5-93f3-b522c625fcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650708588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3650708588
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2647422434
Short name T1384
Test name
Test status
Simulation time 160544297 ps
CPU time 0.95 seconds
Started Mar 17 03:13:54 PM PDT 24
Finished Mar 17 03:13:55 PM PDT 24
Peak memory 205420 kb
Host smart-acbd8fd4-4243-4e26-aedb-41fd5eaad407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2647422434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2647422434
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.3450630424
Short name T651
Test name
Test status
Simulation time 30878103 ps
CPU time 0.74 seconds
Started Mar 17 01:29:27 PM PDT 24
Finished Mar 17 01:29:28 PM PDT 24
Peak memory 205120 kb
Host smart-070e33c4-07fb-47a9-8785-6dd2f052f3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450630424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3450630424
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1935238861
Short name T47
Test name
Test status
Simulation time 2080689630 ps
CPU time 8.51 seconds
Started Mar 17 01:29:26 PM PDT 24
Finished Mar 17 01:29:35 PM PDT 24
Peak memory 239604 kb
Host smart-2220bae1-d18e-4008-b77e-d2a17c307c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935238861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1935238861
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_upload.2558539677
Short name T539
Test name
Test status
Simulation time 1617573313 ps
CPU time 4.78 seconds
Started Mar 17 03:13:52 PM PDT 24
Finished Mar 17 03:13:57 PM PDT 24
Peak memory 218888 kb
Host smart-f914524f-95dc-47b7-a974-cd6dfeeaa787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558539677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2558539677
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.2495581471
Short name T724
Test name
Test status
Simulation time 36756336 ps
CPU time 0.73 seconds
Started Mar 17 03:14:09 PM PDT 24
Finished Mar 17 03:14:10 PM PDT 24
Peak memory 205328 kb
Host smart-b3ab7f00-1f13-4c00-8b7d-b9c3eeb059bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495581471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.2
495581471
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3144739414
Short name T301
Test name
Test status
Simulation time 15505550 ps
CPU time 0.76 seconds
Started Mar 17 01:29:36 PM PDT 24
Finished Mar 17 01:29:37 PM PDT 24
Peak memory 204820 kb
Host smart-04bee50f-7d1d-4e95-bd23-f0c54523fe91
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144739414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
144739414
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.3906081280
Short name T1561
Test name
Test status
Simulation time 1603958222 ps
CPU time 2.95 seconds
Started Mar 17 03:14:04 PM PDT 24
Finished Mar 17 03:14:07 PM PDT 24
Peak memory 219360 kb
Host smart-48f72ce5-9624-4a75-90a2-158bbd362179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906081280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3906081280
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.636561207
Short name T1311
Test name
Test status
Simulation time 912472150 ps
CPU time 4.78 seconds
Started Mar 17 01:29:32 PM PDT 24
Finished Mar 17 01:29:37 PM PDT 24
Peak memory 232796 kb
Host smart-186c1ca2-16df-4f0a-9077-1e0f0e253883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636561207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.636561207
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2177832649
Short name T319
Test name
Test status
Simulation time 62314340 ps
CPU time 0.79 seconds
Started Mar 17 03:14:02 PM PDT 24
Finished Mar 17 03:14:03 PM PDT 24
Peak memory 206180 kb
Host smart-5f75a431-8987-4e4b-b5fa-7b18cbfe9c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177832649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2177832649
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.471844714
Short name T605
Test name
Test status
Simulation time 68473719 ps
CPU time 0.78 seconds
Started Mar 17 01:29:29 PM PDT 24
Finished Mar 17 01:29:29 PM PDT 24
Peak memory 206304 kb
Host smart-e35c8800-8039-41da-b385-ae27e304252d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471844714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.471844714
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.1924186199
Short name T1701
Test name
Test status
Simulation time 163047193671 ps
CPU time 179.31 seconds
Started Mar 17 03:14:05 PM PDT 24
Finished Mar 17 03:17:04 PM PDT 24
Peak memory 240728 kb
Host smart-c25d9fda-9a2f-4cea-951d-053e82c99ffd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924186199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.1924186199
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.3049688732
Short name T1906
Test name
Test status
Simulation time 16012944618 ps
CPU time 81.36 seconds
Started Mar 17 01:29:34 PM PDT 24
Finished Mar 17 01:30:55 PM PDT 24
Peak memory 252700 kb
Host smart-84140705-0717-4d55-8ced-7ca2e9df2123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049688732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3049688732
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2153202102
Short name T244
Test name
Test status
Simulation time 165236149000 ps
CPU time 405.44 seconds
Started Mar 17 03:14:03 PM PDT 24
Finished Mar 17 03:20:49 PM PDT 24
Peak memory 267432 kb
Host smart-b05823d3-8591-45aa-8cd4-6950f57d3dd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153202102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2153202102
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.4195995441
Short name T590
Test name
Test status
Simulation time 23815967718 ps
CPU time 86.09 seconds
Started Mar 17 01:29:36 PM PDT 24
Finished Mar 17 01:31:02 PM PDT 24
Peak memory 256980 kb
Host smart-90e8366b-603b-4665-90d3-860f6e67834f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195995441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.4195995441
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.236817882
Short name T1510
Test name
Test status
Simulation time 39182246823 ps
CPU time 48.28 seconds
Started Mar 17 01:29:32 PM PDT 24
Finished Mar 17 01:30:20 PM PDT 24
Peak memory 255288 kb
Host smart-4efb02fd-3557-45fa-bacb-797509ebe6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236817882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.
236817882
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.3993407417
Short name T577
Test name
Test status
Simulation time 3003736488 ps
CPU time 23.82 seconds
Started Mar 17 03:14:08 PM PDT 24
Finished Mar 17 03:14:33 PM PDT 24
Peak memory 232700 kb
Host smart-b83ce393-4686-4958-81f6-14714c9d341a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993407417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.3993407417
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2881128681
Short name T1102
Test name
Test status
Simulation time 27780934002 ps
CPU time 45.42 seconds
Started Mar 17 03:14:05 PM PDT 24
Finished Mar 17 03:14:51 PM PDT 24
Peak memory 240716 kb
Host smart-76a05f50-7fe6-49fb-aa0d-a704f47a1617
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2881128681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2881128681
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3933037452
Short name T1165
Test name
Test status
Simulation time 41692094136 ps
CPU time 45.03 seconds
Started Mar 17 01:29:35 PM PDT 24
Finished Mar 17 01:30:20 PM PDT 24
Peak memory 236128 kb
Host smart-f310c6c8-6ed3-4973-899b-eb64b0d2b519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933037452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3933037452
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_intercept.3574579730
Short name T1411
Test name
Test status
Simulation time 2629197074 ps
CPU time 4.51 seconds
Started Mar 17 03:14:06 PM PDT 24
Finished Mar 17 03:14:11 PM PDT 24
Peak memory 218952 kb
Host smart-80dd1b53-0cfb-4eec-ae09-2beaf735cade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574579730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3574579730
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_intercept.4097255309
Short name T424
Test name
Test status
Simulation time 2915476982 ps
CPU time 6.14 seconds
Started Mar 17 01:29:33 PM PDT 24
Finished Mar 17 01:29:39 PM PDT 24
Peak memory 218300 kb
Host smart-86c673d3-03e7-491b-a0d3-159c0c262cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097255309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.4097255309
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1026274769
Short name T723
Test name
Test status
Simulation time 5552575407 ps
CPU time 11.13 seconds
Started Mar 17 01:29:27 PM PDT 24
Finished Mar 17 01:29:38 PM PDT 24
Peak memory 232196 kb
Host smart-22a0b9fd-b062-4257-8ac7-8de8ede30205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026274769 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1026274769
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.282525712
Short name T1043
Test name
Test status
Simulation time 48954046576 ps
CPU time 31.14 seconds
Started Mar 17 03:14:05 PM PDT 24
Finished Mar 17 03:14:36 PM PDT 24
Peak memory 240344 kb
Host smart-686e5a94-6dd6-4c1b-b2f2-bb2224d62de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282525712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.282525712
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_mem_parity.1614435878
Short name T1797
Test name
Test status
Simulation time 104129021 ps
CPU time 1.04 seconds
Started Mar 17 01:29:28 PM PDT 24
Finished Mar 17 01:29:29 PM PDT 24
Peak memory 217756 kb
Host smart-87f973c4-d7b7-4c83-9123-db7acce42f2a
User root
Command /workspace/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614435878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_T
EST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_nam
e 9.spi_device_mem_parity.1614435878
Directory /workspace/9.spi_device_mem_parity/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1834931565
Short name T26
Test name
Test status
Simulation time 342075157 ps
CPU time 3.31 seconds
Started Mar 17 03:14:06 PM PDT 24
Finished Mar 17 03:14:10 PM PDT 24
Peak memory 233472 kb
Host smart-ead75f30-b6ee-4eba-8c6a-e4d7fa36e8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834931565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1834931565
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3246025316
Short name T1289
Test name
Test status
Simulation time 547799807 ps
CPU time 6.56 seconds
Started Mar 17 01:29:29 PM PDT 24
Finished Mar 17 01:29:36 PM PDT 24
Peak memory 236064 kb
Host smart-ca81333b-4aa3-4dce-9ad1-9e973fc42780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246025316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3246025316
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2216316609
Short name T1814
Test name
Test status
Simulation time 351630475 ps
CPU time 3.2 seconds
Started Mar 17 01:29:28 PM PDT 24
Finished Mar 17 01:29:31 PM PDT 24
Peak memory 217636 kb
Host smart-2bcad6a9-0680-4d8b-9cc4-3a307bcfc090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216316609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2216316609
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3526124325
Short name T201
Test name
Test status
Simulation time 564502955 ps
CPU time 2.71 seconds
Started Mar 17 03:14:05 PM PDT 24
Finished Mar 17 03:14:08 PM PDT 24
Peak memory 218424 kb
Host smart-ccc73638-e21a-4e20-b7f8-f242883b8349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3526124325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3526124325
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.2571570042
Short name T883
Test name
Test status
Simulation time 18810480 ps
CPU time 0.75 seconds
Started Mar 17 03:14:02 PM PDT 24
Finished Mar 17 03:14:03 PM PDT 24
Peak memory 216036 kb
Host smart-8b903e85-8bb9-4760-ade5-3ef932a1d3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571570042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.2571570042
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_ram_cfg.3970647275
Short name T490
Test name
Test status
Simulation time 18183182 ps
CPU time 0.72 seconds
Started Mar 17 01:29:31 PM PDT 24
Finished Mar 17 01:29:31 PM PDT 24
Peak memory 215756 kb
Host smart-23a46282-edb2-48dc-ba6c-ed634346bb96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970647275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_ram_cfg.3970647275
Directory /workspace/9.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3844166712
Short name T386
Test name
Test status
Simulation time 8161508720 ps
CPU time 5.88 seconds
Started Mar 17 01:29:33 PM PDT 24
Finished Mar 17 01:29:39 PM PDT 24
Peak memory 222352 kb
Host smart-1f607ffd-b33f-46f2-bf60-b224d1f0029b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3844166712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3844166712
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3929319666
Short name T1857
Test name
Test status
Simulation time 1070694514 ps
CPU time 5.45 seconds
Started Mar 17 03:14:05 PM PDT 24
Finished Mar 17 03:14:11 PM PDT 24
Peak memory 219012 kb
Host smart-ebac567b-d800-4e10-820a-8df3696001ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3929319666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3929319666
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4138897694
Short name T511
Test name
Test status
Simulation time 131665470500 ps
CPU time 282.53 seconds
Started Mar 17 03:14:09 PM PDT 24
Finished Mar 17 03:18:52 PM PDT 24
Peak memory 266436 kb
Host smart-49852637-67cd-4cff-b778-a68d6f0d1ace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138897694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4138897694
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.4149079583
Short name T1057
Test name
Test status
Simulation time 206602974 ps
CPU time 1.03 seconds
Started Mar 17 01:29:33 PM PDT 24
Finished Mar 17 01:29:34 PM PDT 24
Peak memory 206608 kb
Host smart-63338cae-f937-427a-bca1-3ccdc05e422e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149079583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.4149079583
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.2684615493
Short name T503
Test name
Test status
Simulation time 465315357 ps
CPU time 5.68 seconds
Started Mar 17 03:14:02 PM PDT 24
Finished Mar 17 03:14:07 PM PDT 24
Peak memory 216156 kb
Host smart-da847a19-b060-4664-b154-aed4533f6ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684615493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.2684615493
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3972747307
Short name T553
Test name
Test status
Simulation time 11313023435 ps
CPU time 45.96 seconds
Started Mar 17 01:29:27 PM PDT 24
Finished Mar 17 01:30:13 PM PDT 24
Peak memory 216196 kb
Host smart-def4f92d-f511-4b97-8f01-b4fdb915232b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972747307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3972747307
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1221430796
Short name T1064
Test name
Test status
Simulation time 8923391117 ps
CPU time 24.59 seconds
Started Mar 17 01:29:27 PM PDT 24
Finished Mar 17 01:29:52 PM PDT 24
Peak memory 215884 kb
Host smart-6fe67711-67da-4e79-a723-d047434cfd74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221430796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1221430796
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.2023241841
Short name T1867
Test name
Test status
Simulation time 1492257143 ps
CPU time 6.22 seconds
Started Mar 17 03:13:59 PM PDT 24
Finished Mar 17 03:14:06 PM PDT 24
Peak memory 216060 kb
Host smart-4a32c709-eb7c-4be4-9997-eead37755f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023241841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2023241841
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1324995653
Short name T798
Test name
Test status
Simulation time 110060096 ps
CPU time 1.22 seconds
Started Mar 17 01:29:26 PM PDT 24
Finished Mar 17 01:29:28 PM PDT 24
Peak memory 207516 kb
Host smart-614e599d-3ee2-47a4-a210-77af4accd43f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1324995653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1324995653
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3787971855
Short name T1631
Test name
Test status
Simulation time 6436522604 ps
CPU time 11.5 seconds
Started Mar 17 03:14:04 PM PDT 24
Finished Mar 17 03:14:15 PM PDT 24
Peak memory 216216 kb
Host smart-8fe0152c-87cc-4db3-9e73-59e4b1552e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787971855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3787971855
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3117579106
Short name T1907
Test name
Test status
Simulation time 48026767 ps
CPU time 0.9 seconds
Started Mar 17 01:29:33 PM PDT 24
Finished Mar 17 01:29:34 PM PDT 24
Peak memory 205612 kb
Host smart-5a25c9e3-577e-4e78-a431-a1fe16d89e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3117579106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3117579106
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.4005637748
Short name T1012
Test name
Test status
Simulation time 500419414 ps
CPU time 0.97 seconds
Started Mar 17 03:14:04 PM PDT 24
Finished Mar 17 03:14:05 PM PDT 24
Peak memory 206388 kb
Host smart-8ac84342-b799-42ae-915f-59c6529b616a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005637748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4005637748
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.212049132
Short name T432
Test name
Test status
Simulation time 10656882438 ps
CPU time 10.37 seconds
Started Mar 17 03:14:05 PM PDT 24
Finished Mar 17 03:14:15 PM PDT 24
Peak memory 227340 kb
Host smart-4158b9eb-681a-4631-928f-831f0ecd78cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212049132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.212049132
Directory /workspace/9.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_upload.2869789507
Short name T1449
Test name
Test status
Simulation time 10604729293 ps
CPU time 12.43 seconds
Started Mar 17 01:29:27 PM PDT 24
Finished Mar 17 01:29:40 PM PDT 24
Peak memory 228272 kb
Host smart-990828d7-87fc-494c-9c67-4c22742af271
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869789507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2869789507
Directory /workspace/9.spi_device_upload/latest
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