SPI_DEVICE/1R1W Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	10.740m	980.336ms	50	50	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.250s	37.299us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.770s	42.569us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	37.490s	5.763ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	24.510s	3.779ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.140s	218.223us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.770s	42.569us	20	20	100.00
		spi_device_csr_aliasing	24.510s	3.779ms	4	5	80.00
V1	mem_walk	spi_device_mem_walk	0.660s	14.191us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.180s	89.632us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	0.850s	20.079us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	0.760s	7.783us	0	20	0.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	16.829us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	9.590s	342.995us	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	9.590s	342.995us	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	33.920s	51.390ms	50	50	100.00
		spi_device_tpm_sts_read	1.160s	151.284us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	59.470s	21.026ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	46.030s	17.403ms	50	50	100.00
		spi_device_flash_all	8.911m	107.848ms	48	50	96.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	43.260s	13.396ms	50	50	100.00
		spi_device_flash_all	8.911m	107.848ms	48	50	96.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	43.260s	13.396ms	50	50	100.00
		spi_device_flash_all	8.911m	107.848ms	48	50	96.00
V2	cmd_info_slots	spi_device_flash_all	8.911m	107.848ms	48	50	96.00
V2	cmd_read_status	spi_device_intercept	13.430s	30.767ms	50	50	100.00
		spi_device_flash_all	8.911m	107.848ms	48	50	96.00
V2	cmd_read_jedec	spi_device_intercept	13.430s	30.767ms	50	50	100.00
		spi_device_flash_all	8.911m	107.848ms	48	50	96.00
V2	cmd_read_sfdp	spi_device_intercept	13.430s	30.767ms	50	50	100.00
		spi_device_flash_all	8.911m	107.848ms	48	50	96.00
V2	cmd_fast_read	spi_device_intercept	13.430s	30.767ms	50	50	100.00
		spi_device_flash_all	8.911m	107.848ms	48	50	96.00
V2	cmd_read_pipeline	spi_device_intercept	13.430s	30.767ms	50	50	100.00
		spi_device_flash_all	8.911m	107.848ms	48	50	96.00
V2	flash_cmd_upload	spi_device_upload	36.790s	51.449ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	43.930s	60.599ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	43.930s	60.599ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	43.930s	60.599ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.228m	38.449ms	50	50	100.00
		spi_device_read_buffer_direct	7.230s	10.192ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	43.930s	60.599ms	50	50	100.00
		spi_device_flash_all	8.911m	107.848ms	48	50	96.00
V2	quad_spi	spi_device_flash_all	8.911m	107.848ms	48	50	96.00
V2	dual_spi	spi_device_flash_all	8.911m	107.848ms	48	50	96.00
V2	4b_3b_feature	spi_device_cfg_cmd	11.300s	51.213ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	11.300s	51.213ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	10.740m	980.336ms	50	50	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	12.278m	398.403ms	49	50	98.00
V2	stress_all	spi_device_stress_all	24.482m	187.618ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	18.319us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.820s	53.745us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.490s	812.453us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.490s	812.453us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.250s	37.299us	5	5	100.00
		spi_device_csr_rw	2.770s	42.569us	20	20	100.00
		spi_device_csr_aliasing	24.510s	3.779ms	4	5	80.00
		spi_device_same_csr_outstanding	4.260s	226.135us	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.250s	37.299us	5	5	100.00
		spi_device_csr_rw	2.770s	42.569us	20	20	100.00
		spi_device_csr_aliasing	24.510s	3.779ms	4	5	80.00
		spi_device_same_csr_outstanding	4.260s	226.135us	20	20	100.00
V2		TOTAL			957	980	97.65
V2S	tl_intg_err	spi_device_sec_cm	1.320s	81.427us	5	5	100.00
		spi_device_tl_intg_err	23.350s	1.030ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	23.350s	1.030ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1096	1120	97.86

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	19	86.36
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.95	98.30	94.34	98.61	89.36	97.00	95.84	98.17

Failure Buckets

UVM_ERROR (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[*]) has 20 failures:

Test spi_device_mem_parity has 20 failures.

0.spi_device_mem_parity.39233418343753586559845620232812139782671334664209988680479141708883294878080
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

  UVM_ERROR @   7410256 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[26])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @   7410256 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @   7410256 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[922])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

1.spi_device_mem_parity.99211762346829184778872571616245102561299112883828797228490183755821636191694
Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/1.spi_device_mem_parity/latest/run.log

  UVM_ERROR @  17250549 ps: (uvm_hdl_vcs.c:992) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[94])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name
  UVM_ERROR @  17250549 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
  UVM_ERROR @  17250549 ps: (uvm_hdl_vcs.c:1142) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.gen_generic.u_impl_generic.mem[990])
   Either the name is incorrect, or you may not have PLI/ACC visibility to that name

... and 18 more failures.

Exit reason: Error: User command failed Job returned non-zero exit code has 1 failures:

Test spi_device_csr_aliasing has 1 failures.

0.spi_device_csr_aliasing.97264564579448665745906557530772010595092346038188608602585302299290587691140
Log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/0.spi_device_csr_aliasing/latest/run.log

  [make]: simulate
  cd /workspace/0.spi_device_csr_aliasing/latest && /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937649284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.2937649284
  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Mar 24 12:36 2024
  Cannot find license file.
  Make sure that you have a license file and that your
  LM_LICENSE_FILE is pointing to the right location.
  
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255

UVM_ERROR (spi_device_scoreboard.sv:1070) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_flash_all has 1 failures.

2.spi_device_flash_all.109153532064211838667139628725503969586746531758106491448398715625911326827230
Line 259, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 20761104319 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x221824) != exp '{'{other_status:'h1beab4, wel:'h0, busy:'h0}}
  UVM_INFO @ 20918388814 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 10/20
  UVM_INFO @ 22927004065 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 11/20
  UVM_INFO @ 24095814878 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 12/20
  UVM_INFO @ 25601598930 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 13/20

UVM_WARNING (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "busy" while containing register "spi_device_reg_block.flash_status" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem. has 1 failures:

Test spi_device_flash_all has 1 failures.

23.spi_device_flash_all.91676070146035808368478229211167759417325111764983480598424126330967766648924
Line 261, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest/run.log

  UVM_WARNING @ 5016861863 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "busy" while containing register "spi_device_reg_block.flash_status" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 5016861863 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "wel" while containing register "spi_device_reg_block.flash_status" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_WARNING @ 5016861863 ps: (uvm_reg_field.svh:1264) [UVM/FLD/SET/BSY] Setting the value of field "status" while containing register "spi_device_reg_block.flash_status" is being accessed may result in loss of desired field value. A race condition between threads concurrently accessing the register model is the likely cause of the problem.
  UVM_INFO @ 5175269607 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 12/18
  UVM_INFO @ 5695256616 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 13/18

UVM_ERROR (spi_device_scoreboard.sv:478) [scoreboard] Check failed flash_status_q.size <= * (* [*] vs * [*]) has 1 failures:
- Test spi_device_flash_and_tpm_min_idle has 1 failures.
  - 47.spi_device_flash_and_tpm_min_idle.66069323653760559666372457821186664559384003724819637554513102224578665001149
    Line 269, in log /container/opentitan-public/scratch/os_regression/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest/run.log
```
  UVM_ERROR @ 17691939369 ps: (spi_device_scoreboard.sv:478) [uvm_test_top.env.scoreboard] Check failed flash_status_q.size <= 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 18292844369 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```