Unified Coverage Report :: Module :: prim_sram_arbiter

Module : prim_sram_arbiter

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	83.33

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_upload.u_arbiter	66.67	100.00	33.33
tb.dut.u_sys_sram_arbiter	83.33	100.00	66.67
tb.dut.u_spi_tpm.u_arbiter	91.67	100.00	83.33

---

Module Instance : tb.dut.u_upload.u_arbiter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
66.67	100.00	33.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
70.02	92.11	45.10			71.43	71.43

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.37	100.00	86.11		100.00	95.74	100.00	u_upload

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
u_req_fifo	59.07	84.62	36.11			55.56	60.00

---

Module Instance : tb.dut.u_sys_sram_arbiter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	100.00	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.65	100.00	76.47			96.43	85.71

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.61	93.86	84.31	96.94		87.50	95.45	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25
u_req_fifo	92.36	100.00	75.00			94.44	100.00

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	100.00	83.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
87.57	100.00	76.47			92.86	80.95

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.66	99.29	91.20		91.67	96.13	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
u_req_fifo	92.36	100.00	75.00			94.44	100.00

Line Coverage for Module : prim_sram_arbiter ( parameter N=3,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 )
Line Coverage for Module self-instances :

SCORE	LINE
66.67	100.00

tb.dut.u_upload.u_arbiter

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	3	3
67	1	1
68	1	1
69	1	1
70	1	1
125	1	1
147	1	1
150	3	3
151	3	3

---

Line Coverage for Module : prim_sram_arbiter ( parameter N=2,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 )
Line Coverage for Module self-instances :

SCORE	LINE
91.67	100.00

tb.dut.u_spi_tpm.u_arbiter

	Line No.	Total	Covered	Percent
TOTAL		12	12	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	2	2
67	1	1
68	1	1
69	1	1
70	1	1
125	1	1
147	1	1
150	2	2
151	2	2

---

Line Coverage for Module : prim_sram_arbiter ( parameter N=5,SramDw=32,SramAw=10,ArbiterImpl="PPC",EnMask=1 )
Line Coverage for Module self-instances :

SCORE	LINE
83.33	100.00

tb.dut.u_sys_sram_arbiter

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	5	5
67	1	1
68	1	1
69	1	1
70	1	1
125	1	1
147	1	1
150	5	5
151	5	5

---

Cond Coverage for Module : prim_sram_arbiter

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T16,T28
1	1	Covered	T5,T8,T9

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T5,T8,T9

Line Coverage for Instance : tb.dut.u_upload.u_arbiter

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	3	3
67	1	1
68	1	1
69	1	1
70	1	1
125	1	1
147	1	1
150	3	3
151	3	3

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter

	Total	Covered	Percent
Conditions	6	2	33.33
Logical	6	2	33.33
Non-Logical	0	0
Event	0	0

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T9
1	1	Not Covered

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter

	Line No.	Total	Covered	Percent
TOTAL		21	21	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	5	5
67	1	1
68	1	1
69	1	1
70	1	1
125	1	1
147	1	1
150	5	5
151	5	5

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter

	Total	Covered	Percent
Conditions	6	4	66.67
Logical	6	4	66.67
Non-Logical	0	0
Event	0	0

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Covered	T5,T8,T9

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T4
1	1	Covered	T5,T8,T9

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter

	Line No.	Total	Covered	Percent
TOTAL		12	12	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	56	1	1	100.00
CONT_ASSIGN	67	1	1	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	70	1	1	100.00
CONT_ASSIGN	125	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	150	1	1	100.00
CONT_ASSIGN	151	1	1	100.00
CONT_ASSIGN	151	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_sram_arbiter.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
56	2	2
67	1	1
68	1	1
69	1	1
70	1	1
125	1	1
147	1	1
150	2	2
151	2	2

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       125
 EXPRESSION (sram_rvalid_i & ((|steer)))
             ------1------   -----2----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T8,T16,T28
1	1	Covered	T5,T8,T16

 LINE       132
 EXPRESSION (sram_req_o & ((~sram_write_o)))
             -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T5,T8,T16
1	1	Covered	T5,T8,T16