Unified Coverage Report :: Module :: prim_arbiter_ppc

Module : prim_arbiter_ppc

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.61	100.00	85.19			100.00	81.25

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb	85.69	100.00	77.78			90.00	75.00
tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb	90.97	100.00	88.89			100.00	75.00
tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb	92.53	100.00	88.89			100.00	81.25

---

Module Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.69	100.00	77.78			90.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.97	100.00	88.89			100.00	75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.53	100.00	88.89			100.00	81.25

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.33	100.00	66.67					u_sys_sram_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 + N=5,DW=75,EnDataPort=1,IdxW=3 )
Line Coverage for Module self-instances :

SCORE	LINE
90.97	100.00

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

SCORE	LINE
92.53	100.00

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Line Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Line Coverage for Module self-instances :

SCORE	LINE
85.69	100.00

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=2,DW=75,EnDataPort=1,IdxW=1 )
Cond Coverage for Module self-instances :

SCORE	COND
85.69	77.78

tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T16
1	0	Covered	T5,T8,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T5,T8,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=3,DW=75,EnDataPort=1,IdxW=2 )
Cond Coverage for Module self-instances :

SCORE	COND
90.97	88.89

tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T5,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Cond Coverage for Module : prim_arbiter_ppc ( parameter N=5,DW=75,EnDataPort=1,IdxW=3 )
Cond Coverage for Module self-instances :

SCORE	COND
92.53	88.89

tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Module : prim_arbiter_ppc

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_arbiter_ppc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	676439027	543129260	0	0
CheckNGreaterZero_A	2718	2718	0	0
GntImpliesReady_A	676439027	3141643	0	0
GntImpliesValid_A	676439027	3141643	0	0
GrantKnown_A	676439027	543129260	0	0
IdxKnown_A	676439027	543129260	0	0
IndexIsCorrect_A	676439027	3141643	0	0
LockArbDecision_A	676439027	0	0	0
NoReadyValidNoGrant_A	676439027	0	0	0
ReadyAndValidImplyGrant_A	676439027	3141643	0	0
ReqAndReadyImplyGrant_A	676439027	3141643	0	0
ReqImpliesValid_A	676439027	3141643	0	0
ReqStaysHighUntilGranted0_M	676439027	0	0	0
RoundRobin_A	676439027	4	0	906
ValidKnown_A	676439027	543129260	0	0
gen_data_port_assertion.DataFlow_A	676439027	3141643	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	543129260	0	0
T1	155468	155400	0	0
T2	7625	5394	0	0
T3	12272	12172	0	0
T4	61843	61771	0	0
T5	974485	778993	0	0
T6	1085	958	0	0
T7	4977	3841	0	0
T8	2314960	1538738	0	0
T9	2322800	1394447	0	0
T10	1774	1708	0	0
T11	1586590	788972	0	0
T12	171504	85568	0	0
T13	14364	14364	0	0
T14	69258	68848	0	0
T15	0	576	0	0
T16	0	179696	0	0
T17	0	71216	0	0
T18	0	936	0	0
T19	0	3472	0	0
T31	115218	0	0	0
T42	0	54832	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2718	2718	0	0
T1	3	3	0	0
T2	3	3	0	0
T3	3	3	0	0
T4	3	3	0	0
T5	3	3	0	0
T6	3	3	0	0
T7	3	3	0	0
T8	3	3	0	0
T9	3	3	0	0
T10	3	3	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	3141643	0	0
T1	79578	1856	0	0
T2	7625	0	0	0
T3	10028	832	0	0
T4	47239	832	0	0
T5	974485	5977	0	0
T6	1085	0	0	0
T7	4977	0	0	0
T8	2314960	15648	0	0
T9	2322800	15180	0	0
T10	1774	0	0	0
T11	1586590	13104	0	0
T12	171504	832	0	0
T13	28728	832	0	0
T14	138516	0	0	0
T16	0	8207	0	0
T17	0	2991	0	0
T19	0	282	0	0
T22	0	2238	0	0
T26	0	3883	0	0
T28	0	7800	0	0
T29	0	9379	0	0
T30	0	832	0	0
T31	230436	2	0	0
T43	0	2458	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	3141643	0	0
T1	79578	1856	0	0
T2	7625	0	0	0
T3	10028	832	0	0
T4	47239	832	0	0
T5	974485	5977	0	0
T6	1085	0	0	0
T7	4977	0	0	0
T8	2314960	15648	0	0
T9	2322800	15180	0	0
T10	1774	0	0	0
T11	1586590	13104	0	0
T12	171504	832	0	0
T13	28728	832	0	0
T14	138516	0	0	0
T16	0	8207	0	0
T17	0	2991	0	0
T19	0	282	0	0
T22	0	2238	0	0
T26	0	3883	0	0
T28	0	7800	0	0
T29	0	9379	0	0
T30	0	832	0	0
T31	230436	2	0	0
T43	0	2458	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	543129260	0	0
T1	155468	155400	0	0
T2	7625	5394	0	0
T3	12272	12172	0	0
T4	61843	61771	0	0
T5	974485	778993	0	0
T6	1085	958	0	0
T7	4977	3841	0	0
T8	2314960	1538738	0	0
T9	2322800	1394447	0	0
T10	1774	1708	0	0
T11	1586590	788972	0	0
T12	171504	85568	0	0
T13	14364	14364	0	0
T14	69258	68848	0	0
T15	0	576	0	0
T16	0	179696	0	0
T17	0	71216	0	0
T18	0	936	0	0
T19	0	3472	0	0
T31	115218	0	0	0
T42	0	54832	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	543129260	0	0
T1	155468	155400	0	0
T2	7625	5394	0	0
T3	12272	12172	0	0
T4	61843	61771	0	0
T5	974485	778993	0	0
T6	1085	958	0	0
T7	4977	3841	0	0
T8	2314960	1538738	0	0
T9	2322800	1394447	0	0
T10	1774	1708	0	0
T11	1586590	788972	0	0
T12	171504	85568	0	0
T13	14364	14364	0	0
T14	69258	68848	0	0
T15	0	576	0	0
T16	0	179696	0	0
T17	0	71216	0	0
T18	0	936	0	0
T19	0	3472	0	0
T31	115218	0	0	0
T42	0	54832	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	3141643	0	0
T1	79578	1856	0	0
T2	7625	0	0	0
T3	10028	832	0	0
T4	47239	832	0	0
T5	974485	5977	0	0
T6	1085	0	0	0
T7	4977	0	0	0
T8	2314960	15648	0	0
T9	2322800	15180	0	0
T10	1774	0	0	0
T11	1586590	13104	0	0
T12	171504	832	0	0
T13	28728	832	0	0
T14	138516	0	0	0
T16	0	8207	0	0
T17	0	2991	0	0
T19	0	282	0	0
T22	0	2238	0	0
T26	0	3883	0	0
T28	0	7800	0	0
T29	0	9379	0	0
T30	0	832	0	0
T31	230436	2	0	0
T43	0	2458	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	3141643	0	0
T1	79578	1856	0	0
T2	7625	0	0	0
T3	10028	832	0	0
T4	47239	832	0	0
T5	974485	5977	0	0
T6	1085	0	0	0
T7	4977	0	0	0
T8	2314960	15648	0	0
T9	2322800	15180	0	0
T10	1774	0	0	0
T11	1586590	13104	0	0
T12	171504	832	0	0
T13	28728	832	0	0
T14	138516	0	0	0
T16	0	8207	0	0
T17	0	2991	0	0
T19	0	282	0	0
T22	0	2238	0	0
T26	0	3883	0	0
T28	0	7800	0	0
T29	0	9379	0	0
T30	0	832	0	0
T31	230436	2	0	0
T43	0	2458	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	3141643	0	0
T1	79578	1856	0	0
T2	7625	0	0	0
T3	10028	832	0	0
T4	47239	832	0	0
T5	974485	5977	0	0
T6	1085	0	0	0
T7	4977	0	0	0
T8	2314960	15648	0	0
T9	2322800	15180	0	0
T10	1774	0	0	0
T11	1586590	13104	0	0
T12	171504	832	0	0
T13	28728	832	0	0
T14	138516	0	0	0
T16	0	8207	0	0
T17	0	2991	0	0
T19	0	282	0	0
T22	0	2238	0	0
T26	0	3883	0	0
T28	0	7800	0	0
T29	0	9379	0	0
T30	0	832	0	0
T31	230436	2	0	0
T43	0	2458	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	3141643	0	0
T1	79578	1856	0	0
T2	7625	0	0	0
T3	10028	832	0	0
T4	47239	832	0	0
T5	974485	5977	0	0
T6	1085	0	0	0
T7	4977	0	0	0
T8	2314960	15648	0	0
T9	2322800	15180	0	0
T10	1774	0	0	0
T11	1586590	13104	0	0
T12	171504	832	0	0
T13	28728	832	0	0
T14	138516	0	0	0
T16	0	8207	0	0
T17	0	2991	0	0
T19	0	282	0	0
T22	0	2238	0	0
T26	0	3883	0	0
T28	0	7800	0	0
T29	0	9379	0	0
T30	0	832	0	0
T31	230436	2	0	0
T43	0	2458	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	4	0	906
T23	300730	1	0	1
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	910	0	0	1
T48	240978	0	0	1
T49	188757	0	0	1
T50	171970	0	0	1
T51	278523	0	0	1
T52	222457	0	0	1
T53	26227	0	0	1
T54	469735	0	0	1
T55	108387	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	543129260	0	0
T1	155468	155400	0	0
T2	7625	5394	0	0
T3	12272	12172	0	0
T4	61843	61771	0	0
T5	974485	778993	0	0
T6	1085	958	0	0
T7	4977	3841	0	0
T8	2314960	1538738	0	0
T9	2322800	1394447	0	0
T10	1774	1708	0	0
T11	1586590	788972	0	0
T12	171504	85568	0	0
T13	14364	14364	0	0
T14	69258	68848	0	0
T15	0	576	0	0
T16	0	179696	0	0
T17	0	71216	0	0
T18	0	936	0	0
T19	0	3472	0	0
T31	115218	0	0	0
T42	0	54832	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	676439027	3141643	0	0
T1	79578	1856	0	0
T2	7625	0	0	0
T3	10028	832	0	0
T4	47239	832	0	0
T5	974485	5977	0	0
T6	1085	0	0	0
T7	4977	0	0	0
T8	2314960	15648	0	0
T9	2322800	15180	0	0
T10	1774	0	0	0
T11	1586590	13104	0	0
T12	171504	832	0	0
T13	28728	832	0	0
T14	138516	0	0	0
T16	0	8207	0	0
T17	0	2991	0	0
T19	0	282	0	0
T22	0	2238	0	0
T26	0	3883	0	0
T28	0	7800	0	0
T29	0	9379	0	0
T30	0	832	0	0
T31	230436	2	0	0
T43	0	2458	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	7	77.78
Logical	9	7	77.78
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T16
1	0	Covered	T5,T8,T16

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T7
1	0	Unreachable
1	1	Covered	T5,T8,T16

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	9	90.00
TERNARY	76	2	1	50.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T8,T16
0	0	1	Unreachable
0	0	0	Covered	T5,T6,T7

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T16
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T16
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	131941413	27950326	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	131941413	622077	0	0
GntImpliesValid_A	131941413	622077	0	0
GrantKnown_A	131941413	27950326	0	0
IdxKnown_A	131941413	27950326	0	0
IndexIsCorrect_A	131941413	622077	0	0
LockArbDecision_A	131941413	0	0	0
NoReadyValidNoGrant_A	131941413	0	0	0
ReadyAndValidImplyGrant_A	131941413	622077	0	0
ReqAndReadyImplyGrant_A	131941413	622077	0	0
ReqImpliesValid_A	131941413	622077	0	0
ReqStaysHighUntilGranted0_M	131941413	0	0	0
RoundRobin_A	131941413	0	0	0
ValidKnown_A	131941413	27950326	0	0
gen_data_port_assertion.DataFlow_A	131941413	622077	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	27950326	0	0
T5	192832	61104	0	0
T6	72	72	0	0
T7	916	792	0	0
T8	769543	120512	0	0
T9	925468	0	0	0
T11	793295	0	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T15	0	576	0	0
T16	0	179696	0	0
T17	0	71216	0	0
T18	0	936	0	0
T19	0	3472	0	0
T31	115218	0	0	0
T42	0	54832	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	622077	0	0
T5	192832	2323	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	2819	0	0
T9	925468	0	0	0
T11	793295	0	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	4548	0	0
T17	0	2991	0	0
T19	0	282	0	0
T22	0	2225	0	0
T26	0	3625	0	0
T28	0	146	0	0
T29	0	6654	0	0
T31	115218	0	0	0
T43	0	2458	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	622077	0	0
T5	192832	2323	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	2819	0	0
T9	925468	0	0	0
T11	793295	0	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	4548	0	0
T17	0	2991	0	0
T19	0	282	0	0
T22	0	2225	0	0
T26	0	3625	0	0
T28	0	146	0	0
T29	0	6654	0	0
T31	115218	0	0	0
T43	0	2458	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	27950326	0	0
T5	192832	61104	0	0
T6	72	72	0	0
T7	916	792	0	0
T8	769543	120512	0	0
T9	925468	0	0	0
T11	793295	0	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T15	0	576	0	0
T16	0	179696	0	0
T17	0	71216	0	0
T18	0	936	0	0
T19	0	3472	0	0
T31	115218	0	0	0
T42	0	54832	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	27950326	0	0
T5	192832	61104	0	0
T6	72	72	0	0
T7	916	792	0	0
T8	769543	120512	0	0
T9	925468	0	0	0
T11	793295	0	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T15	0	576	0	0
T16	0	179696	0	0
T17	0	71216	0	0
T18	0	936	0	0
T19	0	3472	0	0
T31	115218	0	0	0
T42	0	54832	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	622077	0	0
T5	192832	2323	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	2819	0	0
T9	925468	0	0	0
T11	793295	0	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	4548	0	0
T17	0	2991	0	0
T19	0	282	0	0
T22	0	2225	0	0
T26	0	3625	0	0
T28	0	146	0	0
T29	0	6654	0	0
T31	115218	0	0	0
T43	0	2458	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	622077	0	0
T5	192832	2323	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	2819	0	0
T9	925468	0	0	0
T11	793295	0	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	4548	0	0
T17	0	2991	0	0
T19	0	282	0	0
T22	0	2225	0	0
T26	0	3625	0	0
T28	0	146	0	0
T29	0	6654	0	0
T31	115218	0	0	0
T43	0	2458	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	622077	0	0
T5	192832	2323	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	2819	0	0
T9	925468	0	0	0
T11	793295	0	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	4548	0	0
T17	0	2991	0	0
T19	0	282	0	0
T22	0	2225	0	0
T26	0	3625	0	0
T28	0	146	0	0
T29	0	6654	0	0
T31	115218	0	0	0
T43	0	2458	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	622077	0	0
T5	192832	2323	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	2819	0	0
T9	925468	0	0	0
T11	793295	0	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	4548	0	0
T17	0	2991	0	0
T19	0	282	0	0
T22	0	2225	0	0
T26	0	3625	0	0
T28	0	146	0	0
T29	0	6654	0	0
T31	115218	0	0	0
T43	0	2458	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	27950326	0	0
T5	192832	61104	0	0
T6	72	72	0	0
T7	916	792	0	0
T8	769543	120512	0	0
T9	925468	0	0	0
T11	793295	0	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T15	0	576	0	0
T16	0	179696	0	0
T17	0	71216	0	0
T18	0	936	0	0
T19	0	3472	0	0
T31	115218	0	0	0
T42	0	54832	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	622077	0	0
T5	192832	2323	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	2819	0	0
T9	925468	0	0	0
T11	793295	0	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	4548	0	0
T17	0	2991	0	0
T19	0	282	0	0
T22	0	2225	0	0
T26	0	3625	0	0
T28	0	146	0	0
T29	0	6654	0	0
T31	115218	0	0	0
T43	0	2458	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T5,T8,T9

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T4
1	0	Unreachable
1	1	Covered	T5,T8,T9

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T5,T8,T9
0	0	1	Unreachable
0	0	0	Covered	T1,T3,T4

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	12	75.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	12	75.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	131941413	102705757	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	131941413	540987	0	0
GntImpliesValid_A	131941413	540987	0	0
GrantKnown_A	131941413	102705757	0	0
IdxKnown_A	131941413	102705757	0	0
IndexIsCorrect_A	131941413	540987	0	0
LockArbDecision_A	131941413	0	0	0
NoReadyValidNoGrant_A	131941413	0	0	0
ReadyAndValidImplyGrant_A	131941413	540987	0	0
ReqAndReadyImplyGrant_A	131941413	540987	0	0
ReqImpliesValid_A	131941413	540987	0	0
ReqStaysHighUntilGranted0_M	131941413	0	0	0
RoundRobin_A	131941413	0	0	0
ValidKnown_A	131941413	102705757	0	0
gen_data_port_assertion.DataFlow_A	131941413	540987	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	102705757	0	0
T1	75890	75890	0	0
T3	2244	2244	0	0
T4	14604	14604	0	0
T5	192832	129164	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	642405	0	0
T9	925468	922591	0	0
T11	793295	788972	0	0
T12	85752	85568	0	0
T13	0	14364	0	0
T14	0	68848	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	540987	0	0
T5	192832	6	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	3713	0	0
T9	925468	6468	0	0
T11	793295	3611	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	3659	0	0
T22	0	13	0	0
T26	0	258	0	0
T28	0	7654	0	0
T29	0	2725	0	0
T31	115218	2	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	540987	0	0
T5	192832	6	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	3713	0	0
T9	925468	6468	0	0
T11	793295	3611	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	3659	0	0
T22	0	13	0	0
T26	0	258	0	0
T28	0	7654	0	0
T29	0	2725	0	0
T31	115218	2	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	102705757	0	0
T1	75890	75890	0	0
T3	2244	2244	0	0
T4	14604	14604	0	0
T5	192832	129164	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	642405	0	0
T9	925468	922591	0	0
T11	793295	788972	0	0
T12	85752	85568	0	0
T13	0	14364	0	0
T14	0	68848	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	102705757	0	0
T1	75890	75890	0	0
T3	2244	2244	0	0
T4	14604	14604	0	0
T5	192832	129164	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	642405	0	0
T9	925468	922591	0	0
T11	793295	788972	0	0
T12	85752	85568	0	0
T13	0	14364	0	0
T14	0	68848	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	540987	0	0
T5	192832	6	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	3713	0	0
T9	925468	6468	0	0
T11	793295	3611	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	3659	0	0
T22	0	13	0	0
T26	0	258	0	0
T28	0	7654	0	0
T29	0	2725	0	0
T31	115218	2	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	540987	0	0
T5	192832	6	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	3713	0	0
T9	925468	6468	0	0
T11	793295	3611	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	3659	0	0
T22	0	13	0	0
T26	0	258	0	0
T28	0	7654	0	0
T29	0	2725	0	0
T31	115218	2	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	540987	0	0
T5	192832	6	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	3713	0	0
T9	925468	6468	0	0
T11	793295	3611	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	3659	0	0
T22	0	13	0	0
T26	0	258	0	0
T28	0	7654	0	0
T29	0	2725	0	0
T31	115218	2	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	540987	0	0
T5	192832	6	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	3713	0	0
T9	925468	6468	0	0
T11	793295	3611	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	3659	0	0
T22	0	13	0	0
T26	0	258	0	0
T28	0	7654	0	0
T29	0	2725	0	0
T31	115218	2	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	102705757	0	0
T1	75890	75890	0	0
T3	2244	2244	0	0
T4	14604	14604	0	0
T5	192832	129164	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	642405	0	0
T9	925468	922591	0	0
T11	793295	788972	0	0
T12	85752	85568	0	0
T13	0	14364	0	0
T14	0	68848	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	131941413	540987	0	0
T5	192832	6	0	0
T6	72	0	0	0
T7	916	0	0	0
T8	769543	3713	0	0
T9	925468	6468	0	0
T11	793295	3611	0	0
T12	85752	0	0	0
T13	14364	0	0	0
T14	69258	0	0	0
T16	0	3659	0	0
T22	0	13	0	0
T26	0	258	0	0
T28	0	7654	0	0
T29	0	2725	0	0
T31	115218	2	0	0

Line Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	55	0	0
CONT_ASSIGN	75	1	1	100.00
CONT_ASSIGN	76	1	1	100.00
ALWAYS	82	3	3	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	96	5	5	100.00
ALWAYS	109	4	4	100.00
ALWAYS	124	4	4	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
55		unreachable
75	1	1
76	1	1
82	1	1
83	1	1
84	1	1
89	1	1
90	1	1
92	1	1
94	1	1
96	1	1
97	1	1
98	1	1
100	1	1
101	1	1
103		unreachable
			MISSING_ELSE
109	1	1
110	1	1
111	1	1
112	1	1
			MISSING_ELSE
124	1	1
125	1	1
126	1	1
127	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Covered	Percent
Conditions	9	8	88.89
Logical	9	8	88.89
Non-Logical	0	0
Event	0	0

 LINE       76
 EXPRESSION (((|gen_normal_case.masked_req)) ? gen_normal_case.masked_req : req_i)
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T8,T9

 LINE       84
 EXPRESSION (gen_normal_case.ppc_out[(i - 1)] | gen_normal_case.arb_req[i])
             ----------------1---------------   -------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T8,T9
1	0	Covered	T1,T3,T4

 LINE       90
 EXPRESSION (ready_i ? gen_normal_case.winner : '0)
             ---1---

-1-	Status	Tests
0	Unreachable
1	Covered	T1,T2,T3

 LINE       98
 EXPRESSION (valid_o && ready_i)
             ---1---    ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T1,T3,T4

 LINE       101
 EXPRESSION (valid_o && ((!ready_i)))
             ---1---    ------2-----

-1-	-2-	Status	Tests
0	1	Unreachable
1	0	Not Covered
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Line No.	Total	Covered	Percent
Branches		10	10	100.00
TERNARY	76	2	2	100.00
TERNARY	90	1	1	100.00
IF	96	3	3	100.00
IF	126	2	2	100.00
IF	111	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_ppc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	76	((|gen_normal_case.masked_req)) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	90	(ready_i) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Unreachable

	LineNo.	Expression
-1-:	96	if ((!rst_ni))
-2-:	98	if ((valid_o && ready_i))
-3-:	101	if ((valid_o && (!ready_i)))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T3,T4
0	0	1	Unreachable
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	126	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	111	if (gen_normal_case.winner[i])

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T4
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_sys_sram_arbiter.gen_arb_ppc.u_reqarb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	13	81.25
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	13	81.25

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	412556201	412473177	0	0
CheckNGreaterZero_A	906	906	0	0
GntImpliesReady_A	412556201	1978579	0	0
GntImpliesValid_A	412556201	1978579	0	0
GrantKnown_A	412556201	412473177	0	0
IdxKnown_A	412556201	412473177	0	0
IndexIsCorrect_A	412556201	1978579	0	0
LockArbDecision_A	412556201	0	0	0
NoReadyValidNoGrant_A	412556201	0	0	0
ReadyAndValidImplyGrant_A	412556201	1978579	0	0
ReqAndReadyImplyGrant_A	412556201	1978579	0	0
ReqImpliesValid_A	412556201	1978579	0	0
ReqStaysHighUntilGranted0_M	412556201	0	0	0
RoundRobin_A	412556201	4	0	906
ValidKnown_A	412556201	412473177	0	0
gen_data_port_assertion.DataFlow_A	412556201	1978579	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	412473177	0	0
T1	79578	79510	0	0
T2	7625	5394	0	0
T3	10028	9928	0	0
T4	47239	47167	0	0
T5	588821	588725	0	0
T6	941	886	0	0
T7	3145	3049	0	0
T8	775874	775821	0	0
T9	471864	471856	0	0
T10	1774	1708	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906	906	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	1978579	0	0
T1	79578	1856	0	0
T2	7625	0	0	0
T3	10028	832	0	0
T4	47239	832	0	0
T5	588821	3648	0	0
T6	941	0	0	0
T7	3145	0	0	0
T8	775874	9116	0	0
T9	471864	8712	0	0
T10	1774	0	0	0
T11	0	9493	0	0
T12	0	832	0	0
T13	0	832	0	0
T30	0	832	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	1978579	0	0
T1	79578	1856	0	0
T2	7625	0	0	0
T3	10028	832	0	0
T4	47239	832	0	0
T5	588821	3648	0	0
T6	941	0	0	0
T7	3145	0	0	0
T8	775874	9116	0	0
T9	471864	8712	0	0
T10	1774	0	0	0
T11	0	9493	0	0
T12	0	832	0	0
T13	0	832	0	0
T30	0	832	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	412473177	0	0
T1	79578	79510	0	0
T2	7625	5394	0	0
T3	10028	9928	0	0
T4	47239	47167	0	0
T5	588821	588725	0	0
T6	941	886	0	0
T7	3145	3049	0	0
T8	775874	775821	0	0
T9	471864	471856	0	0
T10	1774	1708	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	412473177	0	0
T1	79578	79510	0	0
T2	7625	5394	0	0
T3	10028	9928	0	0
T4	47239	47167	0	0
T5	588821	588725	0	0
T6	941	886	0	0
T7	3145	3049	0	0
T8	775874	775821	0	0
T9	471864	471856	0	0
T10	1774	1708	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	1978579	0	0
T1	79578	1856	0	0
T2	7625	0	0	0
T3	10028	832	0	0
T4	47239	832	0	0
T5	588821	3648	0	0
T6	941	0	0	0
T7	3145	0	0	0
T8	775874	9116	0	0
T9	471864	8712	0	0
T10	1774	0	0	0
T11	0	9493	0	0
T12	0	832	0	0
T13	0	832	0	0
T30	0	832	0	0

LockArbDecision_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	1978579	0	0
T1	79578	1856	0	0
T2	7625	0	0	0
T3	10028	832	0	0
T4	47239	832	0	0
T5	588821	3648	0	0
T6	941	0	0	0
T7	3145	0	0	0
T8	775874	9116	0	0
T9	471864	8712	0	0
T10	1774	0	0	0
T11	0	9493	0	0
T12	0	832	0	0
T13	0	832	0	0
T30	0	832	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	1978579	0	0
T1	79578	1856	0	0
T2	7625	0	0	0
T3	10028	832	0	0
T4	47239	832	0	0
T5	588821	3648	0	0
T6	941	0	0	0
T7	3145	0	0	0
T8	775874	9116	0	0
T9	471864	8712	0	0
T10	1774	0	0	0
T11	0	9493	0	0
T12	0	832	0	0
T13	0	832	0	0
T30	0	832	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	1978579	0	0
T1	79578	1856	0	0
T2	7625	0	0	0
T3	10028	832	0	0
T4	47239	832	0	0
T5	588821	3648	0	0
T6	941	0	0	0
T7	3145	0	0	0
T8	775874	9116	0	0
T9	471864	8712	0	0
T10	1774	0	0	0
T11	0	9493	0	0
T12	0	832	0	0
T13	0	832	0	0
T30	0	832	0	0

ReqStaysHighUntilGranted0_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	0	0	0

RoundRobin_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	4	0	906
T23	300730	1	0	1
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	910	0	0	1
T48	240978	0	0	1
T49	188757	0	0	1
T50	171970	0	0	1
T51	278523	0	0	1
T52	222457	0	0	1
T53	26227	0	0	1
T54	469735	0	0	1
T55	108387	0	0	1

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	412473177	0	0
T1	79578	79510	0	0
T2	7625	5394	0	0
T3	10028	9928	0	0
T4	47239	47167	0	0
T5	588821	588725	0	0
T6	941	886	0	0
T7	3145	3049	0	0
T8	775874	775821	0	0
T9	471864	471856	0	0
T10	1774	1708	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	412556201	1978579	0	0
T1	79578	1856	0	0
T2	7625	0	0	0
T3	10028	832	0	0
T4	47239	832	0	0
T5	588821	3648	0	0
T6	941	0	0	0
T7	3145	0	0	0
T8	775874	9116	0	0
T9	471864	8712	0	0
T10	1774	0	0	0
T11	0	9493	0	0
T12	0	832	0	0
T13	0	832	0	0
T30	0	832	0	0