Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	207212	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

162964

1

T1

1543

T2

11557

T3

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	273226	1			T1	806		T2	8569		T3	11
values[0x0]	48021	1			T1	358		T2	4262		T3	5
values[0x1]	48929	1			T1	379		T2	4306		T3	6

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	148410	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

221766

1

T1

1543

T2

12641

T3

7

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	997	1			T1	4		T2	38		T10	8
valid_sources[0x01]	979	1			T1	4		T2	57		T10	5
valid_sources[0x02]	1201	1			T1	4		T2	71		T10	6
valid_sources[0x03]	1050	1			T1	7		T2	105		T4	3
valid_sources[0x04]	2046	1			T1	11		T2	40		T10	2
valid_sources[0x05]	1151	1			T1	5		T2	50		T10	4
valid_sources[0x06]	1419	1			T1	6		T2	65		T10	3
valid_sources[0x07]	1435	1			T1	9		T2	82		T10	3
valid_sources[0x08]	1454	1			T1	4		T2	53		T10	4
valid_sources[0x09]	1360	1			T1	11		T2	72		T10	5
valid_sources[0x0a]	1235	1			T1	2		T2	65		T10	5
valid_sources[0x0b]	1432	1			T1	6		T2	76		T10	3
valid_sources[0x0c]	1103	1			T1	4		T2	44		T10	7
valid_sources[0x0d]	1292	1			T1	5		T2	124		T10	8
valid_sources[0x0e]	1740	1			T1	3		T2	52		T10	2
valid_sources[0x0f]	1219	1			T1	5		T2	96		T10	2
valid_sources[0x10]	1148	1			T2	50		T10	6		T4	9
valid_sources[0x11]	1622	1			T1	8		T2	62		T10	9
valid_sources[0x12]	1747	1			T1	4		T2	15		T10	4
valid_sources[0x13]	1249	1			T1	7		T2	48		T10	7
valid_sources[0x14]	6091	1			T1	3		T2	65		T10	3
valid_sources[0x15]	1386	1			T1	3		T2	65		T10	11
valid_sources[0x16]	1289	1			T1	6		T2	44		T10	6
valid_sources[0x17]	1726	1			T1	9		T2	54		T10	6
valid_sources[0x18]	2281	1			T1	6		T2	69		T10	2
valid_sources[0x19]	1272	1			T1	3		T2	91		T10	2
valid_sources[0x1a]	1135	1			T1	9		T2	52		T10	3
valid_sources[0x1b]	1338	1			T1	3		T2	68		T10	2
valid_sources[0x1c]	1563	1			T1	9		T2	76		T10	6
valid_sources[0x1d]	1435	1			T1	4		T2	76		T10	6
valid_sources[0x1e]	1375	1			T1	3		T2	92		T10	3
valid_sources[0x1f]	1193	1			T1	5		T2	64		T10	1
valid_sources[0x20]	1548	1			T1	8		T2	57		T10	5
valid_sources[0x21]	1367	1			T1	6		T2	57		T10	4
valid_sources[0x22]	1439	1			T1	4		T2	63		T10	2
valid_sources[0x23]	1710	1			T1	5		T2	110		T10	3
valid_sources[0x24]	1343	1			T1	7		T2	48		T10	7
valid_sources[0x25]	1209	1			T1	7		T2	51		T10	2
valid_sources[0x26]	1207	1			T1	9		T2	72		T10	8
valid_sources[0x27]	1110	1			T1	6		T2	82		T10	8
valid_sources[0x28]	1437	1			T1	5		T2	60		T10	1
valid_sources[0x29]	1559	1			T1	10		T2	64		T10	1
valid_sources[0x2a]	1249	1			T1	17		T2	26		T10	4
valid_sources[0x2b]	1260	1			T1	2		T2	63		T10	4
valid_sources[0x2c]	1715	1			T1	3		T2	10		T10	3
valid_sources[0x2d]	1805	1			T1	5		T2	98		T10	1
valid_sources[0x2e]	1473	1			T1	7		T2	36		T10	3
valid_sources[0x2f]	1748	1			T1	1		T2	68		T10	3
valid_sources[0x30]	1674	1			T1	5		T2	59		T10	2
valid_sources[0x31]	1444	1			T1	6		T2	78		T10	2
valid_sources[0x32]	1343	1			T1	4		T2	90		T10	10
valid_sources[0x33]	1228	1			T1	4		T2	72		T10	2
valid_sources[0x34]	2312	1			T2	61		T10	4		T4	7
valid_sources[0x35]	1254	1			T1	12		T2	41		T10	5
valid_sources[0x36]	1081	1			T1	7		T2	40		T10	7
valid_sources[0x37]	1645	1			T1	3		T2	60		T10	7
valid_sources[0x38]	1232	1			T1	10		T2	57		T10	2
valid_sources[0x39]	1703	1			T1	9		T2	84		T10	4
valid_sources[0x3a]	1365	1			T1	6		T2	110		T10	7
valid_sources[0x3b]	1682	1			T1	4		T2	83		T10	2
valid_sources[0x3c]	1127	1			T1	2		T2	53		T10	5
valid_sources[0x3d]	1003	1			T1	4		T2	36		T10	4
valid_sources[0x3e]	1136	1			T1	5		T2	52		T10	1
valid_sources[0x3f]	1584	1			T1	1		T2	35		T10	10
valid_sources[0x40]	1087	1			T1	8		T2	65		T10	2
valid_sources[0x41]	1475	1			T1	8		T2	81		T10	6
valid_sources[0x42]	1400	1			T1	5		T2	88		T10	1
valid_sources[0x43]	1362	1			T1	4		T2	85		T10	2
valid_sources[0x44]	1323	1			T1	4		T2	41		T10	3
valid_sources[0x45]	1527	1			T1	7		T2	94		T3	2
valid_sources[0x46]	1165	1			T1	8		T2	62		T10	1
valid_sources[0x47]	2232	1			T1	11		T2	62		T10	4
valid_sources[0x48]	1298	1			T1	8		T2	65		T10	3
valid_sources[0x49]	1032	1			T1	4		T2	53		T10	3
valid_sources[0x4a]	1183	1			T1	6		T2	73		T10	3
valid_sources[0x4b]	1212	1			T1	4		T2	93		T10	5
valid_sources[0x4c]	1700	1			T1	4		T2	79		T10	4
valid_sources[0x4d]	1077	1			T1	6		T2	32		T10	2
valid_sources[0x4e]	1985	1			T1	7		T2	59		T10	2
valid_sources[0x4f]	1302	1			T1	5		T2	119		T10	4
valid_sources[0x50]	1070	1			T1	4		T2	44		T10	5
valid_sources[0x51]	1323	1			T1	3		T2	74		T10	4
valid_sources[0x52]	1674	1			T1	5		T2	68		T10	9
valid_sources[0x53]	1347	1			T1	4		T2	77		T10	3
valid_sources[0x54]	1212	1			T1	7		T2	91		T10	3
valid_sources[0x55]	1303	1			T1	7		T2	70		T10	2
valid_sources[0x56]	1238	1			T1	4		T2	32		T10	4
valid_sources[0x57]	1748	1			T1	6		T2	95		T10	4
valid_sources[0x58]	1258	1			T1	11		T2	94		T10	4
valid_sources[0x59]	1627	1			T1	4		T2	94		T10	4
valid_sources[0x5a]	1078	1			T1	7		T2	93		T10	3
valid_sources[0x5b]	1137	1			T1	3		T2	59		T10	4
valid_sources[0x5c]	1406	1			T1	6		T2	55		T4	18
valid_sources[0x5d]	1260	1			T1	8		T2	99		T10	3
valid_sources[0x5e]	1359	1			T1	2		T2	84		T10	4
valid_sources[0x5f]	1237	1			T1	5		T2	80		T10	4
valid_sources[0x60]	1780	1			T1	5		T2	62		T10	4
valid_sources[0x61]	1605	1			T1	5		T2	85		T10	2
valid_sources[0x62]	1411	1			T1	6		T2	65		T10	6
valid_sources[0x63]	1041	1			T1	3		T2	90		T10	1
valid_sources[0x64]	1633	1			T1	5		T2	80		T10	6
valid_sources[0x65]	1968	1			T1	7		T2	63		T10	1
valid_sources[0x66]	2448	1			T1	6		T2	70		T10	3
valid_sources[0x67]	1248	1			T1	7		T2	55		T10	4
valid_sources[0x68]	981	1			T1	3		T2	38		T10	2
valid_sources[0x69]	1672	1			T1	3		T2	51		T10	4
valid_sources[0x6a]	1291	1			T1	3		T2	59		T10	6
valid_sources[0x6b]	1098	1			T1	8		T2	52		T10	5
valid_sources[0x6c]	1396	1			T1	6		T2	68		T3	7
valid_sources[0x6d]	1248	1			T1	4		T2	84		T10	5
valid_sources[0x6e]	1170	1			T1	3		T2	47		T10	6
valid_sources[0x6f]	1227	1			T1	9		T2	52		T3	5
valid_sources[0x70]	1131	1			T1	4		T2	51		T10	6
valid_sources[0x71]	1449	1			T1	3		T2	112		T10	2
valid_sources[0x72]	1451	1			T1	11		T2	73		T10	6
valid_sources[0x73]	1158	1			T1	8		T2	36		T10	2
valid_sources[0x74]	1087	1			T1	14		T2	83		T10	1
valid_sources[0x75]	1553	1			T1	14		T2	140		T10	4
valid_sources[0x76]	1267	1			T1	2		T2	83		T10	5
valid_sources[0x77]	1110	1			T1	12		T2	55		T10	7
valid_sources[0x78]	1331	1			T1	15		T2	52		T10	4
valid_sources[0x79]	1430	1			T1	11		T2	64		T10	7
valid_sources[0x7a]	1359	1			T2	95		T10	9		T4	13
valid_sources[0x7b]	1153	1			T1	10		T2	59		T4	14
valid_sources[0x7c]	1856	1			T1	7		T2	96		T10	11
valid_sources[0x7d]	1272	1			T1	6		T2	60		T10	8
valid_sources[0x7e]	1323	1			T1	3		T2	78		T10	7
valid_sources[0x7f]	1070	1			T1	7		T2	97		T10	5
valid_sources[0x80]	1582	1			T1	9		T2	64		T10	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

78190

1

T1

806

T2

4281

T3

4

values[0x0]

all_enables

biggest_size

43610

1

T1

358

T2

3758

T3

2

values[0x1]

all_enables

biggest_size

41164

1

T1

379

T2

3518

T6

3