Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.83	95.83	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	95.83	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.83	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	1	15	93.75

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	1	15	93.75	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

229255

1

T2

5580

T3

16

T6

26

full_word

164251

1

T1

1543

T2

11557

T3

6

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	393156	1			T1	1543		T2	17137		T3	22
auto[TlIntgErrCmd]	104	1			T9	3		T26	3		T28	2
auto[TlIntgErrData]	115	1			T9	1		T26	4		T28	2
auto[TlIntgErrBoth]	131	1			T9	6		T26	3		T28	6

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

277679

1

T1

806

T2

8569

T3

11

auto[1]

115827

1

T1

737

T2

8568

T3

11

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	1	15	93.75	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	NUMBER	STATUS
[auto[TlIntgErrData]]	[full_word]	[auto[1]]	0	1	1

Covered bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	198996	1			T2	4288		T3	7		T6	11
auto[TlIntgErrNone]	partial	auto[1]	29935	1			T2	1292		T3	9		T6	15
auto[TlIntgErrNone]	full_word	auto[0]	78516	1			T1	806		T2	4281		T3	4
auto[TlIntgErrNone]	full_word	auto[1]	85709	1			T1	737		T2	7276		T3	2
auto[TlIntgErrCmd]	partial	auto[0]	41	1			T9	3		T26	2		T58	5
auto[TlIntgErrCmd]	partial	auto[1]	58	1			T28	2		T59	3		T58	2
auto[TlIntgErrCmd]	full_word	auto[0]	3	1			T26	1		T60	1		T61	1
auto[TlIntgErrCmd]	full_word	auto[1]	2	1			T62	1		T54	1		-	-
auto[TlIntgErrData]	partial	auto[0]	58	1			T9	1		T26	2		T28	1
auto[TlIntgErrData]	partial	auto[1]	52	1			T26	2		T28	1		T59	3
auto[TlIntgErrData]	full_word	auto[0]	5	1			T59	1		T63	1		T64	1
auto[TlIntgErrBoth]	partial	auto[0]	52	1			T9	2		T28	1		T59	4
auto[TlIntgErrBoth]	partial	auto[1]	63	1			T9	4		T26	2		T28	5
auto[TlIntgErrBoth]	full_word	auto[0]	8	1			T59	2		T65	1		T54	2
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T26	1		T62	2		T65	1