Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2291755	32639	0	0
DepthKnown_A	2291755	2250811	0	0
RvalidKnown_A	2291755	2250811	0	0
WreadyKnown_A	2291755	2250811	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	32639	0	0
T4	20041	0	0	0
T5	2266	156	0	0
T7	4461	603	0	0
T8	8518	895	0	0
T11	903	0	0	0
T12	1330	0	0	0
T13	1537	0	0	0
T14	4363	0	0	0
T15	0	1681	0	0
T16	0	563	0	0
T17	0	1304	0	0
T18	0	457	0	0
T19	0	482	0	0
T20	0	2209	0	0
T21	0	566	0	0
T24	6536	0	0	0
T25	3902	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2291755	28507	0	0
DepthKnown_A	2291755	2250811	0	0
RvalidKnown_A	2291755	2250811	0	0
WreadyKnown_A	2291755	2250811	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	28507	0	0
T4	20041	0	0	0
T5	2266	93	0	0
T7	4461	557	0	0
T8	8518	421	0	0
T11	903	0	0	0
T12	1330	0	0	0
T13	1537	0	0	0
T14	4363	0	0	0
T15	0	819	0	0
T16	0	326	0	0
T17	0	2605	0	0
T18	0	288	0	0
T19	0	954	0	0
T20	0	1073	0	0
T21	0	1322	0	0
T24	6536	0	0	0
T25	3902	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2291755	12811	0	0
DepthKnown_A	2291755	2250811	0	0
RvalidKnown_A	2291755	2250811	0	0
WreadyKnown_A	2291755	2250811	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	12811	0	0
T5	2266	9	0	0
T8	8518	472	0	0
T9	10170	0	0	0
T12	1330	0	0	0
T15	8031	1037	0	0
T16	5106	31	0	0
T18	0	16	0	0
T19	0	172	0	0
T20	0	1328	0	0
T21	0	17	0	0
T22	0	423	0	0
T23	0	697	0	0
T25	3902	0	0	0
T26	35486	0	0	0
T27	35122	0	0	0
T28	27601	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2291755	9630	0	0
DepthKnown_A	2291755	2250811	0	0
RvalidKnown_A	2291755	2250811	0	0
WreadyKnown_A	2291755	2250811	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	9630	0	0
T5	2266	4	0	0
T8	8518	214	0	0
T9	10170	0	0	0
T12	1330	0	0	0
T15	8031	502	0	0
T16	5106	15	0	0
T18	0	8	0	0
T19	0	391	0	0
T20	0	645	0	0
T21	0	29	0	0
T22	0	201	0	0
T23	0	332	0	0
T25	3902	0	0	0
T26	35486	0	0	0
T27	35122	0	0	0
T28	27601	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2291755	560119	0	0
DepthKnown_A	2291755	2250811	0	0
RvalidKnown_A	2291755	2250811	0	0
WreadyKnown_A	2291755	2250811	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	560119	0	0
T1	10531	1668	0	0
T2	180562	17259	0	0
T3	962	22	0	0
T4	20041	4841	0	0
T6	955	40	0	0
T7	4461	1	0	0
T10	3313	2242	0	0
T11	903	58	0	0
T13	1537	826	0	0
T14	4363	3040	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2291755	660364	0	0
DepthKnown_A	2291755	2250811	0	0
RvalidKnown_A	2291755	2250811	0	0
WreadyKnown_A	2291755	2250811	0	0
gen_passthru_fifo.paramCheckPass	175	175	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	660364	0	0
T1	10531	1543	0	0
T2	180562	77007	0	0
T3	962	22	0	0
T4	20041	10790	0	0
T6	955	40	0	0
T7	4461	1	0	0
T10	3313	1123	0	0
T11	903	58	0	0
T13	1537	414	0	0
T14	4363	1592	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2291755	2250811	0	0
T1	10531	10378	0	0
T2	180562	180467	0	0
T3	962	897	0	0
T4	20041	19920	0	0
T6	955	889	0	0
T7	4461	4373	0	0
T10	3313	3221	0	0
T11	903	823	0	0
T13	1537	1470	0	0
T14	4363	4284	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	175	175	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T10	1	1	0	0
T11	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0