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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1129
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html

T263 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.2464777816 Aug 23 08:52:13 PM UTC 24 Aug 23 08:52:34 PM UTC 24 16703834253 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.4168287652 Aug 23 08:52:33 PM UTC 24 Aug 23 08:52:35 PM UTC 24 13695504 ps
T244 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.1559585664 Aug 23 08:53:29 PM UTC 24 Aug 23 08:54:56 PM UTC 24 69371605228 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.406978881 Aug 23 08:52:34 PM UTC 24 Aug 23 08:52:36 PM UTC 24 39184780 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.2921806440 Aug 23 08:52:37 PM UTC 24 Aug 23 08:52:39 PM UTC 24 124310814 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.1649853401 Aug 23 08:52:37 PM UTC 24 Aug 23 08:52:40 PM UTC 24 37978666 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.279221650 Aug 23 08:52:35 PM UTC 24 Aug 23 08:52:43 PM UTC 24 1551049822 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.81439797 Aug 23 08:52:45 PM UTC 24 Aug 23 08:52:48 PM UTC 24 76060198 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.1806966189 Aug 23 08:52:35 PM UTC 24 Aug 23 08:52:49 PM UTC 24 4340836214 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.114128365 Aug 23 08:52:41 PM UTC 24 Aug 23 08:52:51 PM UTC 24 4764750431 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.3378100375 Aug 23 08:52:49 PM UTC 24 Aug 23 08:52:52 PM UTC 24 568079128 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.4031598352 Aug 23 08:51:37 PM UTC 24 Aug 23 08:52:53 PM UTC 24 31108528587 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.4186580539 Aug 23 08:48:25 PM UTC 24 Aug 23 08:52:54 PM UTC 24 42013511948 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.332491442 Aug 23 08:52:52 PM UTC 24 Aug 23 08:52:56 PM UTC 24 109404693 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.4292781087 Aug 23 08:48:22 PM UTC 24 Aug 23 08:52:59 PM UTC 24 86836035035 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.1603380160 Aug 23 08:52:41 PM UTC 24 Aug 23 08:53:00 PM UTC 24 7422082182 ps
T260 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.659214350 Aug 23 08:52:05 PM UTC 24 Aug 23 08:53:00 PM UTC 24 11475805155 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.3149099496 Aug 23 08:52:54 PM UTC 24 Aug 23 08:53:04 PM UTC 24 1590627289 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.4172348751 Aug 23 08:52:50 PM UTC 24 Aug 23 08:53:06 PM UTC 24 17209626379 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.2142959559 Aug 23 08:53:05 PM UTC 24 Aug 23 08:53:06 PM UTC 24 14276981 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.1195607096 Aug 23 08:53:07 PM UTC 24 Aug 23 08:53:08 PM UTC 24 49700896 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.1146905200 Aug 23 08:52:52 PM UTC 24 Aug 23 08:53:10 PM UTC 24 999075147 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.4089533832 Aug 23 08:53:11 PM UTC 24 Aug 23 08:53:13 PM UTC 24 88231954 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.838032719 Aug 23 08:53:13 PM UTC 24 Aug 23 08:53:15 PM UTC 24 27446733 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.3956202195 Aug 23 08:53:09 PM UTC 24 Aug 23 08:53:22 PM UTC 24 7631340852 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.227861658 Aug 23 08:53:23 PM UTC 24 Aug 23 08:53:26 PM UTC 24 288703534 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.1902036994 Aug 23 08:53:15 PM UTC 24 Aug 23 08:53:28 PM UTC 24 3109422789 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.95028845 Aug 23 08:53:09 PM UTC 24 Aug 23 08:53:31 PM UTC 24 16926532545 ps
T250 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.3836999125 Aug 23 08:53:27 PM UTC 24 Aug 23 08:53:33 PM UTC 24 564581289 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.4249175637 Aug 23 08:52:22 PM UTC 24 Aug 23 08:53:42 PM UTC 24 4071022667 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.1431796259 Aug 23 08:49:25 PM UTC 24 Aug 23 08:53:44 PM UTC 24 111798268027 ps
T298 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.664525075 Aug 23 08:53:34 PM UTC 24 Aug 23 08:53:45 PM UTC 24 4354684667 ps
T113 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.952060936 Aug 23 08:52:17 PM UTC 24 Aug 23 08:53:46 PM UTC 24 14546050738 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.2101286485 Aug 23 08:53:47 PM UTC 24 Aug 23 08:53:49 PM UTC 24 21023760 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.341605470 Aug 23 08:53:46 PM UTC 24 Aug 23 08:53:51 PM UTC 24 830164288 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.3197306020 Aug 23 08:53:00 PM UTC 24 Aug 23 08:53:54 PM UTC 24 17977944492 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.1361157302 Aug 23 08:52:54 PM UTC 24 Aug 23 08:53:58 PM UTC 24 12367403554 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.1765624091 Aug 23 08:53:58 PM UTC 24 Aug 23 08:54:00 PM UTC 24 48109479 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.2360979993 Aug 23 08:54:00 PM UTC 24 Aug 23 08:54:02 PM UTC 24 18120719 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.647912922 Aug 23 08:53:43 PM UTC 24 Aug 23 08:54:02 PM UTC 24 3936526842 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.630009430 Aug 23 08:53:32 PM UTC 24 Aug 23 08:54:08 PM UTC 24 45552928743 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.3841189985 Aug 23 08:54:09 PM UTC 24 Aug 23 08:54:11 PM UTC 24 248887777 ps
T265 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.334087790 Aug 23 08:51:33 PM UTC 24 Aug 23 08:54:14 PM UTC 24 44322375266 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.4070482203 Aug 23 08:54:12 PM UTC 24 Aug 23 08:54:15 PM UTC 24 99015872 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.1831266240 Aug 23 08:54:14 PM UTC 24 Aug 23 08:54:21 PM UTC 24 2309128166 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.733129655 Aug 23 08:54:04 PM UTC 24 Aug 23 08:54:23 PM UTC 24 8221717761 ps
T373 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.1761543970 Aug 23 08:54:05 PM UTC 24 Aug 23 08:54:28 PM UTC 24 26601655080 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.3655883473 Aug 23 08:50:59 PM UTC 24 Aug 23 08:54:29 PM UTC 24 24873973911 ps
T266 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.1989412823 Aug 23 08:54:22 PM UTC 24 Aug 23 08:54:29 PM UTC 24 1757573414 ps
T282 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.3332321741 Aug 23 08:53:52 PM UTC 24 Aug 23 08:54:30 PM UTC 24 1751665517 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.3057526869 Aug 23 08:54:29 PM UTC 24 Aug 23 08:54:33 PM UTC 24 146278277 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.3750704231 Aug 23 08:54:15 PM UTC 24 Aug 23 08:54:34 PM UTC 24 6123930546 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.2653969144 Aug 23 08:54:31 PM UTC 24 Aug 23 08:54:38 PM UTC 24 1416337877 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.3466226702 Aug 23 08:54:28 PM UTC 24 Aug 23 08:54:46 PM UTC 24 21021207557 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.891762621 Aug 23 08:54:34 PM UTC 24 Aug 23 08:54:49 PM UTC 24 2124273355 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.2611247628 Aug 23 08:54:31 PM UTC 24 Aug 23 08:54:52 PM UTC 24 1177823709 ps
T227 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1252768607 Aug 23 08:48:05 PM UTC 24 Aug 23 08:54:54 PM UTC 24 69508277823 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.595927760 Aug 23 08:54:53 PM UTC 24 Aug 23 08:54:55 PM UTC 24 53206450 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.463950191 Aug 23 08:57:22 PM UTC 24 Aug 23 08:57:23 PM UTC 24 57621159 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.3837255448 Aug 23 08:54:55 PM UTC 24 Aug 23 08:54:57 PM UTC 24 43494341 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.2638607018 Aug 23 08:54:58 PM UTC 24 Aug 23 08:54:59 PM UTC 24 25530977 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.99001339 Aug 23 08:55:00 PM UTC 24 Aug 23 08:55:02 PM UTC 24 118678091 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.510718513 Aug 23 08:54:58 PM UTC 24 Aug 23 08:55:04 PM UTC 24 685151198 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.1633155373 Aug 23 08:55:03 PM UTC 24 Aug 23 08:55:06 PM UTC 24 153328744 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.1478337976 Aug 23 08:48:09 PM UTC 24 Aug 23 08:55:08 PM UTC 24 49202604103 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.1912748054 Aug 23 08:54:24 PM UTC 24 Aug 23 08:55:14 PM UTC 24 51421355024 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.558138534 Aug 23 08:55:07 PM UTC 24 Aug 23 08:55:14 PM UTC 24 847429652 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.3067668306 Aug 23 08:52:57 PM UTC 24 Aug 23 08:55:18 PM UTC 24 97386347103 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.4123456717 Aug 23 08:55:14 PM UTC 24 Aug 23 08:55:18 PM UTC 24 414098378 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.1938684370 Aug 23 08:54:58 PM UTC 24 Aug 23 08:55:22 PM UTC 24 9922361655 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.3173161962 Aug 23 08:55:18 PM UTC 24 Aug 23 08:55:22 PM UTC 24 243093898 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.2873565688 Aug 23 08:54:35 PM UTC 24 Aug 23 08:55:23 PM UTC 24 51167420198 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.2474346634 Aug 23 08:55:05 PM UTC 24 Aug 23 08:55:26 PM UTC 24 63738083905 ps
T257 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.3755685056 Aug 23 08:55:14 PM UTC 24 Aug 23 08:55:28 PM UTC 24 3785370549 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.1517036578 Aug 23 08:55:24 PM UTC 24 Aug 23 08:55:34 PM UTC 24 5682976773 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.2995028830 Aug 23 08:55:23 PM UTC 24 Aug 23 08:55:35 PM UTC 24 2345166450 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.217190547 Aug 23 08:53:49 PM UTC 24 Aug 23 08:55:35 PM UTC 24 23278371375 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.1076854416 Aug 23 08:55:35 PM UTC 24 Aug 23 08:55:37 PM UTC 24 162878084 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.1377586010 Aug 23 08:57:19 PM UTC 24 Aug 23 08:57:21 PM UTC 24 15607110 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.1210585259 Aug 23 08:55:36 PM UTC 24 Aug 23 08:55:38 PM UTC 24 82993934 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.2269321563 Aug 23 08:55:39 PM UTC 24 Aug 23 08:55:41 PM UTC 24 83820497 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.2347577827 Aug 23 08:55:38 PM UTC 24 Aug 23 08:55:42 PM UTC 24 5927171875 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.4259143448 Aug 23 08:55:42 PM UTC 24 Aug 23 08:55:44 PM UTC 24 17465828 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.1408268432 Aug 23 08:54:50 PM UTC 24 Aug 23 08:55:45 PM UTC 24 17592181332 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.2928672020 Aug 23 08:52:59 PM UTC 24 Aug 23 08:55:51 PM UTC 24 17515116518 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.2029501947 Aug 23 08:55:28 PM UTC 24 Aug 23 08:55:51 PM UTC 24 4462446632 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.3977171327 Aug 23 08:55:43 PM UTC 24 Aug 23 08:55:52 PM UTC 24 5646961141 ps
T261 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.2366542897 Aug 23 08:55:45 PM UTC 24 Aug 23 08:55:53 PM UTC 24 766037863 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.643570205 Aug 23 08:55:53 PM UTC 24 Aug 23 08:55:59 PM UTC 24 552316535 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.1565380254 Aug 23 08:55:53 PM UTC 24 Aug 23 08:56:01 PM UTC 24 3918334697 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.3899186779 Aug 23 08:55:53 PM UTC 24 Aug 23 08:56:02 PM UTC 24 1920777058 ps
T241 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.2510260483 Aug 23 08:55:45 PM UTC 24 Aug 23 08:56:03 PM UTC 24 1991989767 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.2728310308 Aug 23 08:55:39 PM UTC 24 Aug 23 08:56:04 PM UTC 24 7457482346 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.2171868 Aug 23 08:56:03 PM UTC 24 Aug 23 08:56:05 PM UTC 24 13928910 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3668983602 Aug 23 08:50:11 PM UTC 24 Aug 23 08:56:05 PM UTC 24 166664508909 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.2366505287 Aug 23 08:52:32 PM UTC 24 Aug 23 08:56:06 PM UTC 24 102647555682 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.2558561552 Aug 23 08:53:54 PM UTC 24 Aug 23 08:56:07 PM UTC 24 43333257584 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.1961008549 Aug 23 08:55:08 PM UTC 24 Aug 23 08:56:07 PM UTC 24 32389695799 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.1145682253 Aug 23 08:56:07 PM UTC 24 Aug 23 08:56:08 PM UTC 24 27148550 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.3786010041 Aug 23 08:57:23 PM UTC 24 Aug 23 08:57:25 PM UTC 24 41833791 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.705419385 Aug 23 08:56:08 PM UTC 24 Aug 23 08:56:10 PM UTC 24 54099385 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.80301780 Aug 23 08:50:56 PM UTC 24 Aug 23 08:56:10 PM UTC 24 169663707612 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.487841723 Aug 23 08:56:09 PM UTC 24 Aug 23 08:56:11 PM UTC 24 44974146 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.2445589070 Aug 23 08:56:10 PM UTC 24 Aug 23 08:56:12 PM UTC 24 19567907 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.2607900078 Aug 23 08:56:10 PM UTC 24 Aug 23 08:56:14 PM UTC 24 168269505 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.1603436206 Aug 23 08:56:02 PM UTC 24 Aug 23 08:56:16 PM UTC 24 10018191397 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.2041196822 Aug 23 08:56:08 PM UTC 24 Aug 23 08:56:16 PM UTC 24 6518505686 ps
T267 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.2239442121 Aug 23 08:56:13 PM UTC 24 Aug 23 08:56:17 PM UTC 24 457997604 ps
T330 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.580214620 Aug 23 08:56:17 PM UTC 24 Aug 23 08:56:20 PM UTC 24 245602768 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.1779125283 Aug 23 08:56:12 PM UTC 24 Aug 23 08:56:20 PM UTC 24 1980113091 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1748225778 Aug 23 08:56:12 PM UTC 24 Aug 23 08:56:22 PM UTC 24 5764654138 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.1112556508 Aug 23 08:56:17 PM UTC 24 Aug 23 08:56:23 PM UTC 24 2173651498 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.2276748091 Aug 23 08:56:21 PM UTC 24 Aug 23 08:56:27 PM UTC 24 220368626 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.3755932105 Aug 23 08:56:15 PM UTC 24 Aug 23 08:56:30 PM UTC 24 14133220786 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.178120867 Aug 23 08:55:54 PM UTC 24 Aug 23 08:56:36 PM UTC 24 13226483981 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.2346687886 Aug 23 08:56:36 PM UTC 24 Aug 23 08:56:38 PM UTC 24 35052633 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.942051030 Aug 23 08:56:18 PM UTC 24 Aug 23 08:56:40 PM UTC 24 3148405328 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.982014151 Aug 23 08:56:38 PM UTC 24 Aug 23 08:56:40 PM UTC 24 19319541 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.2324832111 Aug 23 08:56:40 PM UTC 24 Aug 23 08:56:42 PM UTC 24 27761552 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.1203648959 Aug 23 08:56:43 PM UTC 24 Aug 23 08:56:45 PM UTC 24 64383784 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1020200928 Aug 23 08:56:40 PM UTC 24 Aug 23 08:56:47 PM UTC 24 947217193 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.1063092526 Aug 23 08:56:46 PM UTC 24 Aug 23 08:56:57 PM UTC 24 3785291417 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.385668563 Aug 23 08:56:40 PM UTC 24 Aug 23 08:56:58 PM UTC 24 1798300124 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.3751424905 Aug 23 08:56:28 PM UTC 24 Aug 23 08:56:59 PM UTC 24 5616496229 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.1808324663 Aug 23 08:56:48 PM UTC 24 Aug 23 08:57:01 PM UTC 24 7230797148 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2963627223 Aug 23 08:52:27 PM UTC 24 Aug 23 08:57:02 PM UTC 24 41428783124 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.1737308072 Aug 23 08:56:21 PM UTC 24 Aug 23 08:57:05 PM UTC 24 7441477905 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.4061441241 Aug 23 08:57:00 PM UTC 24 Aug 23 08:57:06 PM UTC 24 342855216 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.1628593089 Aug 23 08:56:58 PM UTC 24 Aug 23 08:57:06 PM UTC 24 717930750 ps
T292 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.3222971405 Aug 23 08:57:01 PM UTC 24 Aug 23 08:57:07 PM UTC 24 716353305 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.1919194797 Aug 23 08:57:02 PM UTC 24 Aug 23 08:57:10 PM UTC 24 729654547 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.3482397521 Aug 23 08:56:06 PM UTC 24 Aug 23 08:57:11 PM UTC 24 9283155242 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.2344899347 Aug 23 08:56:59 PM UTC 24 Aug 23 08:57:16 PM UTC 24 23555544212 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.220900725 Aug 23 08:57:07 PM UTC 24 Aug 23 08:57:19 PM UTC 24 3479195752 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.1402771483 Aug 23 08:57:17 PM UTC 24 Aug 23 08:57:19 PM UTC 24 14085295 ps
T114 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.2557573439 Aug 23 08:53:45 PM UTC 24 Aug 23 08:57:21 PM UTC 24 167723157628 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.2625586870 Aug 23 08:55:20 PM UTC 24 Aug 23 08:57:21 PM UTC 24 9532903241 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.730098481 Aug 23 08:54:47 PM UTC 24 Aug 23 08:57:27 PM UTC 24 117344082913 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.3496343632 Aug 23 08:57:22 PM UTC 24 Aug 23 08:57:29 PM UTC 24 2241916617 ps
T291 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.2132528696 Aug 23 08:56:24 PM UTC 24 Aug 23 08:57:30 PM UTC 24 13627187581 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.3279487010 Aug 23 08:57:19 PM UTC 24 Aug 23 08:57:31 PM UTC 24 15284247414 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.2197712201 Aug 23 08:57:26 PM UTC 24 Aug 23 08:57:32 PM UTC 24 431517942 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.2248126340 Aug 23 08:57:28 PM UTC 24 Aug 23 08:57:34 PM UTC 24 856318825 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.52061702 Aug 23 08:53:00 PM UTC 24 Aug 23 08:57:35 PM UTC 24 38175251501 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.3418234711 Aug 23 08:57:24 PM UTC 24 Aug 23 08:57:36 PM UTC 24 2970568352 ps
T115 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.1669193544 Aug 23 08:57:31 PM UTC 24 Aug 23 08:57:36 PM UTC 24 320410334 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.4128020031 Aug 23 08:56:05 PM UTC 24 Aug 23 08:57:38 PM UTC 24 10830535514 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.3755156100 Aug 23 08:57:36 PM UTC 24 Aug 23 08:57:40 PM UTC 24 71708095 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.393760278 Aug 23 08:57:31 PM UTC 24 Aug 23 08:57:43 PM UTC 24 11625860220 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.4004185723 Aug 23 08:57:35 PM UTC 24 Aug 23 08:57:44 PM UTC 24 2189054356 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.1553530155 Aug 23 08:57:44 PM UTC 24 Aug 23 08:57:46 PM UTC 24 15329221 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.539512835 Aug 23 08:57:45 PM UTC 24 Aug 23 08:57:47 PM UTC 24 60948242 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.2041000964 Aug 23 08:57:47 PM UTC 24 Aug 23 08:57:48 PM UTC 24 27665716 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.1991972997 Aug 23 08:57:49 PM UTC 24 Aug 23 08:57:51 PM UTC 24 106293554 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.387492012 Aug 23 08:57:30 PM UTC 24 Aug 23 08:57:51 PM UTC 24 2746502261 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.1387498512 Aug 23 08:57:52 PM UTC 24 Aug 23 08:57:55 PM UTC 24 243803626 ps
T40 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.2507247322 Aug 23 08:54:39 PM UTC 24 Aug 23 08:57:57 PM UTC 24 37254361547 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.371734211 Aug 23 08:57:48 PM UTC 24 Aug 23 08:58:04 PM UTC 24 8296745490 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.873567646 Aug 23 08:57:52 PM UTC 24 Aug 23 08:58:06 PM UTC 24 15378596299 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.1550467285 Aug 23 08:57:33 PM UTC 24 Aug 23 08:58:06 PM UTC 24 6441766173 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.2099774378 Aug 23 08:58:04 PM UTC 24 Aug 23 08:58:08 PM UTC 24 506763701 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.1515081453 Aug 23 08:57:56 PM UTC 24 Aug 23 08:58:09 PM UTC 24 18524759063 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.4101994722 Aug 23 08:56:04 PM UTC 24 Aug 23 08:58:10 PM UTC 24 26230976223 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2100253954 Aug 23 08:58:08 PM UTC 24 Aug 23 08:58:11 PM UTC 24 113400461 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.565018162 Aug 23 08:58:09 PM UTC 24 Aug 23 08:58:15 PM UTC 24 448765042 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.1656708959 Aug 23 08:58:11 PM UTC 24 Aug 23 08:58:15 PM UTC 24 83439664 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.2472150039 Aug 23 08:57:58 PM UTC 24 Aug 23 08:58:16 PM UTC 24 29006173057 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.343388479 Aug 23 08:58:06 PM UTC 24 Aug 23 08:58:18 PM UTC 24 703942413 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.3094105442 Aug 23 08:58:19 PM UTC 24 Aug 23 08:58:20 PM UTC 24 20490663 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.2864858960 Aug 23 08:58:21 PM UTC 24 Aug 23 08:58:22 PM UTC 24 48635190 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.2113931448 Aug 23 08:55:27 PM UTC 24 Aug 23 08:58:23 PM UTC 24 36450454576 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.2441952827 Aug 23 08:50:56 PM UTC 24 Aug 23 08:58:23 PM UTC 24 304748738284 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.3924162053 Aug 23 08:58:24 PM UTC 24 Aug 23 08:58:26 PM UTC 24 58223276 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.840428461 Aug 23 08:57:11 PM UTC 24 Aug 23 08:58:28 PM UTC 24 3234050298 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2967528321 Aug 23 08:51:34 PM UTC 24 Aug 23 08:58:29 PM UTC 24 100518382697 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.4252985347 Aug 23 08:58:26 PM UTC 24 Aug 23 08:58:29 PM UTC 24 2731041425 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.1213036267 Aug 23 08:50:16 PM UTC 24 Aug 23 08:58:30 PM UTC 24 54710751436 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.3700654626 Aug 23 08:57:41 PM UTC 24 Aug 23 08:58:33 PM UTC 24 11696831964 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.3831952130 Aug 23 08:57:37 PM UTC 24 Aug 23 08:58:33 PM UTC 24 2664970397 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.3630828711 Aug 23 08:58:23 PM UTC 24 Aug 23 08:58:34 PM UTC 24 3742235903 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.2419436703 Aug 23 08:58:31 PM UTC 24 Aug 23 08:58:35 PM UTC 24 209315264 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.3552883835 Aug 23 08:58:34 PM UTC 24 Aug 23 08:58:38 PM UTC 24 255145047 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.917654622 Aug 23 08:58:35 PM UTC 24 Aug 23 08:58:39 PM UTC 24 632580922 ps
T157 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.3777075947 Aug 23 08:58:29 PM UTC 24 Aug 23 08:58:39 PM UTC 24 4250799233 ps
T158 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.3658735131 Aug 23 08:57:37 PM UTC 24 Aug 23 08:58:42 PM UTC 24 5494680274 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.3152791653 Aug 23 08:57:39 PM UTC 24 Aug 23 08:58:42 PM UTC 24 30215782188 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.2546344255 Aug 23 08:58:43 PM UTC 24 Aug 23 08:58:45 PM UTC 24 49907869 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.1951486378 Aug 23 08:58:46 PM UTC 24 Aug 23 08:58:48 PM UTC 24 11839828 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.3754800352 Aug 23 08:58:40 PM UTC 24 Aug 23 08:58:48 PM UTC 24 590593990 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.4168033624 Aug 23 08:52:24 PM UTC 24 Aug 23 08:58:48 PM UTC 24 46745880348 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.774829613 Aug 23 08:58:24 PM UTC 24 Aug 23 08:58:49 PM UTC 24 3118362616 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.138398293 Aug 23 08:58:48 PM UTC 24 Aug 23 08:58:50 PM UTC 24 71381016 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.3112001158 Aug 23 08:58:50 PM UTC 24 Aug 23 08:58:51 PM UTC 24 76827231 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.2218545488 Aug 23 08:58:31 PM UTC 24 Aug 23 08:58:52 PM UTC 24 76548372457 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.2456800830 Aug 23 08:58:51 PM UTC 24 Aug 23 08:58:53 PM UTC 24 27250261 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.2022023298 Aug 23 08:58:31 PM UTC 24 Aug 23 08:58:56 PM UTC 24 2996166701 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.1095085875 Aug 23 08:58:35 PM UTC 24 Aug 23 08:59:00 PM UTC 24 1969544430 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.2680151696 Aug 23 08:58:53 PM UTC 24 Aug 23 08:59:00 PM UTC 24 625374079 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.2698840634 Aug 23 08:58:50 PM UTC 24 Aug 23 08:59:02 PM UTC 24 3117324934 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3066606952 Aug 23 08:58:16 PM UTC 24 Aug 23 08:59:02 PM UTC 24 12985591784 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.2145891336 Aug 23 08:58:52 PM UTC 24 Aug 23 08:59:03 PM UTC 24 2869992866 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.3687976669 Aug 23 08:58:40 PM UTC 24 Aug 23 08:59:04 PM UTC 24 3143148913 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.4242005330 Aug 23 08:59:02 PM UTC 24 Aug 23 08:59:05 PM UTC 24 1951847665 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.3903790725 Aug 23 08:59:03 PM UTC 24 Aug 23 08:59:07 PM UTC 24 165223937 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.2388003904 Aug 23 08:59:04 PM UTC 24 Aug 23 08:59:09 PM UTC 24 140043174 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.1590942987 Aug 23 08:59:02 PM UTC 24 Aug 23 08:59:09 PM UTC 24 3973147424 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.2898359831 Aug 23 08:59:10 PM UTC 24 Aug 23 08:59:12 PM UTC 24 10799168 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.3938605400 Aug 23 08:59:12 PM UTC 24 Aug 23 08:59:14 PM UTC 24 19638209 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.3351006206 Aug 23 08:58:50 PM UTC 24 Aug 23 08:59:15 PM UTC 24 10600401513 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.562308139 Aug 23 08:58:53 PM UTC 24 Aug 23 08:59:16 PM UTC 24 5476662187 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.3649557636 Aug 23 08:59:17 PM UTC 24 Aug 23 08:59:19 PM UTC 24 88480142 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.3270461827 Aug 23 08:58:11 PM UTC 24 Aug 23 08:59:20 PM UTC 24 25949897136 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.2056864761 Aug 23 08:59:19 PM UTC 24 Aug 23 08:59:21 PM UTC 24 19393314 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.1857865847 Aug 23 08:59:16 PM UTC 24 Aug 23 08:59:27 PM UTC 24 9126796063 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.2506278580 Aug 23 08:58:15 PM UTC 24 Aug 23 08:59:29 PM UTC 24 7398706169 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.689688158 Aug 23 08:59:14 PM UTC 24 Aug 23 08:59:32 PM UTC 24 22902778686 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.2848945518 Aug 23 08:59:21 PM UTC 24 Aug 23 08:59:32 PM UTC 24 9891379052 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.3266651413 Aug 23 08:59:21 PM UTC 24 Aug 23 08:59:36 PM UTC 24 3634578351 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.4221049412 Aug 23 08:59:33 PM UTC 24 Aug 23 08:59:36 PM UTC 24 300523640 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.3512473107 Aug 23 08:59:06 PM UTC 24 Aug 23 08:59:37 PM UTC 24 4166458978 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.2616223166 Aug 23 08:59:33 PM UTC 24 Aug 23 08:59:38 PM UTC 24 215917364 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.3859403163 Aug 23 08:59:36 PM UTC 24 Aug 23 08:59:40 PM UTC 24 73453738 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.1980815650 Aug 23 08:59:30 PM UTC 24 Aug 23 08:59:41 PM UTC 24 3457549245 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.2742417701 Aug 23 08:57:12 PM UTC 24 Aug 23 08:59:43 PM UTC 24 19013829686 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.407039926 Aug 23 08:59:44 PM UTC 24 Aug 23 08:59:46 PM UTC 24 98708723 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.2048562003 Aug 23 08:59:47 PM UTC 24 Aug 23 08:59:49 PM UTC 24 25587694 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.2059166130 Aug 23 08:59:38 PM UTC 24 Aug 23 08:59:50 PM UTC 24 1298192655 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.611481461 Aug 23 08:59:28 PM UTC 24 Aug 23 08:59:50 PM UTC 24 4097993579 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.3663409327 Aug 23 08:59:51 PM UTC 24 Aug 23 08:59:53 PM UTC 24 28409401 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.2157580378 Aug 23 08:59:53 PM UTC 24 Aug 23 08:59:55 PM UTC 24 44176344 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.2080520144 Aug 23 08:59:51 PM UTC 24 Aug 23 08:59:57 PM UTC 24 1985994901 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.1998897953 Aug 23 08:59:51 PM UTC 24 Aug 23 08:59:58 PM UTC 24 2344568293 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.445419104 Aug 23 08:59:56 PM UTC 24 Aug 23 08:59:59 PM UTC 24 48431931 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.1087621892 Aug 23 08:58:56 PM UTC 24 Aug 23 08:59:59 PM UTC 24 9464162670 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.3630097595 Aug 23 08:59:57 PM UTC 24 Aug 23 09:00:01 PM UTC 24 54114819 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.2899245172 Aug 23 09:00:00 PM UTC 24 Aug 23 09:00:03 PM UTC 24 453430749 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3761695033 Aug 23 08:56:00 PM UTC 24 Aug 23 09:00:08 PM UTC 24 35232939375 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.684055663 Aug 23 09:00:00 PM UTC 24 Aug 23 09:00:09 PM UTC 24 5715966168 ps
T273 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.3813096519 Aug 23 08:59:06 PM UTC 24 Aug 23 09:00:12 PM UTC 24 14529424671 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1074510952 Aug 23 09:00:12 PM UTC 24 Aug 23 09:00:15 PM UTC 24 100568427 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.915430040 Aug 23 08:57:07 PM UTC 24 Aug 23 09:00:16 PM UTC 24 197729654828 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.1897808615 Aug 23 08:59:03 PM UTC 24 Aug 23 09:00:16 PM UTC 24 9825001633 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.3498306831 Aug 23 09:00:13 PM UTC 24 Aug 23 09:00:18 PM UTC 24 343502847 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.2645598328 Aug 23 09:00:12 PM UTC 24 Aug 23 09:00:18 PM UTC 24 399171790 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.2899186017 Aug 23 09:00:01 PM UTC 24 Aug 23 09:00:21 PM UTC 24 1387298948 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.21502395 Aug 23 09:00:20 PM UTC 24 Aug 23 09:00:22 PM UTC 24 45546507 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.4241867833 Aug 23 09:00:22 PM UTC 24 Aug 23 09:00:24 PM UTC 24 19398233 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.1552738753 Aug 23 09:00:01 PM UTC 24 Aug 23 09:00:28 PM UTC 24 2529317819 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.578097706 Aug 23 09:00:23 PM UTC 24 Aug 23 09:00:29 PM UTC 24 1342392653 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.1220204925 Aug 23 09:00:30 PM UTC 24 Aug 23 09:00:31 PM UTC 24 52765397 ps
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