| T815 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.2895001137 |
|
|
Aug 23 09:07:12 PM UTC 24 |
Aug 23 09:08:15 PM UTC 24 |
6917553040 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.3137414714 |
|
|
Aug 23 09:08:01 PM UTC 24 |
Aug 23 09:08:15 PM UTC 24 |
23731891285 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.860547208 |
|
|
Aug 23 09:07:13 PM UTC 24 |
Aug 23 09:08:15 PM UTC 24 |
8513234390 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.1122771443 |
|
|
Aug 23 09:07:51 PM UTC 24 |
Aug 23 09:08:15 PM UTC 24 |
7359736493 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.3950342409 |
|
|
Aug 23 09:07:11 PM UTC 24 |
Aug 23 09:08:16 PM UTC 24 |
8881093036 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2310148913 |
|
|
Aug 23 09:07:58 PM UTC 24 |
Aug 23 09:08:17 PM UTC 24 |
17764748839 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.4143467787 |
|
|
Aug 23 09:07:33 PM UTC 24 |
Aug 23 09:08:18 PM UTC 24 |
3385705410 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.4270823403 |
|
|
Aug 23 09:08:17 PM UTC 24 |
Aug 23 09:08:21 PM UTC 24 |
1582376448 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.3439978385 |
|
|
Aug 23 09:08:08 PM UTC 24 |
Aug 23 09:08:21 PM UTC 24 |
1343787488 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.2742572205 |
|
|
Aug 23 09:08:17 PM UTC 24 |
Aug 23 09:08:21 PM UTC 24 |
742553303 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.1691034937 |
|
|
Aug 23 09:08:18 PM UTC 24 |
Aug 23 09:08:23 PM UTC 24 |
586254206 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.2109828691 |
|
|
Aug 23 09:08:22 PM UTC 24 |
Aug 23 09:08:24 PM UTC 24 |
48028550 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.3148791403 |
|
|
Aug 23 09:08:23 PM UTC 24 |
Aug 23 09:08:25 PM UTC 24 |
70953980 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.1135841569 |
|
|
Aug 23 09:08:17 PM UTC 24 |
Aug 23 09:08:26 PM UTC 24 |
399870429 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3472934710 |
|
|
Aug 23 09:08:27 PM UTC 24 |
Aug 23 09:08:29 PM UTC 24 |
154501887 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.863342933 |
|
|
Aug 23 09:08:25 PM UTC 24 |
Aug 23 09:08:30 PM UTC 24 |
1788399201 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.573652295 |
|
|
Aug 23 09:08:29 PM UTC 24 |
Aug 23 09:08:32 PM UTC 24 |
58030634 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.3614433531 |
|
|
Aug 23 09:08:38 PM UTC 24 |
Aug 23 09:08:44 PM UTC 24 |
164649199 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.1564041589 |
|
|
Aug 23 09:08:19 PM UTC 24 |
Aug 23 09:08:46 PM UTC 24 |
4217317901 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.950110514 |
|
|
Aug 23 09:08:47 PM UTC 24 |
Aug 23 09:08:50 PM UTC 24 |
71056223 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.3813132985 |
|
|
Aug 23 09:03:47 PM UTC 24 |
Aug 23 09:08:50 PM UTC 24 |
467907675209 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.2322090648 |
|
|
Aug 23 09:08:26 PM UTC 24 |
Aug 23 09:08:52 PM UTC 24 |
19957923856 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.2871944990 |
|
|
Aug 23 09:07:12 PM UTC 24 |
Aug 23 09:08:59 PM UTC 24 |
47432846348 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.1640539179 |
|
|
Aug 23 09:08:51 PM UTC 24 |
Aug 23 09:08:59 PM UTC 24 |
584501463 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.3880365613 |
|
|
Aug 23 09:08:33 PM UTC 24 |
Aug 23 09:09:01 PM UTC 24 |
9577345225 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.752490029 |
|
|
Aug 23 09:08:51 PM UTC 24 |
Aug 23 09:09:03 PM UTC 24 |
1190528069 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1572627874 |
|
|
Aug 23 09:08:22 PM UTC 24 |
Aug 23 09:09:03 PM UTC 24 |
4109817957 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.892958974 |
|
|
Aug 23 09:08:45 PM UTC 24 |
Aug 23 09:09:03 PM UTC 24 |
2288934958 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.1314420233 |
|
|
Aug 23 09:09:05 PM UTC 24 |
Aug 23 09:09:07 PM UTC 24 |
17533458 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2921916814 |
|
|
Aug 23 09:09:07 PM UTC 24 |
Aug 23 09:09:09 PM UTC 24 |
13509939 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.68264888 |
|
|
Aug 23 09:09:00 PM UTC 24 |
Aug 23 09:09:10 PM UTC 24 |
4124044804 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1054640419 |
|
|
Aug 23 09:09:09 PM UTC 24 |
Aug 23 09:09:11 PM UTC 24 |
31181821 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.673077394 |
|
|
Aug 23 09:06:40 PM UTC 24 |
Aug 23 09:09:12 PM UTC 24 |
36472892606 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.1782356439 |
|
|
Aug 23 09:08:15 PM UTC 24 |
Aug 23 09:09:14 PM UTC 24 |
6057127100 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.3148145899 |
|
|
Aug 23 09:09:12 PM UTC 24 |
Aug 23 09:09:14 PM UTC 24 |
63872460 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3960474240 |
|
|
Aug 23 09:09:00 PM UTC 24 |
Aug 23 09:09:15 PM UTC 24 |
1668404225 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.3144098662 |
|
|
Aug 23 09:09:13 PM UTC 24 |
Aug 23 09:09:17 PM UTC 24 |
1584877783 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.2563153241 |
|
|
Aug 23 09:02:48 PM UTC 24 |
Aug 23 09:09:22 PM UTC 24 |
42719221126 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.1060056374 |
|
|
Aug 23 09:08:18 PM UTC 24 |
Aug 23 09:09:24 PM UTC 24 |
3834551183 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.3912729039 |
|
|
Aug 23 09:09:18 PM UTC 24 |
Aug 23 09:09:25 PM UTC 24 |
1071603036 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2633013870 |
|
|
Aug 23 09:09:15 PM UTC 24 |
Aug 23 09:09:26 PM UTC 24 |
11890911206 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3464433167 |
|
|
Aug 23 09:09:25 PM UTC 24 |
Aug 23 09:09:28 PM UTC 24 |
76431456 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.1625060676 |
|
|
Aug 23 09:09:16 PM UTC 24 |
Aug 23 09:09:29 PM UTC 24 |
13760959911 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.218352219 |
|
|
Aug 23 09:09:15 PM UTC 24 |
Aug 23 09:09:30 PM UTC 24 |
7322819616 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.1966740656 |
|
|
Aug 23 09:09:26 PM UTC 24 |
Aug 23 09:09:31 PM UTC 24 |
558816530 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.2052745106 |
|
|
Aug 23 09:09:22 PM UTC 24 |
Aug 23 09:09:32 PM UTC 24 |
3460342806 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2330093904 |
|
|
Aug 23 09:09:28 PM UTC 24 |
Aug 23 09:09:35 PM UTC 24 |
299430305 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.1795219471 |
|
|
Aug 23 09:09:36 PM UTC 24 |
Aug 23 09:09:38 PM UTC 24 |
14815769 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.3596268244 |
|
|
Aug 23 09:09:12 PM UTC 24 |
Aug 23 09:09:39 PM UTC 24 |
2919001772 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.4042754057 |
|
|
Aug 23 09:09:39 PM UTC 24 |
Aug 23 09:09:41 PM UTC 24 |
49494217 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2493640168 |
|
|
Aug 23 09:08:53 PM UTC 24 |
Aug 23 09:09:45 PM UTC 24 |
11175844923 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.2438897872 |
|
|
Aug 23 09:09:46 PM UTC 24 |
Aug 23 09:09:48 PM UTC 24 |
661589415 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.3493562362 |
|
|
Aug 23 09:03:16 PM UTC 24 |
Aug 23 09:09:48 PM UTC 24 |
242096248841 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.4240532662 |
|
|
Aug 23 09:09:40 PM UTC 24 |
Aug 23 09:09:50 PM UTC 24 |
6003120862 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.456940131 |
|
|
Aug 23 09:09:49 PM UTC 24 |
Aug 23 09:09:51 PM UTC 24 |
15347380 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.1839511711 |
|
|
Aug 23 09:09:31 PM UTC 24 |
Aug 23 09:09:54 PM UTC 24 |
1557251113 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.3370270386 |
|
|
Aug 23 09:09:52 PM UTC 24 |
Aug 23 09:09:55 PM UTC 24 |
300257241 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.2568841302 |
|
|
Aug 23 09:09:52 PM UTC 24 |
Aug 23 09:09:57 PM UTC 24 |
219306138 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.2351900504 |
|
|
Aug 23 09:07:06 PM UTC 24 |
Aug 23 09:09:58 PM UTC 24 |
98740367346 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.2022051368 |
|
|
Aug 23 09:09:49 PM UTC 24 |
Aug 23 09:10:00 PM UTC 24 |
3451164635 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.3133706853 |
|
|
Aug 23 09:09:57 PM UTC 24 |
Aug 23 09:10:01 PM UTC 24 |
214509036 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.997777672 |
|
|
Aug 23 09:10:01 PM UTC 24 |
Aug 23 09:10:07 PM UTC 24 |
924356175 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.2559455376 |
|
|
Aug 23 09:09:56 PM UTC 24 |
Aug 23 09:10:13 PM UTC 24 |
3456389360 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.1424611410 |
|
|
Aug 23 09:09:41 PM UTC 24 |
Aug 23 09:10:16 PM UTC 24 |
25861916068 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.1580906254 |
|
|
Aug 23 09:10:07 PM UTC 24 |
Aug 23 09:10:25 PM UTC 24 |
819639809 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.3373986524 |
|
|
Aug 23 09:10:00 PM UTC 24 |
Aug 23 09:10:25 PM UTC 24 |
5610483915 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.3160942011 |
|
|
Aug 23 09:10:26 PM UTC 24 |
Aug 23 09:10:28 PM UTC 24 |
15609203 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.3825482581 |
|
|
Aug 23 09:10:30 PM UTC 24 |
Aug 23 09:10:32 PM UTC 24 |
137197539 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3571984507 |
|
|
Aug 23 09:10:17 PM UTC 24 |
Aug 23 09:10:33 PM UTC 24 |
1229304932 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.502007596 |
|
|
Aug 23 09:10:34 PM UTC 24 |
Aug 23 09:10:37 PM UTC 24 |
1471475993 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1162319546 |
|
|
Aug 23 09:10:33 PM UTC 24 |
Aug 23 09:10:37 PM UTC 24 |
353604602 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.4072151553 |
|
|
Aug 23 09:09:01 PM UTC 24 |
Aug 23 09:10:39 PM UTC 24 |
47918996465 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.2217621507 |
|
|
Aug 23 09:10:39 PM UTC 24 |
Aug 23 09:10:40 PM UTC 24 |
66602675 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.670350400 |
|
|
Aug 23 09:10:39 PM UTC 24 |
Aug 23 09:10:41 PM UTC 24 |
158001416 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.2027251219 |
|
|
Aug 23 09:03:13 PM UTC 24 |
Aug 23 09:10:47 PM UTC 24 |
229950619269 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.566086944 |
|
|
Aug 23 09:09:33 PM UTC 24 |
Aug 23 09:10:49 PM UTC 24 |
13576514035 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.476137745 |
|
|
Aug 23 09:10:41 PM UTC 24 |
Aug 23 09:10:50 PM UTC 24 |
3028123775 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.3889976299 |
|
|
Aug 23 09:10:48 PM UTC 24 |
Aug 23 09:10:51 PM UTC 24 |
75263694 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.3886150396 |
|
|
Aug 23 09:10:50 PM UTC 24 |
Aug 23 09:10:53 PM UTC 24 |
615713199 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.3627938962 |
|
|
Aug 23 09:10:42 PM UTC 24 |
Aug 23 09:10:53 PM UTC 24 |
3724750611 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.3933832884 |
|
|
Aug 23 09:10:40 PM UTC 24 |
Aug 23 09:10:55 PM UTC 24 |
8602156582 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.3739162582 |
|
|
Aug 23 09:09:55 PM UTC 24 |
Aug 23 09:11:01 PM UTC 24 |
33175287391 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.3185780877 |
|
|
Aug 23 09:10:54 PM UTC 24 |
Aug 23 09:11:03 PM UTC 24 |
4116152610 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.1485805221 |
|
|
Aug 23 09:11:11 PM UTC 24 |
Aug 23 09:11:13 PM UTC 24 |
541207135 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.1567727147 |
|
|
Aug 23 09:10:51 PM UTC 24 |
Aug 23 09:11:04 PM UTC 24 |
4090894039 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.891263132 |
|
|
Aug 23 09:06:37 PM UTC 24 |
Aug 23 09:11:06 PM UTC 24 |
67158334024 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.939300688 |
|
|
Aug 23 09:11:05 PM UTC 24 |
Aug 23 09:11:07 PM UTC 24 |
43172932 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.2306857684 |
|
|
Aug 23 09:11:06 PM UTC 24 |
Aug 23 09:11:08 PM UTC 24 |
42214350 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.2959286367 |
|
|
Aug 23 09:11:07 PM UTC 24 |
Aug 23 09:11:09 PM UTC 24 |
13952176 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.958131000 |
|
|
Aug 23 09:10:14 PM UTC 24 |
Aug 23 09:11:10 PM UTC 24 |
11341777616 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.2774335683 |
|
|
Aug 23 09:11:09 PM UTC 24 |
Aug 23 09:11:10 PM UTC 24 |
11068987 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.3364427710 |
|
|
Aug 23 09:09:05 PM UTC 24 |
Aug 23 09:11:12 PM UTC 24 |
24422973489 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2663716929 |
|
|
Aug 23 09:11:11 PM UTC 24 |
Aug 23 09:11:13 PM UTC 24 |
45048958 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.1066724001 |
|
|
Aug 23 09:06:40 PM UTC 24 |
Aug 23 09:11:14 PM UTC 24 |
28549932461 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.1259065512 |
|
|
Aug 23 09:11:14 PM UTC 24 |
Aug 23 09:11:21 PM UTC 24 |
1318571703 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.1527950778 |
|
|
Aug 23 09:09:27 PM UTC 24 |
Aug 23 09:11:21 PM UTC 24 |
17920392027 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.2911532084 |
|
|
Aug 23 09:07:39 PM UTC 24 |
Aug 23 09:11:23 PM UTC 24 |
25435510462 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.358871088 |
|
|
Aug 23 09:11:23 PM UTC 24 |
Aug 23 09:11:26 PM UTC 24 |
261775114 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.4117221692 |
|
|
Aug 23 09:11:23 PM UTC 24 |
Aug 23 09:11:27 PM UTC 24 |
408918113 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.2158132016 |
|
|
Aug 23 09:11:10 PM UTC 24 |
Aug 23 09:11:32 PM UTC 24 |
16664042537 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.1176684774 |
|
|
Aug 23 09:11:27 PM UTC 24 |
Aug 23 09:11:32 PM UTC 24 |
2880231449 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.2824341456 |
|
|
Aug 23 09:10:56 PM UTC 24 |
Aug 23 09:11:34 PM UTC 24 |
8326128897 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.4195884991 |
|
|
Aug 23 09:09:32 PM UTC 24 |
Aug 23 09:11:35 PM UTC 24 |
77139432024 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1414768064 |
|
|
Aug 23 09:08:17 PM UTC 24 |
Aug 23 09:11:36 PM UTC 24 |
28823337174 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.170854543 |
|
|
Aug 23 09:11:38 PM UTC 24 |
Aug 23 09:11:39 PM UTC 24 |
36733585 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.397297242 |
|
|
Aug 23 09:11:40 PM UTC 24 |
Aug 23 09:11:42 PM UTC 24 |
17887573 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.239202288 |
|
|
Aug 23 09:11:13 PM UTC 24 |
Aug 23 09:11:44 PM UTC 24 |
36063520988 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2718793839 |
|
|
Aug 23 09:06:12 PM UTC 24 |
Aug 23 09:11:45 PM UTC 24 |
41411027104 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.3380224366 |
|
|
Aug 23 09:11:46 PM UTC 24 |
Aug 23 09:11:48 PM UTC 24 |
41877515 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.1227408532 |
|
|
Aug 23 09:11:14 PM UTC 24 |
Aug 23 09:11:50 PM UTC 24 |
34838777465 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.3660460571 |
|
|
Aug 23 09:11:15 PM UTC 24 |
Aug 23 09:11:51 PM UTC 24 |
9636718440 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.3791055424 |
|
|
Aug 23 09:11:24 PM UTC 24 |
Aug 23 09:11:51 PM UTC 24 |
1707285085 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.1898647551 |
|
|
Aug 23 09:11:49 PM UTC 24 |
Aug 23 09:11:52 PM UTC 24 |
88735374 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.1077901791 |
|
|
Aug 23 09:10:52 PM UTC 24 |
Aug 23 09:11:53 PM UTC 24 |
4455562389 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2008916759 |
|
|
Aug 23 09:11:42 PM UTC 24 |
Aug 23 09:11:53 PM UTC 24 |
46678736039 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.2314799420 |
|
|
Aug 23 09:09:03 PM UTC 24 |
Aug 23 09:11:56 PM UTC 24 |
16107263116 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.1476345064 |
|
|
Aug 23 09:06:43 PM UTC 24 |
Aug 23 09:11:58 PM UTC 24 |
176720499490 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3904550450 |
|
|
Aug 23 09:11:54 PM UTC 24 |
Aug 23 09:12:00 PM UTC 24 |
983469229 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.1841638118 |
|
|
Aug 23 09:11:54 PM UTC 24 |
Aug 23 09:12:02 PM UTC 24 |
5691593062 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.2817005660 |
|
|
Aug 23 09:11:58 PM UTC 24 |
Aug 23 09:12:02 PM UTC 24 |
83812555 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.2738078753 |
|
|
Aug 23 09:12:03 PM UTC 24 |
Aug 23 09:12:04 PM UTC 24 |
144500500 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.4068575874 |
|
|
Aug 23 09:11:52 PM UTC 24 |
Aug 23 09:12:08 PM UTC 24 |
13048361380 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.2793022608 |
|
|
Aug 23 09:12:01 PM UTC 24 |
Aug 23 09:12:09 PM UTC 24 |
1232720607 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.285021113 |
|
|
Aug 23 09:11:52 PM UTC 24 |
Aug 23 09:12:09 PM UTC 24 |
2422622844 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3629886446 |
|
|
Aug 23 09:11:50 PM UTC 24 |
Aug 23 09:12:10 PM UTC 24 |
25137943345 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.2931744803 |
|
|
Aug 23 09:12:09 PM UTC 24 |
Aug 23 09:12:11 PM UTC 24 |
14237884 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.761762928 |
|
|
Aug 23 09:12:11 PM UTC 24 |
Aug 23 09:12:13 PM UTC 24 |
36113892 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.181063632 |
|
|
Aug 23 09:11:44 PM UTC 24 |
Aug 23 09:12:15 PM UTC 24 |
3497664119 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.1966346000 |
|
|
Aug 23 09:12:13 PM UTC 24 |
Aug 23 09:12:15 PM UTC 24 |
431292861 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.4173375435 |
|
|
Aug 23 09:12:16 PM UTC 24 |
Aug 23 09:12:18 PM UTC 24 |
92091022 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.457512916 |
|
|
Aug 23 09:11:33 PM UTC 24 |
Aug 23 09:12:18 PM UTC 24 |
13159260926 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.765076389 |
|
|
Aug 23 09:11:05 PM UTC 24 |
Aug 23 09:12:19 PM UTC 24 |
19962068349 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.3540601665 |
|
|
Aug 23 09:12:17 PM UTC 24 |
Aug 23 09:12:20 PM UTC 24 |
46792772 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.202090402 |
|
|
Aug 23 09:12:19 PM UTC 24 |
Aug 23 09:12:23 PM UTC 24 |
124016473 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.719479634 |
|
|
Aug 23 09:07:40 PM UTC 24 |
Aug 23 09:12:27 PM UTC 24 |
28306028616 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.493537127 |
|
|
Aug 23 09:07:45 PM UTC 24 |
Aug 23 09:12:28 PM UTC 24 |
54415461862 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.1927328924 |
|
|
Aug 23 09:11:53 PM UTC 24 |
Aug 23 09:12:29 PM UTC 24 |
15677803920 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.1688104929 |
|
|
Aug 23 09:12:11 PM UTC 24 |
Aug 23 09:12:30 PM UTC 24 |
14200983632 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1777581133 |
|
|
Aug 23 09:11:02 PM UTC 24 |
Aug 23 09:12:33 PM UTC 24 |
6322996084 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.1601580609 |
|
|
Aug 23 09:12:12 PM UTC 24 |
Aug 23 09:12:33 PM UTC 24 |
18412434303 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.2047741186 |
|
|
Aug 23 09:12:21 PM UTC 24 |
Aug 23 09:12:33 PM UTC 24 |
4878829932 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.1608453543 |
|
|
Aug 23 09:12:19 PM UTC 24 |
Aug 23 09:12:33 PM UTC 24 |
6616546821 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3722680743 |
|
|
Aug 23 09:12:24 PM UTC 24 |
Aug 23 09:12:35 PM UTC 24 |
2079736499 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.4154227107 |
|
|
Aug 23 09:10:01 PM UTC 24 |
Aug 23 09:12:36 PM UTC 24 |
18976202893 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.3900375720 |
|
|
Aug 23 09:12:35 PM UTC 24 |
Aug 23 09:12:37 PM UTC 24 |
21227068 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.1329935757 |
|
|
Aug 23 09:12:21 PM UTC 24 |
Aug 23 09:12:38 PM UTC 24 |
8543400363 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.2803208550 |
|
|
Aug 23 09:12:36 PM UTC 24 |
Aug 23 09:12:38 PM UTC 24 |
28264572 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1888638167 |
|
|
Aug 23 09:12:31 PM UTC 24 |
Aug 23 09:12:39 PM UTC 24 |
3291407081 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.1771329023 |
|
|
Aug 23 09:12:38 PM UTC 24 |
Aug 23 09:12:39 PM UTC 24 |
39117377 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.4180635059 |
|
|
Aug 23 09:12:27 PM UTC 24 |
Aug 23 09:12:41 PM UTC 24 |
6391771823 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.3643070423 |
|
|
Aug 23 09:12:39 PM UTC 24 |
Aug 23 09:12:41 PM UTC 24 |
102573227 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.59483160 |
|
|
Aug 23 09:12:39 PM UTC 24 |
Aug 23 09:12:42 PM UTC 24 |
165611010 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2855102881 |
|
|
Aug 23 09:12:39 PM UTC 24 |
Aug 23 09:12:42 PM UTC 24 |
356158410 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.1556100053 |
|
|
Aug 23 09:12:41 PM UTC 24 |
Aug 23 09:12:44 PM UTC 24 |
191600940 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2867640470 |
|
|
Aug 23 09:12:06 PM UTC 24 |
Aug 23 09:12:46 PM UTC 24 |
9855342809 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2256189788 |
|
|
Aug 23 09:11:27 PM UTC 24 |
Aug 23 09:12:47 PM UTC 24 |
19340655668 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2763428443 |
|
|
Aug 23 09:12:44 PM UTC 24 |
Aug 23 09:12:47 PM UTC 24 |
149451615 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.4249322319 |
|
|
Aug 23 09:12:42 PM UTC 24 |
Aug 23 09:12:47 PM UTC 24 |
405698965 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.1573109120 |
|
|
Aug 23 09:12:43 PM UTC 24 |
Aug 23 09:12:48 PM UTC 24 |
1677276258 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3360570529 |
|
|
Aug 23 09:12:34 PM UTC 24 |
Aug 23 09:12:52 PM UTC 24 |
2367750979 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1359433976 |
|
|
Aug 23 09:12:48 PM UTC 24 |
Aug 23 09:12:54 PM UTC 24 |
1167350567 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.1554039067 |
|
|
Aug 23 09:12:38 PM UTC 24 |
Aug 23 09:12:55 PM UTC 24 |
3932056904 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.2466104669 |
|
|
Aug 23 09:11:35 PM UTC 24 |
Aug 23 09:12:55 PM UTC 24 |
6434446175 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.3051027647 |
|
|
Aug 23 09:09:30 PM UTC 24 |
Aug 23 09:12:55 PM UTC 24 |
155453073235 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.1630191666 |
|
|
Aug 23 09:12:45 PM UTC 24 |
Aug 23 09:12:55 PM UTC 24 |
799250952 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.2059633942 |
|
|
Aug 23 09:12:55 PM UTC 24 |
Aug 23 09:12:56 PM UTC 24 |
22728813 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.3973366280 |
|
|
Aug 23 09:12:57 PM UTC 24 |
Aug 23 09:12:59 PM UTC 24 |
55167172 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2661078371 |
|
|
Aug 23 09:12:57 PM UTC 24 |
Aug 23 09:12:59 PM UTC 24 |
237892456 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.2501907156 |
|
|
Aug 23 09:12:43 PM UTC 24 |
Aug 23 09:12:59 PM UTC 24 |
6561564258 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.1455257448 |
|
|
Aug 23 09:12:57 PM UTC 24 |
Aug 23 09:13:01 PM UTC 24 |
285238073 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.740332575 |
|
|
Aug 23 09:12:59 PM UTC 24 |
Aug 23 09:13:02 PM UTC 24 |
509120645 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.1861878920 |
|
|
Aug 23 09:13:01 PM UTC 24 |
Aug 23 09:13:05 PM UTC 24 |
510727249 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.2714165614 |
|
|
Aug 23 09:13:06 PM UTC 24 |
Aug 23 09:13:11 PM UTC 24 |
440051764 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.476586619 |
|
|
Aug 23 09:13:02 PM UTC 24 |
Aug 23 09:13:11 PM UTC 24 |
288522338 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.226762078 |
|
|
Aug 23 09:13:03 PM UTC 24 |
Aug 23 09:13:12 PM UTC 24 |
4471165061 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.3021774563 |
|
|
Aug 23 09:12:57 PM UTC 24 |
Aug 23 09:13:14 PM UTC 24 |
86870477015 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.3587742921 |
|
|
Aug 23 09:13:12 PM UTC 24 |
Aug 23 09:13:18 PM UTC 24 |
766152269 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.1566513388 |
|
|
Aug 23 09:12:59 PM UTC 24 |
Aug 23 09:13:18 PM UTC 24 |
7492559491 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1937103398 |
|
|
Aug 23 09:13:13 PM UTC 24 |
Aug 23 09:13:23 PM UTC 24 |
1071699879 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.3288191391 |
|
|
Aug 23 09:12:31 PM UTC 24 |
Aug 23 09:13:24 PM UTC 24 |
10585320507 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2447116509 |
|
|
Aug 23 09:12:30 PM UTC 24 |
Aug 23 09:13:24 PM UTC 24 |
43506770712 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.1563901318 |
|
|
Aug 23 09:11:36 PM UTC 24 |
Aug 23 09:13:26 PM UTC 24 |
33324164820 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.1057871148 |
|
|
Aug 23 09:13:24 PM UTC 24 |
Aug 23 09:13:27 PM UTC 24 |
33602417 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.1687898814 |
|
|
Aug 23 09:12:57 PM UTC 24 |
Aug 23 09:13:28 PM UTC 24 |
12746808397 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.136911617 |
|
|
Aug 23 09:12:49 PM UTC 24 |
Aug 23 09:13:31 PM UTC 24 |
5372550995 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.312682647 |
|
|
Aug 23 09:10:54 PM UTC 24 |
Aug 23 09:13:32 PM UTC 24 |
183169224689 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.3488385149 |
|
|
Aug 23 09:12:48 PM UTC 24 |
Aug 23 09:13:38 PM UTC 24 |
4890653931 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.993705501 |
|
|
Aug 23 09:11:33 PM UTC 24 |
Aug 23 09:13:49 PM UTC 24 |
40958701536 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.2418383269 |
|
|
Aug 23 09:11:59 PM UTC 24 |
Aug 23 09:13:57 PM UTC 24 |
35123056815 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3796226466 |
|
|
Aug 23 09:13:13 PM UTC 24 |
Aug 23 09:14:02 PM UTC 24 |
3282115588 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.4038033034 |
|
|
Aug 23 09:12:49 PM UTC 24 |
Aug 23 09:14:04 PM UTC 24 |
5191729381 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1536822004 |
|
|
Aug 23 09:12:09 PM UTC 24 |
Aug 23 09:14:07 PM UTC 24 |
14229103729 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.3000954236 |
|
|
Aug 23 09:10:26 PM UTC 24 |
Aug 23 09:14:16 PM UTC 24 |
21901084117 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.858472814 |
|
|
Aug 23 09:12:03 PM UTC 24 |
Aug 23 09:14:35 PM UTC 24 |
24289224411 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.1901565278 |
|
|
Aug 23 09:12:34 PM UTC 24 |
Aug 23 09:14:40 PM UTC 24 |
14527830284 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.640048929 |
|
|
Aug 23 09:13:19 PM UTC 24 |
Aug 23 09:15:04 PM UTC 24 |
29028408059 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.3616909008 |
|
|
Aug 23 09:13:19 PM UTC 24 |
Aug 23 09:15:15 PM UTC 24 |
13396347956 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.4048490478 |
|
|
Aug 23 09:12:48 PM UTC 24 |
Aug 23 09:15:49 PM UTC 24 |
54065780498 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.1162463790 |
|
|
Aug 23 09:13:24 PM UTC 24 |
Aug 23 09:16:09 PM UTC 24 |
66430422492 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.1699641171 |
|
|
Aug 23 09:13:14 PM UTC 24 |
Aug 23 09:16:25 PM UTC 24 |
150845195711 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.1104515776 |
|
|
Aug 23 09:12:34 PM UTC 24 |
Aug 23 09:17:19 PM UTC 24 |
33895320201 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.3709319793 |
|
|
Aug 23 09:08:22 PM UTC 24 |
Aug 23 09:18:40 PM UTC 24 |
74983112928 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.3567496919 |
|
|
Aug 23 09:06:14 PM UTC 24 |
Aug 23 09:18:51 PM UTC 24 |
1417954005022 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.3094719662 |
|
|
Aug 23 09:12:52 PM UTC 24 |
Aug 23 09:20:46 PM UTC 24 |
101998964511 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2449381641 |
|
|
Aug 23 07:34:41 PM UTC 24 |
Aug 23 07:34:42 PM UTC 24 |
10188233 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.971848486 |
|
|
Aug 23 07:34:40 PM UTC 24 |
Aug 23 07:34:42 PM UTC 24 |
12196647 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2665239653 |
|
|
Aug 23 07:34:42 PM UTC 24 |
Aug 23 07:34:44 PM UTC 24 |
61830348 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1084354465 |
|
|
Aug 23 07:34:41 PM UTC 24 |
Aug 23 07:34:44 PM UTC 24 |
55345884 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.87874969 |
|
|
Aug 23 07:34:42 PM UTC 24 |
Aug 23 07:34:44 PM UTC 24 |
160423427 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2652480785 |
|
|
Aug 23 07:34:40 PM UTC 24 |
Aug 23 07:34:45 PM UTC 24 |
548431575 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3474309706 |
|
|
Aug 23 07:34:43 PM UTC 24 |
Aug 23 07:34:45 PM UTC 24 |
59313854 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2973374979 |
|
|
Aug 23 07:34:51 PM UTC 24 |
Aug 23 07:35:07 PM UTC 24 |
1144351134 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.555940441 |
|
|
Aug 23 07:34:45 PM UTC 24 |
Aug 23 07:34:47 PM UTC 24 |
54444518 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1003319283 |
|
|
Aug 23 07:34:46 PM UTC 24 |
Aug 23 07:34:48 PM UTC 24 |
15411241 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.1042517082 |
|
|
Aug 23 07:34:46 PM UTC 24 |
Aug 23 07:34:48 PM UTC 24 |
12113369 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.100589064 |
|
|
Aug 23 07:34:46 PM UTC 24 |
Aug 23 07:34:49 PM UTC 24 |
66323846 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3925008244 |
|
|
Aug 23 07:34:40 PM UTC 24 |
Aug 23 07:34:49 PM UTC 24 |
353315152 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.36622779 |
|
|
Aug 23 07:34:47 PM UTC 24 |
Aug 23 07:34:49 PM UTC 24 |
22868836 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.621933937 |
|
|
Aug 23 07:34:45 PM UTC 24 |
Aug 23 07:34:50 PM UTC 24 |
179458550 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3732304022 |
|
|
Aug 23 07:34:48 PM UTC 24 |
Aug 23 07:34:50 PM UTC 24 |
41264115 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2172526418 |
|
|
Aug 23 07:34:49 PM UTC 24 |
Aug 23 07:34:51 PM UTC 24 |
24980416 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.3965301572 |
|
|
Aug 23 07:34:49 PM UTC 24 |
Aug 23 07:34:51 PM UTC 24 |
41953510 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2452947000 |
|
|
Aug 23 07:34:49 PM UTC 24 |
Aug 23 07:34:52 PM UTC 24 |
79101170 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.3855132907 |
|
|
Aug 23 07:34:49 PM UTC 24 |
Aug 23 07:34:52 PM UTC 24 |
232693622 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3922227547 |
|
|
Aug 23 07:34:48 PM UTC 24 |
Aug 23 07:34:52 PM UTC 24 |
122797682 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.4037259192 |
|
|
Aug 23 07:34:48 PM UTC 24 |
Aug 23 07:34:52 PM UTC 24 |
216860793 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3836494927 |
|
|
Aug 23 07:34:48 PM UTC 24 |
Aug 23 07:34:52 PM UTC 24 |
163669826 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2543063750 |
|
|
Aug 23 07:34:50 PM UTC 24 |
Aug 23 07:34:53 PM UTC 24 |
49956489 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.4096892458 |
|
|
Aug 23 07:35:06 PM UTC 24 |
Aug 23 07:35:07 PM UTC 24 |
46360081 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2485497205 |
|
|
Aug 23 07:34:50 PM UTC 24 |
Aug 23 07:34:53 PM UTC 24 |
56647900 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1972606319 |
|
|
Aug 23 07:34:51 PM UTC 24 |
Aug 23 07:34:53 PM UTC 24 |
37137928 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.1373668602 |
|
|
Aug 23 07:34:51 PM UTC 24 |
Aug 23 07:34:53 PM UTC 24 |
26173714 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3446055611 |
|
|
Aug 23 07:34:42 PM UTC 24 |
Aug 23 07:34:55 PM UTC 24 |
907541782 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1816322443 |
|
|
Aug 23 07:34:50 PM UTC 24 |
Aug 23 07:34:55 PM UTC 24 |
57445461 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.3466516639 |
|
|
Aug 23 07:34:53 PM UTC 24 |
Aug 23 07:34:55 PM UTC 24 |
52616383 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1706380729 |
|
|
Aug 23 07:34:53 PM UTC 24 |
Aug 23 07:34:55 PM UTC 24 |
59088364 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3201276919 |
|
|
Aug 23 07:35:08 PM UTC 24 |
Aug 23 07:35:11 PM UTC 24 |
213825950 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.626284511 |
|
|
Aug 23 07:34:48 PM UTC 24 |
Aug 23 07:34:55 PM UTC 24 |
659390089 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.1780799858 |
|
|
Aug 23 07:34:53 PM UTC 24 |
Aug 23 07:34:56 PM UTC 24 |
90752064 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2479700444 |
|
|
Aug 23 07:34:51 PM UTC 24 |
Aug 23 07:34:56 PM UTC 24 |
273881271 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2394041506 |
|
|
Aug 23 07:34:54 PM UTC 24 |
Aug 23 07:34:56 PM UTC 24 |
188065072 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.1340292183 |
|
|
Aug 23 07:34:55 PM UTC 24 |
Aug 23 07:34:57 PM UTC 24 |
25000712 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3430722762 |
|
|
Aug 23 07:34:54 PM UTC 24 |
Aug 23 07:34:57 PM UTC 24 |
153976276 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.2179518781 |
|
|
Aug 23 07:34:56 PM UTC 24 |
Aug 23 07:34:58 PM UTC 24 |
16169461 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.601062472 |
|
|
Aug 23 07:34:43 PM UTC 24 |
Aug 23 07:34:58 PM UTC 24 |
877870400 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3453411787 |
|
|
Aug 23 07:34:56 PM UTC 24 |
Aug 23 07:34:58 PM UTC 24 |
115005240 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.112993186 |
|
|
Aug 23 07:34:56 PM UTC 24 |
Aug 23 07:34:58 PM UTC 24 |
34107986 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1495795476 |
|
|
Aug 23 07:34:56 PM UTC 24 |
Aug 23 07:34:59 PM UTC 24 |
155194653 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.781912415 |
|
|
Aug 23 07:34:54 PM UTC 24 |
Aug 23 07:34:59 PM UTC 24 |
411711424 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.1886076963 |
|
|
Aug 23 07:34:57 PM UTC 24 |
Aug 23 07:35:01 PM UTC 24 |
84343860 ps |