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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1129
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T182 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.3827123672 Aug 23 08:59:10 PM UTC 24 Aug 23 09:00:32 PM UTC 24 16821404686 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.3871240088 Aug 23 09:00:30 PM UTC 24 Aug 23 09:00:32 PM UTC 24 73217457 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.1524966183 Aug 23 09:00:25 PM UTC 24 Aug 23 09:00:35 PM UTC 24 813751916 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.893829056 Aug 23 09:00:33 PM UTC 24 Aug 23 09:00:37 PM UTC 24 716440270 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.4223207343 Aug 23 09:00:33 PM UTC 24 Aug 23 09:00:38 PM UTC 24 995115312 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.3460552502 Aug 23 09:00:32 PM UTC 24 Aug 23 09:00:46 PM UTC 24 4449838922 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.3931147255 Aug 23 09:00:39 PM UTC 24 Aug 23 09:00:48 PM UTC 24 735531260 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.3777039155 Aug 23 09:00:36 PM UTC 24 Aug 23 09:00:56 PM UTC 24 1700501217 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.397511331 Aug 23 09:00:16 PM UTC 24 Aug 23 09:01:00 PM UTC 24 3469051721 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.4201653967 Aug 23 09:00:57 PM UTC 24 Aug 23 09:01:01 PM UTC 24 242943549 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.1012930944 Aug 23 09:00:39 PM UTC 24 Aug 23 09:01:06 PM UTC 24 6036462575 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.886582395 Aug 23 08:58:36 PM UTC 24 Aug 23 09:01:08 PM UTC 24 25742488550 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1430500888 Aug 23 08:59:08 PM UTC 24 Aug 23 09:01:10 PM UTC 24 14540055896 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.2309296142 Aug 23 09:01:02 PM UTC 24 Aug 23 09:01:10 PM UTC 24 1765337713 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.3597370217 Aug 23 09:01:09 PM UTC 24 Aug 23 09:01:11 PM UTC 24 47538112 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.1418344078 Aug 23 09:01:11 PM UTC 24 Aug 23 09:01:13 PM UTC 24 19348008 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.1919627070 Aug 23 09:01:14 PM UTC 24 Aug 23 09:01:15 PM UTC 24 161850645 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.1917972418 Aug 23 08:57:07 PM UTC 24 Aug 23 09:01:18 PM UTC 24 78943743677 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.921282203 Aug 23 09:01:16 PM UTC 24 Aug 23 09:01:18 PM UTC 24 29530414 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.161745925 Aug 23 09:01:11 PM UTC 24 Aug 23 09:01:20 PM UTC 24 4339562846 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.727382218 Aug 23 09:00:47 PM UTC 24 Aug 23 09:01:25 PM UTC 24 2687218728 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.1071565771 Aug 23 09:01:21 PM UTC 24 Aug 23 09:01:26 PM UTC 24 207151461 ps
T235 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.3498903461 Aug 23 09:01:19 PM UTC 24 Aug 23 09:01:28 PM UTC 24 1832047504 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.3868804389 Aug 23 09:01:11 PM UTC 24 Aug 23 09:01:30 PM UTC 24 13862049824 ps
T333 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.97324353 Aug 23 09:01:19 PM UTC 24 Aug 23 09:01:33 PM UTC 24 11035323908 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.2106897197 Aug 23 09:01:27 PM UTC 24 Aug 23 09:01:33 PM UTC 24 1220438825 ps
T279 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.3360058735 Aug 23 09:00:12 PM UTC 24 Aug 23 09:01:34 PM UTC 24 4286295996 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.2032166789 Aug 23 08:55:24 PM UTC 24 Aug 23 09:01:36 PM UTC 24 40640388404 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.3759609303 Aug 23 09:01:29 PM UTC 24 Aug 23 09:01:39 PM UTC 24 1034771471 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.623337322 Aug 23 08:59:38 PM UTC 24 Aug 23 09:01:39 PM UTC 24 59456222128 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.3181231883 Aug 23 09:01:34 PM UTC 24 Aug 23 09:01:40 PM UTC 24 905584139 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.3576057880 Aug 23 09:01:41 PM UTC 24 Aug 23 09:01:43 PM UTC 24 27829266 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.2756510678 Aug 23 08:58:43 PM UTC 24 Aug 23 09:01:44 PM UTC 24 54043588436 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.1370080645 Aug 23 09:01:43 PM UTC 24 Aug 23 09:01:45 PM UTC 24 57633594 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.1069321756 Aug 23 09:01:45 PM UTC 24 Aug 23 09:01:48 PM UTC 24 721658299 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.3621247579 Aug 23 09:00:19 PM UTC 24 Aug 23 09:01:48 PM UTC 24 4597394867 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.1903716158 Aug 23 09:01:47 PM UTC 24 Aug 23 09:01:52 PM UTC 24 364699344 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.2528187146 Aug 23 09:01:49 PM UTC 24 Aug 23 09:01:52 PM UTC 24 28286870 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.3099383826 Aug 23 09:01:49 PM UTC 24 Aug 23 09:01:52 PM UTC 24 45057430 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.4243767617 Aug 23 09:01:53 PM UTC 24 Aug 23 09:01:56 PM UTC 24 62790442 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.3735463858 Aug 23 09:01:53 PM UTC 24 Aug 23 09:01:57 PM UTC 24 309786158 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.771768476 Aug 23 09:01:53 PM UTC 24 Aug 23 09:01:59 PM UTC 24 477204059 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.1884421032 Aug 23 09:01:37 PM UTC 24 Aug 23 09:02:02 PM UTC 24 9208208327 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.3160628323 Aug 23 09:02:00 PM UTC 24 Aug 23 09:02:03 PM UTC 24 44705266 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.1503064112 Aug 23 09:01:57 PM UTC 24 Aug 23 09:02:04 PM UTC 24 2114189861 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.2383682282 Aug 23 09:02:02 PM UTC 24 Aug 23 09:02:06 PM UTC 24 215186925 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.2754642383 Aug 23 09:01:31 PM UTC 24 Aug 23 09:02:08 PM UTC 24 6577778206 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.3894760126 Aug 23 09:01:02 PM UTC 24 Aug 23 09:02:08 PM UTC 24 6333512042 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.286663552 Aug 23 09:01:57 PM UTC 24 Aug 23 09:02:09 PM UTC 24 2073377989 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.402573463 Aug 23 09:01:27 PM UTC 24 Aug 23 09:02:15 PM UTC 24 22899817434 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.1388650450 Aug 23 09:02:05 PM UTC 24 Aug 23 09:02:17 PM UTC 24 3889849853 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.3925882425 Aug 23 09:02:16 PM UTC 24 Aug 23 09:02:17 PM UTC 24 39373824 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.3987917501 Aug 23 09:02:18 PM UTC 24 Aug 23 09:02:20 PM UTC 24 53292163 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.4156310559 Aug 23 09:01:40 PM UTC 24 Aug 23 09:02:24 PM UTC 24 17754805068 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.3078701944 Aug 23 09:02:18 PM UTC 24 Aug 23 09:02:25 PM UTC 24 8656975330 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.4222349905 Aug 23 09:02:25 PM UTC 24 Aug 23 09:02:26 PM UTC 24 27440460 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.440330179 Aug 23 09:02:26 PM UTC 24 Aug 23 09:02:27 PM UTC 24 11981846 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.49239805 Aug 23 08:59:42 PM UTC 24 Aug 23 09:02:28 PM UTC 24 70847953949 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.1382411354 Aug 23 09:02:20 PM UTC 24 Aug 23 09:02:29 PM UTC 24 1624277741 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.1778100019 Aug 23 09:02:27 PM UTC 24 Aug 23 09:02:38 PM UTC 24 7686949103 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.3049063395 Aug 23 09:02:28 PM UTC 24 Aug 23 09:02:39 PM UTC 24 3867749847 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.3519859043 Aug 23 09:02:28 PM UTC 24 Aug 23 09:02:40 PM UTC 24 11849651333 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.167781509 Aug 23 09:00:16 PM UTC 24 Aug 23 09:02:41 PM UTC 24 9672454750 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.2953525754 Aug 23 09:02:39 PM UTC 24 Aug 23 09:02:42 PM UTC 24 70118092 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.3236983422 Aug 23 09:01:35 PM UTC 24 Aug 23 09:02:43 PM UTC 24 176144225918 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.373805707 Aug 23 09:02:29 PM UTC 24 Aug 23 09:02:43 PM UTC 24 8880040337 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.973530951 Aug 23 09:02:10 PM UTC 24 Aug 23 09:02:45 PM UTC 24 5949826830 ps
T231 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.2870232210 Aug 23 08:56:24 PM UTC 24 Aug 23 09:02:47 PM UTC 24 41261697196 ps
T656 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.4144742175 Aug 23 09:02:42 PM UTC 24 Aug 23 09:02:47 PM UTC 24 914726239 ps
T657 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.2071417618 Aug 23 09:02:07 PM UTC 24 Aug 23 09:02:50 PM UTC 24 9742791078 ps
T658 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.2767171003 Aug 23 09:02:48 PM UTC 24 Aug 23 09:02:50 PM UTC 24 38708597 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.3628783873 Aug 23 09:02:41 PM UTC 24 Aug 23 09:02:50 PM UTC 24 424084560 ps
T116 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.3323051585 Aug 23 09:02:40 PM UTC 24 Aug 23 09:02:51 PM UTC 24 3987326004 ps
T659 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.141735192 Aug 23 09:02:51 PM UTC 24 Aug 23 09:02:52 PM UTC 24 20039238 ps
T660 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.549342164 Aug 23 09:02:52 PM UTC 24 Aug 23 09:02:54 PM UTC 24 50652621 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.1366748242 Aug 23 08:58:17 PM UTC 24 Aug 23 09:02:54 PM UTC 24 24414292490 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.1552857872 Aug 23 08:59:41 PM UTC 24 Aug 23 09:02:55 PM UTC 24 77996415604 ps
T661 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.2521950052 Aug 23 09:02:53 PM UTC 24 Aug 23 09:02:56 PM UTC 24 1592739394 ps
T662 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.728177671 Aug 23 09:02:51 PM UTC 24 Aug 23 09:02:58 PM UTC 24 2564638716 ps
T663 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.171941733 Aug 23 09:02:56 PM UTC 24 Aug 23 09:02:59 PM UTC 24 29561697 ps
T664 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.229264563 Aug 23 09:02:56 PM UTC 24 Aug 23 09:03:02 PM UTC 24 22807019565 ps
T665 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.803918228 Aug 23 09:02:59 PM UTC 24 Aug 23 09:03:02 PM UTC 24 31254826 ps
T666 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.653948052 Aug 23 09:02:54 PM UTC 24 Aug 23 09:03:02 PM UTC 24 629813219 ps
T667 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.314259431 Aug 23 09:02:59 PM UTC 24 Aug 23 09:03:07 PM UTC 24 443317274 ps
T668 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.2449877773 Aug 23 09:03:02 PM UTC 24 Aug 23 09:03:08 PM UTC 24 549520151 ps
T669 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.4059202287 Aug 23 09:03:04 PM UTC 24 Aug 23 09:03:13 PM UTC 24 2754228419 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.222549446 Aug 23 09:02:57 PM UTC 24 Aug 23 09:03:15 PM UTC 24 1747079755 ps
T670 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.2450880001 Aug 23 09:02:52 PM UTC 24 Aug 23 09:03:19 PM UTC 24 5532661772 ps
T671 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.2862228044 Aug 23 09:02:46 PM UTC 24 Aug 23 09:03:21 PM UTC 24 30037266866 ps
T672 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.2318819563 Aug 23 09:03:20 PM UTC 24 Aug 23 09:03:22 PM UTC 24 14729875 ps
T673 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.3071641034 Aug 23 09:00:17 PM UTC 24 Aug 23 09:03:22 PM UTC 24 20399264495 ps
T674 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.4213285283 Aug 23 09:03:22 PM UTC 24 Aug 23 09:03:24 PM UTC 24 21131322 ps
T675 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.3654595785 Aug 23 09:03:23 PM UTC 24 Aug 23 09:03:25 PM UTC 24 21156039 ps
T676 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.4057701917 Aug 23 09:03:24 PM UTC 24 Aug 23 09:03:26 PM UTC 24 113266275 ps
T677 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.200854217 Aug 23 09:03:26 PM UTC 24 Aug 23 09:03:27 PM UTC 24 172256833 ps
T678 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.1458011086 Aug 23 09:03:22 PM UTC 24 Aug 23 09:03:28 PM UTC 24 1888316431 ps
T679 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.1077551518 Aug 23 09:03:27 PM UTC 24 Aug 23 09:03:30 PM UTC 24 31032045 ps
T680 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.1732188318 Aug 23 09:00:48 PM UTC 24 Aug 23 09:03:30 PM UTC 24 44579178075 ps
T681 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.1279517310 Aug 23 09:03:28 PM UTC 24 Aug 23 09:03:34 PM UTC 24 234161031 ps
T682 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.3919593670 Aug 23 09:03:35 PM UTC 24 Aug 23 09:03:38 PM UTC 24 396949429 ps
T683 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.443765337 Aug 23 09:03:28 PM UTC 24 Aug 23 09:03:38 PM UTC 24 2318115778 ps
T684 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.2552769435 Aug 23 09:03:32 PM UTC 24 Aug 23 09:03:41 PM UTC 24 677767603 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.2103676713 Aug 23 09:03:04 PM UTC 24 Aug 23 09:03:43 PM UTC 24 2982871314 ps
T685 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.3867502575 Aug 23 09:03:41 PM UTC 24 Aug 23 09:03:46 PM UTC 24 208545879 ps
T686 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.1842590055 Aug 23 09:03:39 PM UTC 24 Aug 23 09:03:46 PM UTC 24 192672164 ps
T687 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.731549977 Aug 23 09:03:39 PM UTC 24 Aug 23 09:03:48 PM UTC 24 2615530757 ps
T688 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.1009670024 Aug 23 09:02:43 PM UTC 24 Aug 23 09:03:49 PM UTC 24 14694554890 ps
T689 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.2617352372 Aug 23 09:03:50 PM UTC 24 Aug 23 09:03:52 PM UTC 24 28847267 ps
T690 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.4217538248 Aug 23 09:03:30 PM UTC 24 Aug 23 09:03:53 PM UTC 24 13139061697 ps
T691 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.3435335579 Aug 23 09:03:53 PM UTC 24 Aug 23 09:03:55 PM UTC 24 70158794 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.3210442024 Aug 23 09:01:40 PM UTC 24 Aug 23 09:03:56 PM UTC 24 7127975609 ps
T692 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.606887005 Aug 23 09:03:57 PM UTC 24 Aug 23 09:03:59 PM UTC 24 201470834 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.3363301561 Aug 23 08:57:08 PM UTC 24 Aug 23 09:04:00 PM UTC 24 193766052727 ps
T693 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.3545942697 Aug 23 09:03:09 PM UTC 24 Aug 23 09:04:01 PM UTC 24 49894927141 ps
T694 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.929877640 Aug 23 09:04:00 PM UTC 24 Aug 23 09:04:02 PM UTC 24 86890512 ps
T695 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.680696777 Aug 23 09:04:01 PM UTC 24 Aug 23 09:04:04 PM UTC 24 105181378 ps
T696 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.4201135884 Aug 23 09:03:56 PM UTC 24 Aug 23 09:04:04 PM UTC 24 1648896909 ps
T697 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.1625350227 Aug 23 09:01:02 PM UTC 24 Aug 23 09:04:07 PM UTC 24 58157242546 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2744859415 Aug 23 09:02:45 PM UTC 24 Aug 23 09:04:07 PM UTC 24 64231269869 ps
T698 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.3057934404 Aug 23 09:04:03 PM UTC 24 Aug 23 09:04:09 PM UTC 24 1998396097 ps
T699 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.1511927372 Aug 23 09:04:08 PM UTC 24 Aug 23 09:04:10 PM UTC 24 33301067 ps
T700 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.2413553200 Aug 23 09:04:05 PM UTC 24 Aug 23 09:04:13 PM UTC 24 3826857491 ps
T701 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.3297239138 Aug 23 09:04:11 PM UTC 24 Aug 23 09:04:16 PM UTC 24 713638032 ps
T702 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.2973916222 Aug 23 09:04:08 PM UTC 24 Aug 23 09:04:17 PM UTC 24 8132392612 ps
T703 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.2660772641 Aug 23 09:03:54 PM UTC 24 Aug 23 09:04:20 PM UTC 24 44755237908 ps
T704 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.2133067325 Aug 23 09:04:04 PM UTC 24 Aug 23 09:04:22 PM UTC 24 2213671680 ps
T705 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.931319531 Aug 23 09:04:23 PM UTC 24 Aug 23 09:04:25 PM UTC 24 105640710 ps
T706 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.2845595872 Aug 23 09:04:05 PM UTC 24 Aug 23 09:04:27 PM UTC 24 1584706106 ps
T707 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.2344370306 Aug 23 09:04:26 PM UTC 24 Aug 23 09:04:28 PM UTC 24 13455166 ps
T708 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.3363282995 Aug 23 09:04:29 PM UTC 24 Aug 23 09:04:30 PM UTC 24 40528565 ps
T709 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.2441720658 Aug 23 09:04:31 PM UTC 24 Aug 23 09:04:33 PM UTC 24 21432912 ps
T710 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.236031836 Aug 23 09:04:28 PM UTC 24 Aug 23 09:04:33 PM UTC 24 534476613 ps
T711 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.1478362218 Aug 23 09:04:34 PM UTC 24 Aug 23 09:04:36 PM UTC 24 71464576 ps
T712 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.437399073 Aug 23 09:04:37 PM UTC 24 Aug 23 09:04:41 PM UTC 24 297333923 ps
T713 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.117841419 Aug 23 09:04:34 PM UTC 24 Aug 23 09:04:41 PM UTC 24 2889018670 ps
T714 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.1141722428 Aug 23 09:04:18 PM UTC 24 Aug 23 09:04:41 PM UTC 24 8929957247 ps
T715 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.2554699910 Aug 23 09:04:13 PM UTC 24 Aug 23 09:04:47 PM UTC 24 2955064861 ps
T716 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.4188249394 Aug 23 09:04:42 PM UTC 24 Aug 23 09:04:48 PM UTC 24 330541910 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.2795744721 Aug 23 09:03:44 PM UTC 24 Aug 23 09:04:49 PM UTC 24 5133156602 ps
T717 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.2325504509 Aug 23 09:04:48 PM UTC 24 Aug 23 09:04:52 PM UTC 24 325291639 ps
T718 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.1020152380 Aug 23 09:08:32 PM UTC 24 Aug 23 09:08:37 PM UTC 24 1666956144 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.469644631 Aug 23 09:02:10 PM UTC 24 Aug 23 09:04:55 PM UTC 24 23018430665 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.391475773 Aug 23 09:04:43 PM UTC 24 Aug 23 09:04:56 PM UTC 24 600225551 ps
T719 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.357736429 Aug 23 09:04:49 PM UTC 24 Aug 23 09:04:57 PM UTC 24 1065224511 ps
T720 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.4044550818 Aug 23 09:04:49 PM UTC 24 Aug 23 09:04:58 PM UTC 24 1248096709 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.1334661898 Aug 23 09:04:43 PM UTC 24 Aug 23 09:04:58 PM UTC 24 7746094643 ps
T721 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.660905126 Aug 23 09:01:34 PM UTC 24 Aug 23 09:04:59 PM UTC 24 106397160922 ps
T722 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.976168523 Aug 23 09:04:54 PM UTC 24 Aug 23 09:04:59 PM UTC 24 1019099792 ps
T723 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.2765111055 Aug 23 09:05:00 PM UTC 24 Aug 23 09:05:02 PM UTC 24 16435609 ps
T724 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.2263961895 Aug 23 09:05:00 PM UTC 24 Aug 23 09:05:02 PM UTC 24 16950216 ps
T725 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.2364072557 Aug 23 09:05:02 PM UTC 24 Aug 23 09:05:04 PM UTC 24 12394426 ps
T726 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.1528738554 Aug 23 09:05:00 PM UTC 24 Aug 23 09:05:06 PM UTC 24 4233870078 ps
T727 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.1367191491 Aug 23 09:05:05 PM UTC 24 Aug 23 09:05:06 PM UTC 24 56697683 ps
T728 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.4073614511 Aug 23 09:05:07 PM UTC 24 Aug 23 09:05:13 PM UTC 24 3404241133 ps
T729 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.4136928338 Aug 23 09:05:07 PM UTC 24 Aug 23 09:05:15 PM UTC 24 1259460756 ps
T730 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.2612891212 Aug 23 09:05:02 PM UTC 24 Aug 23 09:05:16 PM UTC 24 1319931482 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.1121596443 Aug 23 09:03:08 PM UTC 24 Aug 23 09:05:16 PM UTC 24 52954720327 ps
T731 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.3734725256 Aug 23 09:05:14 PM UTC 24 Aug 23 09:05:17 PM UTC 24 31333434 ps
T732 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.583348965 Aug 23 09:04:56 PM UTC 24 Aug 23 09:05:17 PM UTC 24 9602301743 ps
T733 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.59313296 Aug 23 09:04:10 PM UTC 24 Aug 23 09:05:17 PM UTC 24 26952340386 ps
T734 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.3930315603 Aug 23 09:05:18 PM UTC 24 Aug 23 09:05:24 PM UTC 24 479550921 ps
T735 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.3371397207 Aug 23 09:05:18 PM UTC 24 Aug 23 09:05:25 PM UTC 24 1451957055 ps
T736 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.2500077692 Aug 23 09:05:16 PM UTC 24 Aug 23 09:05:31 PM UTC 24 13739365338 ps
T737 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.2674637000 Aug 23 09:05:18 PM UTC 24 Aug 23 09:05:36 PM UTC 24 1002521044 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.4077997411 Aug 23 09:02:05 PM UTC 24 Aug 23 09:05:37 PM UTC 24 50618509200 ps
T738 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.728782767 Aug 23 09:05:38 PM UTC 24 Aug 23 09:05:41 PM UTC 24 17401926 ps
T739 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.3153881186 Aug 23 09:05:41 PM UTC 24 Aug 23 09:05:43 PM UTC 24 15695347 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.3959930548 Aug 23 09:04:21 PM UTC 24 Aug 23 09:05:45 PM UTC 24 9652792480 ps
T740 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.495178170 Aug 23 09:05:15 PM UTC 24 Aug 23 09:05:48 PM UTC 24 15553139388 ps
T741 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.2304715289 Aug 23 09:05:44 PM UTC 24 Aug 23 09:05:49 PM UTC 24 1124627746 ps
T742 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.2079946063 Aug 23 09:05:49 PM UTC 24 Aug 23 09:05:51 PM UTC 24 29117305 ps
T743 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.2704311832 Aug 23 09:05:50 PM UTC 24 Aug 23 09:05:52 PM UTC 24 64182350 ps
T744 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.3016174342 Aug 23 09:05:53 PM UTC 24 Aug 23 09:05:59 PM UTC 24 234769725 ps
T745 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.3576500338 Aug 23 09:05:46 PM UTC 24 Aug 23 09:06:00 PM UTC 24 3901933895 ps
T746 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.2611747721 Aug 23 09:04:16 PM UTC 24 Aug 23 09:06:00 PM UTC 24 18383028191 ps
T747 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.1545115498 Aug 23 09:06:00 PM UTC 24 Aug 23 09:06:04 PM UTC 24 245080502 ps
T748 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.4056713488 Aug 23 09:03:47 PM UTC 24 Aug 23 09:06:05 PM UTC 24 14746135599 ps
T749 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.311188515 Aug 23 09:04:58 PM UTC 24 Aug 23 09:06:08 PM UTC 24 3332883559 ps
T750 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.2691176552 Aug 23 09:06:05 PM UTC 24 Aug 23 09:06:09 PM UTC 24 211899939 ps
T751 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.1140657496 Aug 23 09:06:02 PM UTC 24 Aug 23 09:06:11 PM UTC 24 1881390877 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.545580301 Aug 23 09:05:24 PM UTC 24 Aug 23 09:06:11 PM UTC 24 9859581317 ps
T752 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.83854640 Aug 23 09:06:06 PM UTC 24 Aug 23 09:06:11 PM UTC 24 94720330 ps
T753 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.2145082107 Aug 23 09:06:11 PM UTC 24 Aug 23 09:06:13 PM UTC 24 71007037 ps
T754 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.172363506 Aug 23 09:06:10 PM UTC 24 Aug 23 09:06:14 PM UTC 24 202881213 ps
T255 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.657442989 Aug 23 09:05:51 PM UTC 24 Aug 23 09:06:15 PM UTC 24 22881934207 ps
T755 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.4128864716 Aug 23 09:06:15 PM UTC 24 Aug 23 09:06:16 PM UTC 24 11754864 ps
T756 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.2778625603 Aug 23 09:06:16 PM UTC 24 Aug 23 09:06:18 PM UTC 24 66241122 ps
T757 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.804616936 Aug 23 09:06:01 PM UTC 24 Aug 23 09:06:18 PM UTC 24 1522818495 ps
T758 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.1630020571 Aug 23 09:06:20 PM UTC 24 Aug 23 09:06:21 PM UTC 24 26182347 ps
T759 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.1798599377 Aug 23 09:06:22 PM UTC 24 Aug 23 09:06:25 PM UTC 24 352222245 ps
T760 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.3583716545 Aug 23 09:06:17 PM UTC 24 Aug 23 09:06:25 PM UTC 24 1074710244 ps
T761 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.179817821 Aug 23 09:06:26 PM UTC 24 Aug 23 09:06:29 PM UTC 24 129383764 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.2981105346 Aug 23 08:59:39 PM UTC 24 Aug 23 09:06:32 PM UTC 24 265562109708 ps
T762 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.1336521983 Aug 23 09:06:30 PM UTC 24 Aug 23 09:06:33 PM UTC 24 207019513 ps
T763 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.4067523451 Aug 23 09:06:26 PM UTC 24 Aug 23 09:06:34 PM UTC 24 1672304923 ps
T764 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.447183807 Aug 23 09:04:57 PM UTC 24 Aug 23 09:06:35 PM UTC 24 32189495035 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.2011702847 Aug 23 08:58:10 PM UTC 24 Aug 23 09:06:36 PM UTC 24 331443634401 ps
T765 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.1270601187 Aug 23 09:06:12 PM UTC 24 Aug 23 09:06:37 PM UTC 24 1922063036 ps
T766 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.3735334901 Aug 23 09:06:18 PM UTC 24 Aug 23 09:06:39 PM UTC 24 1633867471 ps
T767 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.1034402226 Aug 23 09:06:35 PM UTC 24 Aug 23 09:06:39 PM UTC 24 404730671 ps
T768 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.3496101134 Aug 23 09:06:35 PM UTC 24 Aug 23 09:06:39 PM UTC 24 950909349 ps
T769 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.1417194917 Aug 23 09:06:36 PM UTC 24 Aug 23 09:06:42 PM UTC 24 229304962 ps
T770 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1098738162 Aug 23 09:06:38 PM UTC 24 Aug 23 09:06:43 PM UTC 24 264224267 ps
T771 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.449538260 Aug 23 09:06:43 PM UTC 24 Aug 23 09:06:45 PM UTC 24 39579625 ps
T772 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.392605369 Aug 23 09:06:46 PM UTC 24 Aug 23 09:06:47 PM UTC 24 17076820 ps
T773 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.2710169552 Aug 23 08:56:31 PM UTC 24 Aug 23 09:06:49 PM UTC 24 576642443242 ps
T774 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.2395370255 Aug 23 09:06:50 PM UTC 24 Aug 23 09:06:52 PM UTC 24 22785957 ps
T775 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.3562632460 Aug 23 09:06:49 PM UTC 24 Aug 23 09:06:52 PM UTC 24 209880852 ps
T776 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.2712860938 Aug 23 09:05:33 PM UTC 24 Aug 23 09:06:52 PM UTC 24 31694685838 ps
T777 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.357446779 Aug 23 09:06:52 PM UTC 24 Aug 23 09:06:54 PM UTC 24 176836878 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.12612011 Aug 23 09:06:52 PM UTC 24 Aug 23 09:06:54 PM UTC 24 69164247 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.881855044 Aug 23 09:06:33 PM UTC 24 Aug 23 09:06:55 PM UTC 24 2079262193 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1334210021 Aug 23 09:02:10 PM UTC 24 Aug 23 09:07:03 PM UTC 24 136168519844 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.3100694787 Aug 23 09:06:54 PM UTC 24 Aug 23 09:07:04 PM UTC 24 1690153166 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.672696268 Aug 23 09:06:55 PM UTC 24 Aug 23 09:07:04 PM UTC 24 1135210182 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.4227083578 Aug 23 09:06:55 PM UTC 24 Aug 23 09:07:05 PM UTC 24 6199783305 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.2852077485 Aug 23 09:03:49 PM UTC 24 Aug 23 09:07:05 PM UTC 24 96253279932 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.2249750742 Aug 23 09:06:56 PM UTC 24 Aug 23 09:07:09 PM UTC 24 5093727853 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.134282200 Aug 23 09:07:05 PM UTC 24 Aug 23 09:07:11 PM UTC 24 459998621 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.4274178987 Aug 23 09:07:05 PM UTC 24 Aug 23 09:07:11 PM UTC 24 204414700 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.40680844 Aug 23 09:06:09 PM UTC 24 Aug 23 09:07:12 PM UTC 24 4876580063 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.713902766 Aug 23 09:07:05 PM UTC 24 Aug 23 09:07:12 PM UTC 24 875533342 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.2354255079 Aug 23 09:07:13 PM UTC 24 Aug 23 09:07:15 PM UTC 24 18357562 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.824703054 Aug 23 09:07:16 PM UTC 24 Aug 23 09:07:17 PM UTC 24 41480036 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.124282414 Aug 23 09:07:06 PM UTC 24 Aug 23 09:07:17 PM UTC 24 3686551400 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.1765785302 Aug 23 09:04:58 PM UTC 24 Aug 23 09:07:17 PM UTC 24 27752399171 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1438109794 Aug 23 09:06:40 PM UTC 24 Aug 23 09:07:19 PM UTC 24 45042069388 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3149599034 Aug 23 09:07:19 PM UTC 24 Aug 23 09:07:21 PM UTC 24 31941311 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.2507708211 Aug 23 09:07:19 PM UTC 24 Aug 23 09:07:21 PM UTC 24 37916528 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.2565574804 Aug 23 09:07:18 PM UTC 24 Aug 23 09:07:22 PM UTC 24 473365496 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.3867824602 Aug 23 09:07:18 PM UTC 24 Aug 23 09:07:24 PM UTC 24 13508010840 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.2077992990 Aug 23 09:07:22 PM UTC 24 Aug 23 09:07:25 PM UTC 24 115278132 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.4217280752 Aug 23 09:07:25 PM UTC 24 Aug 23 09:07:29 PM UTC 24 152293708 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.3609582121 Aug 23 09:05:37 PM UTC 24 Aug 23 09:07:32 PM UTC 24 16749624464 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.242700245 Aug 23 09:01:07 PM UTC 24 Aug 23 09:07:32 PM UTC 24 195646345325 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.3016407748 Aug 23 09:07:23 PM UTC 24 Aug 23 09:07:37 PM UTC 24 4242849910 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.874519817 Aug 23 09:07:33 PM UTC 24 Aug 23 09:07:38 PM UTC 24 83932959 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.3719791765 Aug 23 09:07:30 PM UTC 24 Aug 23 09:07:38 PM UTC 24 1193710705 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2647998295 Aug 23 09:05:26 PM UTC 24 Aug 23 09:07:39 PM UTC 24 13983506525 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.592777258 Aug 23 09:07:27 PM UTC 24 Aug 23 09:07:44 PM UTC 24 35418820649 ps
T72 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.844550688 Aug 23 08:58:40 PM UTC 24 Aug 23 09:07:45 PM UTC 24 65567562767 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.1990789811 Aug 23 09:07:46 PM UTC 24 Aug 23 09:07:47 PM UTC 24 39799836 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.1348392425 Aug 23 09:07:39 PM UTC 24 Aug 23 09:07:50 PM UTC 24 1167543018 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.3955709322 Aug 23 09:07:49 PM UTC 24 Aug 23 09:07:51 PM UTC 24 19855659 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.3192352943 Aug 23 09:07:22 PM UTC 24 Aug 23 09:07:51 PM UTC 24 40419646609 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.3002262260 Aug 23 09:07:53 PM UTC 24 Aug 23 09:07:54 PM UTC 24 356470533 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.1591170410 Aug 23 09:07:55 PM UTC 24 Aug 23 09:07:57 PM UTC 24 121688483 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.4263838909 Aug 23 09:07:51 PM UTC 24 Aug 23 09:08:00 PM UTC 24 2447035847 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.204700761 Aug 23 09:07:39 PM UTC 24 Aug 23 09:08:08 PM UTC 24 14282462304 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_22/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.3163341479 Aug 23 09:05:18 PM UTC 24 Aug 23 09:08:13 PM UTC 24 103175850887 ps
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