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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 94.01 98.62 89.36 97.19 95.45 99.21


Total test records in report: 1131
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html

T436 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.1488702381 Aug 29 03:09:17 AM UTC 24 Aug 29 03:09:19 AM UTC 24 52477913 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.2711521098 Aug 29 03:09:19 AM UTC 24 Aug 29 03:09:22 AM UTC 24 245528100 ps
T96 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.3009697408 Aug 29 03:07:07 AM UTC 24 Aug 29 03:09:33 AM UTC 24 21806416519 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.902495146 Aug 29 03:09:23 AM UTC 24 Aug 29 03:09:35 AM UTC 24 572907582 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.1717780462 Aug 29 03:09:17 AM UTC 24 Aug 29 03:09:41 AM UTC 24 2555789024 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.2484401467 Aug 29 03:09:20 AM UTC 24 Aug 29 03:09:41 AM UTC 24 9345219028 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.4125532269 Aug 29 03:08:00 AM UTC 24 Aug 29 03:09:47 AM UTC 24 13827507929 ps
T207 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.28160421 Aug 29 03:09:34 AM UTC 24 Aug 29 03:09:48 AM UTC 24 690422993 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.270870617 Aug 29 03:01:25 AM UTC 24 Aug 29 03:09:48 AM UTC 24 149693368124 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.4042775968 Aug 29 03:09:00 AM UTC 24 Aug 29 03:09:48 AM UTC 24 26155071727 ps
T211 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.2589504484 Aug 29 03:08:17 AM UTC 24 Aug 29 03:09:51 AM UTC 24 60641228499 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.3329336501 Aug 29 03:08:29 AM UTC 24 Aug 29 03:09:51 AM UTC 24 6479585077 ps
T242 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.506851138 Aug 29 03:07:57 AM UTC 24 Aug 29 03:09:56 AM UTC 24 36160765668 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.429385428 Aug 29 03:07:00 AM UTC 24 Aug 29 03:09:56 AM UTC 24 32705318032 ps
T249 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.866361668 Aug 29 03:07:34 AM UTC 24 Aug 29 03:09:57 AM UTC 24 58903438343 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.3872297104 Aug 29 03:09:57 AM UTC 24 Aug 29 03:09:59 AM UTC 24 34350069 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.1201928175 Aug 29 03:09:57 AM UTC 24 Aug 29 03:09:59 AM UTC 24 123092153 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.2969706228 Aug 29 03:11:20 AM UTC 24 Aug 29 03:11:36 AM UTC 24 256193001 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.3846719191 Aug 29 03:09:49 AM UTC 24 Aug 29 03:10:02 AM UTC 24 865941380 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.3508451638 Aug 29 03:10:03 AM UTC 24 Aug 29 03:10:05 AM UTC 24 16096195 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.465549975 Aug 29 03:10:04 AM UTC 24 Aug 29 03:10:07 AM UTC 24 56167005 ps
T237 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.3872346463 Aug 29 03:09:41 AM UTC 24 Aug 29 03:10:08 AM UTC 24 2917954352 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.3640280154 Aug 29 03:09:49 AM UTC 24 Aug 29 03:10:08 AM UTC 24 661308207 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.3571311950 Aug 29 03:10:06 AM UTC 24 Aug 29 03:10:14 AM UTC 24 803806861 ps
T300 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.3989717347 Aug 29 03:09:42 AM UTC 24 Aug 29 03:10:17 AM UTC 24 5884742401 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.1783983546 Aug 29 03:10:09 AM UTC 24 Aug 29 03:10:20 AM UTC 24 1718861578 ps
T349 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.1969887704 Aug 29 03:10:02 AM UTC 24 Aug 29 03:10:25 AM UTC 24 2853150597 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.1354199442 Aug 29 03:10:21 AM UTC 24 Aug 29 03:10:27 AM UTC 24 81412010 ps
T299 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.318725449 Aug 29 03:10:14 AM UTC 24 Aug 29 03:10:27 AM UTC 24 1990900056 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.3127059645 Aug 29 03:10:26 AM UTC 24 Aug 29 03:10:29 AM UTC 24 61418144 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.992367883 Aug 29 03:09:49 AM UTC 24 Aug 29 03:10:30 AM UTC 24 4315264616 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.332221483 Aug 29 03:10:28 AM UTC 24 Aug 29 03:10:35 AM UTC 24 1103990635 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.819443219 Aug 29 03:10:00 AM UTC 24 Aug 29 03:10:36 AM UTC 24 27609016671 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.3803097291 Aug 29 03:10:37 AM UTC 24 Aug 29 03:10:39 AM UTC 24 22210153 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.1802751838 Aug 29 03:10:40 AM UTC 24 Aug 29 03:10:42 AM UTC 24 26434193 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.3970873447 Aug 29 03:10:18 AM UTC 24 Aug 29 03:10:45 AM UTC 24 6126193071 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.1058645117 Aug 29 03:10:07 AM UTC 24 Aug 29 03:10:49 AM UTC 24 6623863623 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.667930354 Aug 29 03:10:46 AM UTC 24 Aug 29 03:10:51 AM UTC 24 734146376 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.136577295 Aug 29 03:10:50 AM UTC 24 Aug 29 03:10:53 AM UTC 24 274487643 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.1909405729 Aug 29 03:10:52 AM UTC 24 Aug 29 03:10:54 AM UTC 24 41029625 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.1584930690 Aug 29 03:10:46 AM UTC 24 Aug 29 03:10:57 AM UTC 24 8387085520 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2361128321 Aug 29 03:07:05 AM UTC 24 Aug 29 03:10:58 AM UTC 24 40899423871 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.480867972 Aug 29 03:10:55 AM UTC 24 Aug 29 03:10:59 AM UTC 24 109767367 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.594106064 Aug 29 03:10:09 AM UTC 24 Aug 29 03:11:00 AM UTC 24 2286534074 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.1276690355 Aug 29 03:10:58 AM UTC 24 Aug 29 03:11:02 AM UTC 24 77977244 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.1667740497 Aug 29 03:10:59 AM UTC 24 Aug 29 03:11:05 AM UTC 24 1373299674 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.1394887775 Aug 29 03:11:01 AM UTC 24 Aug 29 03:11:05 AM UTC 24 186329846 ps
T301 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.1408599653 Aug 29 03:10:54 AM UTC 24 Aug 29 03:11:06 AM UTC 24 2785519561 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.633235302 Aug 29 03:11:03 AM UTC 24 Aug 29 03:11:08 AM UTC 24 36883202 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.4127812329 Aug 29 03:09:36 AM UTC 24 Aug 29 03:11:11 AM UTC 24 8126418649 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.771605757 Aug 29 03:10:59 AM UTC 24 Aug 29 03:11:11 AM UTC 24 2421816108 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.2522124650 Aug 29 03:11:06 AM UTC 24 Aug 29 03:11:12 AM UTC 24 209407205 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.3924089009 Aug 29 03:11:11 AM UTC 24 Aug 29 03:11:14 AM UTC 24 15118039 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.1937850765 Aug 29 03:11:13 AM UTC 24 Aug 29 03:11:16 AM UTC 24 21884191 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.233003516 Aug 29 03:06:13 AM UTC 24 Aug 29 03:11:57 AM UTC 24 24913826265 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.1348729514 Aug 29 03:09:57 AM UTC 24 Aug 29 03:11:17 AM UTC 24 21365733119 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.2699512119 Aug 29 03:11:17 AM UTC 24 Aug 29 03:11:20 AM UTC 24 20933261 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.3657348691 Aug 29 03:11:16 AM UTC 24 Aug 29 03:11:26 AM UTC 24 1481455683 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.3326544452 Aug 29 03:11:17 AM UTC 24 Aug 29 03:11:26 AM UTC 24 3954185504 ps
T208 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.3632959227 Aug 29 03:09:52 AM UTC 24 Aug 29 03:11:26 AM UTC 24 2449434149 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1665541657 Aug 29 03:06:14 AM UTC 24 Aug 29 03:11:31 AM UTC 24 23325964156 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2397426476 Aug 29 03:09:07 AM UTC 24 Aug 29 03:11:35 AM UTC 24 4829738273 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.2934859104 Aug 29 03:11:27 AM UTC 24 Aug 29 03:11:52 AM UTC 24 7092492313 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.3728531606 Aug 29 03:07:27 AM UTC 24 Aug 29 03:11:56 AM UTC 24 24396569488 ps
T243 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.3843823996 Aug 29 03:09:07 AM UTC 24 Aug 29 03:11:58 AM UTC 24 14135102041 ps
T271 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.2026642934 Aug 29 03:09:49 AM UTC 24 Aug 29 03:11:58 AM UTC 24 23139011965 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.1539238958 Aug 29 03:11:33 AM UTC 24 Aug 29 03:11:58 AM UTC 24 2133048161 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.1699502591 Aug 29 03:11:52 AM UTC 24 Aug 29 03:11:59 AM UTC 24 324328874 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.3107117204 Aug 29 03:11:58 AM UTC 24 Aug 29 03:12:00 AM UTC 24 83367661 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.2119422395 Aug 29 03:11:59 AM UTC 24 Aug 29 03:12:01 AM UTC 24 38507237 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.2747240238 Aug 29 03:11:59 AM UTC 24 Aug 29 03:12:01 AM UTC 24 49761680 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.4134482434 Aug 29 03:12:00 AM UTC 24 Aug 29 03:12:02 AM UTC 24 28558755 ps
T268 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.2414595872 Aug 29 03:11:06 AM UTC 24 Aug 29 03:12:02 AM UTC 24 1706167332 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.2668723909 Aug 29 03:12:03 AM UTC 24 Aug 29 03:12:06 AM UTC 24 203139725 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.1500971658 Aug 29 03:11:27 AM UTC 24 Aug 29 03:12:08 AM UTC 24 8263357233 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.57434594 Aug 29 03:12:03 AM UTC 24 Aug 29 03:12:08 AM UTC 24 157053936 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.2225757876 Aug 29 03:11:32 AM UTC 24 Aug 29 03:12:10 AM UTC 24 7584600230 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.2297183896 Aug 29 03:12:02 AM UTC 24 Aug 29 03:12:11 AM UTC 24 735179865 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.710323221 Aug 29 03:12:04 AM UTC 24 Aug 29 03:12:12 AM UTC 24 437787905 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.3440151955 Aug 29 03:12:12 AM UTC 24 Aug 29 03:12:16 AM UTC 24 74129152 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.546121906 Aug 29 03:11:35 AM UTC 24 Aug 29 03:12:16 AM UTC 24 25917089282 ps
T236 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.2170501522 Aug 29 03:02:47 AM UTC 24 Aug 29 03:12:20 AM UTC 24 72827759364 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.2522721493 Aug 29 03:11:37 AM UTC 24 Aug 29 03:12:21 AM UTC 24 5400688910 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.256493977 Aug 29 03:04:51 AM UTC 24 Aug 29 03:12:21 AM UTC 24 181124347206 ps
T258 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.1952773075 Aug 29 03:10:28 AM UTC 24 Aug 29 03:12:25 AM UTC 24 26082340830 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.3000266329 Aug 29 03:12:06 AM UTC 24 Aug 29 03:12:26 AM UTC 24 10378642626 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.2646577446 Aug 29 03:12:09 AM UTC 24 Aug 29 03:12:27 AM UTC 24 466629866 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.3732079293 Aug 29 03:12:13 AM UTC 24 Aug 29 03:12:29 AM UTC 24 568556335 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.3326147538 Aug 29 03:12:27 AM UTC 24 Aug 29 03:12:30 AM UTC 24 14922393 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.1995409854 Aug 29 03:12:27 AM UTC 24 Aug 29 03:12:30 AM UTC 24 48354231 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.3438772639 Aug 29 03:12:17 AM UTC 24 Aug 29 03:12:31 AM UTC 24 939058820 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.3796983424 Aug 29 03:12:32 AM UTC 24 Aug 29 03:12:34 AM UTC 24 20534938 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.3653405976 Aug 29 03:09:52 AM UTC 24 Aug 29 03:12:35 AM UTC 24 12061844027 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.202675799 Aug 29 03:12:31 AM UTC 24 Aug 29 03:12:36 AM UTC 24 1292492979 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.477012963 Aug 29 03:12:33 AM UTC 24 Aug 29 03:12:37 AM UTC 24 137640646 ps
T296 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.2550176216 Aug 29 03:12:09 AM UTC 24 Aug 29 03:12:42 AM UTC 24 8789637449 ps
T232 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.3953015544 Aug 29 03:12:37 AM UTC 24 Aug 29 03:12:45 AM UTC 24 300071699 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.132428696 Aug 29 03:12:31 AM UTC 24 Aug 29 03:12:47 AM UTC 24 9470496280 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.4101852749 Aug 29 03:12:43 AM UTC 24 Aug 29 03:12:49 AM UTC 24 662675878 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.2185502237 Aug 29 03:12:46 AM UTC 24 Aug 29 03:12:52 AM UTC 24 942733263 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.45820823 Aug 29 03:06:14 AM UTC 24 Aug 29 03:12:53 AM UTC 24 41978657951 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.2095023030 Aug 29 03:12:53 AM UTC 24 Aug 29 03:12:59 AM UTC 24 341639363 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.3417034952 Aug 29 03:12:11 AM UTC 24 Aug 29 03:13:00 AM UTC 24 39591708342 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1525036733 Aug 29 03:12:35 AM UTC 24 Aug 29 03:13:01 AM UTC 24 17226111612 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.3665154229 Aug 29 03:08:39 AM UTC 24 Aug 29 03:13:03 AM UTC 24 26203223601 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.2252523637 Aug 29 03:13:04 AM UTC 24 Aug 29 03:13:06 AM UTC 24 17803225 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.586953564 Aug 29 03:13:07 AM UTC 24 Aug 29 03:13:09 AM UTC 24 91971130 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.3621406340 Aug 29 03:12:02 AM UTC 24 Aug 29 03:13:12 AM UTC 24 43600416320 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.2333692664 Aug 29 03:11:58 AM UTC 24 Aug 29 03:13:14 AM UTC 24 23103907898 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.69400464 Aug 29 03:11:03 AM UTC 24 Aug 29 03:13:16 AM UTC 24 51976007587 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.3115874893 Aug 29 03:13:14 AM UTC 24 Aug 29 03:13:16 AM UTC 24 117013472 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.4250380005 Aug 29 03:13:17 AM UTC 24 Aug 29 03:13:20 AM UTC 24 16998997 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.3013773879 Aug 29 03:13:10 AM UTC 24 Aug 29 03:13:22 AM UTC 24 3285357660 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.462969952 Aug 29 03:12:36 AM UTC 24 Aug 29 03:13:24 AM UTC 24 9998010017 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.661173466 Aug 29 03:13:23 AM UTC 24 Aug 29 03:13:31 AM UTC 24 6399261495 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.3620787122 Aug 29 03:13:21 AM UTC 24 Aug 29 03:13:35 AM UTC 24 1612582774 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.1857093412 Aug 29 03:12:48 AM UTC 24 Aug 29 03:13:36 AM UTC 24 13891860024 ps
T246 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.659674182 Aug 29 03:11:11 AM UTC 24 Aug 29 03:13:38 AM UTC 24 91899692234 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.182354395 Aug 29 03:07:56 AM UTC 24 Aug 29 03:13:39 AM UTC 24 222730120136 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.823402877 Aug 29 03:13:25 AM UTC 24 Aug 29 03:13:43 AM UTC 24 1481182778 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.3536180939 Aug 29 03:11:59 AM UTC 24 Aug 29 03:13:44 AM UTC 24 3923153948 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.130789708 Aug 29 03:11:29 AM UTC 24 Aug 29 03:13:45 AM UTC 24 24322424898 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.1479262173 Aug 29 03:13:17 AM UTC 24 Aug 29 03:13:46 AM UTC 24 40143563802 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.3061419275 Aug 29 03:13:37 AM UTC 24 Aug 29 03:13:49 AM UTC 24 262729129 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.4132246702 Aug 29 03:13:40 AM UTC 24 Aug 29 03:13:52 AM UTC 24 726661863 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.2001802180 Aug 29 03:13:50 AM UTC 24 Aug 29 03:13:52 AM UTC 24 35439381 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.85181650 Aug 29 03:13:02 AM UTC 24 Aug 29 03:13:53 AM UTC 24 6233327712 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.3185657979 Aug 29 03:13:53 AM UTC 24 Aug 29 03:13:55 AM UTC 24 174100588 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.3527367058 Aug 29 03:10:30 AM UTC 24 Aug 29 03:13:56 AM UTC 24 62994602003 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.1119986131 Aug 29 03:13:32 AM UTC 24 Aug 29 03:13:57 AM UTC 24 10131825649 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.469862864 Aug 29 03:13:56 AM UTC 24 Aug 29 03:13:58 AM UTC 24 631562063 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.415554134 Aug 29 03:10:36 AM UTC 24 Aug 29 03:14:00 AM UTC 24 45729197833 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.2290152627 Aug 29 03:12:37 AM UTC 24 Aug 29 03:14:00 AM UTC 24 10849765567 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.837494174 Aug 29 03:13:57 AM UTC 24 Aug 29 03:14:01 AM UTC 24 988484069 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.2643720380 Aug 29 03:14:00 AM UTC 24 Aug 29 03:14:04 AM UTC 24 231147082 ps
T351 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.767002947 Aug 29 03:13:13 AM UTC 24 Aug 29 03:14:05 AM UTC 24 9844870540 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.2412424619 Aug 29 03:13:36 AM UTC 24 Aug 29 03:14:06 AM UTC 24 5174739326 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.980727921 Aug 29 03:13:53 AM UTC 24 Aug 29 03:14:08 AM UTC 24 1337501883 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.2468323170 Aug 29 03:13:54 AM UTC 24 Aug 29 03:14:09 AM UTC 24 14680949974 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.1322940136 Aug 29 03:14:05 AM UTC 24 Aug 29 03:14:09 AM UTC 24 181154565 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.150666983 Aug 29 03:08:35 AM UTC 24 Aug 29 03:14:12 AM UTC 24 117730209072 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.2962111020 Aug 29 03:14:06 AM UTC 24 Aug 29 03:14:13 AM UTC 24 4953260041 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.2455064696 Aug 29 03:12:21 AM UTC 24 Aug 29 03:14:15 AM UTC 24 23527828668 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.1010499105 Aug 29 03:14:14 AM UTC 24 Aug 29 03:14:16 AM UTC 24 46309083 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.3332167459 Aug 29 03:09:05 AM UTC 24 Aug 29 03:14:17 AM UTC 24 117854980701 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.3482580471 Aug 29 03:14:09 AM UTC 24 Aug 29 03:14:17 AM UTC 24 500412315 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.1504904553 Aug 29 03:14:16 AM UTC 24 Aug 29 03:14:19 AM UTC 24 13199363 ps
T225 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.4012736488 Aug 29 03:13:58 AM UTC 24 Aug 29 03:14:20 AM UTC 24 54627301845 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3106296567 Aug 29 03:14:19 AM UTC 24 Aug 29 03:14:21 AM UTC 24 114989622 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.1976133673 Aug 29 03:14:20 AM UTC 24 Aug 29 03:14:23 AM UTC 24 146995539 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.3682172618 Aug 29 03:14:01 AM UTC 24 Aug 29 03:14:25 AM UTC 24 5523789211 ps
T247 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.1180702070 Aug 29 03:13:38 AM UTC 24 Aug 29 03:14:29 AM UTC 24 8448035318 ps
T206 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.3421082348 Aug 29 03:12:21 AM UTC 24 Aug 29 03:14:33 AM UTC 24 23742081947 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.2367053476 Aug 29 03:14:21 AM UTC 24 Aug 29 03:14:35 AM UTC 24 16709465796 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.1293094258 Aug 29 03:13:59 AM UTC 24 Aug 29 03:14:39 AM UTC 24 27232230012 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.62149402 Aug 29 03:14:33 AM UTC 24 Aug 29 03:14:41 AM UTC 24 1565625186 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.2841636385 Aug 29 03:12:21 AM UTC 24 Aug 29 03:14:42 AM UTC 24 14397755439 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.3088670081 Aug 29 03:14:24 AM UTC 24 Aug 29 03:14:44 AM UTC 24 5039635578 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.2462776360 Aug 29 03:14:21 AM UTC 24 Aug 29 03:14:47 AM UTC 24 4678734608 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.921978891 Aug 29 03:14:02 AM UTC 24 Aug 29 03:14:48 AM UTC 24 8752602956 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.3360821907 Aug 29 03:14:42 AM UTC 24 Aug 29 03:14:49 AM UTC 24 673245148 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.528517488 Aug 29 03:12:54 AM UTC 24 Aug 29 03:14:49 AM UTC 24 3497279738 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.44035305 Aug 29 03:14:50 AM UTC 24 Aug 29 03:14:52 AM UTC 24 12789722 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.2283271303 Aug 29 03:14:50 AM UTC 24 Aug 29 03:14:52 AM UTC 24 22944535 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.505400967 Aug 29 03:13:44 AM UTC 24 Aug 29 03:14:52 AM UTC 24 5178294316 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.559046792 Aug 29 03:14:18 AM UTC 24 Aug 29 03:14:55 AM UTC 24 7863913998 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.1035451215 Aug 29 03:14:53 AM UTC 24 Aug 29 03:14:55 AM UTC 24 49558962 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.3421441228 Aug 29 03:14:25 AM UTC 24 Aug 29 03:14:57 AM UTC 24 1882279598 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.356067696 Aug 29 03:14:18 AM UTC 24 Aug 29 03:14:58 AM UTC 24 2787932180 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.887379121 Aug 29 03:14:29 AM UTC 24 Aug 29 03:14:59 AM UTC 24 29481572697 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.1831711882 Aug 29 03:14:56 AM UTC 24 Aug 29 03:14:59 AM UTC 24 43022824 ps
T264 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.1259302127 Aug 29 03:14:59 AM UTC 24 Aug 29 03:15:02 AM UTC 24 174995897 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.1521492620 Aug 29 03:14:35 AM UTC 24 Aug 29 03:15:03 AM UTC 24 5470771376 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.83903975 Aug 29 03:14:53 AM UTC 24 Aug 29 03:15:04 AM UTC 24 882031265 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.1665690950 Aug 29 03:15:03 AM UTC 24 Aug 29 03:15:07 AM UTC 24 196530404 ps
T254 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.1079109071 Aug 29 03:14:57 AM UTC 24 Aug 29 03:15:09 AM UTC 24 1342800372 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.3396059888 Aug 29 03:15:00 AM UTC 24 Aug 29 03:15:11 AM UTC 24 1089093052 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.2827138001 Aug 29 03:14:56 AM UTC 24 Aug 29 03:15:11 AM UTC 24 21849220682 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.1451588223 Aug 29 03:11:07 AM UTC 24 Aug 29 03:15:14 AM UTC 24 41696987112 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.2967566814 Aug 29 03:14:53 AM UTC 24 Aug 29 03:15:14 AM UTC 24 2647203682 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.3344870162 Aug 29 03:15:15 AM UTC 24 Aug 29 03:15:18 AM UTC 24 15752531 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2004334845 Aug 29 03:15:08 AM UTC 24 Aug 29 03:15:18 AM UTC 24 1040526883 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.2482740959 Aug 29 03:15:10 AM UTC 24 Aug 29 03:15:18 AM UTC 24 808459325 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.2904876535 Aug 29 03:14:07 AM UTC 24 Aug 29 03:15:20 AM UTC 24 1880729109 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.3992186425 Aug 29 03:15:19 AM UTC 24 Aug 29 03:15:21 AM UTC 24 61101135 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.4252959251 Aug 29 03:15:19 AM UTC 24 Aug 29 03:15:21 AM UTC 24 58138875 ps
T274 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2804465209 Aug 29 03:11:09 AM UTC 24 Aug 29 03:15:23 AM UTC 24 12419717432 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.183896427 Aug 29 03:15:22 AM UTC 24 Aug 29 03:15:24 AM UTC 24 21699246 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.2984182526 Aug 29 03:15:22 AM UTC 24 Aug 29 03:15:25 AM UTC 24 49698414 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.2208483514 Aug 29 03:15:12 AM UTC 24 Aug 29 03:15:30 AM UTC 24 495122181 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.1601503053 Aug 29 03:15:24 AM UTC 24 Aug 29 03:15:32 AM UTC 24 663760751 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.2152359491 Aug 29 03:15:22 AM UTC 24 Aug 29 03:15:32 AM UTC 24 2193157693 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.734569409 Aug 29 03:14:13 AM UTC 24 Aug 29 03:15:35 AM UTC 24 5018749761 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.1357818104 Aug 29 03:15:32 AM UTC 24 Aug 29 03:15:37 AM UTC 24 57169267 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.3519246013 Aug 29 03:15:00 AM UTC 24 Aug 29 03:15:39 AM UTC 24 1494704132 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.2749917959 Aug 29 03:15:25 AM UTC 24 Aug 29 03:15:41 AM UTC 24 2602254582 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.3153111659 Aug 29 03:15:32 AM UTC 24 Aug 29 03:15:44 AM UTC 24 1099377622 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.3879756464 Aug 29 03:15:25 AM UTC 24 Aug 29 03:15:47 AM UTC 24 1719208939 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.4135121754 Aug 29 03:15:05 AM UTC 24 Aug 29 03:15:48 AM UTC 24 3640093791 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.56766295 Aug 29 03:15:20 AM UTC 24 Aug 29 03:15:48 AM UTC 24 7925839490 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.1166969209 Aug 29 03:15:49 AM UTC 24 Aug 29 03:15:51 AM UTC 24 28160045 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.3588765001 Aug 29 03:15:49 AM UTC 24 Aug 29 03:15:51 AM UTC 24 39322085 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.2551336253 Aug 29 03:15:37 AM UTC 24 Aug 29 03:15:56 AM UTC 24 5253585571 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.1605765372 Aug 29 03:15:04 AM UTC 24 Aug 29 03:15:56 AM UTC 24 2583236618 ps
T245 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.294172831 Aug 29 03:14:44 AM UTC 24 Aug 29 03:15:57 AM UTC 24 2156415785 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.54861743 Aug 29 03:15:11 AM UTC 24 Aug 29 03:15:59 AM UTC 24 4307625969 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.1199105912 Aug 29 03:15:57 AM UTC 24 Aug 29 03:16:00 AM UTC 24 26537130 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.1316051102 Aug 29 03:15:57 AM UTC 24 Aug 29 03:16:00 AM UTC 24 58646367 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.2979532277 Aug 29 03:09:08 AM UTC 24 Aug 29 03:16:01 AM UTC 24 40405464778 ps
T251 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.2186693324 Aug 29 03:08:33 AM UTC 24 Aug 29 03:16:03 AM UTC 24 105852502868 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.31769491 Aug 29 03:15:59 AM UTC 24 Aug 29 03:16:04 AM UTC 24 732448410 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.3224958658 Aug 29 03:15:58 AM UTC 24 Aug 29 03:16:07 AM UTC 24 1498745400 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.2086724722 Aug 29 03:14:40 AM UTC 24 Aug 29 03:16:05 AM UTC 24 5008080239 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.2663508065 Aug 29 03:16:03 AM UTC 24 Aug 29 03:16:07 AM UTC 24 984597751 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.3564530404 Aug 29 03:16:04 AM UTC 24 Aug 29 03:16:08 AM UTC 24 96315553 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.1870731118 Aug 29 03:16:01 AM UTC 24 Aug 29 03:16:08 AM UTC 24 567743376 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.1784408183 Aug 29 03:16:01 AM UTC 24 Aug 29 03:16:08 AM UTC 24 156167187 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.3313560675 Aug 29 03:15:52 AM UTC 24 Aug 29 03:16:14 AM UTC 24 2487918047 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.1911079591 Aug 29 03:15:52 AM UTC 24 Aug 29 03:16:15 AM UTC 24 36052866095 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.3545051957 Aug 29 03:16:08 AM UTC 24 Aug 29 03:16:16 AM UTC 24 1113304940 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.1735305682 Aug 29 03:16:15 AM UTC 24 Aug 29 03:16:18 AM UTC 24 37938731 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.1639586410 Aug 29 03:15:31 AM UTC 24 Aug 29 03:16:18 AM UTC 24 27169853252 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.3823568162 Aug 29 03:16:16 AM UTC 24 Aug 29 03:16:19 AM UTC 24 55520806 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.2134969465 Aug 29 03:16:05 AM UTC 24 Aug 29 03:16:19 AM UTC 24 445839031 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.1887828262 Aug 29 03:16:19 AM UTC 24 Aug 29 03:16:21 AM UTC 24 245400318 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.3479349738 Aug 29 03:16:20 AM UTC 24 Aug 29 03:16:22 AM UTC 24 28678457 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.620599770 Aug 29 03:10:31 AM UTC 24 Aug 29 03:16:26 AM UTC 24 68666120508 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.804072348 Aug 29 03:16:08 AM UTC 24 Aug 29 03:16:29 AM UTC 24 3333610904 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.953367196 Aug 29 03:16:22 AM UTC 24 Aug 29 03:16:30 AM UTC 24 806857009 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.1321025423 Aug 29 03:16:23 AM UTC 24 Aug 29 03:16:31 AM UTC 24 1109013487 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.3772057423 Aug 29 03:16:20 AM UTC 24 Aug 29 03:16:33 AM UTC 24 2103781752 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.3533474736 Aug 29 03:16:31 AM UTC 24 Aug 29 03:16:36 AM UTC 24 52760601 ps
T228 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.3557089056 Aug 29 03:12:50 AM UTC 24 Aug 29 03:16:37 AM UTC 24 48936621994 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.2181226825 Aug 29 03:13:47 AM UTC 24 Aug 29 03:16:39 AM UTC 24 16592375511 ps
T252 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.373704888 Aug 29 03:14:10 AM UTC 24 Aug 29 03:16:40 AM UTC 24 42007308796 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.1569195724 Aug 29 03:16:32 AM UTC 24 Aug 29 03:16:44 AM UTC 24 403027755 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.2433405124 Aug 29 03:16:19 AM UTC 24 Aug 29 03:16:47 AM UTC 24 3265822779 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.2339996992 Aug 29 03:16:36 AM UTC 24 Aug 29 03:16:48 AM UTC 24 14528073644 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.3722845857 Aug 29 03:16:48 AM UTC 24 Aug 29 03:16:50 AM UTC 24 14768711 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.901812393 Aug 29 03:16:49 AM UTC 24 Aug 29 03:16:51 AM UTC 24 16218439 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.3607437889 Aug 29 03:16:30 AM UTC 24 Aug 29 03:16:52 AM UTC 24 27992145660 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.969758968 Aug 29 03:16:17 AM UTC 24 Aug 29 03:16:56 AM UTC 24 24930819754 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.2517542971 Aug 29 03:16:53 AM UTC 24 Aug 29 03:16:56 AM UTC 24 61241627 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.1332822691 Aug 29 03:16:56 AM UTC 24 Aug 29 03:16:59 AM UTC 24 35779189 ps
T156 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.381359592 Aug 29 03:14:45 AM UTC 24 Aug 29 03:17:02 AM UTC 24 3513122535 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.3130851858 Aug 29 03:16:51 AM UTC 24 Aug 29 03:17:03 AM UTC 24 2419974539 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.1454647545 Aug 29 03:16:38 AM UTC 24 Aug 29 03:17:05 AM UTC 24 3236129318 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2791364793 Aug 29 03:16:06 AM UTC 24 Aug 29 03:17:06 AM UTC 24 7410497577 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.608365631 Aug 29 03:17:03 AM UTC 24 Aug 29 03:17:07 AM UTC 24 460593258 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.3320800590 Aug 29 03:17:04 AM UTC 24 Aug 29 03:17:08 AM UTC 24 123143738 ps