| T828 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.1599104551 |
|
|
Aug 29 03:24:09 AM UTC 24 |
Aug 29 03:24:22 AM UTC 24 |
2503392765 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.1887162507 |
|
|
Aug 29 03:24:13 AM UTC 24 |
Aug 29 03:24:22 AM UTC 24 |
2375348086 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.1462608263 |
|
|
Aug 29 03:24:12 AM UTC 24 |
Aug 29 03:24:23 AM UTC 24 |
1570647490 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1149789167 |
|
|
Aug 29 03:24:00 AM UTC 24 |
Aug 29 03:24:24 AM UTC 24 |
1907264963 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1765689513 |
|
|
Aug 29 03:24:12 AM UTC 24 |
Aug 29 03:24:24 AM UTC 24 |
668284801 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.2320006957 |
|
|
Aug 29 03:24:02 AM UTC 24 |
Aug 29 03:24:25 AM UTC 24 |
1018361310 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.2366849457 |
|
|
Aug 29 03:24:21 AM UTC 24 |
Aug 29 03:24:26 AM UTC 24 |
203883255 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.1978436503 |
|
|
Aug 29 03:23:55 AM UTC 24 |
Aug 29 03:24:26 AM UTC 24 |
3911705258 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.370585004 |
|
|
Aug 29 03:24:09 AM UTC 24 |
Aug 29 03:24:27 AM UTC 24 |
1284757060 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.3501215263 |
|
|
Aug 29 03:23:13 AM UTC 24 |
Aug 29 03:24:29 AM UTC 24 |
2596210496 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.2236429962 |
|
|
Aug 29 03:24:22 AM UTC 24 |
Aug 29 03:24:29 AM UTC 24 |
508004117 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.2134256374 |
|
|
Aug 29 03:24:19 AM UTC 24 |
Aug 29 03:24:29 AM UTC 24 |
255685682 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.3846352909 |
|
|
Aug 29 03:24:27 AM UTC 24 |
Aug 29 03:24:30 AM UTC 24 |
39062218 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.524036687 |
|
|
Aug 29 03:24:27 AM UTC 24 |
Aug 29 03:24:30 AM UTC 24 |
12324207 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.4207589012 |
|
|
Aug 29 03:23:39 AM UTC 24 |
Aug 29 03:24:32 AM UTC 24 |
30055568856 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1705508598 |
|
|
Aug 29 03:24:30 AM UTC 24 |
Aug 29 03:24:32 AM UTC 24 |
88870920 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.2901881650 |
|
|
Aug 29 03:24:30 AM UTC 24 |
Aug 29 03:24:33 AM UTC 24 |
147552399 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.528962652 |
|
|
Aug 29 03:24:29 AM UTC 24 |
Aug 29 03:24:36 AM UTC 24 |
437979508 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.2698116210 |
|
|
Aug 29 03:26:04 AM UTC 24 |
Aug 29 03:26:06 AM UTC 24 |
34100954 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.2949256289 |
|
|
Aug 29 03:19:53 AM UTC 24 |
Aug 29 03:24:36 AM UTC 24 |
52931302663 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.811998639 |
|
|
Aug 29 03:22:55 AM UTC 24 |
Aug 29 03:24:38 AM UTC 24 |
51781158171 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.1016576001 |
|
|
Aug 29 03:24:31 AM UTC 24 |
Aug 29 03:24:39 AM UTC 24 |
296981153 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.3777843798 |
|
|
Aug 29 03:24:03 AM UTC 24 |
Aug 29 03:24:40 AM UTC 24 |
11292170869 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.2823399247 |
|
|
Aug 29 03:23:12 AM UTC 24 |
Aug 29 03:24:40 AM UTC 24 |
5362554101 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.763479923 |
|
|
Aug 29 03:24:33 AM UTC 24 |
Aug 29 03:24:41 AM UTC 24 |
268193670 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1050036273 |
|
|
Aug 29 03:24:27 AM UTC 24 |
Aug 29 03:24:41 AM UTC 24 |
9341668683 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.449365436 |
|
|
Aug 29 03:24:39 AM UTC 24 |
Aug 29 03:24:41 AM UTC 24 |
22102891 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2209256640 |
|
|
Aug 29 03:24:37 AM UTC 24 |
Aug 29 03:24:43 AM UTC 24 |
186236857 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.3356916532 |
|
|
Aug 29 03:24:40 AM UTC 24 |
Aug 29 03:24:43 AM UTC 24 |
12544226 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.1538975916 |
|
|
Aug 29 03:24:40 AM UTC 24 |
Aug 29 03:24:43 AM UTC 24 |
22759910 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.955827435 |
|
|
Aug 29 03:24:41 AM UTC 24 |
Aug 29 03:24:44 AM UTC 24 |
52875899 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.2848362708 |
|
|
Aug 29 03:24:43 AM UTC 24 |
Aug 29 03:24:45 AM UTC 24 |
14618832 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.1435121073 |
|
|
Aug 29 03:23:41 AM UTC 24 |
Aug 29 03:24:46 AM UTC 24 |
19153917924 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.2399925473 |
|
|
Aug 29 03:24:31 AM UTC 24 |
Aug 29 03:24:47 AM UTC 24 |
3918246067 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.2109039469 |
|
|
Aug 29 03:24:43 AM UTC 24 |
Aug 29 03:24:47 AM UTC 24 |
121630598 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.311394717 |
|
|
Aug 29 03:19:24 AM UTC 24 |
Aug 29 03:24:50 AM UTC 24 |
37098768532 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.2851705856 |
|
|
Aug 29 03:24:24 AM UTC 24 |
Aug 29 03:24:51 AM UTC 24 |
1762823103 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.1330103305 |
|
|
Aug 29 03:24:33 AM UTC 24 |
Aug 29 03:24:52 AM UTC 24 |
3331920847 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.1865827263 |
|
|
Aug 29 03:24:44 AM UTC 24 |
Aug 29 03:24:52 AM UTC 24 |
266996997 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.3013881811 |
|
|
Aug 29 03:24:31 AM UTC 24 |
Aug 29 03:24:53 AM UTC 24 |
2177456461 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.776138271 |
|
|
Aug 29 03:24:46 AM UTC 24 |
Aug 29 03:24:53 AM UTC 24 |
297128298 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.2047017416 |
|
|
Aug 29 03:24:45 AM UTC 24 |
Aug 29 03:24:54 AM UTC 24 |
3098858002 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.2553649491 |
|
|
Aug 29 03:24:53 AM UTC 24 |
Aug 29 03:24:55 AM UTC 24 |
147297927 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.725410448 |
|
|
Aug 29 03:24:55 AM UTC 24 |
Aug 29 03:24:57 AM UTC 24 |
46323211 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.1867875808 |
|
|
Aug 29 03:24:44 AM UTC 24 |
Aug 29 03:24:57 AM UTC 24 |
1294127946 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.3805521936 |
|
|
Aug 29 03:23:54 AM UTC 24 |
Aug 29 03:24:58 AM UTC 24 |
49753451056 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.862551171 |
|
|
Aug 29 03:24:57 AM UTC 24 |
Aug 29 03:25:00 AM UTC 24 |
257148593 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.3159915501 |
|
|
Aug 29 03:24:44 AM UTC 24 |
Aug 29 03:25:01 AM UTC 24 |
5130538802 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1408007643 |
|
|
Aug 29 03:24:48 AM UTC 24 |
Aug 29 03:25:01 AM UTC 24 |
1949301174 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.1669805262 |
|
|
Aug 29 03:24:59 AM UTC 24 |
Aug 29 03:25:02 AM UTC 24 |
21485844 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.2982774488 |
|
|
Aug 29 03:24:05 AM UTC 24 |
Aug 29 03:25:02 AM UTC 24 |
15302350330 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2799149110 |
|
|
Aug 29 03:25:00 AM UTC 24 |
Aug 29 03:25:04 AM UTC 24 |
770421955 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.2506804203 |
|
|
Aug 29 03:24:41 AM UTC 24 |
Aug 29 03:25:04 AM UTC 24 |
6480401536 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.3745449427 |
|
|
Aug 29 03:24:55 AM UTC 24 |
Aug 29 03:25:05 AM UTC 24 |
8353021731 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.4029524984 |
|
|
Aug 29 03:24:59 AM UTC 24 |
Aug 29 03:25:07 AM UTC 24 |
154907541 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.2511298916 |
|
|
Aug 29 03:25:04 AM UTC 24 |
Aug 29 03:25:08 AM UTC 24 |
36193996 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.1357959860 |
|
|
Aug 29 03:24:35 AM UTC 24 |
Aug 29 03:25:10 AM UTC 24 |
4181845221 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.1492401498 |
|
|
Aug 29 03:24:24 AM UTC 24 |
Aug 29 03:25:12 AM UTC 24 |
2196364673 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.329193682 |
|
|
Aug 29 03:24:47 AM UTC 24 |
Aug 29 03:25:13 AM UTC 24 |
2853473719 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.1261499580 |
|
|
Aug 29 03:25:12 AM UTC 24 |
Aug 29 03:25:14 AM UTC 24 |
17688528 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.1142165961 |
|
|
Aug 29 03:25:13 AM UTC 24 |
Aug 29 03:25:15 AM UTC 24 |
16389800 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.1057822169 |
|
|
Aug 29 03:22:39 AM UTC 24 |
Aug 29 03:25:15 AM UTC 24 |
16742634162 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.1535744938 |
|
|
Aug 29 03:20:05 AM UTC 24 |
Aug 29 03:25:18 AM UTC 24 |
26156126934 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.1632923489 |
|
|
Aug 29 03:25:16 AM UTC 24 |
Aug 29 03:25:18 AM UTC 24 |
48459015 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.1358060782 |
|
|
Aug 29 03:25:04 AM UTC 24 |
Aug 29 03:25:18 AM UTC 24 |
598421946 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.151405701 |
|
|
Aug 29 03:25:16 AM UTC 24 |
Aug 29 03:25:18 AM UTC 24 |
43237363 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.2558832372 |
|
|
Aug 29 03:24:55 AM UTC 24 |
Aug 29 03:25:20 AM UTC 24 |
7481448168 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3350663837 |
|
|
Aug 29 03:25:16 AM UTC 24 |
Aug 29 03:25:22 AM UTC 24 |
465307590 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.848029497 |
|
|
Aug 29 03:25:14 AM UTC 24 |
Aug 29 03:25:25 AM UTC 24 |
1742885248 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.92031016 |
|
|
Aug 29 03:23:55 AM UTC 24 |
Aug 29 03:25:25 AM UTC 24 |
249606574805 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.2256540317 |
|
|
Aug 29 03:25:19 AM UTC 24 |
Aug 29 03:25:31 AM UTC 24 |
1506780266 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.1069996362 |
|
|
Aug 29 03:25:19 AM UTC 24 |
Aug 29 03:25:32 AM UTC 24 |
989474256 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.1767953854 |
|
|
Aug 29 03:25:23 AM UTC 24 |
Aug 29 03:25:33 AM UTC 24 |
340271204 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.176041252 |
|
|
Aug 29 03:25:02 AM UTC 24 |
Aug 29 03:25:33 AM UTC 24 |
15235312009 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.1374434403 |
|
|
Aug 29 03:25:06 AM UTC 24 |
Aug 29 03:25:35 AM UTC 24 |
1746025898 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.2967000684 |
|
|
Aug 29 03:25:02 AM UTC 24 |
Aug 29 03:25:36 AM UTC 24 |
178160435185 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.3709270668 |
|
|
Aug 29 03:25:28 AM UTC 24 |
Aug 29 03:25:36 AM UTC 24 |
244697111 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.701147149 |
|
|
Aug 29 03:25:35 AM UTC 24 |
Aug 29 03:25:37 AM UTC 24 |
13472033 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.1751038527 |
|
|
Aug 29 03:25:36 AM UTC 24 |
Aug 29 03:25:38 AM UTC 24 |
20989178 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.4224658720 |
|
|
Aug 29 03:25:25 AM UTC 24 |
Aug 29 03:25:41 AM UTC 24 |
2401806177 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.4191623095 |
|
|
Aug 29 03:25:39 AM UTC 24 |
Aug 29 03:25:42 AM UTC 24 |
25765119 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.3237338660 |
|
|
Aug 29 03:25:19 AM UTC 24 |
Aug 29 03:25:42 AM UTC 24 |
6921808216 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.71189075 |
|
|
Aug 29 03:25:36 AM UTC 24 |
Aug 29 03:25:42 AM UTC 24 |
621973453 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.1640180532 |
|
|
Aug 29 03:25:42 AM UTC 24 |
Aug 29 03:25:44 AM UTC 24 |
40961919 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.1433361471 |
|
|
Aug 29 03:25:38 AM UTC 24 |
Aug 29 03:25:45 AM UTC 24 |
1207892550 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.2649086712 |
|
|
Aug 29 03:25:43 AM UTC 24 |
Aug 29 03:25:47 AM UTC 24 |
78296966 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.2069101725 |
|
|
Aug 29 03:25:43 AM UTC 24 |
Aug 29 03:25:47 AM UTC 24 |
30482092 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.1092717901 |
|
|
Aug 29 03:25:45 AM UTC 24 |
Aug 29 03:25:49 AM UTC 24 |
145172458 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.1009035066 |
|
|
Aug 29 03:25:47 AM UTC 24 |
Aug 29 03:25:51 AM UTC 24 |
58186802 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.127975309 |
|
|
Aug 29 03:23:47 AM UTC 24 |
Aug 29 03:25:56 AM UTC 24 |
26339654851 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.4284865623 |
|
|
Aug 29 03:24:37 AM UTC 24 |
Aug 29 03:25:56 AM UTC 24 |
5115444397 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.3462514385 |
|
|
Aug 29 03:25:52 AM UTC 24 |
Aug 29 03:25:58 AM UTC 24 |
536355090 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.3324177556 |
|
|
Aug 29 03:25:47 AM UTC 24 |
Aug 29 03:26:00 AM UTC 24 |
241216956 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.1105199571 |
|
|
Aug 29 03:25:06 AM UTC 24 |
Aug 29 03:26:02 AM UTC 24 |
5519977161 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.3625324738 |
|
|
Aug 29 03:26:01 AM UTC 24 |
Aug 29 03:26:03 AM UTC 24 |
41634160 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.2310527879 |
|
|
Aug 29 03:26:03 AM UTC 24 |
Aug 29 03:26:05 AM UTC 24 |
14732519 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.650153103 |
|
|
Aug 29 03:26:08 AM UTC 24 |
Aug 29 03:26:10 AM UTC 24 |
79617855 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.2476455848 |
|
|
Aug 29 03:26:11 AM UTC 24 |
Aug 29 03:26:14 AM UTC 24 |
18461879 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.1731152872 |
|
|
Aug 29 03:25:46 AM UTC 24 |
Aug 29 03:26:17 AM UTC 24 |
5192874434 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.593298318 |
|
|
Aug 29 03:25:19 AM UTC 24 |
Aug 29 03:26:18 AM UTC 24 |
3817024995 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.712515400 |
|
|
Aug 29 03:25:44 AM UTC 24 |
Aug 29 03:26:20 AM UTC 24 |
2415296103 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.514662683 |
|
|
Aug 29 03:24:53 AM UTC 24 |
Aug 29 03:26:20 AM UTC 24 |
27252510657 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.1950254479 |
|
|
Aug 29 03:26:06 AM UTC 24 |
Aug 29 03:26:22 AM UTC 24 |
2202008939 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.426041177 |
|
|
Aug 29 03:23:11 AM UTC 24 |
Aug 29 03:26:23 AM UTC 24 |
59101839657 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.1685458341 |
|
|
Aug 29 03:26:14 AM UTC 24 |
Aug 29 03:26:23 AM UTC 24 |
391304805 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.3145355532 |
|
|
Aug 29 03:26:20 AM UTC 24 |
Aug 29 03:26:25 AM UTC 24 |
32069673 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.3123063944 |
|
|
Aug 29 03:25:20 AM UTC 24 |
Aug 29 03:26:25 AM UTC 24 |
63235238504 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.2393439727 |
|
|
Aug 29 03:26:23 AM UTC 24 |
Aug 29 03:26:28 AM UTC 24 |
192704860 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.917348469 |
|
|
Aug 29 03:16:45 AM UTC 24 |
Aug 29 03:26:30 AM UTC 24 |
98873215520 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.2754558464 |
|
|
Aug 29 03:26:18 AM UTC 24 |
Aug 29 03:26:32 AM UTC 24 |
1111667953 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.1152342988 |
|
|
Aug 29 03:26:26 AM UTC 24 |
Aug 29 03:26:33 AM UTC 24 |
462243144 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.3634471590 |
|
|
Aug 29 03:26:33 AM UTC 24 |
Aug 29 03:26:35 AM UTC 24 |
12798512 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.2827658406 |
|
|
Aug 29 03:26:21 AM UTC 24 |
Aug 29 03:26:36 AM UTC 24 |
4988506981 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.3347595572 |
|
|
Aug 29 03:24:26 AM UTC 24 |
Aug 29 03:26:38 AM UTC 24 |
7150292880 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.976712570 |
|
|
Aug 29 03:16:08 AM UTC 24 |
Aug 29 03:26:38 AM UTC 24 |
105571879740 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.2576433282 |
|
|
Aug 29 03:24:31 AM UTC 24 |
Aug 29 03:26:38 AM UTC 24 |
47561780704 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.4121834334 |
|
|
Aug 29 03:24:37 AM UTC 24 |
Aug 29 03:26:38 AM UTC 24 |
4639829664 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.2549495661 |
|
|
Aug 29 03:25:50 AM UTC 24 |
Aug 29 03:26:38 AM UTC 24 |
4970172977 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.1670393590 |
|
|
Aug 29 03:26:36 AM UTC 24 |
Aug 29 03:26:38 AM UTC 24 |
21305810 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.698658186 |
|
|
Aug 29 03:26:39 AM UTC 24 |
Aug 29 03:26:41 AM UTC 24 |
207930169 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.3143819304 |
|
|
Aug 29 03:25:59 AM UTC 24 |
Aug 29 03:26:42 AM UTC 24 |
3915867604 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.3269983529 |
|
|
Aug 29 03:26:39 AM UTC 24 |
Aug 29 03:26:42 AM UTC 24 |
215316814 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.3921017291 |
|
|
Aug 29 03:26:24 AM UTC 24 |
Aug 29 03:26:42 AM UTC 24 |
382942706 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.4108824459 |
|
|
Aug 29 03:26:37 AM UTC 24 |
Aug 29 03:26:43 AM UTC 24 |
1257203651 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.461358906 |
|
|
Aug 29 03:23:45 AM UTC 24 |
Aug 29 03:26:43 AM UTC 24 |
15859206175 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.2717250930 |
|
|
Aug 29 03:25:33 AM UTC 24 |
Aug 29 03:26:47 AM UTC 24 |
2463750750 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.870359694 |
|
|
Aug 29 03:26:40 AM UTC 24 |
Aug 29 03:26:50 AM UTC 24 |
1053647489 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.4227960225 |
|
|
Aug 29 03:26:17 AM UTC 24 |
Aug 29 03:26:50 AM UTC 24 |
21449449476 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.3383229266 |
|
|
Aug 29 03:26:44 AM UTC 24 |
Aug 29 03:26:50 AM UTC 24 |
62141688 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.2762760351 |
|
|
Aug 29 03:26:07 AM UTC 24 |
Aug 29 03:26:53 AM UTC 24 |
7594539307 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.2469203000 |
|
|
Aug 29 03:26:50 AM UTC 24 |
Aug 29 03:26:53 AM UTC 24 |
46619543 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.1339554943 |
|
|
Aug 29 03:26:43 AM UTC 24 |
Aug 29 03:26:53 AM UTC 24 |
451844286 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.404846418 |
|
|
Aug 29 03:26:43 AM UTC 24 |
Aug 29 03:26:55 AM UTC 24 |
1662990526 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.2661200907 |
|
|
Aug 29 03:26:54 AM UTC 24 |
Aug 29 03:26:56 AM UTC 24 |
31868290 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.2288241200 |
|
|
Aug 29 03:26:54 AM UTC 24 |
Aug 29 03:26:56 AM UTC 24 |
20580961 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.910396445 |
|
|
Aug 29 03:26:57 AM UTC 24 |
Aug 29 03:26:59 AM UTC 24 |
39638068 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.333716385 |
|
|
Aug 29 03:26:38 AM UTC 24 |
Aug 29 03:26:59 AM UTC 24 |
8342813286 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.1798690046 |
|
|
Aug 29 03:26:26 AM UTC 24 |
Aug 29 03:26:59 AM UTC 24 |
2497757253 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.918454066 |
|
|
Aug 29 03:26:42 AM UTC 24 |
Aug 29 03:27:00 AM UTC 24 |
836308177 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1544952854 |
|
|
Aug 29 03:24:04 AM UTC 24 |
Aug 29 03:27:01 AM UTC 24 |
23808921581 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.3773961555 |
|
|
Aug 29 03:26:39 AM UTC 24 |
Aug 29 03:27:02 AM UTC 24 |
12197730289 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.1108222766 |
|
|
Aug 29 03:26:55 AM UTC 24 |
Aug 29 03:27:03 AM UTC 24 |
7496366822 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.2037574367 |
|
|
Aug 29 03:26:57 AM UTC 24 |
Aug 29 03:27:03 AM UTC 24 |
300258134 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3093465864 |
|
|
Aug 29 03:27:00 AM UTC 24 |
Aug 29 03:27:06 AM UTC 24 |
345675341 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.1764966469 |
|
|
Aug 29 03:27:00 AM UTC 24 |
Aug 29 03:27:09 AM UTC 24 |
700089337 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.3051455775 |
|
|
Aug 29 03:27:02 AM UTC 24 |
Aug 29 03:27:11 AM UTC 24 |
1282288729 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.3939326097 |
|
|
Aug 29 03:22:54 AM UTC 24 |
Aug 29 03:27:13 AM UTC 24 |
28292850561 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.3465846476 |
|
|
Aug 29 03:27:07 AM UTC 24 |
Aug 29 03:27:14 AM UTC 24 |
220446443 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.236449017 |
|
|
Aug 29 03:26:56 AM UTC 24 |
Aug 29 03:27:15 AM UTC 24 |
4362174565 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.3426386478 |
|
|
Aug 29 03:25:02 AM UTC 24 |
Aug 29 03:27:16 AM UTC 24 |
61728804162 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.3542922292 |
|
|
Aug 29 03:27:16 AM UTC 24 |
Aug 29 03:27:18 AM UTC 24 |
39550248 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.4263692980 |
|
|
Aug 29 03:26:44 AM UTC 24 |
Aug 29 03:27:19 AM UTC 24 |
11078513232 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.2227450302 |
|
|
Aug 29 03:26:43 AM UTC 24 |
Aug 29 03:27:20 AM UTC 24 |
8766699947 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.679260836 |
|
|
Aug 29 03:27:03 AM UTC 24 |
Aug 29 03:27:21 AM UTC 24 |
7559345416 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.2422042063 |
|
|
Aug 29 03:19:31 AM UTC 24 |
Aug 29 03:27:22 AM UTC 24 |
45343735964 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1517350086 |
|
|
Aug 29 03:24:48 AM UTC 24 |
Aug 29 03:27:24 AM UTC 24 |
9405826103 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.1918208228 |
|
|
Aug 29 03:25:06 AM UTC 24 |
Aug 29 03:27:27 AM UTC 24 |
27534566743 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.3983997137 |
|
|
Aug 29 03:20:07 AM UTC 24 |
Aug 29 03:27:28 AM UTC 24 |
69401136444 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.1818933214 |
|
|
Aug 29 03:26:30 AM UTC 24 |
Aug 29 03:27:33 AM UTC 24 |
34012750820 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.1869051056 |
|
|
Aug 29 03:26:39 AM UTC 24 |
Aug 29 03:27:40 AM UTC 24 |
9581427120 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.3875919329 |
|
|
Aug 29 03:25:57 AM UTC 24 |
Aug 29 03:27:40 AM UTC 24 |
4969868196 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.3790759415 |
|
|
Aug 29 03:27:04 AM UTC 24 |
Aug 29 03:27:43 AM UTC 24 |
6278591006 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.4127469589 |
|
|
Aug 29 03:16:08 AM UTC 24 |
Aug 29 03:27:45 AM UTC 24 |
79833433601 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.625154749 |
|
|
Aug 29 03:27:13 AM UTC 24 |
Aug 29 03:27:45 AM UTC 24 |
2641768154 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.3016803449 |
|
|
Aug 29 03:27:00 AM UTC 24 |
Aug 29 03:27:48 AM UTC 24 |
8841087417 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.1866364735 |
|
|
Aug 29 03:27:01 AM UTC 24 |
Aug 29 03:27:57 AM UTC 24 |
4812179453 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2709333607 |
|
|
Aug 29 03:24:52 AM UTC 24 |
Aug 29 03:28:11 AM UTC 24 |
69055205804 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.2036973687 |
|
|
Aug 29 03:20:45 AM UTC 24 |
Aug 29 03:28:13 AM UTC 24 |
169746146503 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.517742056 |
|
|
Aug 29 03:24:38 AM UTC 24 |
Aug 29 03:28:13 AM UTC 24 |
61284452889 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.49234178 |
|
|
Aug 29 03:23:49 AM UTC 24 |
Aug 29 03:28:16 AM UTC 24 |
13280724516 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.2698931791 |
|
|
Aug 29 03:25:34 AM UTC 24 |
Aug 29 03:28:20 AM UTC 24 |
35206119196 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.2125701996 |
|
|
Aug 29 03:26:50 AM UTC 24 |
Aug 29 03:28:23 AM UTC 24 |
45505956075 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.2576040504 |
|
|
Aug 29 03:27:05 AM UTC 24 |
Aug 29 03:28:26 AM UTC 24 |
10824770235 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.1353923317 |
|
|
Aug 29 03:14:49 AM UTC 24 |
Aug 29 03:28:30 AM UTC 24 |
377307844641 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.642436818 |
|
|
Aug 29 03:24:24 AM UTC 24 |
Aug 29 03:28:31 AM UTC 24 |
31614513639 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.3651676559 |
|
|
Aug 29 03:24:25 AM UTC 24 |
Aug 29 03:28:38 AM UTC 24 |
12194923872 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.1615759073 |
|
|
Aug 29 03:22:10 AM UTC 24 |
Aug 29 03:29:00 AM UTC 24 |
183973367645 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.3236083481 |
|
|
Aug 29 03:23:12 AM UTC 24 |
Aug 29 03:29:08 AM UTC 24 |
199159488871 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.31910169 |
|
|
Aug 29 03:25:08 AM UTC 24 |
Aug 29 03:29:13 AM UTC 24 |
59496573020 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.4217119471 |
|
|
Aug 29 03:26:28 AM UTC 24 |
Aug 29 03:29:34 AM UTC 24 |
77337068484 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.13802812 |
|
|
Aug 29 03:27:14 AM UTC 24 |
Aug 29 03:29:42 AM UTC 24 |
17158845104 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.2632456032 |
|
|
Aug 29 03:25:11 AM UTC 24 |
Aug 29 03:29:48 AM UTC 24 |
43379676194 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.2613343909 |
|
|
Aug 29 03:15:15 AM UTC 24 |
Aug 29 03:30:12 AM UTC 24 |
455051844314 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.4249449467 |
|
|
Aug 29 03:25:25 AM UTC 24 |
Aug 29 03:30:13 AM UTC 24 |
32763034187 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.3996649808 |
|
|
Aug 29 03:21:28 AM UTC 24 |
Aug 29 03:30:15 AM UTC 24 |
62830143147 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.2297246387 |
|
|
Aug 29 03:14:10 AM UTC 24 |
Aug 29 03:30:33 AM UTC 24 |
292493217481 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.3864409408 |
|
|
Aug 29 03:26:50 AM UTC 24 |
Aug 29 03:30:47 AM UTC 24 |
15756126801 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.2464367904 |
|
|
Aug 29 03:15:42 AM UTC 24 |
Aug 29 03:30:55 AM UTC 24 |
336971569683 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.4232322108 |
|
|
Aug 29 03:17:12 AM UTC 24 |
Aug 29 03:32:13 AM UTC 24 |
79029976532 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.1751665503 |
|
|
Aug 29 03:18:20 AM UTC 24 |
Aug 29 03:32:17 AM UTC 24 |
266190361468 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.42441582 |
|
|
Aug 29 03:24:53 AM UTC 24 |
Aug 29 03:33:19 AM UTC 24 |
86173629275 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.2070725678 |
|
|
Aug 29 03:08:39 AM UTC 24 |
Aug 29 03:33:53 AM UTC 24 |
135472937511 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.1008566918 |
|
|
Aug 29 03:27:15 AM UTC 24 |
Aug 29 03:34:47 AM UTC 24 |
143894871532 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.3419643013 |
|
|
Aug 29 03:25:56 AM UTC 24 |
Aug 29 03:35:03 AM UTC 24 |
320315407379 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.1076305679 |
|
|
Aug 29 03:27:10 AM UTC 24 |
Aug 29 03:35:09 AM UTC 24 |
205019700930 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.2240641480 |
|
|
Aug 29 03:26:47 AM UTC 24 |
Aug 29 03:35:30 AM UTC 24 |
844789229431 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2912780576 |
|
|
Aug 29 03:26:25 AM UTC 24 |
Aug 29 03:35:35 AM UTC 24 |
60530973055 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.1685967982 |
|
|
Aug 29 03:25:34 AM UTC 24 |
Aug 29 03:35:41 AM UTC 24 |
57436017279 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.3611615864 |
|
|
Aug 29 03:23:29 AM UTC 24 |
Aug 29 03:36:01 AM UTC 24 |
87739004453 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.648268558 |
|
|
Aug 29 03:23:48 AM UTC 24 |
Aug 29 03:36:19 AM UTC 24 |
263229996589 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.2129800752 |
|
|
Aug 29 03:25:09 AM UTC 24 |
Aug 29 03:36:21 AM UTC 24 |
908600397807 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.1953247131 |
|
|
Aug 29 03:24:25 AM UTC 24 |
Aug 29 03:37:01 AM UTC 24 |
317468175713 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.1696952495 |
|
|
Aug 29 03:19:01 AM UTC 24 |
Aug 29 03:37:09 AM UTC 24 |
1959264915623 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.3402066219 |
|
|
Aug 29 03:25:32 AM UTC 24 |
Aug 29 03:37:10 AM UTC 24 |
95211555780 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.3910709976 |
|
|
Aug 29 03:26:32 AM UTC 24 |
Aug 29 03:37:47 AM UTC 24 |
61260275674 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.21306449 |
|
|
Aug 29 03:24:39 AM UTC 24 |
Aug 29 03:42:07 AM UTC 24 |
437321140472 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2266862507 |
|
|
Aug 29 07:20:01 AM UTC 24 |
Aug 29 07:20:10 AM UTC 24 |
80749266 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.3387214708 |
|
|
Aug 29 07:20:10 AM UTC 24 |
Aug 29 07:20:13 AM UTC 24 |
14813981 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.1447154102 |
|
|
Aug 29 07:20:14 AM UTC 24 |
Aug 29 07:20:16 AM UTC 24 |
16392927 ps |
| T98 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1093995853 |
|
|
Aug 29 07:20:14 AM UTC 24 |
Aug 29 07:20:16 AM UTC 24 |
292615447 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2968639232 |
|
|
Aug 29 07:20:14 AM UTC 24 |
Aug 29 07:20:18 AM UTC 24 |
62001208 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.4101736030 |
|
|
Aug 29 07:20:14 AM UTC 24 |
Aug 29 07:20:18 AM UTC 24 |
33068726 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3707591982 |
|
|
Aug 29 07:20:04 AM UTC 24 |
Aug 29 07:20:22 AM UTC 24 |
196976364 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.128828067 |
|
|
Aug 29 07:20:19 AM UTC 24 |
Aug 29 07:20:23 AM UTC 24 |
236655365 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2366255574 |
|
|
Aug 29 07:20:19 AM UTC 24 |
Aug 29 07:20:25 AM UTC 24 |
145236644 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.2640152156 |
|
|
Aug 29 07:20:24 AM UTC 24 |
Aug 29 07:20:26 AM UTC 24 |
35371864 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.565848735 |
|
|
Aug 29 07:20:25 AM UTC 24 |
Aug 29 07:20:27 AM UTC 24 |
30647609 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.442222202 |
|
|
Aug 29 07:20:18 AM UTC 24 |
Aug 29 07:20:29 AM UTC 24 |
443970245 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.1792523389 |
|
|
Aug 29 07:20:23 AM UTC 24 |
Aug 29 07:20:31 AM UTC 24 |
265049808 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1366783330 |
|
|
Aug 29 07:20:29 AM UTC 24 |
Aug 29 07:20:31 AM UTC 24 |
21107671 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1425933976 |
|
|
Aug 29 07:20:27 AM UTC 24 |
Aug 29 07:20:31 AM UTC 24 |
89861231 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.80221880 |
|
|
Aug 29 07:20:30 AM UTC 24 |
Aug 29 07:20:34 AM UTC 24 |
176438404 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2832794319 |
|
|
Aug 29 07:20:32 AM UTC 24 |
Aug 29 07:20:36 AM UTC 24 |
232655043 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.709714582 |
|
|
Aug 29 07:20:33 AM UTC 24 |
Aug 29 07:20:36 AM UTC 24 |
220883001 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.1001244170 |
|
|
Aug 29 07:20:35 AM UTC 24 |
Aug 29 07:20:37 AM UTC 24 |
16529390 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2885612962 |
|
|
Aug 29 07:20:36 AM UTC 24 |
Aug 29 07:20:39 AM UTC 24 |
12954828 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2868475621 |
|
|
Aug 29 07:20:38 AM UTC 24 |
Aug 29 07:20:41 AM UTC 24 |
504272367 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1998590315 |
|
|
Aug 29 07:20:37 AM UTC 24 |
Aug 29 07:20:42 AM UTC 24 |
62573470 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3772845638 |
|
|
Aug 29 07:20:34 AM UTC 24 |
Aug 29 07:20:42 AM UTC 24 |
142656869 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2852894374 |
|
|
Aug 29 07:20:40 AM UTC 24 |
Aug 29 07:20:43 AM UTC 24 |
152402153 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.653389675 |
|
|
Aug 29 07:20:23 AM UTC 24 |
Aug 29 07:20:45 AM UTC 24 |
1092483329 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3532725706 |
|
|
Aug 29 07:20:43 AM UTC 24 |
Aug 29 07:20:47 AM UTC 24 |
50958919 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4267070463 |
|
|
Aug 29 07:20:17 AM UTC 24 |
Aug 29 07:20:48 AM UTC 24 |
374767259 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.2509654781 |
|
|
Aug 29 07:20:44 AM UTC 24 |
Aug 29 07:20:49 AM UTC 24 |
373993637 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1670611944 |
|
|
Aug 29 07:20:44 AM UTC 24 |
Aug 29 07:20:49 AM UTC 24 |
105961679 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.4069846706 |
|
|
Aug 29 07:20:32 AM UTC 24 |
Aug 29 07:20:50 AM UTC 24 |
242958912 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.2529318333 |
|
|
Aug 29 07:20:48 AM UTC 24 |
Aug 29 07:20:50 AM UTC 24 |
11242933 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.3094207884 |
|
|
Aug 29 07:20:34 AM UTC 24 |
Aug 29 07:20:51 AM UTC 24 |
397170910 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.4026770442 |
|
|
Aug 29 07:20:49 AM UTC 24 |
Aug 29 07:20:51 AM UTC 24 |
34580309 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.3152808841 |
|
|
Aug 29 07:20:49 AM UTC 24 |
Aug 29 07:20:53 AM UTC 24 |
277745175 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3761167472 |
|
|
Aug 29 07:20:51 AM UTC 24 |
Aug 29 07:20:53 AM UTC 24 |
43097665 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.220786717 |
|
|
Aug 29 07:21:18 AM UTC 24 |
Aug 29 07:21:23 AM UTC 24 |
44523474 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.1147127615 |
|
|
Aug 29 07:20:51 AM UTC 24 |
Aug 29 07:20:54 AM UTC 24 |
151094446 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3019607947 |
|
|
Aug 29 07:20:52 AM UTC 24 |
Aug 29 07:20:56 AM UTC 24 |
68810115 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.3154355125 |
|
|
Aug 29 07:20:54 AM UTC 24 |
Aug 29 07:20:58 AM UTC 24 |
237891758 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.353161225 |
|
|
Aug 29 07:20:56 AM UTC 24 |
Aug 29 07:20:59 AM UTC 24 |
46677719 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.20371959 |
|
|
Aug 29 07:20:58 AM UTC 24 |
Aug 29 07:21:01 AM UTC 24 |
19388258 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.1701869509 |
|
|
Aug 29 07:20:32 AM UTC 24 |
Aug 29 07:21:02 AM UTC 24 |
2856303084 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.3470612819 |
|
|
Aug 29 07:20:59 AM UTC 24 |
Aug 29 07:21:03 AM UTC 24 |
36848192 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.3393220627 |
|
|
Aug 29 07:21:02 AM UTC 24 |
Aug 29 07:21:04 AM UTC 24 |
61186286 ps |