T606 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.732547652 |
|
|
Aug 29 03:16:56 AM UTC 24 |
Aug 29 03:17:11 AM UTC 24 |
4568171059 ps |
T607 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.3920096026 |
|
|
Aug 29 03:17:06 AM UTC 24 |
Aug 29 03:17:11 AM UTC 24 |
39808227 ps |
T608 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.3120005220 |
|
|
Aug 29 03:17:03 AM UTC 24 |
Aug 29 03:17:14 AM UTC 24 |
485846770 ps |
T609 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.3341792912 |
|
|
Aug 29 03:17:15 AM UTC 24 |
Aug 29 03:17:17 AM UTC 24 |
79753629 ps |
T610 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.377442505 |
|
|
Aug 29 03:16:52 AM UTC 24 |
Aug 29 03:17:19 AM UTC 24 |
4513546635 ps |
T611 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.526798262 |
|
|
Aug 29 03:17:18 AM UTC 24 |
Aug 29 03:17:20 AM UTC 24 |
115544573 ps |
T36 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.524881152 |
|
|
Aug 29 03:14:11 AM UTC 24 |
Aug 29 03:17:20 AM UTC 24 |
18651352739 ps |
T612 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.3903528123 |
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|
Aug 29 03:17:20 AM UTC 24 |
Aug 29 03:17:22 AM UTC 24 |
60098838 ps |
T613 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.1839224582 |
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|
Aug 29 03:17:04 AM UTC 24 |
Aug 29 03:17:23 AM UTC 24 |
3303301126 ps |
T614 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.1040945802 |
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|
Aug 29 03:17:23 AM UTC 24 |
Aug 29 03:17:25 AM UTC 24 |
83587605 ps |
T615 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.2139376997 |
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Aug 29 03:17:08 AM UTC 24 |
Aug 29 03:17:28 AM UTC 24 |
1079652618 ps |
T616 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.602312919 |
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|
Aug 29 03:17:21 AM UTC 24 |
Aug 29 03:17:28 AM UTC 24 |
6990221849 ps |
T617 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.628110499 |
|
|
Aug 29 03:17:24 AM UTC 24 |
Aug 29 03:17:28 AM UTC 24 |
254953428 ps |
T618 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.2866956172 |
|
|
Aug 29 03:17:21 AM UTC 24 |
Aug 29 03:17:31 AM UTC 24 |
4959524074 ps |
T619 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.999807262 |
|
|
Aug 29 03:16:26 AM UTC 24 |
Aug 29 03:17:32 AM UTC 24 |
5223702098 ps |
T620 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.515376568 |
|
|
Aug 29 03:17:26 AM UTC 24 |
Aug 29 03:17:33 AM UTC 24 |
483722563 ps |
T621 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.1947774118 |
|
|
Aug 29 03:15:41 AM UTC 24 |
Aug 29 03:17:33 AM UTC 24 |
6012036038 ps |
T622 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.2116374194 |
|
|
Aug 29 03:17:29 AM UTC 24 |
Aug 29 03:17:34 AM UTC 24 |
204437207 ps |
T623 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.3816231478 |
|
|
Aug 29 03:17:30 AM UTC 24 |
Aug 29 03:17:37 AM UTC 24 |
512302720 ps |
T624 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.621054512 |
|
|
Aug 29 03:17:32 AM UTC 24 |
Aug 29 03:17:37 AM UTC 24 |
2369367143 ps |
T68 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.4029010214 |
|
|
Aug 29 03:16:09 AM UTC 24 |
Aug 29 03:17:37 AM UTC 24 |
17312239718 ps |
T75 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.1260180011 |
|
|
Aug 29 03:16:59 AM UTC 24 |
Aug 29 03:17:45 AM UTC 24 |
8235183178 ps |
T76 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.4250304670 |
|
|
Aug 29 03:15:46 AM UTC 24 |
Aug 29 03:17:45 AM UTC 24 |
20310615673 ps |
T77 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.2448898116 |
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|
Aug 29 03:16:33 AM UTC 24 |
Aug 29 03:17:47 AM UTC 24 |
10738683900 ps |
T78 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.206591856 |
|
|
Aug 29 03:17:46 AM UTC 24 |
Aug 29 03:17:48 AM UTC 24 |
13279139 ps |
T79 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.3639888144 |
|
|
Aug 29 03:17:35 AM UTC 24 |
Aug 29 03:17:49 AM UTC 24 |
2057357098 ps |
T80 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3628525016 |
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|
Aug 29 03:12:17 AM UTC 24 |
Aug 29 03:17:49 AM UTC 24 |
138095832695 ps |
T81 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.2028141641 |
|
|
Aug 29 03:17:47 AM UTC 24 |
Aug 29 03:17:50 AM UTC 24 |
45124433 ps |
T82 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.3638944220 |
|
|
Aug 29 03:17:51 AM UTC 24 |
Aug 29 03:17:53 AM UTC 24 |
17439468 ps |
T83 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.3643345502 |
|
|
Aug 29 03:17:51 AM UTC 24 |
Aug 29 03:17:54 AM UTC 24 |
71141834 ps |
T625 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.1194553734 |
|
|
Aug 29 03:17:34 AM UTC 24 |
Aug 29 03:17:57 AM UTC 24 |
9496108535 ps |
T626 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.2199871731 |
|
|
Aug 29 03:17:58 AM UTC 24 |
Aug 29 03:18:02 AM UTC 24 |
80309429 ps |
T627 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.160772147 |
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|
Aug 29 03:17:34 AM UTC 24 |
Aug 29 03:18:02 AM UTC 24 |
2894937995 ps |
T628 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.2523483496 |
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|
Aug 29 03:17:50 AM UTC 24 |
Aug 29 03:18:04 AM UTC 24 |
3967019729 ps |
T629 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.2899040068 |
|
|
Aug 29 03:17:30 AM UTC 24 |
Aug 29 03:18:06 AM UTC 24 |
2345132162 ps |
T630 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.2358556053 |
|
|
Aug 29 03:17:54 AM UTC 24 |
Aug 29 03:18:09 AM UTC 24 |
14547423244 ps |
T631 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.1536338204 |
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|
Aug 29 03:18:04 AM UTC 24 |
Aug 29 03:18:11 AM UTC 24 |
189048677 ps |
T632 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.722001976 |
|
|
Aug 29 03:18:03 AM UTC 24 |
Aug 29 03:18:13 AM UTC 24 |
2405722165 ps |
T633 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.2352230223 |
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|
Aug 29 03:15:36 AM UTC 24 |
Aug 29 03:18:13 AM UTC 24 |
31134921645 ps |
T634 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.366832573 |
|
|
Aug 29 03:18:14 AM UTC 24 |
Aug 29 03:18:16 AM UTC 24 |
151527092 ps |
T635 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.1987827641 |
|
|
Aug 29 03:18:07 AM UTC 24 |
Aug 29 03:18:19 AM UTC 24 |
198288217 ps |
T636 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.674140817 |
|
|
Aug 29 03:17:50 AM UTC 24 |
Aug 29 03:18:19 AM UTC 24 |
4867043161 ps |
T297 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.1482040552 |
|
|
Aug 29 03:14:48 AM UTC 24 |
Aug 29 03:18:20 AM UTC 24 |
46386321318 ps |
T637 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.1640271159 |
|
|
Aug 29 03:18:20 AM UTC 24 |
Aug 29 03:18:22 AM UTC 24 |
16220815 ps |
T638 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.1758813674 |
|
|
Aug 29 03:18:12 AM UTC 24 |
Aug 29 03:18:23 AM UTC 24 |
23494641941 ps |
T639 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.4127068775 |
|
|
Aug 29 03:17:10 AM UTC 24 |
Aug 29 03:18:23 AM UTC 24 |
5536284670 ps |
T640 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.1584458874 |
|
|
Aug 29 03:18:21 AM UTC 24 |
Aug 29 03:18:23 AM UTC 24 |
20063923 ps |
T641 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.2385534384 |
|
|
Aug 29 03:18:24 AM UTC 24 |
Aug 29 03:18:26 AM UTC 24 |
13395354 ps |
T642 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.3811763446 |
|
|
Aug 29 03:18:24 AM UTC 24 |
Aug 29 03:18:27 AM UTC 24 |
146222396 ps |
T643 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.4012230821 |
|
|
Aug 29 03:18:14 AM UTC 24 |
Aug 29 03:18:30 AM UTC 24 |
586705105 ps |
T644 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.1628436834 |
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|
Aug 29 03:18:23 AM UTC 24 |
Aug 29 03:18:32 AM UTC 24 |
1865293716 ps |
T645 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.505385089 |
|
|
Aug 29 03:18:31 AM UTC 24 |
Aug 29 03:18:35 AM UTC 24 |
64488244 ps |
T646 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.3201886831 |
|
|
Aug 29 03:17:55 AM UTC 24 |
Aug 29 03:18:38 AM UTC 24 |
22182198736 ps |
T647 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.1963213215 |
|
|
Aug 29 03:18:33 AM UTC 24 |
Aug 29 03:18:44 AM UTC 24 |
1095468404 ps |
T648 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.2328407840 |
|
|
Aug 29 03:18:39 AM UTC 24 |
Aug 29 03:18:48 AM UTC 24 |
1612481481 ps |
T649 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.4243285498 |
|
|
Aug 29 03:18:36 AM UTC 24 |
Aug 29 03:18:50 AM UTC 24 |
3084057536 ps |
T650 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.1895938891 |
|
|
Aug 29 03:18:23 AM UTC 24 |
Aug 29 03:18:53 AM UTC 24 |
17318452367 ps |
T651 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.4156522788 |
|
|
Aug 29 03:18:45 AM UTC 24 |
Aug 29 03:18:55 AM UTC 24 |
1137024325 ps |
T652 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.2018193456 |
|
|
Aug 29 03:18:02 AM UTC 24 |
Aug 29 03:19:00 AM UTC 24 |
3583577454 ps |
T653 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.3899984168 |
|
|
Aug 29 03:18:50 AM UTC 24 |
Aug 29 03:19:00 AM UTC 24 |
5327511874 ps |
T654 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.3223013081 |
|
|
Aug 29 03:18:28 AM UTC 24 |
Aug 29 03:19:02 AM UTC 24 |
8684908241 ps |
T655 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.3108751795 |
|
|
Aug 29 03:17:34 AM UTC 24 |
Aug 29 03:19:04 AM UTC 24 |
5921311090 ps |
T656 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.3834317664 |
|
|
Aug 29 03:19:02 AM UTC 24 |
Aug 29 03:19:05 AM UTC 24 |
12841432 ps |
T657 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.3667545381 |
|
|
Aug 29 03:18:27 AM UTC 24 |
Aug 29 03:19:06 AM UTC 24 |
25097751537 ps |
T658 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.1369607268 |
|
|
Aug 29 03:19:04 AM UTC 24 |
Aug 29 03:19:07 AM UTC 24 |
20026863 ps |
T659 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.906049728 |
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|
Aug 29 03:19:06 AM UTC 24 |
Aug 29 03:19:08 AM UTC 24 |
12757672 ps |
T660 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.2116541841 |
|
|
Aug 29 03:19:08 AM UTC 24 |
Aug 29 03:19:10 AM UTC 24 |
16030486 ps |
T661 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.497731252 |
|
|
Aug 29 03:19:09 AM UTC 24 |
Aug 29 03:19:12 AM UTC 24 |
148520363 ps |
T320 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.3714344376 |
|
|
Aug 29 03:16:40 AM UTC 24 |
Aug 29 03:19:14 AM UTC 24 |
9214263532 ps |
T662 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.1245798557 |
|
|
Aug 29 03:19:11 AM UTC 24 |
Aug 29 03:19:15 AM UTC 24 |
103168385 ps |
T663 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.937269888 |
|
|
Aug 29 03:19:13 AM UTC 24 |
Aug 29 03:19:19 AM UTC 24 |
322232255 ps |
T664 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.1772849824 |
|
|
Aug 29 03:17:38 AM UTC 24 |
Aug 29 03:19:20 AM UTC 24 |
33441645265 ps |
T665 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.1604998449 |
|
|
Aug 29 03:13:01 AM UTC 24 |
Aug 29 03:19:22 AM UTC 24 |
38810170882 ps |
T666 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.2144655753 |
|
|
Aug 29 03:19:15 AM UTC 24 |
Aug 29 03:19:23 AM UTC 24 |
517897884 ps |
T667 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.3569545489 |
|
|
Aug 29 03:19:21 AM UTC 24 |
Aug 29 03:19:25 AM UTC 24 |
125401481 ps |
T668 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.2256055204 |
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|
Aug 29 03:19:21 AM UTC 24 |
Aug 29 03:19:28 AM UTC 24 |
299777518 ps |
T292 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.1482312150 |
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|
Aug 29 03:18:09 AM UTC 24 |
Aug 29 03:19:29 AM UTC 24 |
23363905109 ps |
T669 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.2778366210 |
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|
Aug 29 03:19:24 AM UTC 24 |
Aug 29 03:19:30 AM UTC 24 |
211023992 ps |
T670 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.639915735 |
|
|
Aug 29 03:19:16 AM UTC 24 |
Aug 29 03:19:31 AM UTC 24 |
401518849 ps |
T671 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.517694075 |
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|
Aug 29 03:15:48 AM UTC 24 |
Aug 29 03:19:33 AM UTC 24 |
13548188819 ps |
T672 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.4056785378 |
|
|
Aug 29 03:19:32 AM UTC 24 |
Aug 29 03:19:34 AM UTC 24 |
31925956 ps |
T673 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.3360772352 |
|
|
Aug 29 03:19:07 AM UTC 24 |
Aug 29 03:19:35 AM UTC 24 |
2050434826 ps |
T674 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.791887711 |
|
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Aug 29 03:19:34 AM UTC 24 |
Aug 29 03:19:37 AM UTC 24 |
20584254 ps |
T675 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.3202179466 |
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|
Aug 29 03:19:29 AM UTC 24 |
Aug 29 03:19:39 AM UTC 24 |
1755871532 ps |
T676 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.1590764026 |
|
|
Aug 29 03:19:38 AM UTC 24 |
Aug 29 03:19:40 AM UTC 24 |
72132689 ps |
T270 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.1252144818 |
|
|
Aug 29 03:24:48 AM UTC 24 |
Aug 29 03:26:07 AM UTC 24 |
8146306770 ps |
T677 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.3671287740 |
|
|
Aug 29 03:19:20 AM UTC 24 |
Aug 29 03:19:42 AM UTC 24 |
4046738553 ps |
T678 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.852667034 |
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|
Aug 29 03:19:40 AM UTC 24 |
Aug 29 03:19:42 AM UTC 24 |
13106814 ps |
T318 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.2216530823 |
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Aug 29 03:18:54 AM UTC 24 |
Aug 29 03:19:43 AM UTC 24 |
2558203868 ps |
T679 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.1470114208 |
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Aug 29 03:19:35 AM UTC 24 |
Aug 29 03:19:44 AM UTC 24 |
522257187 ps |
T680 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.94588754 |
|
|
Aug 29 03:19:36 AM UTC 24 |
Aug 29 03:19:51 AM UTC 24 |
5017188953 ps |
T681 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.2992483086 |
|
|
Aug 29 03:19:44 AM UTC 24 |
Aug 29 03:19:51 AM UTC 24 |
231294879 ps |
T682 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.2980288094 |
|
|
Aug 29 03:19:43 AM UTC 24 |
Aug 29 03:19:52 AM UTC 24 |
1708169147 ps |
T683 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.4261476845 |
|
|
Aug 29 03:19:41 AM UTC 24 |
Aug 29 03:19:54 AM UTC 24 |
792864854 ps |
T684 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.155704696 |
|
|
Aug 29 03:19:26 AM UTC 24 |
Aug 29 03:20:00 AM UTC 24 |
10479611110 ps |
T685 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.1837659095 |
|
|
Aug 29 03:19:53 AM UTC 24 |
Aug 29 03:20:03 AM UTC 24 |
454571152 ps |
T686 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.1187515760 |
|
|
Aug 29 03:19:44 AM UTC 24 |
Aug 29 03:20:06 AM UTC 24 |
528246362 ps |
T687 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.1953266338 |
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|
Aug 29 03:18:48 AM UTC 24 |
Aug 29 03:20:09 AM UTC 24 |
19075664411 ps |
T688 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.2227796173 |
|
|
Aug 29 03:17:38 AM UTC 24 |
Aug 29 03:20:09 AM UTC 24 |
9920757397 ps |
T689 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.297478888 |
|
|
Aug 29 03:19:53 AM UTC 24 |
Aug 29 03:20:12 AM UTC 24 |
920894644 ps |
T690 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.451376061 |
|
|
Aug 29 03:20:11 AM UTC 24 |
Aug 29 03:20:13 AM UTC 24 |
45079898 ps |
T69 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.3430759326 |
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|
Aug 29 03:12:26 AM UTC 24 |
Aug 29 03:20:13 AM UTC 24 |
72384422373 ps |
T691 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.541463348 |
|
|
Aug 29 03:19:55 AM UTC 24 |
Aug 29 03:20:15 AM UTC 24 |
1836356762 ps |
T692 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.711906927 |
|
|
Aug 29 03:20:14 AM UTC 24 |
Aug 29 03:20:17 AM UTC 24 |
92591320 ps |
T693 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.3241848081 |
|
|
Aug 29 03:20:16 AM UTC 24 |
Aug 29 03:20:18 AM UTC 24 |
36827450 ps |
T694 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.2168188593 |
|
|
Aug 29 03:20:16 AM UTC 24 |
Aug 29 03:20:19 AM UTC 24 |
407885934 ps |
T695 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.300559893 |
|
|
Aug 29 03:19:43 AM UTC 24 |
Aug 29 03:20:22 AM UTC 24 |
3342122305 ps |
T696 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.3008936434 |
|
|
Aug 29 03:13:00 AM UTC 24 |
Aug 29 03:20:33 AM UTC 24 |
111798946370 ps |
T697 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.2812399621 |
|
|
Aug 29 03:20:18 AM UTC 24 |
Aug 29 03:20:34 AM UTC 24 |
2055957529 ps |
T698 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.2349118442 |
|
|
Aug 29 03:20:22 AM UTC 24 |
Aug 29 03:20:40 AM UTC 24 |
1924347380 ps |
T699 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.1547511914 |
|
|
Aug 29 03:20:20 AM UTC 24 |
Aug 29 03:20:45 AM UTC 24 |
1594248298 ps |
T315 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.2036367720 |
|
|
Aug 29 03:18:56 AM UTC 24 |
Aug 29 03:20:46 AM UTC 24 |
11456625623 ps |
T700 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.934481537 |
|
|
Aug 29 03:20:40 AM UTC 24 |
Aug 29 03:20:47 AM UTC 24 |
156893545 ps |
T701 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.1874049072 |
|
|
Aug 29 03:20:14 AM UTC 24 |
Aug 29 03:20:51 AM UTC 24 |
12665146392 ps |
T328 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.3349792134 |
|
|
Aug 29 03:13:44 AM UTC 24 |
Aug 29 03:20:52 AM UTC 24 |
313983263744 ps |
T702 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.1567122381 |
|
|
Aug 29 03:20:15 AM UTC 24 |
Aug 29 03:20:53 AM UTC 24 |
3133157735 ps |
T703 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.2953788038 |
|
|
Aug 29 03:20:47 AM UTC 24 |
Aug 29 03:20:54 AM UTC 24 |
531418907 ps |
T704 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.898832842 |
|
|
Aug 29 03:20:19 AM UTC 24 |
Aug 29 03:20:56 AM UTC 24 |
12908081409 ps |
T705 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.1426895505 |
|
|
Aug 29 03:20:55 AM UTC 24 |
Aug 29 03:20:57 AM UTC 24 |
13214651 ps |
T706 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.3569347320 |
|
|
Aug 29 03:20:57 AM UTC 24 |
Aug 29 03:20:59 AM UTC 24 |
67241968 ps |
T707 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.190216468 |
|
|
Aug 29 03:16:41 AM UTC 24 |
Aug 29 03:21:03 AM UTC 24 |
98029910590 ps |
T708 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.3304891309 |
|
|
Aug 29 03:20:48 AM UTC 24 |
Aug 29 03:21:05 AM UTC 24 |
3727861745 ps |
T709 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.1768765282 |
|
|
Aug 29 03:21:04 AM UTC 24 |
Aug 29 03:21:07 AM UTC 24 |
50149935 ps |
T710 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.413836293 |
|
|
Aug 29 03:21:05 AM UTC 24 |
Aug 29 03:21:09 AM UTC 24 |
67584531 ps |
T711 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.1943046589 |
|
|
Aug 29 03:20:35 AM UTC 24 |
Aug 29 03:21:11 AM UTC 24 |
2289030492 ps |
T712 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.1580710332 |
|
|
Aug 29 03:21:07 AM UTC 24 |
Aug 29 03:21:12 AM UTC 24 |
46598436 ps |
T713 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.3202069743 |
|
|
Aug 29 03:21:11 AM UTC 24 |
Aug 29 03:21:16 AM UTC 24 |
30110041 ps |
T714 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.1232716281 |
|
|
Aug 29 03:21:00 AM UTC 24 |
Aug 29 03:21:21 AM UTC 24 |
2921819716 ps |
T715 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.4270000823 |
|
|
Aug 29 03:20:33 AM UTC 24 |
Aug 29 03:21:21 AM UTC 24 |
27153720335 ps |
T716 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.1268627143 |
|
|
Aug 29 03:20:58 AM UTC 24 |
Aug 29 03:21:27 AM UTC 24 |
4950008539 ps |
T717 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.2341372424 |
|
|
Aug 29 03:21:14 AM UTC 24 |
Aug 29 03:21:30 AM UTC 24 |
1519776680 ps |
T718 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.1987759923 |
|
|
Aug 29 03:21:09 AM UTC 24 |
Aug 29 03:21:31 AM UTC 24 |
14463860330 ps |
T719 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.35354339 |
|
|
Aug 29 03:21:17 AM UTC 24 |
Aug 29 03:21:33 AM UTC 24 |
2114693746 ps |
T322 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.1321868183 |
|
|
Aug 29 03:18:17 AM UTC 24 |
Aug 29 03:21:35 AM UTC 24 |
24402194492 ps |
T720 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3947625846 |
|
|
Aug 29 03:21:22 AM UTC 24 |
Aug 29 03:21:36 AM UTC 24 |
1186332348 ps |
T721 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.2078555543 |
|
|
Aug 29 03:21:31 AM UTC 24 |
Aug 29 03:21:38 AM UTC 24 |
87241780 ps |
T722 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.1015873274 |
|
|
Aug 29 03:21:22 AM UTC 24 |
Aug 29 03:21:40 AM UTC 24 |
3316537087 ps |
T723 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.4263091843 |
|
|
Aug 29 03:21:38 AM UTC 24 |
Aug 29 03:21:40 AM UTC 24 |
19706949 ps |
T310 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.1505381022 |
|
|
Aug 29 03:17:12 AM UTC 24 |
Aug 29 03:21:40 AM UTC 24 |
47853914086 ps |
T724 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.3444679715 |
|
|
Aug 29 03:21:40 AM UTC 24 |
Aug 29 03:21:43 AM UTC 24 |
41901227 ps |
T725 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.4112940424 |
|
|
Aug 29 03:21:44 AM UTC 24 |
Aug 29 03:21:46 AM UTC 24 |
28060765 ps |
T317 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.4164695264 |
|
|
Aug 29 03:17:38 AM UTC 24 |
Aug 29 03:21:49 AM UTC 24 |
48831487148 ps |
T726 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.4268198331 |
|
|
Aug 29 03:21:47 AM UTC 24 |
Aug 29 03:21:50 AM UTC 24 |
27731520 ps |
T727 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.2321926814 |
|
|
Aug 29 03:21:42 AM UTC 24 |
Aug 29 03:21:51 AM UTC 24 |
2197570886 ps |
T728 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.1466721633 |
|
|
Aug 29 03:21:33 AM UTC 24 |
Aug 29 03:21:52 AM UTC 24 |
11645963878 ps |
T326 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.3171901917 |
|
|
Aug 29 03:17:07 AM UTC 24 |
Aug 29 03:22:00 AM UTC 24 |
216069656907 ps |
T729 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.2202553828 |
|
|
Aug 29 03:21:53 AM UTC 24 |
Aug 29 03:22:02 AM UTC 24 |
1099922954 ps |
T730 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.3442229870 |
|
|
Aug 29 03:21:50 AM UTC 24 |
Aug 29 03:22:05 AM UTC 24 |
1883889444 ps |
T731 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.3745261189 |
|
|
Aug 29 03:21:51 AM UTC 24 |
Aug 29 03:22:10 AM UTC 24 |
40568259414 ps |
T732 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.2617308578 |
|
|
Aug 29 03:21:52 AM UTC 24 |
Aug 29 03:22:12 AM UTC 24 |
8357083946 ps |
T733 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.2153783932 |
|
|
Aug 29 03:21:42 AM UTC 24 |
Aug 29 03:22:13 AM UTC 24 |
6936804677 ps |
T734 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.2265403689 |
|
|
Aug 29 03:22:05 AM UTC 24 |
Aug 29 03:22:13 AM UTC 24 |
281700467 ps |
T735 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.2148007128 |
|
|
Aug 29 03:22:02 AM UTC 24 |
Aug 29 03:22:16 AM UTC 24 |
708350005 ps |
T736 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.2748648063 |
|
|
Aug 29 03:21:36 AM UTC 24 |
Aug 29 03:22:17 AM UTC 24 |
5751654741 ps |
T737 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.3009373950 |
|
|
Aug 29 03:22:11 AM UTC 24 |
Aug 29 03:22:19 AM UTC 24 |
640353993 ps |
T738 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.95452396 |
|
|
Aug 29 03:22:17 AM UTC 24 |
Aug 29 03:22:20 AM UTC 24 |
63697997 ps |
T739 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.2806975488 |
|
|
Aug 29 03:22:18 AM UTC 24 |
Aug 29 03:22:20 AM UTC 24 |
21802794 ps |
T740 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.3516530288 |
|
|
Aug 29 03:22:01 AM UTC 24 |
Aug 29 03:22:21 AM UTC 24 |
5246106891 ps |
T741 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.2371342685 |
|
|
Aug 29 03:22:20 AM UTC 24 |
Aug 29 03:22:23 AM UTC 24 |
170873887 ps |
T742 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.3097252522 |
|
|
Aug 29 03:22:22 AM UTC 24 |
Aug 29 03:22:24 AM UTC 24 |
25878569 ps |
T743 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.2999258594 |
|
|
Aug 29 03:22:24 AM UTC 24 |
Aug 29 03:22:27 AM UTC 24 |
170396381 ps |
T744 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.3522639269 |
|
|
Aug 29 03:17:46 AM UTC 24 |
Aug 29 03:22:27 AM UTC 24 |
22494596637 ps |
T745 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.2671134164 |
|
|
Aug 29 03:22:25 AM UTC 24 |
Aug 29 03:22:30 AM UTC 24 |
70488640 ps |
T746 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.3101654228 |
|
|
Aug 29 03:22:20 AM UTC 24 |
Aug 29 03:22:32 AM UTC 24 |
1159245902 ps |
T747 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.823576861 |
|
|
Aug 29 03:22:28 AM UTC 24 |
Aug 29 03:22:35 AM UTC 24 |
4518029794 ps |
T748 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.663867060 |
|
|
Aug 29 03:22:21 AM UTC 24 |
Aug 29 03:22:37 AM UTC 24 |
469234660 ps |
T749 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.1168195744 |
|
|
Aug 29 03:22:28 AM UTC 24 |
Aug 29 03:22:39 AM UTC 24 |
446572514 ps |
T750 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.2530297693 |
|
|
Aug 29 03:22:36 AM UTC 24 |
Aug 29 03:22:40 AM UTC 24 |
211065892 ps |
T751 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.4028511222 |
|
|
Aug 29 03:20:52 AM UTC 24 |
Aug 29 03:22:51 AM UTC 24 |
18085015502 ps |
T752 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.3226229542 |
|
|
Aug 29 03:22:13 AM UTC 24 |
Aug 29 03:22:52 AM UTC 24 |
4398721710 ps |
T753 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.1617465484 |
|
|
Aug 29 03:22:41 AM UTC 24 |
Aug 29 03:22:53 AM UTC 24 |
2617226710 ps |
T754 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.1953007774 |
|
|
Aug 29 03:22:51 AM UTC 24 |
Aug 29 03:22:54 AM UTC 24 |
12213907 ps |
T755 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.1833950194 |
|
|
Aug 29 03:22:38 AM UTC 24 |
Aug 29 03:22:56 AM UTC 24 |
572283373 ps |
T756 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.279836170 |
|
|
Aug 29 03:22:57 AM UTC 24 |
Aug 29 03:22:59 AM UTC 24 |
48644875 ps |
T757 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.44441312 |
|
|
Aug 29 03:22:57 AM UTC 24 |
Aug 29 03:22:59 AM UTC 24 |
57115036 ps |
T758 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.1992248600 |
|
|
Aug 29 03:19:30 AM UTC 24 |
Aug 29 03:23:01 AM UTC 24 |
21879844973 ps |
T759 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.2533208465 |
|
|
Aug 29 03:23:00 AM UTC 24 |
Aug 29 03:23:03 AM UTC 24 |
26023296 ps |
T760 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.2517460615 |
|
|
Aug 29 03:23:01 AM UTC 24 |
Aug 29 03:23:04 AM UTC 24 |
11292464 ps |
T338 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.3307004061 |
|
|
Aug 29 03:20:01 AM UTC 24 |
Aug 29 03:23:06 AM UTC 24 |
26536761866 ps |
T761 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.2809933514 |
|
|
Aug 29 03:21:32 AM UTC 24 |
Aug 29 03:23:08 AM UTC 24 |
11237195864 ps |
T762 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.1441562556 |
|
|
Aug 29 03:22:54 AM UTC 24 |
Aug 29 03:23:08 AM UTC 24 |
547352419 ps |
T763 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.2065051701 |
|
|
Aug 29 03:22:14 AM UTC 24 |
Aug 29 03:23:09 AM UTC 24 |
3704211621 ps |
T764 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.667228451 |
|
|
Aug 29 03:20:09 AM UTC 24 |
Aug 29 03:23:10 AM UTC 24 |
74356023119 ps |
T765 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.2150600010 |
|
|
Aug 29 03:23:04 AM UTC 24 |
Aug 29 03:23:10 AM UTC 24 |
3958137127 ps |
T766 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.287394511 |
|
|
Aug 29 03:23:07 AM UTC 24 |
Aug 29 03:23:11 AM UTC 24 |
524218757 ps |
T767 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.3327596588 |
|
|
Aug 29 03:13:46 AM UTC 24 |
Aug 29 03:23:15 AM UTC 24 |
362850672150 ps |
T768 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.2374325668 |
|
|
Aug 29 03:23:00 AM UTC 24 |
Aug 29 03:23:16 AM UTC 24 |
7171517994 ps |
T769 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.2815483752 |
|
|
Aug 29 03:23:09 AM UTC 24 |
Aug 29 03:23:16 AM UTC 24 |
5315472523 ps |
T770 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1181574445 |
|
|
Aug 29 03:23:11 AM UTC 24 |
Aug 29 03:23:17 AM UTC 24 |
259353521 ps |
T771 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.1017448540 |
|
|
Aug 29 03:23:09 AM UTC 24 |
Aug 29 03:23:17 AM UTC 24 |
160090505 ps |
T772 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.182721759 |
|
|
Aug 29 03:23:16 AM UTC 24 |
Aug 29 03:23:18 AM UTC 24 |
139701427 ps |
T773 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.4266419853 |
|
|
Aug 29 03:23:17 AM UTC 24 |
Aug 29 03:23:20 AM UTC 24 |
62319877 ps |
T774 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.1563659779 |
|
|
Aug 29 03:23:19 AM UTC 24 |
Aug 29 03:23:21 AM UTC 24 |
59874844 ps |
T775 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.400831993 |
|
|
Aug 29 03:23:19 AM UTC 24 |
Aug 29 03:23:21 AM UTC 24 |
112989137 ps |
T776 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.2180646463 |
|
|
Aug 29 03:23:21 AM UTC 24 |
Aug 29 03:23:28 AM UTC 24 |
369867629 ps |
T777 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.3568492828 |
|
|
Aug 29 03:23:03 AM UTC 24 |
Aug 29 03:23:28 AM UTC 24 |
29846996235 ps |
T327 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.3039415388 |
|
|
Aug 29 03:21:36 AM UTC 24 |
Aug 29 03:23:29 AM UTC 24 |
11349924223 ps |
T778 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.2677576660 |
|
|
Aug 29 03:23:17 AM UTC 24 |
Aug 29 03:23:32 AM UTC 24 |
2402425430 ps |
T779 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.3141225576 |
|
|
Aug 29 03:23:33 AM UTC 24 |
Aug 29 03:23:35 AM UTC 24 |
268415343 ps |
T780 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.515946814 |
|
|
Aug 29 03:23:22 AM UTC 24 |
Aug 29 03:23:35 AM UTC 24 |
692037330 ps |
T781 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.3704808169 |
|
|
Aug 29 03:22:14 AM UTC 24 |
Aug 29 03:23:36 AM UTC 24 |
8885777251 ps |
T782 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.990353980 |
|
|
Aug 29 03:23:30 AM UTC 24 |
Aug 29 03:23:36 AM UTC 24 |
114819449 ps |
T783 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.3026156405 |
|
|
Aug 29 03:23:22 AM UTC 24 |
Aug 29 03:23:37 AM UTC 24 |
2974080958 ps |
T784 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.877519645 |
|
|
Aug 29 03:24:22 AM UTC 24 |
Aug 29 03:24:35 AM UTC 24 |
4116966597 ps |
T785 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.2411659779 |
|
|
Aug 29 03:24:32 AM UTC 24 |
Aug 29 03:24:36 AM UTC 24 |
119581880 ps |
T323 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.1365620241 |
|
|
Aug 29 03:23:21 AM UTC 24 |
Aug 29 03:23:38 AM UTC 24 |
8695550038 ps |
T786 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.1374972645 |
|
|
Aug 29 03:23:21 AM UTC 24 |
Aug 29 03:23:38 AM UTC 24 |
1189962145 ps |
T787 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.378692282 |
|
|
Aug 29 03:23:36 AM UTC 24 |
Aug 29 03:23:38 AM UTC 24 |
240229396 ps |
T788 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.2710994185 |
|
|
Aug 29 03:22:33 AM UTC 24 |
Aug 29 03:23:39 AM UTC 24 |
39350732688 ps |
T789 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.982349348 |
|
|
Aug 29 03:20:53 AM UTC 24 |
Aug 29 03:23:39 AM UTC 24 |
23142025022 ps |
T790 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.602627949 |
|
|
Aug 29 03:23:37 AM UTC 24 |
Aug 29 03:23:39 AM UTC 24 |
294296128 ps |
T791 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.1015907185 |
|
|
Aug 29 03:23:37 AM UTC 24 |
Aug 29 03:23:39 AM UTC 24 |
55500348 ps |
T792 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.4079319919 |
|
|
Aug 29 03:23:23 AM UTC 24 |
Aug 29 03:23:40 AM UTC 24 |
1481117158 ps |
T793 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.1708286170 |
|
|
Aug 29 03:23:07 AM UTC 24 |
Aug 29 03:23:40 AM UTC 24 |
7449423054 ps |
T794 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.4006358377 |
|
|
Aug 29 03:23:39 AM UTC 24 |
Aug 29 03:23:42 AM UTC 24 |
55148438 ps |
T795 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.1868285003 |
|
|
Aug 29 03:23:10 AM UTC 24 |
Aug 29 03:23:43 AM UTC 24 |
1029881400 ps |
T796 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.1064920936 |
|
|
Aug 29 03:19:00 AM UTC 24 |
Aug 29 03:23:44 AM UTC 24 |
78649347560 ps |
T797 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.817926231 |
|
|
Aug 29 03:23:39 AM UTC 24 |
Aug 29 03:23:44 AM UTC 24 |
2833811925 ps |
T798 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.362661581 |
|
|
Aug 29 03:23:41 AM UTC 24 |
Aug 29 03:23:45 AM UTC 24 |
286037272 ps |
T799 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.3485302414 |
|
|
Aug 29 03:22:31 AM UTC 24 |
Aug 29 03:23:47 AM UTC 24 |
24580383623 ps |
T800 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.106449890 |
|
|
Aug 29 03:23:45 AM UTC 24 |
Aug 29 03:23:47 AM UTC 24 |
11226954 ps |
T801 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.2816002481 |
|
|
Aug 29 03:23:08 AM UTC 24 |
Aug 29 03:23:47 AM UTC 24 |
5515266063 ps |
T802 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.2593361528 |
|
|
Aug 29 03:23:41 AM UTC 24 |
Aug 29 03:23:48 AM UTC 24 |
233830867 ps |
T803 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.228103194 |
|
|
Aug 29 03:23:29 AM UTC 24 |
Aug 29 03:23:50 AM UTC 24 |
5382878432 ps |
T804 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.3058435256 |
|
|
Aug 29 03:23:49 AM UTC 24 |
Aug 29 03:23:51 AM UTC 24 |
14012843 ps |
T805 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.1848204845 |
|
|
Aug 29 03:23:49 AM UTC 24 |
Aug 29 03:23:51 AM UTC 24 |
57996953 ps |
T806 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.1651093613 |
|
|
Aug 29 03:23:00 AM UTC 24 |
Aug 29 03:23:51 AM UTC 24 |
33651599629 ps |
T807 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.2952920758 |
|
|
Aug 29 03:23:43 AM UTC 24 |
Aug 29 03:23:53 AM UTC 24 |
4183586665 ps |
T808 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.3490585835 |
|
|
Aug 29 03:23:44 AM UTC 24 |
Aug 29 03:23:54 AM UTC 24 |
230674919 ps |
T809 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.4061387988 |
|
|
Aug 29 03:23:45 AM UTC 24 |
Aug 29 03:23:54 AM UTC 24 |
1269943654 ps |
T810 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.4054264977 |
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|
Aug 29 03:23:52 AM UTC 24 |
Aug 29 03:23:54 AM UTC 24 |
17688944 ps |
T811 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.3807404598 |
|
|
Aug 29 03:23:51 AM UTC 24 |
Aug 29 03:23:55 AM UTC 24 |
488971999 ps |
T812 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.850239478 |
|
|
Aug 29 03:23:38 AM UTC 24 |
Aug 29 03:23:55 AM UTC 24 |
1622265079 ps |
T813 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.3099618559 |
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|
Aug 29 03:23:52 AM UTC 24 |
Aug 29 03:23:56 AM UTC 24 |
181981919 ps |
T814 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.1891929787 |
|
|
Aug 29 03:23:52 AM UTC 24 |
Aug 29 03:23:58 AM UTC 24 |
1622023026 ps |
T815 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.1938340035 |
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|
Aug 29 03:23:42 AM UTC 24 |
Aug 29 03:23:59 AM UTC 24 |
1262457710 ps |
T816 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.3640476155 |
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|
Aug 29 03:23:57 AM UTC 24 |
Aug 29 03:24:01 AM UTC 24 |
216144393 ps |
T817 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.1379487946 |
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|
Aug 29 03:23:18 AM UTC 24 |
Aug 29 03:24:02 AM UTC 24 |
44850284391 ps |
T319 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.2800525628 |
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|
Aug 29 03:20:54 AM UTC 24 |
Aug 29 03:24:03 AM UTC 24 |
10914853727 ps |
T818 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.844029127 |
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|
Aug 29 03:23:41 AM UTC 24 |
Aug 29 03:24:04 AM UTC 24 |
2431686835 ps |
T819 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.3697831239 |
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|
Aug 29 03:23:54 AM UTC 24 |
Aug 29 03:24:04 AM UTC 24 |
279058154 ps |
T820 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.2377504455 |
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|
Aug 29 03:24:05 AM UTC 24 |
Aug 29 03:24:07 AM UTC 24 |
60543239 ps |
T821 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.1355971746 |
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|
Aug 29 03:24:05 AM UTC 24 |
Aug 29 03:24:08 AM UTC 24 |
18667380 ps |
T822 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.2567490922 |
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|
Aug 29 03:23:57 AM UTC 24 |
Aug 29 03:24:09 AM UTC 24 |
907943365 ps |
T823 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3228015452 |
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|
Aug 29 03:24:09 AM UTC 24 |
Aug 29 03:24:11 AM UTC 24 |
23187829 ps |
T314 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.2863278355 |
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|
Aug 29 03:23:36 AM UTC 24 |
Aug 29 03:24:11 AM UTC 24 |
15001100018 ps |
T824 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.411304413 |
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|
Aug 29 03:24:10 AM UTC 24 |
Aug 29 03:24:12 AM UTC 24 |
22901890 ps |
T825 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.3487432877 |
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|
Aug 29 03:23:54 AM UTC 24 |
Aug 29 03:24:18 AM UTC 24 |
3749069578 ps |
T826 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.2173159493 |
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|
Aug 29 03:24:00 AM UTC 24 |
Aug 29 03:24:21 AM UTC 24 |
1590227045 ps |
T827 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.2040097375 |
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|
Aug 29 03:23:36 AM UTC 24 |
Aug 29 03:24:21 AM UTC 24 |
11197368897 ps |