Line Coverage for Module :
prim_fifo_async
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| ALWAYS | 59 | 4 | 4 | 100.00 |
| ALWAYS | 68 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| ALWAYS | 92 | 4 | 4 | 100.00 |
| ALWAYS | 101 | 4 | 4 | 100.00 |
| ALWAYS | 117 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
| ALWAYS | 182 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 207 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 276 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 277 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
52
53 1/1 assign fifo_incr_wptr = wvalid_i & wready_o;
Tests: T1 T2 T3
54
55 // decimal version
56 1/1 assign fifo_wptr_d = fifo_wptr_q + PTR_WIDTH'(1'b1);
Tests: T1 T2 T3
57
58 always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
59 1/1 if (!rst_wr_ni) begin
Tests: T1 T2 T3
60 1/1 fifo_wptr_q <= '0;
Tests: T1 T2 T3
61 1/1 end else if (fifo_incr_wptr) begin
Tests: T1 T2 T3
62 1/1 fifo_wptr_q <= fifo_wptr_d;
Tests: T1 T4 T5
63 end
MISSING_ELSE
64 end
65
66 // gray-coded version
67 always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
68 1/1 if (!rst_wr_ni) begin
Tests: T1 T2 T3
69 1/1 fifo_wptr_gray_q <= '0;
Tests: T1 T2 T3
70 1/1 end else if (fifo_incr_wptr) begin
Tests: T1 T2 T3
71 1/1 fifo_wptr_gray_q <= fifo_wptr_gray_d;
Tests: T1 T4 T5
72 end
MISSING_ELSE
73 end
74
75 // sync gray-coded pointer to read clk
76 prim_flop_2sync #(.Width(PTR_WIDTH)) sync_wptr (
77 .clk_i (clk_rd_i),
78 .rst_ni (rst_rd_ni),
79 .d_i (fifo_wptr_gray_q),
80 .q_o (fifo_wptr_gray_sync));
81
82 //////////////////
83 // Read Pointer //
84 //////////////////
85
86 1/1 assign fifo_incr_rptr = rvalid_o & rready_i;
Tests: T1 T2 T3
87
88 // decimal version
89 1/1 assign fifo_rptr_d = fifo_rptr_q + PTR_WIDTH'(1'b1);
Tests: T1 T2 T3
90
91 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
92 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
93 1/1 fifo_rptr_q <= '0;
Tests: T1 T2 T3
94 1/1 end else if (fifo_incr_rptr) begin
Tests: T1 T2 T3
95 1/1 fifo_rptr_q <= fifo_rptr_d;
Tests: T1 T4 T5
96 end
MISSING_ELSE
97 end
98
99 // gray-coded version
100 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
101 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
102 1/1 fifo_rptr_gray_q <= '0;
Tests: T1 T2 T3
103 1/1 end else if (fifo_incr_rptr) begin
Tests: T1 T2 T3
104 1/1 fifo_rptr_gray_q <= fifo_rptr_gray_d;
Tests: T1 T4 T5
105 end
MISSING_ELSE
106 end
107
108 // sync gray-coded pointer to write clk
109 prim_flop_2sync #(.Width(PTR_WIDTH)) sync_rptr (
110 .clk_i (clk_wr_i),
111 .rst_ni (rst_wr_ni),
112 .d_i (fifo_rptr_gray_q),
113 .q_o (fifo_rptr_gray_sync));
114
115 // Registered version of synced read pointer
116 always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
117 1/1 if (!rst_wr_ni) begin
Tests: T1 T2 T3
118 1/1 fifo_rptr_sync_q <= '0;
Tests: T1 T2 T3
119 end else begin
120 1/1 fifo_rptr_sync_q <= fifo_rptr_sync_combi;
Tests: T1 T2 T3
121 end
122 end
123
124 //////////////////
125 // Empty / Full //
126 //////////////////
127
128 logic [PTR_WIDTH-1:0] xor_mask;
129 assign xor_mask = PTR_WIDTH'(1'b1) << (PTR_WIDTH-1);
130 1/1 assign full_wclk = (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask));
Tests: T1 T2 T3
131 1/1 assign full_rclk = (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask));
Tests: T1 T2 T3
132 1/1 assign empty_rclk = (fifo_wptr_sync_combi == fifo_rptr_q);
Tests: T1 T2 T3
133
134 if (Depth > 1) begin : g_depth_calc
135
136 // Current depth in the write clock side
137 logic wptr_msb;
138 logic rptr_sync_msb;
139 logic [PTRV_W-1:0] wptr_value;
140 logic [PTRV_W-1:0] rptr_sync_value;
141
142 1/1 assign wptr_msb = fifo_wptr_q[PTR_WIDTH-1];
Tests: T1 T2 T3
143 1/1 assign rptr_sync_msb = fifo_rptr_sync_q[PTR_WIDTH-1];
Tests: T1 T2 T3
144 1/1 assign wptr_value = fifo_wptr_q[0+:PTRV_W];
Tests: T1 T2 T3
145 1/1 assign rptr_sync_value = fifo_rptr_sync_q[0+:PTRV_W];
Tests: T1 T2 T3
146 1/1 assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
Tests: T1 T2 T3
147 (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
148 (DepthW'(Depth) - DepthW'(rptr_sync_value) + DepthW'(wptr_value)) ;
149
150 // Current depth in the read clock side
151 logic rptr_msb;
152 logic wptr_sync_msb;
153 logic [PTRV_W-1:0] rptr_value;
154 logic [PTRV_W-1:0] wptr_sync_value;
155
156 1/1 assign wptr_sync_msb = fifo_wptr_sync_combi[PTR_WIDTH-1];
Tests: T1 T2 T3
157 1/1 assign rptr_msb = fifo_rptr_q[PTR_WIDTH-1];
Tests: T1 T2 T3
158 1/1 assign wptr_sync_value = fifo_wptr_sync_combi[0+:PTRV_W];
Tests: T1 T2 T3
159 1/1 assign rptr_value = fifo_rptr_q[0+:PTRV_W];
Tests: T1 T2 T3
160 1/1 assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
Tests: T1 T2 T3
161 (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
162 (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_sync_value)) ;
163
164 end else begin : g_no_depth_calc
165
166 assign rdepth_o = full_rclk;
167 assign wdepth_o = full_wclk;
168
169 end
170
171 1/1 assign wready_o = ~full_wclk;
Tests: T1 T2 T3
172 1/1 assign rvalid_o = ~empty_rclk;
Tests: T1 T2 T3
173
174 /////////////
175 // Storage //
176 /////////////
177
178 logic [Width-1:0] rdata_int;
179 if (Depth > 1) begin : g_storage_mux
180
181 always_ff @(posedge clk_wr_i) begin
182 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
183 1/1 storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
Tests: T1 T4 T5
184 end
MISSING_ELSE
185 end
186
187 1/1 assign rdata_int = storage[fifo_rptr_q[PTRV_W-1:0]];
Tests: T1 T2 T3
188
189 end else begin : g_storage_simple
190
191 always_ff @(posedge clk_wr_i) begin
192 if (fifo_incr_wptr) begin
193 storage[0] <= wdata_i;
194 end
195 end
196
197 assign rdata_int = storage[0];
198
199 end
200
201 // rdata_o is qualified with rvalid_o to avoid CDC error
202 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
203 if (OutputZeroIfInvalid == 1'b1) begin : gen_invalid_zero
204 assign rdata_o = empty_rclk ? '0 : (rvalid_o ? rdata_int : '0);
205 end
206 else begin : gen_invalid_non_zero
207 1/1 assign rdata_o = empty_rclk ? '0 : rdata_int;
Tests: T1 T2 T3
208 end
209 end else begin : gen_no_output_zero
210 if (OutputZeroIfInvalid == 1'b1) begin : gen_invalid_zero
211 assign rdata_o = rvalid_o ? rdata_int : '0;
212 end
213 else begin : gen_invalid_non_zero
214 assign rdata_o = rdata_int;
215 end
216 end
217
218 //////////////////////////////////////
219 // Decimal <-> Gray-code Conversion //
220 //////////////////////////////////////
221
222 // This code is all in a generate context to avoid lint errors when Depth <= 2
223 if (Depth > 2) begin : g_full_gray_conversion
224
225 function automatic [PTR_WIDTH-1:0] dec2gray(input logic [PTR_WIDTH-1:0] decval);
226 logic [PTR_WIDTH-1:0] decval_sub;
227 logic [PTR_WIDTH-1:0] decval_in;
228 logic unused_decval_msb;
229
230 decval_sub = (PTR_WIDTH)'(Depth) - {1'b0, decval[PTR_WIDTH-2:0]} - 1'b1;
231
232 decval_in = decval[PTR_WIDTH-1] ? decval_sub : decval;
233
234 // We do not care about the MSB, hence we mask it out
235 unused_decval_msb = decval_in[PTR_WIDTH-1];
236 decval_in[PTR_WIDTH-1] = 1'b0;
237
238 // Perform the XOR conversion
239 dec2gray = decval_in;
240 dec2gray ^= (decval_in >> 1);
241
242 // Override the MSB
243 dec2gray[PTR_WIDTH-1] = decval[PTR_WIDTH-1];
244 endfunction
245
246 // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
247 function automatic [PTR_WIDTH-1:0] gray2dec(input logic [PTR_WIDTH-1:0] grayval);
248 logic [PTR_WIDTH-1:0] dec_tmp, dec_tmp_sub;
249 logic unused_decsub_msb;
250
251 dec_tmp = '0;
252 for (int i = PTR_WIDTH-2; i >= 0; i--) begin
253 dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
254 end
255 dec_tmp_sub = (PTR_WIDTH)'(Depth) - dec_tmp - 1'b1;
256 if (grayval[PTR_WIDTH-1]) begin
257 gray2dec = dec_tmp_sub;
258 // Override MSB
259 gray2dec[PTR_WIDTH-1] = 1'b1;
260 unused_decsub_msb = dec_tmp_sub[PTR_WIDTH-1];
261 end else begin
262 gray2dec = dec_tmp;
263 end
264 endfunction
265
266 // decimal version of read pointer in write domain
267 assign fifo_rptr_sync_combi = gray2dec(fifo_rptr_gray_sync);
268 // decimal version of write pointer in read domain
269 assign fifo_wptr_sync_combi = gray2dec(fifo_wptr_gray_sync);
270
271 assign fifo_rptr_gray_d = dec2gray(fifo_rptr_d);
272 assign fifo_wptr_gray_d = dec2gray(fifo_wptr_d);
273
274 end else if (Depth == 2) begin : g_simple_gray_conversion
275
276 1/1 assign fifo_rptr_sync_combi = {fifo_rptr_gray_sync[PTR_WIDTH-1], ^fifo_rptr_gray_sync};
Tests: T1 T2 T3
277 1/1 assign fifo_wptr_sync_combi = {fifo_wptr_gray_sync[PTR_WIDTH-1], ^fifo_wptr_gray_sync};
Tests: T1 T2 T3
278
279 1/1 assign fifo_rptr_gray_d = {fifo_rptr_d[PTR_WIDTH-1], ^fifo_rptr_d};
Tests: T1 T2 T3
280 1/1 assign fifo_wptr_gray_d = {fifo_wptr_d[PTR_WIDTH-1], ^fifo_wptr_d};
Tests: T1 T2 T3
Cond Coverage for Module :
prim_fifo_async ( parameter Width=24,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 25 | 24 | 96.00 |
| Logical | 25 | 24 | 96.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T5,T7 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T1,T5,T7 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T118,T119,T120 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T121,T122,T85 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION
Number Term
1 full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T118,T119,T120 |
LINE 146
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T5,T7 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T5,T7 |
| 1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION
Number Term
1 full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T121,T122,T85 |
LINE 160
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T5,T7 |
| 1 | Covered | T1,T2,T3 |
LINE 160
SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T5,T7 |
| 1 | Covered | T1,T2,T3 |
LINE 207
EXPRESSION (empty_rclk ? '0 : rdata_int)
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T5,T7 |
| 1 | Covered | T1,T2,T3 |
Cond Coverage for Module :
prim_fifo_async ( parameter Width=32,Depth=2,OutputZeroIfEmpty=1,OutputZeroIfInvalid=0,DepthW=2,PTRV_W=1,PTR_WIDTH=2 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 26 | 20 | 76.92 |
| Logical | 26 | 20 | 76.92 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T4,T6,T27 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T4,T6,T27 |
| 1 | 1 | Covered | T4,T6,T27 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION
Number Term
1 full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 146
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T6,T27 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T6,T27 |
| 1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION
Number Term
1 full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 160
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T6,T27 |
| 1 | Covered | T1,T2,T3 |
LINE 160
SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T6,T27 |
| 1 | Covered | T1,T2,T3 |
LINE 207
EXPRESSION (empty_rclk ? '0 : rdata_int)
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T6,T27 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Module :
prim_fifo_async
| Line No. | Total | Covered | Percent |
| Branches |
|
24 |
24 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
160 |
3 |
3 |
100.00 |
| TERNARY |
207 |
2 |
2 |
100.00 |
| IF |
59 |
3 |
3 |
100.00 |
| IF |
68 |
3 |
3 |
100.00 |
| IF |
92 |
3 |
3 |
100.00 |
| IF |
101 |
3 |
3 |
100.00 |
| IF |
117 |
2 |
2 |
100.00 |
| IF |
182 |
2 |
2 |
100.00 |
146 assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
-1-
==>
147 (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T118,T119,T120 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T4,T5 |
160 assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
-1-
==>
161 (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T121,T122,T85 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T4,T5 |
207 assign rdata_o = empty_rclk ? '0 : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T4,T5 |
59 if (!rst_wr_ni) begin
-1-
60 fifo_wptr_q <= '0;
==>
61 end else if (fifo_incr_wptr) begin
-2-
62 fifo_wptr_q <= fifo_wptr_d;
==>
63 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
68 if (!rst_wr_ni) begin
-1-
69 fifo_wptr_gray_q <= '0;
==>
70 end else if (fifo_incr_wptr) begin
-2-
71 fifo_wptr_gray_q <= fifo_wptr_gray_d;
==>
72 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
92 if (!rst_rd_ni) begin
-1-
93 fifo_rptr_q <= '0;
==>
94 end else if (fifo_incr_rptr) begin
-2-
95 fifo_rptr_q <= fifo_rptr_d;
==>
96 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
101 if (!rst_rd_ni) begin
-1-
102 fifo_rptr_gray_q <= '0;
==>
103 end else if (fifo_incr_rptr) begin
-2-
104 fifo_rptr_gray_q <= fifo_rptr_gray_d;
==>
105 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T4,T5 |
| 0 |
0 |
Covered |
T1,T2,T3 |
117 if (!rst_wr_ni) begin
-1-
118 fifo_rptr_sync_q <= '0;
==>
119 end else begin
120 fifo_rptr_sync_q <= fifo_rptr_sync_combi;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
182 if (fifo_incr_wptr) begin
-1-
183 storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
==>
184 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_fifo_async
Assertion Details
GrayRptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
626944160 |
626855151 |
0 |
0 |
| T1 |
46165 |
46085 |
0 |
0 |
| T2 |
1597 |
1498 |
0 |
0 |
| T3 |
23447 |
23382 |
0 |
0 |
| T4 |
35387 |
35297 |
0 |
0 |
| T5 |
20902 |
20803 |
0 |
0 |
| T6 |
252929 |
252859 |
0 |
0 |
| T7 |
52915 |
52856 |
0 |
0 |
| T8 |
32725 |
32656 |
0 |
0 |
| T9 |
35846 |
35794 |
0 |
0 |
| T10 |
84079 |
84018 |
0 |
0 |
| T11 |
8976 |
8975 |
0 |
0 |
GrayWptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
626944160 |
626855151 |
0 |
0 |
| T1 |
46165 |
46085 |
0 |
0 |
| T2 |
1597 |
1498 |
0 |
0 |
| T3 |
23447 |
23382 |
0 |
0 |
| T4 |
35387 |
35297 |
0 |
0 |
| T5 |
20902 |
20803 |
0 |
0 |
| T6 |
252929 |
252859 |
0 |
0 |
| T7 |
52915 |
52856 |
0 |
0 |
| T8 |
32725 |
32656 |
0 |
0 |
| T9 |
35846 |
35794 |
0 |
0 |
| T10 |
84079 |
84018 |
0 |
0 |
| T11 |
8976 |
8975 |
0 |
0 |
ParamCheckDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
1894 |
1894 |
0 |
0 |
| T1 |
2 |
2 |
0 |
0 |
| T2 |
2 |
2 |
0 |
0 |
| T3 |
2 |
2 |
0 |
0 |
| T4 |
2 |
2 |
0 |
0 |
| T5 |
2 |
2 |
0 |
0 |
| T6 |
2 |
2 |
0 |
0 |
| T7 |
2 |
2 |
0 |
0 |
| T8 |
2 |
2 |
0 |
0 |
| T9 |
2 |
2 |
0 |
0 |
| T10 |
2 |
2 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| ALWAYS | 59 | 4 | 4 | 100.00 |
| ALWAYS | 68 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| ALWAYS | 92 | 4 | 4 | 100.00 |
| ALWAYS | 101 | 4 | 4 | 100.00 |
| ALWAYS | 117 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
| ALWAYS | 182 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 207 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 276 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 277 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
52
53 1/1 assign fifo_incr_wptr = wvalid_i & wready_o;
Tests: T1 T2 T3
54
55 // decimal version
56 1/1 assign fifo_wptr_d = fifo_wptr_q + PTR_WIDTH'(1'b1);
Tests: T1 T2 T3
57
58 always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
59 1/1 if (!rst_wr_ni) begin
Tests: T1 T2 T3
60 1/1 fifo_wptr_q <= '0;
Tests: T1 T2 T3
61 1/1 end else if (fifo_incr_wptr) begin
Tests: T1 T3 T4
62 1/1 fifo_wptr_q <= fifo_wptr_d;
Tests: T4 T6 T27
63 end
MISSING_ELSE
64 end
65
66 // gray-coded version
67 always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
68 1/1 if (!rst_wr_ni) begin
Tests: T1 T2 T3
69 1/1 fifo_wptr_gray_q <= '0;
Tests: T1 T2 T3
70 1/1 end else if (fifo_incr_wptr) begin
Tests: T1 T3 T4
71 1/1 fifo_wptr_gray_q <= fifo_wptr_gray_d;
Tests: T4 T6 T27
72 end
MISSING_ELSE
73 end
74
75 // sync gray-coded pointer to read clk
76 prim_flop_2sync #(.Width(PTR_WIDTH)) sync_wptr (
77 .clk_i (clk_rd_i),
78 .rst_ni (rst_rd_ni),
79 .d_i (fifo_wptr_gray_q),
80 .q_o (fifo_wptr_gray_sync));
81
82 //////////////////
83 // Read Pointer //
84 //////////////////
85
86 1/1 assign fifo_incr_rptr = rvalid_o & rready_i;
Tests: T1 T2 T3
87
88 // decimal version
89 1/1 assign fifo_rptr_d = fifo_rptr_q + PTR_WIDTH'(1'b1);
Tests: T1 T2 T3
90
91 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
92 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
93 1/1 fifo_rptr_q <= '0;
Tests: T1 T2 T3
94 1/1 end else if (fifo_incr_rptr) begin
Tests: T1 T2 T3
95 1/1 fifo_rptr_q <= fifo_rptr_d;
Tests: T4 T6 T27
96 end
MISSING_ELSE
97 end
98
99 // gray-coded version
100 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
101 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
102 1/1 fifo_rptr_gray_q <= '0;
Tests: T1 T2 T3
103 1/1 end else if (fifo_incr_rptr) begin
Tests: T1 T2 T3
104 1/1 fifo_rptr_gray_q <= fifo_rptr_gray_d;
Tests: T4 T6 T27
105 end
MISSING_ELSE
106 end
107
108 // sync gray-coded pointer to write clk
109 prim_flop_2sync #(.Width(PTR_WIDTH)) sync_rptr (
110 .clk_i (clk_wr_i),
111 .rst_ni (rst_wr_ni),
112 .d_i (fifo_rptr_gray_q),
113 .q_o (fifo_rptr_gray_sync));
114
115 // Registered version of synced read pointer
116 always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
117 1/1 if (!rst_wr_ni) begin
Tests: T1 T2 T3
118 1/1 fifo_rptr_sync_q <= '0;
Tests: T1 T2 T3
119 end else begin
120 1/1 fifo_rptr_sync_q <= fifo_rptr_sync_combi;
Tests: T1 T3 T4
121 end
122 end
123
124 //////////////////
125 // Empty / Full //
126 //////////////////
127
128 logic [PTR_WIDTH-1:0] xor_mask;
129 assign xor_mask = PTR_WIDTH'(1'b1) << (PTR_WIDTH-1);
130 1/1 assign full_wclk = (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask));
Tests: T1 T2 T3
131 1/1 assign full_rclk = (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask));
Tests: T1 T2 T3
132 1/1 assign empty_rclk = (fifo_wptr_sync_combi == fifo_rptr_q);
Tests: T1 T2 T3
133
134 if (Depth > 1) begin : g_depth_calc
135
136 // Current depth in the write clock side
137 logic wptr_msb;
138 logic rptr_sync_msb;
139 logic [PTRV_W-1:0] wptr_value;
140 logic [PTRV_W-1:0] rptr_sync_value;
141
142 1/1 assign wptr_msb = fifo_wptr_q[PTR_WIDTH-1];
Tests: T1 T2 T3
143 1/1 assign rptr_sync_msb = fifo_rptr_sync_q[PTR_WIDTH-1];
Tests: T1 T2 T3
144 1/1 assign wptr_value = fifo_wptr_q[0+:PTRV_W];
Tests: T1 T2 T3
145 1/1 assign rptr_sync_value = fifo_rptr_sync_q[0+:PTRV_W];
Tests: T1 T2 T3
146 1/1 assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
Tests: T1 T2 T3
147 (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
148 (DepthW'(Depth) - DepthW'(rptr_sync_value) + DepthW'(wptr_value)) ;
149
150 // Current depth in the read clock side
151 logic rptr_msb;
152 logic wptr_sync_msb;
153 logic [PTRV_W-1:0] rptr_value;
154 logic [PTRV_W-1:0] wptr_sync_value;
155
156 1/1 assign wptr_sync_msb = fifo_wptr_sync_combi[PTR_WIDTH-1];
Tests: T1 T2 T3
157 1/1 assign rptr_msb = fifo_rptr_q[PTR_WIDTH-1];
Tests: T1 T2 T3
158 1/1 assign wptr_sync_value = fifo_wptr_sync_combi[0+:PTRV_W];
Tests: T1 T2 T3
159 1/1 assign rptr_value = fifo_rptr_q[0+:PTRV_W];
Tests: T1 T2 T3
160 1/1 assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
Tests: T1 T2 T3
161 (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
162 (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_sync_value)) ;
163
164 end else begin : g_no_depth_calc
165
166 assign rdepth_o = full_rclk;
167 assign wdepth_o = full_wclk;
168
169 end
170
171 1/1 assign wready_o = ~full_wclk;
Tests: T1 T2 T3
172 1/1 assign rvalid_o = ~empty_rclk;
Tests: T1 T2 T3
173
174 /////////////
175 // Storage //
176 /////////////
177
178 logic [Width-1:0] rdata_int;
179 if (Depth > 1) begin : g_storage_mux
180
181 always_ff @(posedge clk_wr_i) begin
182 1/1 if (fifo_incr_wptr) begin
Tests: T1 T3 T4
183 1/1 storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
Tests: T4 T6 T27
184 end
MISSING_ELSE
185 end
186
187 1/1 assign rdata_int = storage[fifo_rptr_q[PTRV_W-1:0]];
Tests: T1 T2 T3
188
189 end else begin : g_storage_simple
190
191 always_ff @(posedge clk_wr_i) begin
192 if (fifo_incr_wptr) begin
193 storage[0] <= wdata_i;
194 end
195 end
196
197 assign rdata_int = storage[0];
198
199 end
200
201 // rdata_o is qualified with rvalid_o to avoid CDC error
202 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
203 if (OutputZeroIfInvalid == 1'b1) begin : gen_invalid_zero
204 assign rdata_o = empty_rclk ? '0 : (rvalid_o ? rdata_int : '0);
205 end
206 else begin : gen_invalid_non_zero
207 1/1 assign rdata_o = empty_rclk ? '0 : rdata_int;
Tests: T1 T2 T3
208 end
209 end else begin : gen_no_output_zero
210 if (OutputZeroIfInvalid == 1'b1) begin : gen_invalid_zero
211 assign rdata_o = rvalid_o ? rdata_int : '0;
212 end
213 else begin : gen_invalid_non_zero
214 assign rdata_o = rdata_int;
215 end
216 end
217
218 //////////////////////////////////////
219 // Decimal <-> Gray-code Conversion //
220 //////////////////////////////////////
221
222 // This code is all in a generate context to avoid lint errors when Depth <= 2
223 if (Depth > 2) begin : g_full_gray_conversion
224
225 function automatic [PTR_WIDTH-1:0] dec2gray(input logic [PTR_WIDTH-1:0] decval);
226 logic [PTR_WIDTH-1:0] decval_sub;
227 logic [PTR_WIDTH-1:0] decval_in;
228 logic unused_decval_msb;
229
230 decval_sub = (PTR_WIDTH)'(Depth) - {1'b0, decval[PTR_WIDTH-2:0]} - 1'b1;
231
232 decval_in = decval[PTR_WIDTH-1] ? decval_sub : decval;
233
234 // We do not care about the MSB, hence we mask it out
235 unused_decval_msb = decval_in[PTR_WIDTH-1];
236 decval_in[PTR_WIDTH-1] = 1'b0;
237
238 // Perform the XOR conversion
239 dec2gray = decval_in;
240 dec2gray ^= (decval_in >> 1);
241
242 // Override the MSB
243 dec2gray[PTR_WIDTH-1] = decval[PTR_WIDTH-1];
244 endfunction
245
246 // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
247 function automatic [PTR_WIDTH-1:0] gray2dec(input logic [PTR_WIDTH-1:0] grayval);
248 logic [PTR_WIDTH-1:0] dec_tmp, dec_tmp_sub;
249 logic unused_decsub_msb;
250
251 dec_tmp = '0;
252 for (int i = PTR_WIDTH-2; i >= 0; i--) begin
253 dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
254 end
255 dec_tmp_sub = (PTR_WIDTH)'(Depth) - dec_tmp - 1'b1;
256 if (grayval[PTR_WIDTH-1]) begin
257 gray2dec = dec_tmp_sub;
258 // Override MSB
259 gray2dec[PTR_WIDTH-1] = 1'b1;
260 unused_decsub_msb = dec_tmp_sub[PTR_WIDTH-1];
261 end else begin
262 gray2dec = dec_tmp;
263 end
264 endfunction
265
266 // decimal version of read pointer in write domain
267 assign fifo_rptr_sync_combi = gray2dec(fifo_rptr_gray_sync);
268 // decimal version of write pointer in read domain
269 assign fifo_wptr_sync_combi = gray2dec(fifo_wptr_gray_sync);
270
271 assign fifo_rptr_gray_d = dec2gray(fifo_rptr_d);
272 assign fifo_wptr_gray_d = dec2gray(fifo_wptr_d);
273
274 end else if (Depth == 2) begin : g_simple_gray_conversion
275
276 1/1 assign fifo_rptr_sync_combi = {fifo_rptr_gray_sync[PTR_WIDTH-1], ^fifo_rptr_gray_sync};
Tests: T1 T2 T3
277 1/1 assign fifo_wptr_sync_combi = {fifo_wptr_gray_sync[PTR_WIDTH-1], ^fifo_wptr_gray_sync};
Tests: T1 T2 T3
278
279 1/1 assign fifo_rptr_gray_d = {fifo_rptr_d[PTR_WIDTH-1], ^fifo_rptr_d};
Tests: T1 T2 T3
280 1/1 assign fifo_wptr_gray_d = {fifo_wptr_d[PTR_WIDTH-1], ^fifo_wptr_d};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer
| Total | Covered | Percent |
|---|
| Conditions | 26 | 20 | 76.92 |
| Logical | 26 | 20 | 76.92 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T4,T6,T27 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T4,T6,T27 |
| 1 | 1 | Covered | T4,T6,T27 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION
Number Term
1 full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 146
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T6,T27 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T6,T27 |
| 1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION
Number Term
1 full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 160
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T6,T27 |
| 1 | Covered | T1,T2,T3 |
LINE 160
SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T6,T27 |
| 1 | Covered | T1,T2,T3 |
LINE 207
EXPRESSION (empty_rclk ? '0 : rdata_int)
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T6,T27 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer
| Line No. | Total | Covered | Percent |
| Branches |
|
24 |
22 |
91.67 |
| TERNARY |
146 |
3 |
2 |
66.67 |
| TERNARY |
160 |
3 |
2 |
66.67 |
| TERNARY |
207 |
2 |
2 |
100.00 |
| IF |
59 |
3 |
3 |
100.00 |
| IF |
68 |
3 |
3 |
100.00 |
| IF |
92 |
3 |
3 |
100.00 |
| IF |
101 |
3 |
3 |
100.00 |
| IF |
117 |
2 |
2 |
100.00 |
| IF |
182 |
2 |
2 |
100.00 |
146 assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
-1-
==>
147 (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T4,T6,T27 |
160 assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
-1-
==>
161 (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Not Covered |
|
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T4,T6,T27 |
207 assign rdata_o = empty_rclk ? '0 : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T4,T6,T27 |
59 if (!rst_wr_ni) begin
-1-
60 fifo_wptr_q <= '0;
==>
61 end else if (fifo_incr_wptr) begin
-2-
62 fifo_wptr_q <= fifo_wptr_d;
==>
63 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T4,T6,T27 |
| 0 |
0 |
Covered |
T1,T3,T4 |
68 if (!rst_wr_ni) begin
-1-
69 fifo_wptr_gray_q <= '0;
==>
70 end else if (fifo_incr_wptr) begin
-2-
71 fifo_wptr_gray_q <= fifo_wptr_gray_d;
==>
72 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T4,T6,T27 |
| 0 |
0 |
Covered |
T1,T3,T4 |
92 if (!rst_rd_ni) begin
-1-
93 fifo_rptr_q <= '0;
==>
94 end else if (fifo_incr_rptr) begin
-2-
95 fifo_rptr_q <= fifo_rptr_d;
==>
96 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T4,T6,T27 |
| 0 |
0 |
Covered |
T1,T2,T3 |
101 if (!rst_rd_ni) begin
-1-
102 fifo_rptr_gray_q <= '0;
==>
103 end else if (fifo_incr_rptr) begin
-2-
104 fifo_rptr_gray_q <= fifo_rptr_gray_d;
==>
105 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T4,T6,T27 |
| 0 |
0 |
Covered |
T1,T2,T3 |
117 if (!rst_wr_ni) begin
-1-
118 fifo_rptr_sync_q <= '0;
==>
119 end else begin
120 fifo_rptr_sync_q <= fifo_rptr_sync_combi;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T3,T4 |
182 if (fifo_incr_wptr) begin
-1-
183 storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
==>
184 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T6,T27 |
| 0 |
Covered |
T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer
Assertion Details
GrayRptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
480500434 |
480412225 |
0 |
0 |
| T1 |
18125 |
18046 |
0 |
0 |
| T2 |
1597 |
1498 |
0 |
0 |
| T3 |
11309 |
11245 |
0 |
0 |
| T4 |
24683 |
24594 |
0 |
0 |
| T5 |
9341 |
9243 |
0 |
0 |
| T6 |
88558 |
88489 |
0 |
0 |
| T7 |
14577 |
14519 |
0 |
0 |
| T8 |
21533 |
21465 |
0 |
0 |
| T9 |
27558 |
27507 |
0 |
0 |
| T10 |
67823 |
67763 |
0 |
0 |
GrayWptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
146443726 |
146442926 |
0 |
0 |
| T1 |
28040 |
28039 |
0 |
0 |
| T3 |
12138 |
12137 |
0 |
0 |
| T4 |
10704 |
10703 |
0 |
0 |
| T5 |
11561 |
11560 |
0 |
0 |
| T6 |
164371 |
164370 |
0 |
0 |
| T7 |
38338 |
38337 |
0 |
0 |
| T8 |
11192 |
11191 |
0 |
0 |
| T9 |
8288 |
8287 |
0 |
0 |
| T10 |
16256 |
16255 |
0 |
0 |
| T11 |
8976 |
8975 |
0 |
0 |
ParamCheckDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
947 |
947 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 53 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 56 | 1 | 1 | 100.00 |
| ALWAYS | 59 | 4 | 4 | 100.00 |
| ALWAYS | 68 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 86 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 89 | 1 | 1 | 100.00 |
| ALWAYS | 92 | 4 | 4 | 100.00 |
| ALWAYS | 101 | 4 | 4 | 100.00 |
| ALWAYS | 117 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 142 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 143 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 145 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 146 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 156 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 157 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 158 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 159 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 171 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 172 | 1 | 1 | 100.00 |
| ALWAYS | 182 | 2 | 2 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 207 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 276 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 277 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 279 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 280 | 1 | 1 | 100.00 |
52
53 1/1 assign fifo_incr_wptr = wvalid_i & wready_o;
Tests: T1 T2 T3
54
55 // decimal version
56 1/1 assign fifo_wptr_d = fifo_wptr_q + PTR_WIDTH'(1'b1);
Tests: T1 T2 T3
57
58 always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
59 1/1 if (!rst_wr_ni) begin
Tests: T1 T2 T3
60 1/1 fifo_wptr_q <= '0;
Tests: T1 T2 T3
61 1/1 end else if (fifo_incr_wptr) begin
Tests: T1 T2 T3
62 1/1 fifo_wptr_q <= fifo_wptr_d;
Tests: T1 T5 T7
63 end
MISSING_ELSE
64 end
65
66 // gray-coded version
67 always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
68 1/1 if (!rst_wr_ni) begin
Tests: T1 T2 T3
69 1/1 fifo_wptr_gray_q <= '0;
Tests: T1 T2 T3
70 1/1 end else if (fifo_incr_wptr) begin
Tests: T1 T2 T3
71 1/1 fifo_wptr_gray_q <= fifo_wptr_gray_d;
Tests: T1 T5 T7
72 end
MISSING_ELSE
73 end
74
75 // sync gray-coded pointer to read clk
76 prim_flop_2sync #(.Width(PTR_WIDTH)) sync_wptr (
77 .clk_i (clk_rd_i),
78 .rst_ni (rst_rd_ni),
79 .d_i (fifo_wptr_gray_q),
80 .q_o (fifo_wptr_gray_sync));
81
82 //////////////////
83 // Read Pointer //
84 //////////////////
85
86 1/1 assign fifo_incr_rptr = rvalid_o & rready_i;
Tests: T1 T2 T3
87
88 // decimal version
89 1/1 assign fifo_rptr_d = fifo_rptr_q + PTR_WIDTH'(1'b1);
Tests: T1 T2 T3
90
91 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
92 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
93 1/1 fifo_rptr_q <= '0;
Tests: T1 T2 T3
94 1/1 end else if (fifo_incr_rptr) begin
Tests: T1 T3 T4
95 1/1 fifo_rptr_q <= fifo_rptr_d;
Tests: T1 T5 T7
96 end
MISSING_ELSE
97 end
98
99 // gray-coded version
100 always_ff @(posedge clk_rd_i or negedge rst_rd_ni) begin
101 1/1 if (!rst_rd_ni) begin
Tests: T1 T2 T3
102 1/1 fifo_rptr_gray_q <= '0;
Tests: T1 T2 T3
103 1/1 end else if (fifo_incr_rptr) begin
Tests: T1 T3 T4
104 1/1 fifo_rptr_gray_q <= fifo_rptr_gray_d;
Tests: T1 T5 T7
105 end
MISSING_ELSE
106 end
107
108 // sync gray-coded pointer to write clk
109 prim_flop_2sync #(.Width(PTR_WIDTH)) sync_rptr (
110 .clk_i (clk_wr_i),
111 .rst_ni (rst_wr_ni),
112 .d_i (fifo_rptr_gray_q),
113 .q_o (fifo_rptr_gray_sync));
114
115 // Registered version of synced read pointer
116 always_ff @(posedge clk_wr_i or negedge rst_wr_ni) begin
117 1/1 if (!rst_wr_ni) begin
Tests: T1 T2 T3
118 1/1 fifo_rptr_sync_q <= '0;
Tests: T1 T2 T3
119 end else begin
120 1/1 fifo_rptr_sync_q <= fifo_rptr_sync_combi;
Tests: T1 T2 T3
121 end
122 end
123
124 //////////////////
125 // Empty / Full //
126 //////////////////
127
128 logic [PTR_WIDTH-1:0] xor_mask;
129 assign xor_mask = PTR_WIDTH'(1'b1) << (PTR_WIDTH-1);
130 1/1 assign full_wclk = (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask));
Tests: T1 T2 T3
131 1/1 assign full_rclk = (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask));
Tests: T1 T2 T3
132 1/1 assign empty_rclk = (fifo_wptr_sync_combi == fifo_rptr_q);
Tests: T1 T2 T3
133
134 if (Depth > 1) begin : g_depth_calc
135
136 // Current depth in the write clock side
137 logic wptr_msb;
138 logic rptr_sync_msb;
139 logic [PTRV_W-1:0] wptr_value;
140 logic [PTRV_W-1:0] rptr_sync_value;
141
142 1/1 assign wptr_msb = fifo_wptr_q[PTR_WIDTH-1];
Tests: T1 T2 T3
143 1/1 assign rptr_sync_msb = fifo_rptr_sync_q[PTR_WIDTH-1];
Tests: T1 T2 T3
144 1/1 assign wptr_value = fifo_wptr_q[0+:PTRV_W];
Tests: T1 T2 T3
145 1/1 assign rptr_sync_value = fifo_rptr_sync_q[0+:PTRV_W];
Tests: T1 T2 T3
146 1/1 assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
Tests: T1 T2 T3
147 (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
148 (DepthW'(Depth) - DepthW'(rptr_sync_value) + DepthW'(wptr_value)) ;
149
150 // Current depth in the read clock side
151 logic rptr_msb;
152 logic wptr_sync_msb;
153 logic [PTRV_W-1:0] rptr_value;
154 logic [PTRV_W-1:0] wptr_sync_value;
155
156 1/1 assign wptr_sync_msb = fifo_wptr_sync_combi[PTR_WIDTH-1];
Tests: T1 T2 T3
157 1/1 assign rptr_msb = fifo_rptr_q[PTR_WIDTH-1];
Tests: T1 T2 T3
158 1/1 assign wptr_sync_value = fifo_wptr_sync_combi[0+:PTRV_W];
Tests: T1 T2 T3
159 1/1 assign rptr_value = fifo_rptr_q[0+:PTRV_W];
Tests: T1 T2 T3
160 1/1 assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
Tests: T1 T2 T3
161 (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
162 (DepthW'(Depth) - DepthW'(rptr_value) + DepthW'(wptr_sync_value)) ;
163
164 end else begin : g_no_depth_calc
165
166 assign rdepth_o = full_rclk;
167 assign wdepth_o = full_wclk;
168
169 end
170
171 1/1 assign wready_o = ~full_wclk;
Tests: T1 T2 T3
172 1/1 assign rvalid_o = ~empty_rclk;
Tests: T1 T2 T3
173
174 /////////////
175 // Storage //
176 /////////////
177
178 logic [Width-1:0] rdata_int;
179 if (Depth > 1) begin : g_storage_mux
180
181 always_ff @(posedge clk_wr_i) begin
182 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
183 1/1 storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
Tests: T1 T5 T7
184 end
MISSING_ELSE
185 end
186
187 1/1 assign rdata_int = storage[fifo_rptr_q[PTRV_W-1:0]];
Tests: T1 T2 T3
188
189 end else begin : g_storage_simple
190
191 always_ff @(posedge clk_wr_i) begin
192 if (fifo_incr_wptr) begin
193 storage[0] <= wdata_i;
194 end
195 end
196
197 assign rdata_int = storage[0];
198
199 end
200
201 // rdata_o is qualified with rvalid_o to avoid CDC error
202 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
203 if (OutputZeroIfInvalid == 1'b1) begin : gen_invalid_zero
204 assign rdata_o = empty_rclk ? '0 : (rvalid_o ? rdata_int : '0);
205 end
206 else begin : gen_invalid_non_zero
207 1/1 assign rdata_o = empty_rclk ? '0 : rdata_int;
Tests: T1 T2 T3
208 end
209 end else begin : gen_no_output_zero
210 if (OutputZeroIfInvalid == 1'b1) begin : gen_invalid_zero
211 assign rdata_o = rvalid_o ? rdata_int : '0;
212 end
213 else begin : gen_invalid_non_zero
214 assign rdata_o = rdata_int;
215 end
216 end
217
218 //////////////////////////////////////
219 // Decimal <-> Gray-code Conversion //
220 //////////////////////////////////////
221
222 // This code is all in a generate context to avoid lint errors when Depth <= 2
223 if (Depth > 2) begin : g_full_gray_conversion
224
225 function automatic [PTR_WIDTH-1:0] dec2gray(input logic [PTR_WIDTH-1:0] decval);
226 logic [PTR_WIDTH-1:0] decval_sub;
227 logic [PTR_WIDTH-1:0] decval_in;
228 logic unused_decval_msb;
229
230 decval_sub = (PTR_WIDTH)'(Depth) - {1'b0, decval[PTR_WIDTH-2:0]} - 1'b1;
231
232 decval_in = decval[PTR_WIDTH-1] ? decval_sub : decval;
233
234 // We do not care about the MSB, hence we mask it out
235 unused_decval_msb = decval_in[PTR_WIDTH-1];
236 decval_in[PTR_WIDTH-1] = 1'b0;
237
238 // Perform the XOR conversion
239 dec2gray = decval_in;
240 dec2gray ^= (decval_in >> 1);
241
242 // Override the MSB
243 dec2gray[PTR_WIDTH-1] = decval[PTR_WIDTH-1];
244 endfunction
245
246 // Algorithm walks up from 0..N-1 then flips the upper bit and walks down from N-1 to 0.
247 function automatic [PTR_WIDTH-1:0] gray2dec(input logic [PTR_WIDTH-1:0] grayval);
248 logic [PTR_WIDTH-1:0] dec_tmp, dec_tmp_sub;
249 logic unused_decsub_msb;
250
251 dec_tmp = '0;
252 for (int i = PTR_WIDTH-2; i >= 0; i--) begin
253 dec_tmp[i] = dec_tmp[i+1] ^ grayval[i];
254 end
255 dec_tmp_sub = (PTR_WIDTH)'(Depth) - dec_tmp - 1'b1;
256 if (grayval[PTR_WIDTH-1]) begin
257 gray2dec = dec_tmp_sub;
258 // Override MSB
259 gray2dec[PTR_WIDTH-1] = 1'b1;
260 unused_decsub_msb = dec_tmp_sub[PTR_WIDTH-1];
261 end else begin
262 gray2dec = dec_tmp;
263 end
264 endfunction
265
266 // decimal version of read pointer in write domain
267 assign fifo_rptr_sync_combi = gray2dec(fifo_rptr_gray_sync);
268 // decimal version of write pointer in read domain
269 assign fifo_wptr_sync_combi = gray2dec(fifo_wptr_gray_sync);
270
271 assign fifo_rptr_gray_d = dec2gray(fifo_rptr_d);
272 assign fifo_wptr_gray_d = dec2gray(fifo_wptr_d);
273
274 end else if (Depth == 2) begin : g_simple_gray_conversion
275
276 1/1 assign fifo_rptr_sync_combi = {fifo_rptr_gray_sync[PTR_WIDTH-1], ^fifo_rptr_gray_sync};
Tests: T1 T2 T3
277 1/1 assign fifo_wptr_sync_combi = {fifo_wptr_gray_sync[PTR_WIDTH-1], ^fifo_wptr_gray_sync};
Tests: T1 T2 T3
278
279 1/1 assign fifo_rptr_gray_d = {fifo_rptr_d[PTR_WIDTH-1], ^fifo_rptr_d};
Tests: T1 T2 T3
280 1/1 assign fifo_wptr_gray_d = {fifo_wptr_d[PTR_WIDTH-1], ^fifo_wptr_d};
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync
| Total | Covered | Percent |
|---|
| Conditions | 25 | 24 | 96.00 |
| Logical | 25 | 24 | 96.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 53
EXPRESSION (wvalid_i & wready_o)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Not Covered | |
| 1 | 1 | Covered | T1,T5,T7 |
LINE 86
EXPRESSION (rvalid_o & rready_i)
----1--- ----2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Unreachable | |
| 1 | 1 | Covered | T1,T5,T7 |
LINE 130
EXPRESSION (fifo_wptr_q == (fifo_rptr_sync_q ^ xor_mask))
-----------------------1----------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T118,T119,T120 |
LINE 131
EXPRESSION (fifo_wptr_sync_combi == (fifo_rptr_q ^ xor_mask))
-------------------------1------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T121,T122,T85 |
LINE 132
EXPRESSION (fifo_wptr_sync_combi == fifo_rptr_q)
------------------1------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 146
EXPRESSION
Number Term
1 full_wclk ? (2'(Depth)) : ((g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T118,T119,T120 |
LINE 146
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb) ? ((2'(g_depth_calc.wptr_value) - 2'(g_depth_calc.rptr_sync_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_sync_value)) + 2'(g_depth_calc.wptr_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T5,T7 |
| 1 | Covered | T1,T2,T3 |
LINE 146
SUB-EXPRESSION (g_depth_calc.wptr_msb == g_depth_calc.rptr_sync_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T5,T7 |
| 1 | Covered | T1,T2,T3 |
LINE 160
EXPRESSION
Number Term
1 full_rclk ? (2'(Depth)) : ((g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value)))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T121,T122,T85 |
LINE 160
SUB-EXPRESSION
Number Term
1 (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb) ? ((2'(g_depth_calc.wptr_sync_value) - 2'(g_depth_calc.rptr_value))) : (((2'(Depth) - 2'(g_depth_calc.rptr_value)) + 2'(g_depth_calc.wptr_sync_value))))
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T5,T7 |
| 1 | Covered | T1,T2,T3 |
LINE 160
SUB-EXPRESSION (g_depth_calc.wptr_sync_msb == g_depth_calc.rptr_msb)
--------------------------1--------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T5,T7 |
| 1 | Covered | T1,T2,T3 |
LINE 207
EXPRESSION (empty_rclk ? '0 : rdata_int)
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T5,T7 |
| 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync
| Line No. | Total | Covered | Percent |
| Branches |
|
24 |
24 |
100.00 |
| TERNARY |
146 |
3 |
3 |
100.00 |
| TERNARY |
160 |
3 |
3 |
100.00 |
| TERNARY |
207 |
2 |
2 |
100.00 |
| IF |
59 |
3 |
3 |
100.00 |
| IF |
68 |
3 |
3 |
100.00 |
| IF |
92 |
3 |
3 |
100.00 |
| IF |
101 |
3 |
3 |
100.00 |
| IF |
117 |
2 |
2 |
100.00 |
| IF |
182 |
2 |
2 |
100.00 |
146 assign wdepth_o = (full_wclk) ? DepthW'(Depth) :
-1-
==>
147 (wptr_msb == rptr_sync_msb) ? DepthW'(wptr_value) - DepthW'(rptr_sync_value) :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T118,T119,T120 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T5,T7 |
160 assign rdepth_o = (full_rclk) ? DepthW'(Depth) :
-1-
==>
161 (wptr_sync_msb == rptr_msb) ? DepthW'(wptr_sync_value) - DepthW'(rptr_value) :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T121,T122,T85 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T5,T7 |
207 assign rdata_o = empty_rclk ? '0 : rdata_int;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T5,T7 |
59 if (!rst_wr_ni) begin
-1-
60 fifo_wptr_q <= '0;
==>
61 end else if (fifo_incr_wptr) begin
-2-
62 fifo_wptr_q <= fifo_wptr_d;
==>
63 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T5,T7 |
| 0 |
0 |
Covered |
T1,T2,T3 |
68 if (!rst_wr_ni) begin
-1-
69 fifo_wptr_gray_q <= '0;
==>
70 end else if (fifo_incr_wptr) begin
-2-
71 fifo_wptr_gray_q <= fifo_wptr_gray_d;
==>
72 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T5,T7 |
| 0 |
0 |
Covered |
T1,T2,T3 |
92 if (!rst_rd_ni) begin
-1-
93 fifo_rptr_q <= '0;
==>
94 end else if (fifo_incr_rptr) begin
-2-
95 fifo_rptr_q <= fifo_rptr_d;
==>
96 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T5,T7 |
| 0 |
0 |
Covered |
T1,T3,T4 |
101 if (!rst_rd_ni) begin
-1-
102 fifo_rptr_gray_q <= '0;
==>
103 end else if (fifo_incr_rptr) begin
-2-
104 fifo_rptr_gray_q <= fifo_rptr_gray_d;
==>
105 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T5,T7 |
| 0 |
0 |
Covered |
T1,T3,T4 |
117 if (!rst_wr_ni) begin
-1-
118 fifo_rptr_sync_q <= '0;
==>
119 end else begin
120 fifo_rptr_sync_q <= fifo_rptr_sync_combi;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
182 if (fifo_incr_wptr) begin
-1-
183 storage[fifo_wptr_q[PTRV_W-1:0]] <= wdata_i;
==>
184 end
MISSING_ELSE
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T5,T7 |
| 0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_spid_status.u_sw_status_update_sync
Assertion Details
GrayRptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
146443726 |
146442926 |
0 |
0 |
| T1 |
28040 |
28039 |
0 |
0 |
| T3 |
12138 |
12137 |
0 |
0 |
| T4 |
10704 |
10703 |
0 |
0 |
| T5 |
11561 |
11560 |
0 |
0 |
| T6 |
164371 |
164370 |
0 |
0 |
| T7 |
38338 |
38337 |
0 |
0 |
| T8 |
11192 |
11191 |
0 |
0 |
| T9 |
8288 |
8287 |
0 |
0 |
| T10 |
16256 |
16255 |
0 |
0 |
| T11 |
8976 |
8975 |
0 |
0 |
GrayWptr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
480500434 |
480412225 |
0 |
0 |
| T1 |
18125 |
18046 |
0 |
0 |
| T2 |
1597 |
1498 |
0 |
0 |
| T3 |
11309 |
11245 |
0 |
0 |
| T4 |
24683 |
24594 |
0 |
0 |
| T5 |
9341 |
9243 |
0 |
0 |
| T6 |
88558 |
88489 |
0 |
0 |
| T7 |
14577 |
14519 |
0 |
0 |
| T8 |
21533 |
21465 |
0 |
0 |
| T9 |
27558 |
27507 |
0 |
0 |
| T10 |
67823 |
67763 |
0 |
0 |
ParamCheckDepth_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
947 |
947 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T5 |
1 |
1 |
0 |
0 |
| T6 |
1 |
1 |
0 |
0 |
| T7 |
1 |
1 |
0 |
0 |
| T8 |
1 |
1 |
0 |
0 |
| T9 |
1 |
1 |
0 |
0 |
| T10 |
1 |
1 |
0 |
0 |