Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T3 T5
72 1/1 under_rst <= ~under_rst;
Tests: T1 T3 T5
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T1 T3 T7
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T3 T4
112 1/1 storage[0] <= wdata_i;
Tests: T1 T3 T7
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 assign rdata_o = empty ? Width'(0) : rdata_int;
139 end else begin : gen_no_output_zero
140 1/1 assign rdata_o = rdata_int;
Tests: T1 T3 T7
Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
| Total | Covered | Percent |
Conditions | 22 | 16 | 72.73 |
Logical | 22 | 16 | 72.73 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T5 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T5 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T7 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T7 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T7 |
0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T3,T5 |
0 |
0 |
Covered |
T1,T3,T5 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T7 |
0 |
Covered |
T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
21871471 |
0 |
0 |
T1 |
28040 |
3988 |
0 |
0 |
T3 |
12138 |
3972 |
0 |
0 |
T4 |
10704 |
0 |
0 |
0 |
T5 |
11561 |
0 |
0 |
0 |
T6 |
164371 |
0 |
0 |
0 |
T7 |
38338 |
1019 |
0 |
0 |
T8 |
11192 |
6007 |
0 |
0 |
T9 |
8288 |
0 |
0 |
0 |
T10 |
16256 |
2036 |
0 |
0 |
T11 |
8976 |
4476 |
0 |
0 |
T12 |
0 |
20804 |
0 |
0 |
T13 |
0 |
14114 |
0 |
0 |
T46 |
0 |
14392 |
0 |
0 |
T50 |
0 |
980 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
119249854 |
0 |
0 |
T1 |
28040 |
27344 |
0 |
0 |
T3 |
12138 |
12138 |
0 |
0 |
T4 |
10704 |
0 |
0 |
0 |
T5 |
11561 |
11408 |
0 |
0 |
T6 |
164371 |
0 |
0 |
0 |
T7 |
38338 |
38338 |
0 |
0 |
T8 |
11192 |
11192 |
0 |
0 |
T9 |
8288 |
8288 |
0 |
0 |
T10 |
16256 |
16256 |
0 |
0 |
T11 |
8976 |
8976 |
0 |
0 |
T12 |
0 |
50872 |
0 |
0 |
T13 |
0 |
15155 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
119249854 |
0 |
0 |
T1 |
28040 |
27344 |
0 |
0 |
T3 |
12138 |
12138 |
0 |
0 |
T4 |
10704 |
0 |
0 |
0 |
T5 |
11561 |
11408 |
0 |
0 |
T6 |
164371 |
0 |
0 |
0 |
T7 |
38338 |
38338 |
0 |
0 |
T8 |
11192 |
11192 |
0 |
0 |
T9 |
8288 |
8288 |
0 |
0 |
T10 |
16256 |
16256 |
0 |
0 |
T11 |
8976 |
8976 |
0 |
0 |
T12 |
0 |
50872 |
0 |
0 |
T13 |
0 |
15155 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
119249854 |
0 |
0 |
T1 |
28040 |
27344 |
0 |
0 |
T3 |
12138 |
12138 |
0 |
0 |
T4 |
10704 |
0 |
0 |
0 |
T5 |
11561 |
11408 |
0 |
0 |
T6 |
164371 |
0 |
0 |
0 |
T7 |
38338 |
38338 |
0 |
0 |
T8 |
11192 |
11192 |
0 |
0 |
T9 |
8288 |
8288 |
0 |
0 |
T10 |
16256 |
16256 |
0 |
0 |
T11 |
8976 |
8976 |
0 |
0 |
T12 |
0 |
50872 |
0 |
0 |
T13 |
0 |
15155 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
21871471 |
0 |
0 |
T1 |
28040 |
3988 |
0 |
0 |
T3 |
12138 |
3972 |
0 |
0 |
T4 |
10704 |
0 |
0 |
0 |
T5 |
11561 |
0 |
0 |
0 |
T6 |
164371 |
0 |
0 |
0 |
T7 |
38338 |
1019 |
0 |
0 |
T8 |
11192 |
6007 |
0 |
0 |
T9 |
8288 |
0 |
0 |
0 |
T10 |
16256 |
2036 |
0 |
0 |
T11 |
8976 |
4476 |
0 |
0 |
T12 |
0 |
20804 |
0 |
0 |
T13 |
0 |
14114 |
0 |
0 |
T46 |
0 |
14392 |
0 |
0 |
T50 |
0 |
980 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T3 T5
72 1/1 under_rst <= ~under_rst;
Tests: T1 T3 T5
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T3 T4
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T1 T3 T7
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 assign rdata_o = empty ? Width'(0) : rdata_int;
139 end else begin : gen_no_output_zero
140 1/1 assign rdata_o = rdata_int;
Tests: T1 T3 T7
Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
| Total | Covered | Percent |
Conditions | 22 | 18 | 81.82 |
Logical | 22 | 18 | 81.82 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T5 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T7 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T5 |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T7 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T7 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T3,T7 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T7 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T7 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T7 |
1 | 0 | Covered | T1,T3,T7 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T7 |
0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T3,T5 |
0 |
0 |
Covered |
T1,T3,T5 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T7 |
0 |
Covered |
T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
22982875 |
0 |
0 |
T1 |
28040 |
4112 |
0 |
0 |
T3 |
12138 |
4096 |
0 |
0 |
T4 |
10704 |
0 |
0 |
0 |
T5 |
11561 |
0 |
0 |
0 |
T6 |
164371 |
0 |
0 |
0 |
T7 |
38338 |
1080 |
0 |
0 |
T8 |
11192 |
6192 |
0 |
0 |
T9 |
8288 |
0 |
0 |
0 |
T10 |
16256 |
2094 |
0 |
0 |
T11 |
8976 |
4656 |
0 |
0 |
T12 |
0 |
22188 |
0 |
0 |
T13 |
0 |
14899 |
0 |
0 |
T46 |
0 |
15259 |
0 |
0 |
T50 |
0 |
1040 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
119249854 |
0 |
0 |
T1 |
28040 |
27344 |
0 |
0 |
T3 |
12138 |
12138 |
0 |
0 |
T4 |
10704 |
0 |
0 |
0 |
T5 |
11561 |
11408 |
0 |
0 |
T6 |
164371 |
0 |
0 |
0 |
T7 |
38338 |
38338 |
0 |
0 |
T8 |
11192 |
11192 |
0 |
0 |
T9 |
8288 |
8288 |
0 |
0 |
T10 |
16256 |
16256 |
0 |
0 |
T11 |
8976 |
8976 |
0 |
0 |
T12 |
0 |
50872 |
0 |
0 |
T13 |
0 |
15155 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
119249854 |
0 |
0 |
T1 |
28040 |
27344 |
0 |
0 |
T3 |
12138 |
12138 |
0 |
0 |
T4 |
10704 |
0 |
0 |
0 |
T5 |
11561 |
11408 |
0 |
0 |
T6 |
164371 |
0 |
0 |
0 |
T7 |
38338 |
38338 |
0 |
0 |
T8 |
11192 |
11192 |
0 |
0 |
T9 |
8288 |
8288 |
0 |
0 |
T10 |
16256 |
16256 |
0 |
0 |
T11 |
8976 |
8976 |
0 |
0 |
T12 |
0 |
50872 |
0 |
0 |
T13 |
0 |
15155 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
119249854 |
0 |
0 |
T1 |
28040 |
27344 |
0 |
0 |
T3 |
12138 |
12138 |
0 |
0 |
T4 |
10704 |
0 |
0 |
0 |
T5 |
11561 |
11408 |
0 |
0 |
T6 |
164371 |
0 |
0 |
0 |
T7 |
38338 |
38338 |
0 |
0 |
T8 |
11192 |
11192 |
0 |
0 |
T9 |
8288 |
8288 |
0 |
0 |
T10 |
16256 |
16256 |
0 |
0 |
T11 |
8976 |
8976 |
0 |
0 |
T12 |
0 |
50872 |
0 |
0 |
T13 |
0 |
15155 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
22982875 |
0 |
0 |
T1 |
28040 |
4112 |
0 |
0 |
T3 |
12138 |
4096 |
0 |
0 |
T4 |
10704 |
0 |
0 |
0 |
T5 |
11561 |
0 |
0 |
0 |
T6 |
164371 |
0 |
0 |
0 |
T7 |
38338 |
1080 |
0 |
0 |
T8 |
11192 |
6192 |
0 |
0 |
T9 |
8288 |
0 |
0 |
0 |
T10 |
16256 |
2094 |
0 |
0 |
T11 |
8976 |
4656 |
0 |
0 |
T12 |
0 |
22188 |
0 |
0 |
T13 |
0 |
14899 |
0 |
0 |
T46 |
0 |
15259 |
0 |
0 |
T50 |
0 |
1040 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 12 | 85.71 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 1 | 50.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T3 T5
72 1/1 under_rst <= ~under_rst;
Tests: T1 T3 T5
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T3 T4
124 0/1 ==> storage[fifo_wptr] <= wdata_i;
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 0/1 ==> assign rdata_int = storage_rdata;
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
| Total | Covered | Percent |
Conditions | 16 | 5 | 31.25 |
Logical | 16 | 5 | 31.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T3,T5 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T3,T5 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (3'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
5 |
71.43 |
TERNARY |
138 |
2 |
1 |
50.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
1 |
50.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T3,T5 |
0 |
0 |
Covered |
T1,T3,T5 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
119249854 |
0 |
0 |
T1 |
28040 |
27344 |
0 |
0 |
T3 |
12138 |
12138 |
0 |
0 |
T4 |
10704 |
0 |
0 |
0 |
T5 |
11561 |
11408 |
0 |
0 |
T6 |
164371 |
0 |
0 |
0 |
T7 |
38338 |
38338 |
0 |
0 |
T8 |
11192 |
11192 |
0 |
0 |
T9 |
8288 |
8288 |
0 |
0 |
T10 |
16256 |
16256 |
0 |
0 |
T11 |
8976 |
8976 |
0 |
0 |
T12 |
0 |
50872 |
0 |
0 |
T13 |
0 |
15155 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
119249854 |
0 |
0 |
T1 |
28040 |
27344 |
0 |
0 |
T3 |
12138 |
12138 |
0 |
0 |
T4 |
10704 |
0 |
0 |
0 |
T5 |
11561 |
11408 |
0 |
0 |
T6 |
164371 |
0 |
0 |
0 |
T7 |
38338 |
38338 |
0 |
0 |
T8 |
11192 |
11192 |
0 |
0 |
T9 |
8288 |
8288 |
0 |
0 |
T10 |
16256 |
16256 |
0 |
0 |
T11 |
8976 |
8976 |
0 |
0 |
T12 |
0 |
50872 |
0 |
0 |
T13 |
0 |
15155 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
119249854 |
0 |
0 |
T1 |
28040 |
27344 |
0 |
0 |
T3 |
12138 |
12138 |
0 |
0 |
T4 |
10704 |
0 |
0 |
0 |
T5 |
11561 |
11408 |
0 |
0 |
T6 |
164371 |
0 |
0 |
0 |
T7 |
38338 |
38338 |
0 |
0 |
T8 |
11192 |
11192 |
0 |
0 |
T9 |
8288 |
8288 |
0 |
0 |
T10 |
16256 |
16256 |
0 |
0 |
T11 |
8976 |
8976 |
0 |
0 |
T12 |
0 |
50872 |
0 |
0 |
T13 |
0 |
15155 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
0 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 130 | 1 | 1 | 100.00 |
CONT_ASSIGN | 131 | 1 | 1 | 100.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T4 T6 T26
72 1/1 under_rst <= ~under_rst;
Tests: T4 T6 T26
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T4 T6 T27
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T3 T4
112 1/1 storage[0] <= wdata_i;
Tests: T4 T6 T27
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 1/1 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
Tests: T1 T2 T3
131 1/1 assign empty = fifo_empty & ~wvalid_i;
Tests: T1 T2 T3
132 end else begin : gen_nopass
133 assign rdata_int = storage_rdata;
134 assign empty = fifo_empty;
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 assign rdata_o = empty ? Width'(0) : rdata_int;
139 end else begin : gen_no_output_zero
140 1/1 assign rdata_o = rdata_int;
Tests: T4 T6 T27
Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
| Total | Covered | Percent |
Conditions | 22 | 17 | 77.27 |
Logical | 22 | 17 | 77.27 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T27 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T6,T26 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T26 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T6,T27 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T6,T26 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T6,T27 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T6,T27 |
1 | 0 | 1 | Covered | T4,T6,T27 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T6,T27 |
LINE 130
EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
--------------------1-------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T4,T6,T27 |
LINE 130
SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
-------------1------------ ----2---
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T6,T27 |
LINE 131
EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
-------------1------------ ------2------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T27 |
1 | 0 | Covered | T4,T6,T27 |
1 | 1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
130 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
111 |
2 |
2 |
100.00 |
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T6,T27 |
0 |
Covered |
T1,T2,T3 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T4,T6,T26 |
0 |
0 |
Covered |
T4,T6,T26 |
111 if (fifo_incr_wptr) begin
-1-
112 storage[0] <= wdata_i;
==>
113 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T6,T27 |
0 |
Covered |
T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
5644838 |
0 |
0 |
T4 |
10704 |
2470 |
0 |
0 |
T5 |
11561 |
0 |
0 |
0 |
T6 |
164371 |
27958 |
0 |
0 |
T7 |
38338 |
0 |
0 |
0 |
T8 |
11192 |
0 |
0 |
0 |
T9 |
8288 |
0 |
0 |
0 |
T10 |
16256 |
0 |
0 |
0 |
T11 |
8976 |
0 |
0 |
0 |
T12 |
51460 |
0 |
0 |
0 |
T23 |
0 |
1006 |
0 |
0 |
T26 |
1042 |
0 |
0 |
0 |
T27 |
0 |
409 |
0 |
0 |
T28 |
0 |
7324 |
0 |
0 |
T31 |
0 |
1725 |
0 |
0 |
T41 |
0 |
12094 |
0 |
0 |
T42 |
0 |
1197 |
0 |
0 |
T44 |
0 |
254 |
0 |
0 |
T88 |
0 |
1160 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
25903286 |
0 |
0 |
T4 |
10704 |
10528 |
0 |
0 |
T5 |
11561 |
0 |
0 |
0 |
T6 |
164371 |
161120 |
0 |
0 |
T7 |
38338 |
0 |
0 |
0 |
T8 |
11192 |
0 |
0 |
0 |
T9 |
8288 |
0 |
0 |
0 |
T10 |
16256 |
0 |
0 |
0 |
T11 |
8976 |
0 |
0 |
0 |
T12 |
51460 |
0 |
0 |
0 |
T23 |
0 |
2352 |
0 |
0 |
T26 |
1042 |
864 |
0 |
0 |
T27 |
0 |
704 |
0 |
0 |
T28 |
0 |
44192 |
0 |
0 |
T29 |
0 |
105128 |
0 |
0 |
T30 |
0 |
360 |
0 |
0 |
T31 |
0 |
4016 |
0 |
0 |
T32 |
0 |
5240 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
25903286 |
0 |
0 |
T4 |
10704 |
10528 |
0 |
0 |
T5 |
11561 |
0 |
0 |
0 |
T6 |
164371 |
161120 |
0 |
0 |
T7 |
38338 |
0 |
0 |
0 |
T8 |
11192 |
0 |
0 |
0 |
T9 |
8288 |
0 |
0 |
0 |
T10 |
16256 |
0 |
0 |
0 |
T11 |
8976 |
0 |
0 |
0 |
T12 |
51460 |
0 |
0 |
0 |
T23 |
0 |
2352 |
0 |
0 |
T26 |
1042 |
864 |
0 |
0 |
T27 |
0 |
704 |
0 |
0 |
T28 |
0 |
44192 |
0 |
0 |
T29 |
0 |
105128 |
0 |
0 |
T30 |
0 |
360 |
0 |
0 |
T31 |
0 |
4016 |
0 |
0 |
T32 |
0 |
5240 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
25903286 |
0 |
0 |
T4 |
10704 |
10528 |
0 |
0 |
T5 |
11561 |
0 |
0 |
0 |
T6 |
164371 |
161120 |
0 |
0 |
T7 |
38338 |
0 |
0 |
0 |
T8 |
11192 |
0 |
0 |
0 |
T9 |
8288 |
0 |
0 |
0 |
T10 |
16256 |
0 |
0 |
0 |
T11 |
8976 |
0 |
0 |
0 |
T12 |
51460 |
0 |
0 |
0 |
T23 |
0 |
2352 |
0 |
0 |
T26 |
1042 |
864 |
0 |
0 |
T27 |
0 |
704 |
0 |
0 |
T28 |
0 |
44192 |
0 |
0 |
T29 |
0 |
105128 |
0 |
0 |
T30 |
0 |
360 |
0 |
0 |
T31 |
0 |
4016 |
0 |
0 |
T32 |
0 |
5240 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
5644838 |
0 |
0 |
T4 |
10704 |
2470 |
0 |
0 |
T5 |
11561 |
0 |
0 |
0 |
T6 |
164371 |
27958 |
0 |
0 |
T7 |
38338 |
0 |
0 |
0 |
T8 |
11192 |
0 |
0 |
0 |
T9 |
8288 |
0 |
0 |
0 |
T10 |
16256 |
0 |
0 |
0 |
T11 |
8976 |
0 |
0 |
0 |
T12 |
51460 |
0 |
0 |
0 |
T23 |
0 |
1006 |
0 |
0 |
T26 |
1042 |
0 |
0 |
0 |
T27 |
0 |
409 |
0 |
0 |
T28 |
0 |
7324 |
0 |
0 |
T31 |
0 |
1725 |
0 |
0 |
T41 |
0 |
12094 |
0 |
0 |
T42 |
0 |
1197 |
0 |
0 |
T44 |
0 |
254 |
0 |
0 |
T88 |
0 |
1160 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
| Line No. | Total | Covered | Percent |
TOTAL | | 14 | 14 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
ALWAYS | 123 | 2 | 2 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T4 T6 T26
72 1/1 under_rst <= ~under_rst;
Tests: T4 T6 T26
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 if (fifo_incr_wptr) begin
112 storage[0] <= wdata_i;
113 end
114
115 logic unused_ptrs;
116 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 1/1 assign storage_rdata = storage[fifo_rptr];
Tests: T1 T2 T3
121
122 always_ff @(posedge clk_i)
123 1/1 if (fifo_incr_wptr) begin
Tests: T1 T3 T4
124 1/1 storage[fifo_wptr] <= wdata_i;
Tests: T4 T6 T27
125 end
MISSING_ELSE
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T4 T6 T27
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
| Total | Covered | Percent |
Conditions | 16 | 9 | 56.25 |
Logical | 16 | 9 | 56.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T4,T6,T26 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T4,T6,T26 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T4,T6,T27 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T4,T6,T26 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T6,T27 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T4,T6,T27 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (2'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T4,T6,T27 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T4,T6,T27 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T4,T6,T26 |
0 |
0 |
Covered |
T4,T6,T26 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T4,T6,T27 |
0 |
Covered |
T1,T3,T4 |
Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
181315 |
0 |
0 |
T4 |
10704 |
80 |
0 |
0 |
T5 |
11561 |
0 |
0 |
0 |
T6 |
164371 |
897 |
0 |
0 |
T7 |
38338 |
0 |
0 |
0 |
T8 |
11192 |
0 |
0 |
0 |
T9 |
8288 |
0 |
0 |
0 |
T10 |
16256 |
0 |
0 |
0 |
T11 |
8976 |
0 |
0 |
0 |
T12 |
51460 |
0 |
0 |
0 |
T23 |
0 |
32 |
0 |
0 |
T26 |
1042 |
0 |
0 |
0 |
T27 |
0 |
14 |
0 |
0 |
T28 |
0 |
237 |
0 |
0 |
T31 |
0 |
55 |
0 |
0 |
T41 |
0 |
386 |
0 |
0 |
T42 |
0 |
39 |
0 |
0 |
T44 |
0 |
8 |
0 |
0 |
T88 |
0 |
37 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
25903286 |
0 |
0 |
T4 |
10704 |
10528 |
0 |
0 |
T5 |
11561 |
0 |
0 |
0 |
T6 |
164371 |
161120 |
0 |
0 |
T7 |
38338 |
0 |
0 |
0 |
T8 |
11192 |
0 |
0 |
0 |
T9 |
8288 |
0 |
0 |
0 |
T10 |
16256 |
0 |
0 |
0 |
T11 |
8976 |
0 |
0 |
0 |
T12 |
51460 |
0 |
0 |
0 |
T23 |
0 |
2352 |
0 |
0 |
T26 |
1042 |
864 |
0 |
0 |
T27 |
0 |
704 |
0 |
0 |
T28 |
0 |
44192 |
0 |
0 |
T29 |
0 |
105128 |
0 |
0 |
T30 |
0 |
360 |
0 |
0 |
T31 |
0 |
4016 |
0 |
0 |
T32 |
0 |
5240 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
25903286 |
0 |
0 |
T4 |
10704 |
10528 |
0 |
0 |
T5 |
11561 |
0 |
0 |
0 |
T6 |
164371 |
161120 |
0 |
0 |
T7 |
38338 |
0 |
0 |
0 |
T8 |
11192 |
0 |
0 |
0 |
T9 |
8288 |
0 |
0 |
0 |
T10 |
16256 |
0 |
0 |
0 |
T11 |
8976 |
0 |
0 |
0 |
T12 |
51460 |
0 |
0 |
0 |
T23 |
0 |
2352 |
0 |
0 |
T26 |
1042 |
864 |
0 |
0 |
T27 |
0 |
704 |
0 |
0 |
T28 |
0 |
44192 |
0 |
0 |
T29 |
0 |
105128 |
0 |
0 |
T30 |
0 |
360 |
0 |
0 |
T31 |
0 |
4016 |
0 |
0 |
T32 |
0 |
5240 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
25903286 |
0 |
0 |
T4 |
10704 |
10528 |
0 |
0 |
T5 |
11561 |
0 |
0 |
0 |
T6 |
164371 |
161120 |
0 |
0 |
T7 |
38338 |
0 |
0 |
0 |
T8 |
11192 |
0 |
0 |
0 |
T9 |
8288 |
0 |
0 |
0 |
T10 |
16256 |
0 |
0 |
0 |
T11 |
8976 |
0 |
0 |
0 |
T12 |
51460 |
0 |
0 |
0 |
T23 |
0 |
2352 |
0 |
0 |
T26 |
1042 |
864 |
0 |
0 |
T27 |
0 |
704 |
0 |
0 |
T28 |
0 |
44192 |
0 |
0 |
T29 |
0 |
105128 |
0 |
0 |
T30 |
0 |
360 |
0 |
0 |
T31 |
0 |
4016 |
0 |
0 |
T32 |
0 |
5240 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
146443726 |
181315 |
0 |
0 |
T4 |
10704 |
80 |
0 |
0 |
T5 |
11561 |
0 |
0 |
0 |
T6 |
164371 |
897 |
0 |
0 |
T7 |
38338 |
0 |
0 |
0 |
T8 |
11192 |
0 |
0 |
0 |
T9 |
8288 |
0 |
0 |
0 |
T10 |
16256 |
0 |
0 |
0 |
T11 |
8976 |
0 |
0 |
0 |
T12 |
51460 |
0 |
0 |
0 |
T23 |
0 |
32 |
0 |
0 |
T26 |
1042 |
0 |
0 |
0 |
T27 |
0 |
14 |
0 |
0 |
T28 |
0 |
237 |
0 |
0 |
T31 |
0 |
55 |
0 |
0 |
T41 |
0 |
386 |
0 |
0 |
T42 |
0 |
39 |
0 |
0 |
T44 |
0 |
8 |
0 |
0 |
T88 |
0 |
37 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 15 | 100.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 1 | 100.00 |
ALWAYS | 111 | 2 | 2 | 100.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 1 | 100.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 1/1 assign storage_rdata = storage[0];
Tests: T1 T3 T5
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 1/1 storage[0] <= wdata_i;
Tests: T1 T3 T5
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 1/1 assign rdata_int = storage_rdata;
Tests: T1 T3 T5
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
| Total | Covered | Percent |
Conditions | 16 | 11 | 68.75 |
Logical | 16 | 11 | 68.75 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T3,T5 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Covered | T1,T3,T5 |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T5 |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Covered | T1,T3,T5 |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Covered | T1,T3,T5 |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Covered | T1,T3,T5 |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
7 |
100.00 |
TERNARY |
138 |
2 |
2 |
100.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
2 |
100.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T3,T5 |
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T3,T5 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480500434 |
3106897 |
0 |
0 |
T1 |
18125 |
832 |
0 |
0 |
T2 |
1597 |
0 |
0 |
0 |
T3 |
11309 |
832 |
0 |
0 |
T4 |
24683 |
0 |
0 |
0 |
T5 |
9341 |
832 |
0 |
0 |
T6 |
88558 |
0 |
0 |
0 |
T7 |
14577 |
832 |
0 |
0 |
T8 |
21533 |
3759 |
0 |
0 |
T9 |
27558 |
3876 |
0 |
0 |
T10 |
67823 |
832 |
0 |
0 |
T11 |
0 |
832 |
0 |
0 |
T12 |
0 |
832 |
0 |
0 |
T13 |
0 |
832 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480500434 |
480413380 |
0 |
0 |
T1 |
18125 |
18047 |
0 |
0 |
T2 |
1597 |
1499 |
0 |
0 |
T3 |
11309 |
11246 |
0 |
0 |
T4 |
24683 |
24595 |
0 |
0 |
T5 |
9341 |
9244 |
0 |
0 |
T6 |
88558 |
88490 |
0 |
0 |
T7 |
14577 |
14520 |
0 |
0 |
T8 |
21533 |
21466 |
0 |
0 |
T9 |
27558 |
27508 |
0 |
0 |
T10 |
67823 |
67764 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480500434 |
480413380 |
0 |
0 |
T1 |
18125 |
18047 |
0 |
0 |
T2 |
1597 |
1499 |
0 |
0 |
T3 |
11309 |
11246 |
0 |
0 |
T4 |
24683 |
24595 |
0 |
0 |
T5 |
9341 |
9244 |
0 |
0 |
T6 |
88558 |
88490 |
0 |
0 |
T7 |
14577 |
14520 |
0 |
0 |
T8 |
21533 |
21466 |
0 |
0 |
T9 |
27558 |
27508 |
0 |
0 |
T10 |
67823 |
67764 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480500434 |
480413380 |
0 |
0 |
T1 |
18125 |
18047 |
0 |
0 |
T2 |
1597 |
1499 |
0 |
0 |
T3 |
11309 |
11246 |
0 |
0 |
T4 |
24683 |
24595 |
0 |
0 |
T5 |
9341 |
9244 |
0 |
0 |
T6 |
88558 |
88490 |
0 |
0 |
T7 |
14577 |
14520 |
0 |
0 |
T8 |
21533 |
21466 |
0 |
0 |
T9 |
27558 |
27508 |
0 |
0 |
T10 |
67823 |
67764 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480500434 |
3106897 |
0 |
0 |
T1 |
18125 |
832 |
0 |
0 |
T2 |
1597 |
0 |
0 |
0 |
T3 |
11309 |
832 |
0 |
0 |
T4 |
24683 |
0 |
0 |
0 |
T5 |
9341 |
832 |
0 |
0 |
T6 |
88558 |
0 |
0 |
0 |
T7 |
14577 |
832 |
0 |
0 |
T8 |
21533 |
3759 |
0 |
0 |
T9 |
27558 |
3876 |
0 |
0 |
T10 |
67823 |
832 |
0 |
0 |
T11 |
0 |
832 |
0 |
0 |
T12 |
0 |
832 |
0 |
0 |
T13 |
0 |
832 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
| Line No. | Total | Covered | Percent |
TOTAL | | 15 | 12 | 80.00 |
ALWAYS | 69 | 4 | 4 | 100.00 |
CONT_ASSIGN | 81 | 1 | 1 | 100.00 |
CONT_ASSIGN | 82 | 1 | 1 | 100.00 |
CONT_ASSIGN | 100 | 1 | 1 | 100.00 |
CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
CONT_ASSIGN | 108 | 1 | 0 | 0.00 |
ALWAYS | 111 | 2 | 1 | 50.00 |
CONT_ASSIGN | 116 | 1 | 1 | 100.00 |
CONT_ASSIGN | 133 | 1 | 0 | 0.00 |
CONT_ASSIGN | 134 | 1 | 1 | 100.00 |
CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
68 always_ff @(posedge clk_i or negedge rst_ni) begin
69 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
70 1/1 under_rst <= 1'b1;
Tests: T1 T2 T3
71 1/1 end else if (under_rst) begin
Tests: T1 T2 T3
72 1/1 under_rst <= ~under_rst;
Tests: T1 T2 T3
73 end
MISSING_ELSE
74 end
75
76 logic empty;
77
78 // full and not ready for write are two different concepts.
79 // The latter can be '0' when under reset, while the former is an indication that no more
80 // entries can be written.
81 1/1 assign wready_o = ~full_o & ~under_rst;
Tests: T1 T2 T3
82 1/1 assign rvalid_o = ~empty & ~under_rst;
Tests: T1 T2 T3
83
84 prim_fifo_sync_cnt #(
85 .Depth(Depth),
86 .Secure(Secure)
87 ) u_fifo_cnt (
88 .clk_i,
89 .rst_ni,
90 .clr_i,
91 .incr_wptr_i(fifo_incr_wptr),
92 .incr_rptr_i(fifo_incr_rptr),
93 .wptr_o(fifo_wptr),
94 .rptr_o(fifo_rptr),
95 .full_o,
96 .empty_o(fifo_empty),
97 .depth_o,
98 .err_o
99 );
100 1/1 assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
Tests: T1 T2 T3
101 1/1 assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
Tests: T1 T2 T3
102
103 // the generate blocks below are needed to avoid lint errors due to array indexing
104 // in the where the fifo only has one storage element
105 logic [Depth-1:0][Width-1:0] storage;
106 logic [Width-1:0] storage_rdata;
107 if (Depth == 1) begin : gen_depth_eq1
108 0/1 ==> assign storage_rdata = storage[0];
109
110 always_ff @(posedge clk_i)
111 1/1 if (fifo_incr_wptr) begin
Tests: T1 T2 T3
112 0/1 ==> storage[0] <= wdata_i;
113 end
MISSING_ELSE
114
115 logic unused_ptrs;
116 1/1 assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
Tests: T1 T2 T3
117
118 // fifo with more than one storage element
119 end else begin : gen_depth_gt1
120 assign storage_rdata = storage[fifo_rptr];
121
122 always_ff @(posedge clk_i)
123 if (fifo_incr_wptr) begin
124 storage[fifo_wptr] <= wdata_i;
125 end
126 end
127
128 logic [Width-1:0] rdata_int;
129 if (Pass == 1'b1) begin : gen_pass
130 assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131 assign empty = fifo_empty & ~wvalid_i;
132 end else begin : gen_nopass
133 0/1 ==> assign rdata_int = storage_rdata;
134 1/1 assign empty = fifo_empty;
Tests: T1 T2 T3
135 end
136
137 if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138 1/1 assign rdata_o = empty ? Width'(0) : rdata_int;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
| Total | Covered | Percent |
Conditions | 16 | 5 | 31.25 |
Logical | 16 | 5 | 31.25 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 81
EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
-----1----- ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 82
EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
-------------1------------ ---------------2--------------
-1- | -2- | Status | Tests |
0 | 1 | Covered | T1,T2,T3 |
1 | 0 | Not Covered | |
1 | 1 | Not Covered | |
LINE 100
EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Covered | T1,T2,T3 |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 101
EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
----1--- ----2--- ---------------3--------------
-1- | -2- | -3- | Status | Tests |
0 | 1 | 1 | Not Covered | |
1 | 0 | 1 | Not Covered | |
1 | 1 | 0 | Not Covered | |
1 | 1 | 1 | Not Covered | |
LINE 138
EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
----------1----------
-1- | Status | Tests |
0 | Not Covered | |
1 | Covered | T1,T2,T3 |
Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
| Line No. | Total | Covered | Percent |
Branches |
|
7 |
5 |
71.43 |
TERNARY |
138 |
2 |
1 |
50.00 |
IF |
69 |
3 |
3 |
100.00 |
IF |
123 |
2 |
1 |
50.00 |
138 assign rdata_o = empty ? Width'(0) : rdata_int;
-1-
==>
==>
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Not Covered |
|
69 if (!rst_ni) begin
-1-
70 under_rst <= 1'b1;
==>
71 end else if (under_rst) begin
-2-
72 under_rst <= ~under_rst;
==>
73 end
MISSING_ELSE
==>
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Covered |
T1,T2,T3 |
0 |
0 |
Covered |
T1,T2,T3 |
123 if (fifo_incr_wptr) begin
-1-
124 storage[fifo_wptr] <= wdata_i;
==>
125 end
MISSING_ELSE
==>
Branches:
-1- | Status | Tests |
1 |
Not Covered |
|
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo
Assertion Details
DataKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480500434 |
0 |
0 |
0 |
DepthKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480500434 |
480413380 |
0 |
0 |
T1 |
18125 |
18047 |
0 |
0 |
T2 |
1597 |
1499 |
0 |
0 |
T3 |
11309 |
11246 |
0 |
0 |
T4 |
24683 |
24595 |
0 |
0 |
T5 |
9341 |
9244 |
0 |
0 |
T6 |
88558 |
88490 |
0 |
0 |
T7 |
14577 |
14520 |
0 |
0 |
T8 |
21533 |
21466 |
0 |
0 |
T9 |
27558 |
27508 |
0 |
0 |
T10 |
67823 |
67764 |
0 |
0 |
RvalidKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480500434 |
480413380 |
0 |
0 |
T1 |
18125 |
18047 |
0 |
0 |
T2 |
1597 |
1499 |
0 |
0 |
T3 |
11309 |
11246 |
0 |
0 |
T4 |
24683 |
24595 |
0 |
0 |
T5 |
9341 |
9244 |
0 |
0 |
T6 |
88558 |
88490 |
0 |
0 |
T7 |
14577 |
14520 |
0 |
0 |
T8 |
21533 |
21466 |
0 |
0 |
T9 |
27558 |
27508 |
0 |
0 |
T10 |
67823 |
67764 |
0 |
0 |
WreadyKnown_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480500434 |
480413380 |
0 |
0 |
T1 |
18125 |
18047 |
0 |
0 |
T2 |
1597 |
1499 |
0 |
0 |
T3 |
11309 |
11246 |
0 |
0 |
T4 |
24683 |
24595 |
0 |
0 |
T5 |
9341 |
9244 |
0 |
0 |
T6 |
88558 |
88490 |
0 |
0 |
T7 |
14577 |
14520 |
0 |
0 |
T8 |
21533 |
21466 |
0 |
0 |
T9 |
27558 |
27508 |
0 |
0 |
T10 |
67823 |
67764 |
0 |
0 |
gen_normal_fifo.depthShallNotExceedParamDepth
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
480500434 |
0 |
0 |
0 |