Assert Coverage for Module :
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
3123 |
0 |
0 |
T81 |
13298 |
165 |
0 |
0 |
T82 |
14044 |
4 |
0 |
0 |
T83 |
10415 |
1 |
0 |
0 |
T126 |
3998 |
3 |
0 |
0 |
T127 |
18950 |
153 |
0 |
0 |
T128 |
16627 |
282 |
0 |
0 |
T129 |
6017 |
90 |
0 |
0 |
T130 |
28032 |
6 |
0 |
0 |
T138 |
9617 |
195 |
0 |
0 |
T147 |
5126 |
16 |
0 |
0 |
addr_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2302 |
0 |
0 |
T82 |
14044 |
9 |
0 |
0 |
T111 |
2546 |
1 |
0 |
0 |
T145 |
15374 |
14 |
0 |
0 |
T158 |
3960 |
3 |
0 |
0 |
T160 |
6668 |
1 |
0 |
0 |
T183 |
12099 |
24 |
0 |
0 |
T184 |
6704 |
50 |
0 |
0 |
T185 |
21616 |
87 |
0 |
0 |
T186 |
42239 |
257 |
0 |
0 |
T187 |
6450 |
12 |
0 |
0 |
addr_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2377 |
0 |
0 |
T82 |
14044 |
25 |
0 |
0 |
T111 |
2546 |
4 |
0 |
0 |
T145 |
15374 |
37 |
0 |
0 |
T151 |
11418 |
22 |
0 |
0 |
T158 |
3960 |
2 |
0 |
0 |
T183 |
12099 |
14 |
0 |
0 |
T185 |
21616 |
82 |
0 |
0 |
T186 |
42239 |
221 |
0 |
0 |
T187 |
6450 |
34 |
0 |
0 |
T188 |
8221 |
6 |
0 |
0 |
cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2666 |
0 |
0 |
T82 |
14044 |
44 |
0 |
0 |
T111 |
2546 |
4 |
0 |
0 |
T145 |
15374 |
37 |
0 |
0 |
T151 |
11418 |
12 |
0 |
0 |
T160 |
6668 |
11 |
0 |
0 |
T183 |
12099 |
34 |
0 |
0 |
T184 |
6704 |
13 |
0 |
0 |
T185 |
21616 |
54 |
0 |
0 |
T186 |
42239 |
244 |
0 |
0 |
T187 |
6450 |
9 |
0 |
0 |
cmd_filter_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
9420 |
0 |
0 |
T82 |
14044 |
271 |
0 |
0 |
T111 |
2546 |
7 |
0 |
0 |
T145 |
15374 |
130 |
0 |
0 |
T151 |
11418 |
332 |
0 |
0 |
T158 |
3960 |
1 |
0 |
0 |
T160 |
6668 |
3 |
0 |
0 |
T183 |
12099 |
14 |
0 |
0 |
T184 |
6704 |
19 |
0 |
0 |
T185 |
21616 |
72 |
0 |
0 |
T186 |
42239 |
275 |
0 |
0 |
cmd_filter_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
8876 |
0 |
0 |
T82 |
14044 |
140 |
0 |
0 |
T111 |
2546 |
1 |
0 |
0 |
T145 |
15374 |
139 |
0 |
0 |
T151 |
11418 |
249 |
0 |
0 |
T158 |
3960 |
110 |
0 |
0 |
T160 |
6668 |
76 |
0 |
0 |
T183 |
12099 |
16 |
0 |
0 |
T184 |
6704 |
2 |
0 |
0 |
T185 |
21616 |
58 |
0 |
0 |
T186 |
42239 |
224 |
0 |
0 |
cmd_filter_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
9390 |
0 |
0 |
T82 |
14044 |
139 |
0 |
0 |
T111 |
2546 |
7 |
0 |
0 |
T145 |
15374 |
127 |
0 |
0 |
T151 |
11418 |
279 |
0 |
0 |
T158 |
3960 |
116 |
0 |
0 |
T160 |
6668 |
131 |
0 |
0 |
T183 |
12099 |
24 |
0 |
0 |
T184 |
6704 |
9 |
0 |
0 |
T185 |
21616 |
65 |
0 |
0 |
T186 |
42239 |
319 |
0 |
0 |
cmd_filter_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
9006 |
0 |
0 |
T82 |
14044 |
253 |
0 |
0 |
T111 |
2546 |
3 |
0 |
0 |
T145 |
15374 |
153 |
0 |
0 |
T151 |
11418 |
124 |
0 |
0 |
T158 |
3960 |
104 |
0 |
0 |
T160 |
6668 |
8 |
0 |
0 |
T183 |
12099 |
16 |
0 |
0 |
T184 |
6704 |
17 |
0 |
0 |
T185 |
21616 |
135 |
0 |
0 |
T186 |
42239 |
263 |
0 |
0 |
cmd_filter_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
9415 |
0 |
0 |
T82 |
14044 |
22 |
0 |
0 |
T145 |
15374 |
22 |
0 |
0 |
T151 |
11418 |
235 |
0 |
0 |
T158 |
3960 |
82 |
0 |
0 |
T160 |
6668 |
10 |
0 |
0 |
T183 |
12099 |
23 |
0 |
0 |
T184 |
6704 |
15 |
0 |
0 |
T185 |
21616 |
81 |
0 |
0 |
T186 |
42239 |
231 |
0 |
0 |
T187 |
6450 |
17 |
0 |
0 |
cmd_filter_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
10245 |
0 |
0 |
T82 |
14044 |
32 |
0 |
0 |
T145 |
15374 |
358 |
0 |
0 |
T151 |
11418 |
16 |
0 |
0 |
T160 |
6668 |
165 |
0 |
0 |
T183 |
12099 |
47 |
0 |
0 |
T184 |
6704 |
16 |
0 |
0 |
T185 |
21616 |
49 |
0 |
0 |
T186 |
42239 |
251 |
0 |
0 |
T187 |
6450 |
7 |
0 |
0 |
T188 |
8221 |
250 |
0 |
0 |
cmd_filter_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
9609 |
0 |
0 |
T82 |
14044 |
123 |
0 |
0 |
T145 |
15374 |
230 |
0 |
0 |
T151 |
11418 |
136 |
0 |
0 |
T158 |
3960 |
1 |
0 |
0 |
T160 |
6668 |
97 |
0 |
0 |
T183 |
12099 |
28 |
0 |
0 |
T184 |
6704 |
54 |
0 |
0 |
T185 |
21616 |
45 |
0 |
0 |
T186 |
42239 |
239 |
0 |
0 |
T187 |
6450 |
24 |
0 |
0 |
cmd_filter_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
9119 |
0 |
0 |
T82 |
14044 |
19 |
0 |
0 |
T111 |
2546 |
7 |
0 |
0 |
T145 |
15374 |
151 |
0 |
0 |
T151 |
11418 |
216 |
0 |
0 |
T158 |
3960 |
126 |
0 |
0 |
T160 |
6668 |
79 |
0 |
0 |
T183 |
12099 |
31 |
0 |
0 |
T184 |
6704 |
28 |
0 |
0 |
T185 |
21616 |
58 |
0 |
0 |
T186 |
42239 |
294 |
0 |
0 |
cmd_info_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
4827 |
0 |
0 |
T82 |
14044 |
54 |
0 |
0 |
T111 |
2546 |
9 |
0 |
0 |
T145 |
15374 |
98 |
0 |
0 |
T151 |
11418 |
65 |
0 |
0 |
T158 |
3960 |
1 |
0 |
0 |
T160 |
6668 |
3 |
0 |
0 |
T183 |
12099 |
30 |
0 |
0 |
T185 |
21616 |
54 |
0 |
0 |
T186 |
42239 |
241 |
0 |
0 |
T188 |
8221 |
8 |
0 |
0 |
cmd_info_10_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
4931 |
0 |
0 |
T82 |
14044 |
61 |
0 |
0 |
T111 |
2546 |
1 |
0 |
0 |
T145 |
15374 |
102 |
0 |
0 |
T151 |
11418 |
122 |
0 |
0 |
T160 |
6668 |
46 |
0 |
0 |
T183 |
12099 |
14 |
0 |
0 |
T184 |
6704 |
26 |
0 |
0 |
T185 |
21616 |
52 |
0 |
0 |
T186 |
42239 |
318 |
0 |
0 |
T187 |
6450 |
14 |
0 |
0 |
cmd_info_11_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5178 |
0 |
0 |
T82 |
14044 |
96 |
0 |
0 |
T145 |
15374 |
136 |
0 |
0 |
T151 |
11418 |
114 |
0 |
0 |
T158 |
3960 |
26 |
0 |
0 |
T160 |
6668 |
61 |
0 |
0 |
T183 |
12099 |
22 |
0 |
0 |
T184 |
6704 |
32 |
0 |
0 |
T185 |
21616 |
83 |
0 |
0 |
T186 |
42239 |
268 |
0 |
0 |
T187 |
6450 |
12 |
0 |
0 |
cmd_info_12_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5019 |
0 |
0 |
T82 |
14044 |
95 |
0 |
0 |
T111 |
2546 |
8 |
0 |
0 |
T145 |
15374 |
83 |
0 |
0 |
T151 |
11418 |
108 |
0 |
0 |
T158 |
3960 |
1 |
0 |
0 |
T160 |
6668 |
21 |
0 |
0 |
T183 |
12099 |
56 |
0 |
0 |
T184 |
6704 |
5 |
0 |
0 |
T185 |
21616 |
23 |
0 |
0 |
T186 |
42239 |
267 |
0 |
0 |
cmd_info_13_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5586 |
0 |
0 |
T82 |
14044 |
119 |
0 |
0 |
T111 |
2546 |
2 |
0 |
0 |
T145 |
15374 |
140 |
0 |
0 |
T151 |
11418 |
82 |
0 |
0 |
T158 |
3960 |
3 |
0 |
0 |
T160 |
6668 |
28 |
0 |
0 |
T183 |
12099 |
20 |
0 |
0 |
T184 |
6704 |
36 |
0 |
0 |
T185 |
21616 |
18 |
0 |
0 |
T186 |
42239 |
237 |
0 |
0 |
cmd_info_14_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
4653 |
0 |
0 |
T82 |
14044 |
71 |
0 |
0 |
T127 |
18950 |
3 |
0 |
0 |
T145 |
15374 |
68 |
0 |
0 |
T151 |
11418 |
101 |
0 |
0 |
T158 |
3960 |
6 |
0 |
0 |
T160 |
6668 |
3 |
0 |
0 |
T183 |
12099 |
7 |
0 |
0 |
T184 |
6704 |
5 |
0 |
0 |
T185 |
21616 |
66 |
0 |
0 |
T186 |
42239 |
248 |
0 |
0 |
cmd_info_15_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5020 |
0 |
0 |
T82 |
14044 |
61 |
0 |
0 |
T111 |
2546 |
4 |
0 |
0 |
T145 |
15374 |
146 |
0 |
0 |
T151 |
11418 |
56 |
0 |
0 |
T158 |
3960 |
4 |
0 |
0 |
T160 |
6668 |
55 |
0 |
0 |
T183 |
12099 |
8 |
0 |
0 |
T184 |
6704 |
17 |
0 |
0 |
T185 |
21616 |
81 |
0 |
0 |
T186 |
42239 |
259 |
0 |
0 |
cmd_info_16_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5091 |
0 |
0 |
T82 |
14044 |
123 |
0 |
0 |
T111 |
2546 |
2 |
0 |
0 |
T145 |
15374 |
129 |
0 |
0 |
T151 |
11418 |
101 |
0 |
0 |
T158 |
3960 |
6 |
0 |
0 |
T160 |
6668 |
35 |
0 |
0 |
T183 |
12099 |
27 |
0 |
0 |
T184 |
6704 |
20 |
0 |
0 |
T185 |
21616 |
60 |
0 |
0 |
T186 |
42239 |
233 |
0 |
0 |
cmd_info_17_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
4958 |
0 |
0 |
T82 |
14044 |
55 |
0 |
0 |
T111 |
2546 |
3 |
0 |
0 |
T145 |
15374 |
43 |
0 |
0 |
T151 |
11418 |
47 |
0 |
0 |
T158 |
3960 |
43 |
0 |
0 |
T160 |
6668 |
8 |
0 |
0 |
T183 |
12099 |
22 |
0 |
0 |
T184 |
6704 |
10 |
0 |
0 |
T185 |
21616 |
62 |
0 |
0 |
T186 |
42239 |
255 |
0 |
0 |
cmd_info_18_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5350 |
0 |
0 |
T82 |
14044 |
135 |
0 |
0 |
T111 |
2546 |
2 |
0 |
0 |
T145 |
15374 |
99 |
0 |
0 |
T151 |
11418 |
106 |
0 |
0 |
T158 |
3960 |
38 |
0 |
0 |
T160 |
6668 |
69 |
0 |
0 |
T183 |
12099 |
4 |
0 |
0 |
T184 |
6704 |
45 |
0 |
0 |
T185 |
21616 |
63 |
0 |
0 |
T186 |
42239 |
259 |
0 |
0 |
cmd_info_19_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5007 |
0 |
0 |
T82 |
14044 |
118 |
0 |
0 |
T111 |
2546 |
9 |
0 |
0 |
T145 |
15374 |
132 |
0 |
0 |
T151 |
11418 |
131 |
0 |
0 |
T158 |
3960 |
10 |
0 |
0 |
T160 |
6668 |
4 |
0 |
0 |
T183 |
12099 |
30 |
0 |
0 |
T184 |
6704 |
63 |
0 |
0 |
T185 |
21616 |
60 |
0 |
0 |
T186 |
42239 |
262 |
0 |
0 |
cmd_info_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
4898 |
0 |
0 |
T82 |
14044 |
113 |
0 |
0 |
T111 |
2546 |
3 |
0 |
0 |
T145 |
15374 |
70 |
0 |
0 |
T151 |
11418 |
169 |
0 |
0 |
T158 |
3960 |
59 |
0 |
0 |
T160 |
6668 |
26 |
0 |
0 |
T183 |
12099 |
41 |
0 |
0 |
T184 |
6704 |
3 |
0 |
0 |
T185 |
21616 |
75 |
0 |
0 |
T186 |
42239 |
280 |
0 |
0 |
cmd_info_20_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5331 |
0 |
0 |
T82 |
14044 |
20 |
0 |
0 |
T111 |
2546 |
3 |
0 |
0 |
T145 |
15374 |
111 |
0 |
0 |
T151 |
11418 |
117 |
0 |
0 |
T158 |
3960 |
32 |
0 |
0 |
T160 |
6668 |
31 |
0 |
0 |
T183 |
12099 |
29 |
0 |
0 |
T184 |
6704 |
15 |
0 |
0 |
T185 |
21616 |
63 |
0 |
0 |
T186 |
42239 |
295 |
0 |
0 |
cmd_info_21_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5484 |
0 |
0 |
T82 |
14044 |
54 |
0 |
0 |
T111 |
2546 |
7 |
0 |
0 |
T145 |
15374 |
131 |
0 |
0 |
T151 |
11418 |
103 |
0 |
0 |
T158 |
3960 |
2 |
0 |
0 |
T160 |
6668 |
6 |
0 |
0 |
T183 |
12099 |
24 |
0 |
0 |
T184 |
6704 |
43 |
0 |
0 |
T185 |
21616 |
44 |
0 |
0 |
T186 |
42239 |
256 |
0 |
0 |
cmd_info_22_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
4942 |
0 |
0 |
T82 |
14044 |
69 |
0 |
0 |
T111 |
2546 |
1 |
0 |
0 |
T145 |
15374 |
19 |
0 |
0 |
T151 |
11418 |
143 |
0 |
0 |
T158 |
3960 |
4 |
0 |
0 |
T160 |
6668 |
24 |
0 |
0 |
T183 |
12099 |
15 |
0 |
0 |
T184 |
6704 |
20 |
0 |
0 |
T185 |
21616 |
77 |
0 |
0 |
T186 |
42239 |
255 |
0 |
0 |
cmd_info_23_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
4663 |
0 |
0 |
T82 |
14044 |
21 |
0 |
0 |
T145 |
15374 |
108 |
0 |
0 |
T151 |
11418 |
46 |
0 |
0 |
T158 |
3960 |
61 |
0 |
0 |
T183 |
12099 |
21 |
0 |
0 |
T184 |
6704 |
7 |
0 |
0 |
T185 |
21616 |
24 |
0 |
0 |
T186 |
42239 |
276 |
0 |
0 |
T187 |
6450 |
6 |
0 |
0 |
T188 |
8221 |
7 |
0 |
0 |
cmd_info_2_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
4929 |
0 |
0 |
T82 |
14044 |
106 |
0 |
0 |
T111 |
2546 |
8 |
0 |
0 |
T145 |
15374 |
79 |
0 |
0 |
T151 |
11418 |
40 |
0 |
0 |
T160 |
6668 |
34 |
0 |
0 |
T183 |
12099 |
9 |
0 |
0 |
T184 |
6704 |
17 |
0 |
0 |
T185 |
21616 |
73 |
0 |
0 |
T186 |
42239 |
261 |
0 |
0 |
T187 |
6450 |
14 |
0 |
0 |
cmd_info_3_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5016 |
0 |
0 |
T82 |
14044 |
67 |
0 |
0 |
T111 |
2546 |
2 |
0 |
0 |
T145 |
15374 |
103 |
0 |
0 |
T151 |
11418 |
85 |
0 |
0 |
T158 |
3960 |
45 |
0 |
0 |
T160 |
6668 |
17 |
0 |
0 |
T183 |
12099 |
4 |
0 |
0 |
T184 |
6704 |
19 |
0 |
0 |
T185 |
21616 |
75 |
0 |
0 |
T186 |
42239 |
304 |
0 |
0 |
cmd_info_4_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5051 |
0 |
0 |
T82 |
14044 |
101 |
0 |
0 |
T111 |
2546 |
8 |
0 |
0 |
T145 |
15374 |
61 |
0 |
0 |
T151 |
11418 |
72 |
0 |
0 |
T158 |
3960 |
64 |
0 |
0 |
T160 |
6668 |
43 |
0 |
0 |
T183 |
12099 |
56 |
0 |
0 |
T184 |
6704 |
8 |
0 |
0 |
T185 |
21616 |
88 |
0 |
0 |
T186 |
42239 |
264 |
0 |
0 |
cmd_info_5_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5374 |
0 |
0 |
T82 |
14044 |
123 |
0 |
0 |
T145 |
15374 |
139 |
0 |
0 |
T151 |
11418 |
64 |
0 |
0 |
T158 |
3960 |
3 |
0 |
0 |
T160 |
6668 |
42 |
0 |
0 |
T183 |
12099 |
20 |
0 |
0 |
T184 |
6704 |
29 |
0 |
0 |
T185 |
21616 |
89 |
0 |
0 |
T186 |
42239 |
310 |
0 |
0 |
T188 |
8221 |
103 |
0 |
0 |
cmd_info_6_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5327 |
0 |
0 |
T82 |
14044 |
143 |
0 |
0 |
T111 |
2546 |
4 |
0 |
0 |
T145 |
15374 |
117 |
0 |
0 |
T151 |
11418 |
72 |
0 |
0 |
T158 |
3960 |
48 |
0 |
0 |
T160 |
6668 |
3 |
0 |
0 |
T183 |
12099 |
38 |
0 |
0 |
T184 |
6704 |
17 |
0 |
0 |
T185 |
21616 |
52 |
0 |
0 |
T186 |
42239 |
247 |
0 |
0 |
cmd_info_7_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
4843 |
0 |
0 |
T82 |
14044 |
49 |
0 |
0 |
T111 |
2546 |
8 |
0 |
0 |
T145 |
15374 |
113 |
0 |
0 |
T151 |
11418 |
11 |
0 |
0 |
T158 |
3960 |
41 |
0 |
0 |
T160 |
6668 |
22 |
0 |
0 |
T184 |
6704 |
16 |
0 |
0 |
T185 |
21616 |
61 |
0 |
0 |
T186 |
42239 |
218 |
0 |
0 |
T187 |
6450 |
13 |
0 |
0 |
cmd_info_8_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5183 |
0 |
0 |
T82 |
14044 |
145 |
0 |
0 |
T111 |
2546 |
4 |
0 |
0 |
T145 |
15374 |
94 |
0 |
0 |
T151 |
11418 |
129 |
0 |
0 |
T158 |
3960 |
2 |
0 |
0 |
T160 |
6668 |
8 |
0 |
0 |
T183 |
12099 |
11 |
0 |
0 |
T184 |
6704 |
13 |
0 |
0 |
T185 |
21616 |
42 |
0 |
0 |
T186 |
42239 |
297 |
0 |
0 |
cmd_info_9_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
5115 |
0 |
0 |
T82 |
14044 |
61 |
0 |
0 |
T111 |
2546 |
9 |
0 |
0 |
T145 |
15374 |
116 |
0 |
0 |
T151 |
11418 |
114 |
0 |
0 |
T158 |
3960 |
1 |
0 |
0 |
T160 |
6668 |
28 |
0 |
0 |
T183 |
12099 |
22 |
0 |
0 |
T184 |
6704 |
34 |
0 |
0 |
T185 |
21616 |
96 |
0 |
0 |
T186 |
42239 |
248 |
0 |
0 |
cmd_info_en4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2704 |
0 |
0 |
T82 |
14044 |
38 |
0 |
0 |
T111 |
2546 |
7 |
0 |
0 |
T145 |
15374 |
32 |
0 |
0 |
T151 |
11418 |
7 |
0 |
0 |
T158 |
3960 |
11 |
0 |
0 |
T160 |
6668 |
5 |
0 |
0 |
T183 |
12099 |
13 |
0 |
0 |
T184 |
6704 |
28 |
0 |
0 |
T185 |
21616 |
96 |
0 |
0 |
T186 |
42239 |
274 |
0 |
0 |
cmd_info_ex4b_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2559 |
0 |
0 |
T82 |
14044 |
18 |
0 |
0 |
T111 |
2546 |
6 |
0 |
0 |
T145 |
15374 |
28 |
0 |
0 |
T151 |
11418 |
22 |
0 |
0 |
T183 |
12099 |
9 |
0 |
0 |
T184 |
6704 |
21 |
0 |
0 |
T185 |
21616 |
79 |
0 |
0 |
T186 |
42239 |
268 |
0 |
0 |
T187 |
6450 |
3 |
0 |
0 |
T188 |
8221 |
6 |
0 |
0 |
cmd_info_wrdi_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2576 |
0 |
0 |
T82 |
14044 |
32 |
0 |
0 |
T145 |
15374 |
27 |
0 |
0 |
T151 |
11418 |
12 |
0 |
0 |
T158 |
3960 |
7 |
0 |
0 |
T160 |
6668 |
10 |
0 |
0 |
T183 |
12099 |
30 |
0 |
0 |
T184 |
6704 |
11 |
0 |
0 |
T185 |
21616 |
67 |
0 |
0 |
T186 |
42239 |
246 |
0 |
0 |
T187 |
6450 |
7 |
0 |
0 |
cmd_info_wren_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2703 |
0 |
0 |
T82 |
14044 |
43 |
0 |
0 |
T111 |
2546 |
2 |
0 |
0 |
T140 |
16398 |
2 |
0 |
0 |
T145 |
15374 |
19 |
0 |
0 |
T151 |
11418 |
16 |
0 |
0 |
T158 |
3960 |
13 |
0 |
0 |
T183 |
12099 |
13 |
0 |
0 |
T184 |
6704 |
7 |
0 |
0 |
T185 |
21616 |
83 |
0 |
0 |
T186 |
42239 |
300 |
0 |
0 |
intercept_en_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2968 |
0 |
0 |
T82 |
14044 |
48 |
0 |
0 |
T145 |
15374 |
46 |
0 |
0 |
T151 |
11418 |
20 |
0 |
0 |
T158 |
3960 |
6 |
0 |
0 |
T160 |
6668 |
11 |
0 |
0 |
T183 |
12099 |
32 |
0 |
0 |
T184 |
6704 |
10 |
0 |
0 |
T185 |
21616 |
61 |
0 |
0 |
T186 |
42239 |
235 |
0 |
0 |
T188 |
8221 |
17 |
0 |
0 |
intr_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
4772 |
0 |
0 |
T93 |
0 |
15 |
0 |
0 |
T183 |
0 |
50 |
0 |
0 |
T189 |
5432 |
21 |
0 |
0 |
T190 |
447124 |
25 |
0 |
0 |
T191 |
0 |
63 |
0 |
0 |
T192 |
0 |
4 |
0 |
0 |
T193 |
0 |
34 |
0 |
0 |
T194 |
0 |
47 |
0 |
0 |
T195 |
0 |
67 |
0 |
0 |
T196 |
0 |
30 |
0 |
0 |
T197 |
245030 |
0 |
0 |
0 |
T198 |
1017 |
0 |
0 |
0 |
T199 |
397094 |
0 |
0 |
0 |
T200 |
20030 |
0 |
0 |
0 |
T201 |
186345 |
0 |
0 |
0 |
T202 |
1356 |
0 |
0 |
0 |
T203 |
39797 |
0 |
0 |
0 |
T204 |
11355 |
0 |
0 |
0 |
jedec_cc_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2559 |
0 |
0 |
T82 |
14044 |
29 |
0 |
0 |
T111 |
2546 |
1 |
0 |
0 |
T145 |
15374 |
36 |
0 |
0 |
T151 |
11418 |
22 |
0 |
0 |
T158 |
3960 |
17 |
0 |
0 |
T160 |
6668 |
11 |
0 |
0 |
T183 |
12099 |
27 |
0 |
0 |
T184 |
6704 |
30 |
0 |
0 |
T185 |
21616 |
50 |
0 |
0 |
T186 |
42239 |
254 |
0 |
0 |
jedec_id_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2680 |
0 |
0 |
T82 |
14044 |
33 |
0 |
0 |
T111 |
2546 |
2 |
0 |
0 |
T145 |
15374 |
26 |
0 |
0 |
T151 |
11418 |
12 |
0 |
0 |
T158 |
3960 |
2 |
0 |
0 |
T160 |
6668 |
19 |
0 |
0 |
T183 |
12099 |
18 |
0 |
0 |
T184 |
6704 |
6 |
0 |
0 |
T185 |
21616 |
45 |
0 |
0 |
T186 |
42239 |
287 |
0 |
0 |
mailbox_addr_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2570 |
0 |
0 |
T81 |
13298 |
4 |
0 |
0 |
T82 |
14044 |
24 |
0 |
0 |
T111 |
2546 |
1 |
0 |
0 |
T145 |
15374 |
12 |
0 |
0 |
T151 |
11418 |
14 |
0 |
0 |
T158 |
3960 |
1 |
0 |
0 |
T160 |
6668 |
3 |
0 |
0 |
T183 |
12099 |
3 |
0 |
0 |
T184 |
6704 |
54 |
0 |
0 |
T185 |
21616 |
68 |
0 |
0 |
payload_swap_data_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2472 |
0 |
0 |
T82 |
14044 |
36 |
0 |
0 |
T111 |
2546 |
7 |
0 |
0 |
T145 |
15374 |
15 |
0 |
0 |
T151 |
11418 |
13 |
0 |
0 |
T160 |
6668 |
8 |
0 |
0 |
T183 |
12099 |
27 |
0 |
0 |
T184 |
6704 |
27 |
0 |
0 |
T185 |
21616 |
65 |
0 |
0 |
T186 |
42239 |
261 |
0 |
0 |
T187 |
6450 |
21 |
0 |
0 |
payload_swap_mask_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2201 |
0 |
0 |
T82 |
14044 |
21 |
0 |
0 |
T111 |
2546 |
4 |
0 |
0 |
T145 |
15374 |
35 |
0 |
0 |
T151 |
11418 |
2 |
0 |
0 |
T158 |
3960 |
4 |
0 |
0 |
T160 |
6668 |
6 |
0 |
0 |
T183 |
12099 |
25 |
0 |
0 |
T184 |
6704 |
15 |
0 |
0 |
T185 |
21616 |
11 |
0 |
0 |
T186 |
42239 |
259 |
0 |
0 |
read_threshold_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2421 |
0 |
0 |
T82 |
14044 |
13 |
0 |
0 |
T111 |
2546 |
2 |
0 |
0 |
T145 |
15374 |
15 |
0 |
0 |
T151 |
11418 |
17 |
0 |
0 |
T158 |
3960 |
6 |
0 |
0 |
T183 |
12099 |
44 |
0 |
0 |
T184 |
6704 |
36 |
0 |
0 |
T185 |
21616 |
55 |
0 |
0 |
T186 |
42239 |
297 |
0 |
0 |
T187 |
6450 |
23 |
0 |
0 |
tpm_access_0_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2792 |
0 |
0 |
T81 |
13298 |
7 |
0 |
0 |
T82 |
14044 |
31 |
0 |
0 |
T145 |
15374 |
34 |
0 |
0 |
T151 |
11418 |
44 |
0 |
0 |
T158 |
3960 |
21 |
0 |
0 |
T160 |
6668 |
2 |
0 |
0 |
T183 |
12099 |
15 |
0 |
0 |
T184 |
6704 |
8 |
0 |
0 |
T185 |
21616 |
58 |
0 |
0 |
T186 |
42239 |
289 |
0 |
0 |
tpm_access_1_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2460 |
0 |
0 |
T82 |
14044 |
32 |
0 |
0 |
T111 |
2546 |
1 |
0 |
0 |
T145 |
15374 |
9 |
0 |
0 |
T151 |
11418 |
21 |
0 |
0 |
T158 |
3960 |
1 |
0 |
0 |
T160 |
6668 |
2 |
0 |
0 |
T183 |
12099 |
18 |
0 |
0 |
T185 |
21616 |
104 |
0 |
0 |
T186 |
42239 |
304 |
0 |
0 |
T187 |
6450 |
8 |
0 |
0 |
tpm_cfg_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
3243 |
0 |
0 |
T82 |
14044 |
66 |
0 |
0 |
T111 |
2546 |
1 |
0 |
0 |
T145 |
15374 |
61 |
0 |
0 |
T151 |
11418 |
40 |
0 |
0 |
T160 |
6668 |
23 |
0 |
0 |
T183 |
12099 |
10 |
0 |
0 |
T184 |
6704 |
25 |
0 |
0 |
T185 |
21616 |
119 |
0 |
0 |
T186 |
42239 |
240 |
0 |
0 |
T187 |
6450 |
28 |
0 |
0 |
tpm_did_vid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2584 |
0 |
0 |
T82 |
14044 |
21 |
0 |
0 |
T111 |
2546 |
4 |
0 |
0 |
T145 |
15374 |
22 |
0 |
0 |
T151 |
11418 |
14 |
0 |
0 |
T158 |
3960 |
5 |
0 |
0 |
T160 |
6668 |
8 |
0 |
0 |
T183 |
12099 |
21 |
0 |
0 |
T184 |
6704 |
32 |
0 |
0 |
T185 |
21616 |
53 |
0 |
0 |
T186 |
42239 |
271 |
0 |
0 |
tpm_int_enable_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2259 |
0 |
0 |
T82 |
14044 |
17 |
0 |
0 |
T111 |
2546 |
4 |
0 |
0 |
T145 |
15374 |
31 |
0 |
0 |
T151 |
11418 |
9 |
0 |
0 |
T158 |
3960 |
3 |
0 |
0 |
T160 |
6668 |
4 |
0 |
0 |
T183 |
12099 |
5 |
0 |
0 |
T184 |
6704 |
38 |
0 |
0 |
T185 |
21616 |
52 |
0 |
0 |
T186 |
42239 |
206 |
0 |
0 |
tpm_int_status_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2417 |
0 |
0 |
T82 |
14044 |
25 |
0 |
0 |
T111 |
2546 |
7 |
0 |
0 |
T145 |
15374 |
27 |
0 |
0 |
T151 |
11418 |
11 |
0 |
0 |
T160 |
6668 |
6 |
0 |
0 |
T184 |
6704 |
40 |
0 |
0 |
T185 |
21616 |
75 |
0 |
0 |
T186 |
42239 |
249 |
0 |
0 |
T187 |
6450 |
3 |
0 |
0 |
T188 |
8221 |
2 |
0 |
0 |
tpm_int_vector_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2365 |
0 |
0 |
T82 |
14044 |
10 |
0 |
0 |
T111 |
2546 |
6 |
0 |
0 |
T145 |
15374 |
25 |
0 |
0 |
T151 |
11418 |
11 |
0 |
0 |
T158 |
3960 |
3 |
0 |
0 |
T160 |
6668 |
10 |
0 |
0 |
T183 |
12099 |
12 |
0 |
0 |
T184 |
6704 |
24 |
0 |
0 |
T185 |
21616 |
57 |
0 |
0 |
T186 |
42239 |
279 |
0 |
0 |
tpm_intf_capability_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2356 |
0 |
0 |
T82 |
14044 |
23 |
0 |
0 |
T111 |
2546 |
3 |
0 |
0 |
T145 |
15374 |
23 |
0 |
0 |
T151 |
11418 |
15 |
0 |
0 |
T158 |
3960 |
3 |
0 |
0 |
T160 |
6668 |
8 |
0 |
0 |
T183 |
12099 |
7 |
0 |
0 |
T184 |
6704 |
14 |
0 |
0 |
T185 |
21616 |
63 |
0 |
0 |
T186 |
42239 |
271 |
0 |
0 |
tpm_rid_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2413 |
0 |
0 |
T82 |
14044 |
10 |
0 |
0 |
T111 |
2546 |
3 |
0 |
0 |
T145 |
15374 |
17 |
0 |
0 |
T151 |
11418 |
17 |
0 |
0 |
T158 |
3960 |
4 |
0 |
0 |
T160 |
6668 |
2 |
0 |
0 |
T183 |
12099 |
19 |
0 |
0 |
T184 |
6704 |
22 |
0 |
0 |
T185 |
21616 |
123 |
0 |
0 |
T186 |
42239 |
255 |
0 |
0 |
tpm_sts_rd_A
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
482904819 |
2321 |
0 |
0 |
T82 |
14044 |
6 |
0 |
0 |
T111 |
2546 |
2 |
0 |
0 |
T145 |
15374 |
17 |
0 |
0 |
T151 |
11418 |
4 |
0 |
0 |
T158 |
3960 |
9 |
0 |
0 |
T160 |
6668 |
3 |
0 |
0 |
T183 |
12099 |
19 |
0 |
0 |
T184 |
6704 |
16 |
0 |
0 |
T185 |
21616 |
83 |
0 |
0 |
T186 |
42239 |
245 |
0 |
0 |