Unified Coverage Report :: Module Instance :: tb.dut.u_readcmd.u_readsram.u_sram_fifo

Module Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.18	100.00	72.73			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.63	95.00	76.19			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_readcmd.u_readsram.u_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.45	100.00	81.82			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.62	100.00	90.48			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.77	98.25	100.00		100.00	90.62	100.00	u_readsram

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
63.76	85.71	31.25			71.43	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
60.74	84.62	36.11			55.56	66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
66.67	100.00	33.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	56.48	84.00	40.00			45.45

Module Instance : tb.dut.u_spi_tpm.u_sram_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.32	100.00	77.27			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.23	95.00	78.57			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
95.79	99.29	91.20		91.67	96.77	100.00	u_spi_tpm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.06	100.00	56.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.36	100.00	75.00			94.44	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.67	100.00	83.33					u_arbiter

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	93.64	100.00	90.00			90.91

Module Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.19	100.00	68.75			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.33	95.00	75.00			83.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.14	94.52	60.33			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	81.58	92.00	80.00			72.73

Module Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.34	80.00	31.25			71.43	66.67

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
62.99	82.50	47.22			55.56	66.67

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.14	94.52	60.33			73.08	84.62	u_tlul2sram_egress

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	63.15	84.00	60.00			45.45

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T6 T8 T9 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T6 T8 T9 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T9 T11 T12 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T4 T5 T6 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T9 T11 T12 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T9 T11 T12 

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Covered	Percent
Conditions	22	16	72.73
Logical	22	16	72.73
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T9

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Not Covered
1	1	Covered	T9,T11,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T8,T9
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T9,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T12

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T12

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T11,T12

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T12
1	0	Covered	T9,T11,T12
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T1,T2,T3

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
0	0	Covered	T6,T8,T9

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	157354583	24214652	0	0
DataKnown_AKnownEnable	157354583	128988919	0	0
DepthKnown_A	157354583	128988919	0	0
RvalidKnown_A	157354583	128988919	0	0
WreadyKnown_A	157354583	128988919	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	157354583	24214652	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	24214652	0	0
T9	22464	3100	0	0
T10	57680	0	0	0
T11	12656	11141	0	0
T12	148174	15840	0	0
T13	105604	13537	0	0
T16	149029	30739	0	0
T17	31267	9930	0	0
T26	939	0	0	0
T27	1360	0	0	0
T28	82139	0	0	0
T29	0	8956	0	0
T38	0	18783	0	0
T41	0	20768	0	0
T53	0	17571	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	128988919	0	0
T6	28992	28992	0	0
T7	30692	0	0	0
T8	52748	52096	0	0
T9	22464	22464	0	0
T10	57680	57680	0	0
T11	12656	12401	0	0
T12	148174	148174	0	0
T13	105604	105346	0	0
T16	149029	148721	0	0
T17	0	30900	0	0
T18	0	48272	0	0
T26	939	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	128988919	0	0
T6	28992	28992	0	0
T7	30692	0	0	0
T8	52748	52096	0	0
T9	22464	22464	0	0
T10	57680	57680	0	0
T11	12656	12401	0	0
T12	148174	148174	0	0
T13	105604	105346	0	0
T16	149029	148721	0	0
T17	0	30900	0	0
T18	0	48272	0	0
T26	939	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	128988919	0	0
T6	28992	28992	0	0
T7	30692	0	0	0
T8	52748	52096	0	0
T9	22464	22464	0	0
T10	57680	57680	0	0
T11	12656	12401	0	0
T12	148174	148174	0	0
T13	105604	105346	0	0
T16	149029	148721	0	0
T17	0	30900	0	0
T18	0	48272	0	0
T26	939	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	128988919	0	0
T6	28992	28992	0	0
T7	30692	0	0	0
T8	52748	52096	0	0
T9	22464	22464	0	0
T10	57680	57680	0	0
T11	12656	12401	0	0
T12	148174	148174	0	0
T13	105604	105346	0	0
T16	149029	148721	0	0
T17	0	30900	0	0
T18	0	48272	0	0
T26	939	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	24214652	0	0
T9	22464	3100	0	0
T10	57680	0	0	0
T11	12656	11141	0	0
T12	148174	15840	0	0
T13	105604	13537	0	0
T16	149029	30739	0	0
T17	31267	9930	0	0
T26	939	0	0	0
T27	1360	0	0	0
T28	82139	0	0	0
T29	0	8956	0	0
T38	0	18783	0	0
T41	0	20768	0	0
T53	0	17571	0	0

Line Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T6 T8 T9 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T6 T8 T9 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T4 T5 T6 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T9 T11 T12 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T9 T11 T12 

---

Cond Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Covered	Percent
Conditions	22	18	81.82
Logical	22	18	81.82
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T9

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Not Covered
1	1	Covered	T9,T11,T12

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T8,T9
1	0	1	Covered	T9,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T12

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T9,T11,T12
1	1	0	Not Covered
1	1	1	Covered	T9,T11,T12

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T9,T11,T12

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T9,T11,T12

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T9,T11,T12
1	0	Covered	T9,T11,T12
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T1,T2,T3

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
0	0	Covered	T6,T8,T9

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T12
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_readcmd.u_readsram.u_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	157354583	25447968	0	0
DataKnown_AKnownEnable	157354583	128988919	0	0
DepthKnown_A	157354583	128988919	0	0
RvalidKnown_A	157354583	128988919	0	0
WreadyKnown_A	157354583	128988919	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	157354583	25447968	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	25447968	0	0
T9	22464	3296	0	0
T10	57680	0	0	0
T11	12656	12081	0	0
T12	148174	16468	0	0
T13	105604	14362	0	0
T16	149029	31902	0	0
T17	31267	10244	0	0
T26	939	0	0	0
T27	1360	0	0	0
T28	82139	0	0	0
T29	0	9366	0	0
T38	0	19784	0	0
T41	0	22026	0	0
T53	0	18518	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	128988919	0	0
T6	28992	28992	0	0
T7	30692	0	0	0
T8	52748	52096	0	0
T9	22464	22464	0	0
T10	57680	57680	0	0
T11	12656	12401	0	0
T12	148174	148174	0	0
T13	105604	105346	0	0
T16	149029	148721	0	0
T17	0	30900	0	0
T18	0	48272	0	0
T26	939	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	128988919	0	0
T6	28992	28992	0	0
T7	30692	0	0	0
T8	52748	52096	0	0
T9	22464	22464	0	0
T10	57680	57680	0	0
T11	12656	12401	0	0
T12	148174	148174	0	0
T13	105604	105346	0	0
T16	149029	148721	0	0
T17	0	30900	0	0
T18	0	48272	0	0
T26	939	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	128988919	0	0
T6	28992	28992	0	0
T7	30692	0	0	0
T8	52748	52096	0	0
T9	22464	22464	0	0
T10	57680	57680	0	0
T11	12656	12401	0	0
T12	148174	148174	0	0
T13	105604	105346	0	0
T16	149029	148721	0	0
T17	0	30900	0	0
T18	0	48272	0	0
T26	939	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	128988919	0	0
T6	28992	28992	0	0
T7	30692	0	0	0
T8	52748	52096	0	0
T9	22464	22464	0	0
T10	57680	57680	0	0
T11	12656	12401	0	0
T12	148174	148174	0	0
T13	105604	105346	0	0
T16	149029	148721	0	0
T17	0	30900	0	0
T18	0	48272	0	0
T26	939	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	25447968	0	0
T9	22464	3296	0	0
T10	57680	0	0	0
T11	12656	12081	0	0
T12	148174	16468	0	0
T13	105604	14362	0	0
T16	149029	31902	0	0
T17	31267	10244	0	0
T26	939	0	0	0
T27	1360	0	0	0
T28	82139	0	0	0
T29	0	9366	0	0
T38	0	19784	0	0
T41	0	22026	0	0
T53	0	18518	0	0

Line Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	12	85.71
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	1	50.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T6 T8 T9 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T6 T8 T9 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T4 T5 T6 
124        0/1     ==>            storage[fifo_wptr] <= wdata_i;
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        0/1     ==>        assign rdata_int = storage_rdata;
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T6,T8,T9

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T6,T8,T9
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (3'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T6,T8,T9
0	0	Covered	T6,T8,T9

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_upload.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	4	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	4	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	157354583	0	0	0
DataKnown_AKnownEnable	157354583	128988919	0	0
DepthKnown_A	157354583	128988919	0	0
RvalidKnown_A	157354583	128988919	0	0
WreadyKnown_A	157354583	128988919	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	157354583	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	0	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	128988919	0	0
T6	28992	28992	0	0
T7	30692	0	0	0
T8	52748	52096	0	0
T9	22464	22464	0	0
T10	57680	57680	0	0
T11	12656	12401	0	0
T12	148174	148174	0	0
T13	105604	105346	0	0
T16	149029	148721	0	0
T17	0	30900	0	0
T18	0	48272	0	0
T26	939	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	128988919	0	0
T6	28992	28992	0	0
T7	30692	0	0	0
T8	52748	52096	0	0
T9	22464	22464	0	0
T10	57680	57680	0	0
T11	12656	12401	0	0
T12	148174	148174	0	0
T13	105604	105346	0	0
T16	149029	148721	0	0
T17	0	30900	0	0
T18	0	48272	0	0
T26	939	0	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	128988919	0	0
T6	28992	28992	0	0
T7	30692	0	0	0
T8	52748	52096	0	0
T9	22464	22464	0	0
T10	57680	57680	0	0
T11	12656	12401	0	0
T12	148174	148174	0	0
T13	105604	105346	0	0
T16	149029	148721	0	0
T17	0	30900	0	0
T18	0	48272	0	0
T26	939	0	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	128988919	0	0
T6	28992	28992	0	0
T7	30692	0	0	0
T8	52748	52096	0	0
T9	22464	22464	0	0
T10	57680	57680	0	0
T11	12656	12401	0	0
T12	148174	148174	0	0
T13	105604	105346	0	0
T16	149029	148721	0	0
T17	0	30900	0	0
T18	0	48272	0	0
T26	939	0	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	0	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	130	1	1	100.00
CONT_ASSIGN	131	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T4 T5 T7 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T4 T5 T7 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T5 T27 T29 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T4 T5 T6 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T5 T27 T29 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130        1/1                assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
           Tests:       T1 T2 T3 
131        1/1                assign empty = fifo_empty & ~wvalid_i;
           Tests:       T1 T2 T3 
132                         end else begin : gen_nopass
133                           assign rdata_int = storage_rdata;
134                           assign empty = fifo_empty;
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138                           assign rdata_o = empty ? Width'(0) : rdata_int;
139                         end else begin : gen_no_output_zero
140        1/1                assign rdata_o = rdata_int;
           Tests:       T5 T27 T29 

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Covered	Percent
Conditions	22	17	77.27
Logical	22	17	77.27
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T7

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Not Covered
1	1	Covered	T5,T27,T29

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T7
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T27,T29

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T5,T27,T29
1	0	1	Covered	T5,T27,T29
1	1	0	Not Covered
1	1	1	Covered	T5,T27,T29

 LINE       130
 EXPRESSION ((gen_normal_fifo.fifo_empty && wvalid_i) ? wdata_i : gen_normal_fifo.storage_rdata)
             --------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T5,T27,T29

 LINE       130
 SUB-EXPRESSION (gen_normal_fifo.fifo_empty && wvalid_i)
                 -------------1------------    ----2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T5,T27,T29

 LINE       131
 EXPRESSION (gen_normal_fifo.fifo_empty & ((~wvalid_i)))
             -------------1------------   ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T27,T29
1	0	Covered	T5,T27,T29
1	1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	130	2	2	100.00
IF	69	3	3	100.00
IF	111	2	2	100.00

130              assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
                                                             -1-  
                                                             ==>  
                                                             ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T27,T29
0	Covered	T1,T2,T3

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
0	0	Covered	T4,T5,T7

111                if (fifo_incr_wptr) begin
                   -1-     
112                  storage[0] <= wdata_i;
                     ==>
113                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T27,T29
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_sram_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	157354583	6580945	0	0
DataKnown_AKnownEnable	157354583	26921896	0	0
DepthKnown_A	157354583	26921896	0	0
RvalidKnown_A	157354583	26921896	0	0
WreadyKnown_A	157354583	26921896	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	157354583	6580945	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	6580945	0	0
T5	961	137	0	0
T6	28992	0	0	0
T7	30692	0	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T16	149029	0	0	0
T27	0	541	0	0
T29	0	44379	0	0
T31	0	45005	0	0
T42	0	40424	0	0
T43	0	25323	0	0
T44	0	957	0	0
T46	0	51456	0	0
T65	0	32544	0	0
T66	0	541	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	26921896	0	0
T4	288	288	0	0
T5	961	736	0	0
T6	28992	0	0	0
T7	30692	28168	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T26	0	648	0	0
T27	0	1360	0	0
T28	0	77840	0	0
T29	0	91776	0	0
T30	0	9160	0	0
T31	0	130920	0	0
T32	0	360	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	26921896	0	0
T4	288	288	0	0
T5	961	736	0	0
T6	28992	0	0	0
T7	30692	28168	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T26	0	648	0	0
T27	0	1360	0	0
T28	0	77840	0	0
T29	0	91776	0	0
T30	0	9160	0	0
T31	0	130920	0	0
T32	0	360	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	26921896	0	0
T4	288	288	0	0
T5	961	736	0	0
T6	28992	0	0	0
T7	30692	28168	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T26	0	648	0	0
T27	0	1360	0	0
T28	0	77840	0	0
T29	0	91776	0	0
T30	0	9160	0	0
T31	0	130920	0	0
T32	0	360	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	26921896	0	0
T4	288	288	0	0
T5	961	736	0	0
T6	28992	0	0	0
T7	30692	28168	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T26	0	648	0	0
T27	0	1360	0	0
T28	0	77840	0	0
T29	0	91776	0	0
T30	0	9160	0	0
T31	0	130920	0	0
T32	0	360	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	6580945	0	0
T5	961	137	0	0
T6	28992	0	0	0
T7	30692	0	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T16	149029	0	0	0
T27	0	541	0	0
T29	0	44379	0	0
T31	0	45005	0	0
T42	0	40424	0	0
T43	0	25323	0	0
T44	0	957	0	0
T46	0	51456	0	0
T65	0	32544	0	0
T66	0	541	0	0

Line Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T4 T5 T7 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T4 T5 T7 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108                           assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111                             if (fifo_incr_wptr) begin
112                               storage[0] <= wdata_i;
113                             end
114                     
115                           logic unused_ptrs;
116                           assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120        1/1                assign storage_rdata = storage[fifo_rptr];
           Tests:       T1 T2 T3 
121                     
122                           always_ff @(posedge clk_i)
123        1/1                  if (fifo_incr_wptr) begin
           Tests:       T4 T5 T6 
124        1/1                    storage[fifo_wptr] <= wdata_i;
           Tests:       T5 T27 T29 
125                             end
                        MISSING_ELSE
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T5 T27 T29 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Covered	Percent
Conditions	16	9	56.25
Logical	16	9	56.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T5,T7

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T7
1	0	Not Covered
1	1	Covered	T5,T27,T29

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T4,T5,T7
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T27,T29

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T5,T27,T29

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (2'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T5,T27,T29
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T5,T27,T29

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T4,T5,T7
0	0	Covered	T4,T5,T7

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T27,T29
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_spi_tpm.u_arbiter.u_req_fifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	157354583	211504	0	0
DataKnown_AKnownEnable	157354583	26921896	0	0
DepthKnown_A	157354583	26921896	0	0
RvalidKnown_A	157354583	26921896	0	0
WreadyKnown_A	157354583	26921896	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	157354583	211504	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	211504	0	0
T5	961	4	0	0
T6	28992	0	0	0
T7	30692	0	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T16	149029	0	0	0
T27	0	17	0	0
T29	0	1430	0	0
T31	0	1441	0	0
T42	0	1296	0	0
T43	0	813	0	0
T44	0	31	0	0
T46	0	1660	0	0
T65	0	1038	0	0
T66	0	17	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	26921896	0	0
T4	288	288	0	0
T5	961	736	0	0
T6	28992	0	0	0
T7	30692	28168	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T26	0	648	0	0
T27	0	1360	0	0
T28	0	77840	0	0
T29	0	91776	0	0
T30	0	9160	0	0
T31	0	130920	0	0
T32	0	360	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	26921896	0	0
T4	288	288	0	0
T5	961	736	0	0
T6	28992	0	0	0
T7	30692	28168	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T26	0	648	0	0
T27	0	1360	0	0
T28	0	77840	0	0
T29	0	91776	0	0
T30	0	9160	0	0
T31	0	130920	0	0
T32	0	360	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	26921896	0	0
T4	288	288	0	0
T5	961	736	0	0
T6	28992	0	0	0
T7	30692	28168	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T26	0	648	0	0
T27	0	1360	0	0
T28	0	77840	0	0
T29	0	91776	0	0
T30	0	9160	0	0
T31	0	130920	0	0
T32	0	360	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	26921896	0	0
T4	288	288	0	0
T5	961	736	0	0
T6	28992	0	0	0
T7	30692	28168	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T26	0	648	0	0
T27	0	1360	0	0
T28	0	77840	0	0
T29	0	91776	0	0
T30	0	9160	0	0
T31	0	130920	0	0
T32	0	360	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	157354583	211504	0	0
T5	961	4	0	0
T6	28992	0	0	0
T7	30692	0	0	0
T8	52748	0	0	0
T9	22464	0	0	0
T10	57680	0	0	0
T11	12656	0	0	0
T12	148174	0	0	0
T13	105604	0	0	0
T16	149029	0	0	0
T27	0	17	0	0
T29	0	1430	0	0
T31	0	1441	0	0
T42	0	1296	0	0
T43	0	813	0	0
T44	0	31	0	0
T46	0	1660	0	0
T65	0	1038	0	0
T66	0	17	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	15	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
ALWAYS	111	2	2	100.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        1/1                assign storage_rdata = storage[0];
           Tests:       T6 T8 T9 
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        1/1                    storage[0] <= wdata_i;
           Tests:       T6 T8 T9 
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        1/1                assign rdata_int = storage_rdata;
           Tests:       T6 T8 T9 
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Covered	Percent
Conditions	16	11	68.75
Logical	16	11	68.75
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T6,T8,T9

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T6,T8,T9

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T6,T8,T9
1	1	0	Not Covered
1	1	1	Covered	T6,T8,T9

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (17'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T6,T8,T9
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T6,T8,T9

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T9
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	531406946	3372913	0	0
DataKnown_AKnownEnable	531406946	531319440	0	0
DepthKnown_A	531406946	531319440	0	0
RvalidKnown_A	531406946	531319440	0	0
WreadyKnown_A	531406946	531319440	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	531406946	3372913	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531406946	3372913	0	0
T6	10597	833	0	0
T7	225723	0	0	0
T8	60532	832	0	0
T9	160440	832	0	0
T10	36643	832	0	0
T11	42990	832	0	0
T12	892576	832	0	0
T13	109862	1617	0	0
T14	8128	0	0	0
T16	0	5430	0	0
T17	0	832	0	0
T24	3043	832	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	531406946	531319440	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531406946	531319440	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531406946	531319440	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531406946	531319440	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	531406946	3372913	0	0
T6	10597	833	0	0
T7	225723	0	0	0
T8	60532	832	0	0
T9	160440	832	0	0
T10	36643	832	0	0
T11	42990	832	0	0
T12	892576	832	0	0
T13	109862	1617	0	0
T14	8128	0	0	0
T16	0	5430	0	0
T17	0	832	0	0
T24	3043	832	0	0

Line Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
TOTAL		15	12	80.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	108	1	0	0.00
ALWAYS	111	2	1	50.00
CONT_ASSIGN	116	1	1	100.00
CONT_ASSIGN	133	1	0	0.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

68                          always_ff @(posedge clk_i or negedge rst_ni) begin
69         1/1                if (!rst_ni) begin
           Tests:       T1 T2 T3 
70         1/1                  under_rst <= 1'b1;
           Tests:       T1 T2 T3 
71         1/1                end else if (under_rst) begin
           Tests:       T1 T2 T3 
72         1/1                  under_rst <= ~under_rst;
           Tests:       T1 T2 T3 
73                            end
                        MISSING_ELSE
74                          end
75                      
76                          logic empty;
77                      
78                          // full and not ready for write are two different concepts.
79                          // The latter can be '0' when under reset, while the former is an indication that no more
80                          // entries can be written.
81         1/1              assign wready_o = ~full_o & ~under_rst;
           Tests:       T1 T2 T3 
82         1/1              assign rvalid_o = ~empty & ~under_rst;
           Tests:       T1 T2 T3 
83                      
84                          prim_fifo_sync_cnt #(
85                            .Depth(Depth),
86                            .Secure(Secure)
87                          ) u_fifo_cnt (
88                            .clk_i,
89                            .rst_ni,
90                            .clr_i,
91                            .incr_wptr_i(fifo_incr_wptr),
92                            .incr_rptr_i(fifo_incr_rptr),
93                            .wptr_o(fifo_wptr),
94                            .rptr_o(fifo_rptr),
95                            .full_o,
96                            .empty_o(fifo_empty),
97                            .depth_o,
98                            .err_o
99                          );
100        1/1              assign fifo_incr_wptr = wvalid_i & wready_o & ~under_rst;
           Tests:       T1 T2 T3 
101        1/1              assign fifo_incr_rptr = rvalid_o & rready_i & ~under_rst;
           Tests:       T1 T2 T3 
102                     
103                         // the generate blocks below are needed to avoid lint errors due to array indexing
104                         // in the where the fifo only has one storage element
105                         logic [Depth-1:0][Width-1:0] storage;
106                         logic [Width-1:0] storage_rdata;
107                         if (Depth == 1) begin : gen_depth_eq1
108        0/1     ==>        assign storage_rdata = storage[0];
109                     
110                           always_ff @(posedge clk_i)
111        1/1                  if (fifo_incr_wptr) begin
           Tests:       T1 T2 T3 
112        0/1     ==>            storage[0] <= wdata_i;
113                             end
                        MISSING_ELSE
114                     
115                           logic unused_ptrs;
116        1/1                assign unused_ptrs = ^{fifo_wptr, fifo_rptr};
           Tests:       T1 T2 T3 
117                     
118                         // fifo with more than one storage element
119                         end else begin : gen_depth_gt1
120                           assign storage_rdata = storage[fifo_rptr];
121                     
122                           always_ff @(posedge clk_i)
123                             if (fifo_incr_wptr) begin
124                               storage[fifo_wptr] <= wdata_i;
125                             end
126                         end
127                     
128                         logic [Width-1:0] rdata_int;
129                         if (Pass == 1'b1) begin : gen_pass
130                           assign rdata_int = (fifo_empty && wvalid_i) ? wdata_i : storage_rdata;
131                           assign empty = fifo_empty & ~wvalid_i;
132                         end else begin : gen_nopass
133        0/1     ==>        assign rdata_int = storage_rdata;
134        1/1                assign empty = fifo_empty;
           Tests:       T1 T2 T3 
135                         end
136                     
137                         if (OutputZeroIfEmpty == 1'b1) begin : gen_output_zero
138        1/1                assign rdata_o = empty ? Width'(0) : rdata_int;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Covered	Percent
Conditions	16	5	31.25
Logical	16	5	31.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Not Covered

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? (5'(0)) : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Not Covered
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Line No.	Total	Covered	Percent
Branches		7	5	71.43
TERNARY	138	2	1	50.00
IF	69	3	3	100.00
IF	123	2	1	50.00

138              assign rdata_o = empty ? Width'(0) : rdata_int;
                                        -1-  
                                        ==>  
                                        ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Not Covered

69               if (!rst_ni) begin
                 -1-  
70                 under_rst <= 1'b1;
                   ==>
71               end else if (under_rst) begin
                          -2-  
72                 under_rst <= ~under_rst;
                   ==>
73               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

123                if (fifo_incr_wptr) begin
                   -1-     
124                  storage[fifo_wptr] <= wdata_i;
                     ==>
125                end
                   MISSING_ELSE
                   ==>

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_tlul2sram_egress.u_sramreqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	4	66.67
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	4	66.67

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	531406946	0	0	0
DataKnown_AKnownEnable	531406946	531319440	0	0
DepthKnown_A	531406946	531319440	0	0
RvalidKnown_A	531406946	531319440	0	0
WreadyKnown_A	531406946	531319440	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	531406946	0	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531406946	0	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	531406946	531319440	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531406946	531319440	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531406946	531319440	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	531406946	531319440	0	0
T1	1424	1345	0	0
T2	1778	1696	0	0
T3	2044	1977	0	0
T4	1668	1579	0	0
T5	5732	5639	0	0
T6	10597	10538	0	0
T7	225723	225667	0	0
T8	60532	60438	0	0
T9	160440	160342	0	0
T10	36643	36578	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	531406946	0	0	0