Unified Coverage Report :: Module :: spi_device

Module : spi_device

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.52	95.20	84.31	97.00		90.62	95.45

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_08/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	95.10	95.20	93.48	97.84		93.55	95.45

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.10	95.20	93.48	97.84		93.55	95.45

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.32	98.65	96.80	99.01	89.36	98.51	95.57

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
spi_device_csr_assert	100.00						100.00
tlul_assert_device	100.00						100.00
u_clk_csb_buf	100.00	100.00
u_clk_csb_mux	64.81	100.00	44.44				50.00
u_clk_spi	85.19	100.00	55.56				100.00
u_clk_spi_in_buf	100.00	100.00
u_clk_spi_in_mux	64.81	100.00	44.44				50.00
u_clk_spi_out_buf	100.00	100.00
u_clk_spi_out_mux	64.81	100.00	44.44				50.00
u_cmdparse	98.26	100.00	95.40		100.00	95.92	100.00
u_csb_buf	100.00	100.00
u_csb_rst_out_scan_mux	64.81	100.00	44.44				50.00
u_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_flash_readbuf_flip_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_flash_readbuf_watermark_pulse_sync	100.00	100.00	100.00			100.00	100.00
u_intr_cmdfifo_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_not_empty	100.00	100.00	100.00			100.00	100.00
u_intr_payload_overflow	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_flip	100.00	100.00	100.00			100.00	100.00
u_intr_readbuf_watermark	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_cmdaddr_notempty	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_cmd_end	100.00	100.00	100.00			100.00	100.00
u_intr_tpm_rdfifo_drop	97.92	100.00	91.67			100.00	100.00
u_intr_upload_edge	100.00	100.00				100.00
u_jedec	100.00	100.00	100.00		100.00	100.00	100.00
u_p2s	85.98	100.00	71.43			72.50	100.00
u_passthrough	91.08	94.95	91.92		75.00	93.52	100.00
u_read_en_pipe_stg1	100.00	100.00				100.00
u_read_en_pipe_stg2	100.00	100.00				100.00
u_read_intercept_pipe_stg1	100.00	100.00				100.00
u_read_intercept_pipe_stg2	100.00	100.00				100.00
u_read_pipe_stg1	100.00	100.00				100.00
u_read_pipe_stg2	100.00	100.00				100.00
u_readcmd	90.33	93.62	93.33		87.50	85.56	91.67
u_reg	99.89	99.61	99.85	100.00		100.00	100.00
u_rst_spi_out_sync	100.00	100.00				100.00
u_s2p	89.38	100.00	78.57			78.95	100.00
u_scanmode_sync	100.00						100.00
u_spi_tpm	94.15	99.28	90.60		91.67	96.73	92.45
u_spid_addr_4b	91.90	97.59	100.00			95.00	75.00
u_spid_csb_sync	100.00	100.00	100.00			100.00
u_spid_dpram	100.00	100.00	100.00			100.00	100.00
u_spid_status	92.95	100.00	88.46			100.00	83.33
u_sys_csb_syncd	100.00	100.00				100.00
u_sys_sram_arbiter	96.59	100.00	100.00			100.00	86.36
u_sys_tpm_csb_sync	100.00	100.00				100.00
u_tlul2sram_egress	84.73	86.70	82.99			86.36	82.86
u_tlul2sram_ingress	90.81	88.28	85.09			89.87	100.00
u_tpm_csb_buf	100.00	100.00
u_tpm_csb_rst_scan_mux	64.81	100.00	44.44				50.00
u_tpm_csb_rst_sync	70.83	88.89	44.44			100.00	50.00
u_tpm_rst_out_scan_mux	64.81	100.00	44.44				50.00
u_tpm_rst_out_sync	100.00	100.00				100.00
u_upload	92.79	99.29	79.37		100.00	95.81	89.47

Line Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
TOTAL		229	218	95.20
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
ALWAYS	539	4	4	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	564	1	1	100.00
ALWAYS	569	0	0
ALWAYS	569	2	2	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	583	0	0
ALWAYS	583	12	12	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
CONT_ASSIGN	649	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
ALWAYS	828	3	3	100.00
ALWAYS	834	8	8	100.00
ALWAYS	872	9	9	100.00
ALWAYS	896	24	24	100.00
CONT_ASSIGN	964	1	1	100.00
CONT_ASSIGN	965	1	1	100.00
ALWAYS	1028	7	7	100.00
ALWAYS	1041	13	13	100.00
ALWAYS	1078	3	3	100.00
CONT_ASSIGN	1217	1	1	100.00
CONT_ASSIGN	1220	1	1	100.00
CONT_ASSIGN	1224	1	1	100.00
CONT_ASSIGN	1225	1	1	100.00
CONT_ASSIGN	1226	1	1	100.00
CONT_ASSIGN	1228	1	1	100.00
CONT_ASSIGN	1229	1	1	100.00
CONT_ASSIGN	1232	1	1	100.00
CONT_ASSIGN	1282	1	0	0.00
CONT_ASSIGN	1313	1	0	0.00
CONT_ASSIGN	1396	1	1	100.00
CONT_ASSIGN	1397	1	1	100.00
CONT_ASSIGN	1398	1	1	100.00
CONT_ASSIGN	1399	1	1	100.00
CONT_ASSIGN	1400	1	1	100.00
CONT_ASSIGN	1402	1	1	100.00
CONT_ASSIGN	1406	1	1	100.00
CONT_ASSIGN	1413	1	1	100.00
CONT_ASSIGN	1414	1	1	100.00
CONT_ASSIGN	1416	1	1	100.00
CONT_ASSIGN	1420	1	1	100.00
CONT_ASSIGN	1423	1	1	100.00
CONT_ASSIGN	1426	1	1	100.00
CONT_ASSIGN	1429	1	1	100.00
CONT_ASSIGN	1432	1	1	100.00
CONT_ASSIGN	1435	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1443	1	1	100.00
CONT_ASSIGN	1482	1	1	100.00
CONT_ASSIGN	1585	1	0	0.00
CONT_ASSIGN	1593	1	1	100.00
CONT_ASSIGN	1594	1	1	100.00
CONT_ASSIGN	1595	1	1	100.00
CONT_ASSIGN	1596	1	1	100.00
CONT_ASSIGN	1597	1	1	100.00
CONT_ASSIGN	1600	1	1	100.00
CONT_ASSIGN	1607	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1617	1	1	100.00
CONT_ASSIGN	1618	1	1	100.00
CONT_ASSIGN	1619	1	1	100.00
CONT_ASSIGN	1620	1	1	100.00
CONT_ASSIGN	1621	1	1	100.00
CONT_ASSIGN	1622	1	1	100.00
CONT_ASSIGN	1624	1	1	100.00
CONT_ASSIGN	1628	1	1	100.00
CONT_ASSIGN	1630	1	1	100.00
CONT_ASSIGN	1631	1	1	100.00
CONT_ASSIGN	1638	1	1	100.00
CONT_ASSIGN	1640	1	1	100.00
CONT_ASSIGN	1641	1	1	100.00
CONT_ASSIGN	1650	1	1	100.00
CONT_ASSIGN	1651	1	1	100.00
CONT_ASSIGN	1652	1	1	100.00
CONT_ASSIGN	1653	1	1	100.00
CONT_ASSIGN	1716	1	1	100.00
CONT_ASSIGN	1718	1	1	100.00
ALWAYS	1723	4	4	100.00
ALWAYS	1732	0	0
ALWAYS	1732	9	9	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1750	1	1	100.00
CONT_ASSIGN	1750	1	1	100.00
CONT_ASSIGN	1750	1	0	0.00
CONT_ASSIGN	1750	1	0	0.00
CONT_ASSIGN	1750	1	0	0.00
CONT_ASSIGN	1751	1	1	100.00
CONT_ASSIGN	1751	1	1	100.00
CONT_ASSIGN	1751	1	0	0.00
CONT_ASSIGN	1751	1	0	0.00
CONT_ASSIGN	1751	1	1	100.00
CONT_ASSIGN	1752	1	1	100.00
CONT_ASSIGN	1752	1	1	100.00
CONT_ASSIGN	1752	1	0	0.00
CONT_ASSIGN	1752	1	0	0.00
CONT_ASSIGN	1752	1	0	0.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1797	1	1	100.00
CONT_ASSIGN	1799	1	1	100.00
CONT_ASSIGN	1800	1	1	100.00
CONT_ASSIGN	1801	1	1	100.00
CONT_ASSIGN	1802	1	1	100.00
CONT_ASSIGN	1803	1	1	100.00
CONT_ASSIGN	1805	1	1	100.00
CONT_ASSIGN	1806	1	1	100.00
CONT_ASSIGN	1807	1	1	100.00
CONT_ASSIGN	1863	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : spi_device

	Total	Covered	Percent
Conditions	51	43	84.31
Logical	51	43	84.31
Non-Logical	0	0
Event	0	0

 LINE       173
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T46,T49

 LINE       702
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T10

 LINE       736
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       858
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T46,T49

 LINE       885
 EXPRESSION (((!sck_csb)) && ((spi_mode == FlashMode) || (spi_mode == PassThrough)))
             ------1-----    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

 LINE       885
 SUB-EXPRESSION ((spi_mode == FlashMode) || (spi_mode == PassThrough))
                 -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T11,T15,T18
1	0	Covered	T1,T2,T3

 LINE       885
 SUB-EXPRESSION (spi_mode == FlashMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T11,T15,T18
1	Covered	T1,T2,T3

 LINE       885
 SUB-EXPRESSION (spi_mode == PassThrough)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T15,T18

 LINE       1044
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T10
1	0	Covered	T4,T5,T13
1	1	Covered	T4,T5,T13

 LINE       1217
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.wel.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    -------------2------------    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T11,T16,T19

 LINE       1228
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T46,T49

 LINE       1229
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T41,T46

 LINE       1442
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T61,T41

 LINE       1443
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T24,T103

 LINE       1607
 EXPRESSION (reg2hw.tpm_status.wrfifo_pending.qe & ((~reg2hw.tpm_status.wrfifo_pending.q)))
             -----------------1-----------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T14,T26

 LINE       1725
 EXPRESSION ((i != SysSramFwEgress) && (i != SysSramFwIngress))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1725
 SUB-EXPRESSION (i != SysSramFwEgress)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1725
 SUB-EXPRESSION (i != SysSramFwIngress)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1797
 EXPRESSION (tpm_rst_in_n | rst_spi_in_n)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T9,T10
1	0	Covered	T3,T4,T5

 LINE       1863
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T104
1	0	Covered	T1,T3,T4
1	1	Covered	T6,T7,T104

---

Toggle Coverage for Module : spi_device

	Total	Covered	Percent
Totals	63	58	92.06
Total Bits	466	452	97.00
Total Bits 0->1	233	226	97.00
Total Bits 1->0	233	226	97.00

Ports	63	58	92.06
Port Bits	466	452	97.00
Port Bits 0->1	233	226	97.00
Port Bits 1->0	233	226	97.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T12,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T7	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T4,T5	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T10,T12	Yes	T1,T10,T12	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T5,T10	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T10,T12	Yes	T1,T5,T10	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T105,T106,T107	Yes	T105,T106,T107	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T5,T9	Yes	T3,T5,T9	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T3,T4,T5	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T5,T11,T14	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T3,T4,T5	Yes	T2,T3,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T6,T7	Yes	T1,T6,T7	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T6,T7	Yes	T1,T6,T7	OUTPUT
cio_sck_i	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
cio_csb_i	Yes	Yes	T3,T9,T10	Yes	T3,T9,T10	INPUT
cio_sd_o[3:0]	Yes	Yes	T11,T15,T16	Yes	T11,T15,T16	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T15,T16,T18	Yes	T15,T16,T18	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
cio_tpm_csb_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T11,*T15,*T18	Yes	T11,T15,T18	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
passthrough_o.csb_en	No	No		No		OUTPUT
passthrough_o.csb	Yes	Yes	T3,T9,T10	Yes	T3,T9,T10	OUTPUT
passthrough_o.sck_en	No	No		No		OUTPUT
passthrough_o.sck	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T46,T49,T66	Yes	T11,T15,T18	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T34,T37,T39	Yes	T34,T37,T39	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T34,T38,T39	Yes	T34,T38,T39	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T34,T37,T38	Yes	T34,T37,T38	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T34,T37,T38	Yes	T34,T37,T38	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T34,T37,T38	Yes	T34,T37,T38	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T34,T37,T38	Yes	T34,T37,T38	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T34,T37,T38	Yes	T34,T37,T38	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T34,T37,T38	Yes	T34,T37,T38	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.b_ram_lcfg.test	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.a_ram_lcfg.test	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.b_ram_fcfg.test	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.a_ram_fcfg.test	Yes	Yes	T2	Yes	T2	INPUT
sck_monitor_o	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : spi_device

	Line No.	Total	Covered	Percent
Branches		32	29	90.62
IF	539	3	3	100.00
IF	828	2	2	100.00
CASE	844	4	4	100.00
IF	885	3	3	100.00
CASE	901	7	5	71.43
IF	1028	2	2	100.00
IF	1044	5	4	80.00
IF	1078	2	2	100.00
IF	1725	2	2	100.00
IF	1735	2	2	100.00

539            if (!rst_ni) begin
               -1-  
540              readbuf_addr_busclk <= '0;
                 ==>
541            end else if (sys_csb_deasserted_pulse) begin
                        -2-  
542              readbuf_addr_busclk <= readbuf_addr_sck;
                 ==>
543            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T15,T16
0	0	Covered	T1,T2,T3

828            if (!rst_spi_out_n) io_mode_outclk <= SingleIO;
               -1-  
               ==>
829            else                io_mode_outclk <= io_mode;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T11,T15,T16

844            unique case (cmd_dp_sel)
                      -1-  
845              DpReadCmd, DpReadSFDP: begin
846                // SRAM:: Remember this has glitch
847                // switch should happen only when clock gate is disabled.
848                flash_sram_l2m = sub_sram_l2m[IoModeReadCmd];
                   ==>
849                sub_sram_m2l[IoModeReadCmd] = flash_sram_m2l;
850              end
851        
852              DpUpload: begin
853                flash_sram_l2m = sub_sram_l2m[IoModeUpload];
                   ==>
854                sub_sram_m2l[IoModeUpload] = flash_sram_m2l;
855              end
856        
857              default: begin
858                if (cmd_only_dp_sel == DpUpload) begin
                   -2-  
859                  // Be ready to upload commands on the 8th command bit, when directed
860                  flash_sram_l2m = sub_sram_l2m[IoModeUpload];
                     ==>
861                  sub_sram_m2l[IoModeUpload] = flash_sram_m2l;
862                end else begin
863                  // DpNone, DpReadStatus, DpReadJEDEC
864                  flash_sram_l2m = '{default: '0 };
                     ==>

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Covered	T15,T16,T22
DpUpload	-	Covered	T41,T46,T49
default	1	Covered	T41,T46,T49
default	0	Covered	T1,T2,T3

885            if (!sck_csb && ((spi_mode == FlashMode) || (spi_mode == PassThrough))) begin
               -1-  
886              mem_b_l2m = flash_sram_l2m;
                 ==>
887              flash_sram_m2l = mem_b_m2l;
888            end else if (cfg_tpm_en) begin
                        -2-  
889              mem_b_l2m = tpm_sram_l2m;
                 ==>
890              tpm_sram_m2l = mem_b_m2l;
891            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T9,T10
0	1	Covered	T4,T5,T13
0	0	Covered	T1,T2,T3

901            unique case (spi_mode)
                      -1-  
902              FlashMode, PassThrough: begin
903                unique case (cmd_dp_sel)
                          -2-  
904                  DpNone: begin
905                    io_mode = sub_iomode[IoModeCmdParse];
                       ==>
906        
907                    sub_p2s_sent[IoModeCmdParse] = p2s_sent;
908        
909                  end
910                  DpReadCmd, DpReadSFDP: begin
911                    io_mode = sub_iomode[IoModeReadCmd];
                       ==>
912        
913                    p2s_valid = sub_p2s_valid[IoModeReadCmd];
914                    p2s_data  = sub_p2s_data[IoModeReadCmd];
915                    sub_p2s_sent[IoModeReadCmd] = p2s_sent;
916                  end
917                  DpReadStatus: begin
918                    io_mode = sub_iomode[IoModeStatus];
                       ==>
919        
920                    p2s_valid = sub_p2s_valid[IoModeStatus];
921                    p2s_data  = sub_p2s_data[IoModeStatus];
922                    sub_p2s_sent[IoModeStatus] = p2s_sent;
923        
924                  end
925        
926                  DpReadJEDEC: begin
927                    io_mode = sub_iomode[IoModeJedec];
                       ==>
928        
929                    p2s_valid = sub_p2s_valid[IoModeJedec];
930                    p2s_data  = sub_p2s_data[IoModeJedec];
931                    sub_p2s_sent[IoModeJedec] = p2s_sent;
932                  end
933        
934                  DpUpload: begin
935                    io_mode = sub_iomode[IoModeUpload];
                       ==>
936        
937                    p2s_valid = sub_p2s_valid[IoModeUpload];
938                    p2s_data  = sub_p2s_data[IoModeUpload];
939                    sub_p2s_sent[IoModeUpload] = p2s_sent;
940                  end
941                  // DpUnknown:
942                  default: begin
943                    io_mode = sub_iomode[IoModeCmdParse];
                       ==>
944        
945                    sub_p2s_sent[IoModeCmdParse] = p2s_sent;
946                  end
947                endcase
948              end
949        
950              default: begin
951                io_mode = SingleIO;
                   ==>

Branches:

-1-	-2-	Status	Tests
FlashMode PassThrough	DpNone	Covered	T1,T2,T3
FlashMode PassThrough	DpReadCmd DpReadSFDP	Covered	T15,T16,T22
FlashMode PassThrough	DpReadStatus	Covered	T24,T63,T61
FlashMode PassThrough	DpReadJEDEC	Covered	T101,T41,T46
FlashMode PassThrough	DpUpload	Covered	T41,T46,T49
FlashMode PassThrough	default	Not Covered
default	-	Not Covered

1028           if (cmd_read_pipeline_sel) begin
               -1-  
1029             internal_sd_out = internal_sd_stg2_q;
                 ==>
1030             internal_sd_en_out = internal_sd_en_stg2;
1031             intercept_en_out = intercept_en_stg2;
1032           end else begin
1033             internal_sd_out = internal_sd;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T22
0	Covered	T1,T2,T3

1044           if (cfg_tpm_en && !sck_tpm_csb_buf) begin : miso_tpm
               -1-  
1045             // TPM transaction is on-going. MOSI, MISO is being used by TPM
1046             cio_sd_o    = {2'b 00, tpm_miso,    1'b 0};
                 ==>
1047             cio_sd_en_o = {2'b 00, tpm_miso_en, 1'b 0};
1048       
1049           end else begin : spi_out_flash_passthrough
1050             // SPI Flash, Passthrough modes
1051             unique case (spi_mode)
                        -2-  
1052               FlashMode: begin
1053                 cio_sd_o    = internal_sd_out;
                     ==>
1054                 cio_sd_en_o = internal_sd_en_out;
1055               end
1056       
1057               PassThrough: begin
1058                 if (intercept_en_out) begin
                     -3-  
1059                   cio_sd_o    = internal_sd_out;
                       ==>
1060                   cio_sd_en_o = internal_sd_en_out;
1061                 end else begin
1062                   cio_sd_o    = passthrough_sd;
                       ==>
1063                   cio_sd_en_o = passthrough_sd_en;
1064                 end
1065               end
1066       
1067               default: begin
1068                 cio_sd_o    = internal_sd;
                     ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T13
0	FlashMode	-	Covered	T1,T2,T3
0	PassThrough	1	Covered	T24,T58,T63
0	PassThrough	0	Covered	T11,T15,T18
0	default	-	Not Covered

1078           if (!rst_spi_out_n) intercept_en <= 1'b 0;
               -1-  
               ==>
1079           else                intercept_en <= |intercept;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T11,T15,T16

1725             if ((i != SysSramFwEgress) && (i != SysSramFwIngress)) begin
                 -1-  
1726               sys_sram_hw_req |= sys_sram_l2m[i].req;
                   ==>
1727             end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

1735           if (sys_sram_hw_req) begin
               -1-  
1736             // Fixed low priority. (Discussed in #10065)
1737             // When HW requests the SRAM access, lower the SW requests (and grant)
1738             sys_sram_req[SysSramFwEgress] = 1'b0;
                 ==>
1739             sys_sram_fw_gnt[SPI_DEVICE_EGRESS_BUFFER_IDX] = 1'b0;
1740             sys_sram_req[SysSramFwIngress] = 1'b0;
1741             sys_sram_fw_gnt[SPI_DEVICE_INGRESS_BUFFER_IDX] = 1'b0;
1742           end else begin
1743             sys_sram_fw_gnt[SPI_DEVICE_EGRESS_BUFFER_IDX] = sys_sram_gnt[SysSramFwEgress];
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T14,T26
0	Covered	T1,T2,T3

---

Assert Coverage for Module : spi_device

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	21	95.45
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	21	95.45

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	505580215	505494102	0	0
CioSdoEnOKnown	505580215	505494102	0	0
CioSdoEnOffWhenInactive	505580215	505494102	0	0
FpvSecCmRegWeOnehotCheck_A	505580215	90	0	0
InterceptLevel_M	150958911	0	0	0
IntrReadbufFlipOKnown	505580215	505494102	0	0
IntrReadbufWatermarkOKnown	505580215	505494102	0	0
IntrTpmHeaderNotEmptyOKnown	505580215	505494102	0	0
IntrTpmRdfifoCmdEndOKnown	505580215	505494102	0	0
IntrTpmRdfifoDropOKnown	505580215	505494102	0	0
IntrUploadCmdfifoNotEmptyOKnown	505580215	505494102	0	0
IntrUploadPayloadNotEmptyOKnown	505580215	505494102	0	0
IntrUploadPayloadOverflowOKnown	505580215	505494102	0	0
PayloadStartIdxWidthMatch_A	955	955	0	0
SpiModeKnown_A	505580215	505494102	0	0
TpmEnableWhenTpmCsbIdle_M	505580215	344	0	0
g_sram_connect[0].ReqAlwaysAccepted_A	505580215	1910848	0	0
g_sram_connect[1].ReqAlwaysAccepted_A	505580215	174368	0	0
g_sram_connect[2].ReqAlwaysAccepted_A	505580215	2388	0	0
g_sram_connect[3].ReqAlwaysAccepted_A	505580215	1816	0	0
g_sram_connect[4].ReqAlwaysAccepted_A	505580215	184894	0	0
scanmodeKnown	505580215	505580215	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

CioSdoEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

CioSdoEnOffWhenInactive

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	90	0	0
T1	9378	30	0	0
T2	1547	0	0	0
T3	1633	0	0	0
T4	4740	0	0	0
T5	2209	0	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T12	0	10	0	0
T21	0	10	0	0
T33	0	10	0	0
T35	0	30	0	0

InterceptLevel_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150958911	0	0	0

IntrReadbufFlipOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

IntrReadbufWatermarkOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

IntrTpmHeaderNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

IntrTpmRdfifoCmdEndOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

IntrTpmRdfifoDropOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

IntrUploadCmdfifoNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

IntrUploadPayloadNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

IntrUploadPayloadOverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

PayloadStartIdxWidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SpiModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

TpmEnableWhenTpmCsbIdle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	344	0	0
T4	4740	1	0	0
T5	2209	1	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3501	0	0	0
T12	3439	0	0	0
T13	2415	1	0	0
T14	0	1	0	0
T17	0	1	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0

g_sram_connect[0].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	1910848	0	0
T11	3501	832	0	0
T13	2415	0	0	0
T14	4756	0	0	0
T15	51882	832	0	0
T16	16407	832	0	0
T17	135126	0	0	0
T18	9552	832	0	0
T19	19411	832	0	0
T20	8263	832	0	0
T21	3098	0	0	0
T22	0	832	0	0
T23	0	832	0	0
T24	0	832	0	0
T25	0	2112	0	0

g_sram_connect[1].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	174368	0	0
T5	2209	14	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3501	0	0	0
T12	3439	0	0	0
T13	2415	0	0	0
T14	4756	1	0	0
T26	0	218	0	0
T41	0	64	0	0
T42	0	715	0	0
T43	0	1014	0	0
T46	0	483	0	0
T47	0	16	0	0
T48	0	386	0	0
T49	0	352	0	0

g_sram_connect[2].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	2388	0	0
T34	5267	0	0	0
T41	169152	1	0	0
T42	243769	0	0	0
T43	551832	0	0	0
T46	0	14	0	0
T47	4500	0	0	0
T49	0	8	0	0
T54	0	8	0	0
T55	0	7	0	0
T56	8151	0	0	0
T64	0	9	0	0
T66	0	3	0	0
T69	0	17	0	0
T81	30165	0	0	0
T82	619815	0	0	0
T83	12712	0	0	0
T96	0	4	0	0
T97	0	3	0	0
T98	8996	0	0	0

g_sram_connect[3].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	1816	0	0
T34	5267	0	0	0
T41	169152	1	0	0
T42	243769	0	0	0
T43	551832	0	0	0
T46	0	11	0	0
T47	4500	0	0	0
T49	0	6	0	0
T54	0	5	0	0
T55	0	5	0	0
T56	8151	0	0	0
T64	0	8	0	0
T66	0	3	0	0
T69	0	17	0	0
T81	30165	0	0	0
T82	619815	0	0	0
T83	12712	0	0	0
T96	0	4	0	0
T97	0	2	0	0
T98	8996	0	0	0

g_sram_connect[4].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	184894	0	0
T5	2209	2	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3501	0	0	0
T12	3439	0	0	0
T13	2415	0	0	0
T14	4756	6	0	0
T26	0	468	0	0
T32	0	1	0	0
T42	0	1519	0	0
T43	0	1718	0	0
T47	0	16	0	0
T48	0	895	0	0
T79	0	2	0	0
T80	0	59	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505580215	0	0
T1	9378	9378	0	0
T2	1547	1547	0	0
T3	1633	1633	0	0
T4	4740	4740	0	0
T5	2209	2209	0	0
T6	1339	1339	0	0
T7	1300	1300	0	0
T8	1043	1043	0	0
T9	1754	1754	0	0
T10	2086	2086	0	0

Line Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
TOTAL		229	218	95.20
CONT_ASSIGN	173	1	1	100.00
CONT_ASSIGN	309	1	1	100.00
CONT_ASSIGN	372	1	1	100.00
CONT_ASSIGN	373	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	394	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	536	1	1	100.00
ALWAYS	539	4	4	100.00
CONT_ASSIGN	547	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	554	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	560	1	1	100.00
CONT_ASSIGN	564	1	1	100.00
ALWAYS	569	0	0
ALWAYS	569	2	2	100.00
CONT_ASSIGN	574	1	1	100.00
CONT_ASSIGN	575	1	1	100.00
ALWAYS	583	0	0
ALWAYS	583	12	12	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	648	1	1	100.00
CONT_ASSIGN	649	1	1	100.00
CONT_ASSIGN	710	1	1	100.00
ALWAYS	828	3	3	100.00
ALWAYS	834	8	8	100.00
ALWAYS	872	9	9	100.00
ALWAYS	896	24	24	100.00
CONT_ASSIGN	964	1	1	100.00
CONT_ASSIGN	965	1	1	100.00
ALWAYS	1028	7	7	100.00
ALWAYS	1041	13	13	100.00
ALWAYS	1078	3	3	100.00
CONT_ASSIGN	1217	1	1	100.00
CONT_ASSIGN	1220	1	1	100.00
CONT_ASSIGN	1224	1	1	100.00
CONT_ASSIGN	1225	1	1	100.00
CONT_ASSIGN	1226	1	1	100.00
CONT_ASSIGN	1228	1	1	100.00
CONT_ASSIGN	1229	1	1	100.00
CONT_ASSIGN	1232	1	1	100.00
CONT_ASSIGN	1282	1	0	0.00
CONT_ASSIGN	1313	1	0	0.00
CONT_ASSIGN	1396	1	1	100.00
CONT_ASSIGN	1397	1	1	100.00
CONT_ASSIGN	1398	1	1	100.00
CONT_ASSIGN	1399	1	1	100.00
CONT_ASSIGN	1400	1	1	100.00
CONT_ASSIGN	1402	1	1	100.00
CONT_ASSIGN	1406	1	1	100.00
CONT_ASSIGN	1413	1	1	100.00
CONT_ASSIGN	1414	1	1	100.00
CONT_ASSIGN	1416	1	1	100.00
CONT_ASSIGN	1420	1	1	100.00
CONT_ASSIGN	1423	1	1	100.00
CONT_ASSIGN	1426	1	1	100.00
CONT_ASSIGN	1429	1	1	100.00
CONT_ASSIGN	1432	1	1	100.00
CONT_ASSIGN	1435	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1443	1	1	100.00
CONT_ASSIGN	1482	1	1	100.00
CONT_ASSIGN	1585	1	0	0.00
CONT_ASSIGN	1593	1	1	100.00
CONT_ASSIGN	1594	1	1	100.00
CONT_ASSIGN	1595	1	1	100.00
CONT_ASSIGN	1596	1	1	100.00
CONT_ASSIGN	1597	1	1	100.00
CONT_ASSIGN	1600	1	1	100.00
CONT_ASSIGN	1607	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1614	1	1	100.00
CONT_ASSIGN	1617	1	1	100.00
CONT_ASSIGN	1618	1	1	100.00
CONT_ASSIGN	1619	1	1	100.00
CONT_ASSIGN	1620	1	1	100.00
CONT_ASSIGN	1621	1	1	100.00
CONT_ASSIGN	1622	1	1	100.00
CONT_ASSIGN	1624	1	1	100.00
CONT_ASSIGN	1628	1	1	100.00
CONT_ASSIGN	1630	1	1	100.00
CONT_ASSIGN	1631	1	1	100.00
CONT_ASSIGN	1638	1	1	100.00
CONT_ASSIGN	1640	1	1	100.00
CONT_ASSIGN	1641	1	1	100.00
CONT_ASSIGN	1650	1	1	100.00
CONT_ASSIGN	1651	1	1	100.00
CONT_ASSIGN	1652	1	1	100.00
CONT_ASSIGN	1653	1	1	100.00
CONT_ASSIGN	1716	1	1	100.00
CONT_ASSIGN	1718	1	1	100.00
ALWAYS	1723	4	4	100.00
ALWAYS	1732	0	0
ALWAYS	1732	9	9	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1749	1	1	100.00
CONT_ASSIGN	1750	1	1	100.00
CONT_ASSIGN	1750	1	1	100.00
CONT_ASSIGN	1750	1	0	0.00
CONT_ASSIGN	1750	1	0	0.00
CONT_ASSIGN	1750	1	0	0.00
CONT_ASSIGN	1751	1	1	100.00
CONT_ASSIGN	1751	1	1	100.00
CONT_ASSIGN	1751	1	0	0.00
CONT_ASSIGN	1751	1	0	0.00
CONT_ASSIGN	1751	1	1	100.00
CONT_ASSIGN	1752	1	1	100.00
CONT_ASSIGN	1752	1	1	100.00
CONT_ASSIGN	1752	1	0	0.00
CONT_ASSIGN	1752	1	0	0.00
CONT_ASSIGN	1752	1	0	0.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1754	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1755	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1756	1	1	100.00
CONT_ASSIGN	1797	1	1	100.00
CONT_ASSIGN	1799	1	1	100.00
CONT_ASSIGN	1800	1	1	100.00
CONT_ASSIGN	1801	1	1	100.00
CONT_ASSIGN	1802	1	1	100.00
CONT_ASSIGN	1803	1	1	100.00
CONT_ASSIGN	1805	1	1	100.00
CONT_ASSIGN	1806	1	1	100.00
CONT_ASSIGN	1807	1	1	100.00
CONT_ASSIGN	1863	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Instance : tb.dut

	Total	Covered	Percent
Conditions	46	43	93.48
Logical	46	43	93.48
Non-Logical	0	0
Event	0	0

 LINE       173
 EXPRESSION (payload_depth != '0)
            ----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T46,T49

 LINE       702
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T9,T10

 LINE       736
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------

-1-	-2-	Status	Tests	Exclude Annotation
0	1	Excluded		VC_COV_UNR
1	0	Covered	T1,T2,T3
1	1	Covered	T3,T4,T5

 LINE       858
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T46,T49

 LINE       885
 EXPRESSION (((!sck_csb)) && ((spi_mode == FlashMode) || (spi_mode == PassThrough)))
             ------1-----    ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T9,T10

 LINE       885
 SUB-EXPRESSION ((spi_mode == FlashMode) || (spi_mode == PassThrough))
                 -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Covered	T11,T15,T18
1	0	Covered	T1,T2,T3

 LINE       885
 SUB-EXPRESSION (spi_mode == FlashMode)
                -----------1-----------

-1-	Status	Tests
0	Covered	T11,T15,T18
1	Covered	T1,T2,T3

 LINE       885
 SUB-EXPRESSION (spi_mode == PassThrough)
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T15,T18

 LINE       1044
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T3,T9,T10
1	0	Covered	T4,T5,T13
1	1	Covered	T4,T5,T13

 LINE       1217
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.wel.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    -------------2------------    --------------3--------------

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Excluded		VC_COV_UNR
1	0	1	Excluded		VC_COV_UNR
1	1	0	Excluded		VC_COV_UNR
1	1	1	Covered	T11,T16,T19

 LINE       1228
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T41,T46,T49

 LINE       1229
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T103,T41,T46

 LINE       1442
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T20,T61,T41

 LINE       1443
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T11,T24,T103

 LINE       1607
 EXPRESSION (reg2hw.tpm_status.wrfifo_pending.qe & ((~reg2hw.tpm_status.wrfifo_pending.q)))
             -----------------1-----------------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T5,T14,T26

 LINE       1725
 EXPRESSION ((i != SysSramFwEgress) && (i != SysSramFwIngress))
             -----------1----------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       1725
 SUB-EXPRESSION (i != SysSramFwEgress)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1725
 SUB-EXPRESSION (i != SysSramFwIngress)
                -----------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       1797
 EXPRESSION (tpm_rst_in_n | rst_spi_in_n)
             ------1-----   ------2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T9,T10
1	0	Covered	T3,T4,T5

 LINE       1863
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T6,T7,T104
1	0	Covered	T1,T3,T4
1	1	Covered	T6,T7,T104

---

Toggle Coverage for Instance : tb.dut

	Total	Covered	Percent
Totals	61	58	95.08
Total Bits	462	452	97.84
Total Bits 0->1	231	226	97.84
Total Bits 1->0	231	226	97.84

Ports	61	58	95.08
Port Bits	462	452	97.84
Port Bits 0->1	231	226	97.84
Port Bits 1->0	231	226	97.84

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T12,T21	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T7	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T4,T5	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T10,T12	Yes	T1,T10,T12	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T5,T10	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T10,T12	Yes	T1,T5,T10	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T105,T106,T107	Yes	T105,T106,T107	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T3,T5,T9	Yes	T3,T5,T9	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T3,T4,T5	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T5,T11,T14	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T3,T4,T5	Yes	T2,T3,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T4,*T5,*T6	Yes	T4,T5,T6	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T1,T6,T7	Yes	T1,T6,T7	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T1,T6,T7	Yes	T1,T6,T7	OUTPUT
cio_sck_i	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
cio_csb_i	Yes	Yes	T3,T9,T10	Yes	T3,T9,T10	INPUT
cio_sd_o[3:0]	Yes	Yes	T11,T15,T16	Yes	T11,T15,T16	OUTPUT
cio_sd_en_o[3:0]	Yes	Yes	T15,T16,T18	Yes	T15,T16,T18	OUTPUT
cio_sd_i[3:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
cio_tpm_csb_i	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
passthrough_o.s_en[0]	Yes	Yes	*T11,*T15,*T18	Yes	T11,T15,T18	OUTPUT
passthrough_o.s_en[3:1]	No	No		No		OUTPUT
passthrough_o.s[3:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
passthrough_o.csb_en	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
passthrough_o.csb	Yes	Yes	T3,T9,T10	Yes	T3,T9,T10	OUTPUT
passthrough_o.sck_en	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
passthrough_o.sck	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
passthrough_o.passthrough_en	Yes	Yes	T46,T49,T66	Yes	T11,T15,T18	OUTPUT
passthrough_i.s[3:0]	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	INPUT
intr_upload_cmdfifo_not_empty_o	Yes	Yes	T34,T37,T39	Yes	T34,T37,T39	OUTPUT
intr_upload_payload_not_empty_o	Yes	Yes	T34,T38,T39	Yes	T34,T38,T39	OUTPUT
intr_upload_payload_overflow_o	Yes	Yes	T34,T37,T38	Yes	T34,T37,T38	OUTPUT
intr_readbuf_watermark_o	Yes	Yes	T34,T37,T38	Yes	T34,T37,T38	OUTPUT
intr_readbuf_flip_o	Yes	Yes	T34,T37,T38	Yes	T34,T37,T38	OUTPUT
intr_tpm_header_not_empty_o	Yes	Yes	T34,T37,T38	Yes	T34,T37,T38	OUTPUT
intr_tpm_rdfifo_cmd_end_o	Yes	Yes	T34,T37,T38	Yes	T34,T37,T38	OUTPUT
intr_tpm_rdfifo_drop_o	Yes	Yes	T34,T37,T38	Yes	T34,T37,T38	OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0]	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.b_ram_lcfg.cfg_en	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.b_ram_lcfg.test	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0]	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.a_ram_lcfg.cfg_en	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.a_ram_lcfg.test	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0]	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.b_ram_fcfg.cfg_en	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.b_ram_fcfg.test	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0]	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.a_ram_fcfg.cfg_en	Yes	Yes	T2	Yes	T2	INPUT
ram_cfg_i.a_ram_fcfg.test	Yes	Yes	T2	Yes	T2	INPUT
sck_monitor_o	Yes	Yes	T4,T5,T11	Yes	T4,T5,T11	OUTPUT
mbist_en_i	Unreachable	Unreachable		Unreachable		INPUT
scan_clk_i	No	No		No		INPUT
scan_rst_ni	No	No		No		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut

	Line No.	Total	Covered	Percent
Branches		31	29	93.55
IF	539	3	3	100.00
IF	828	2	2	100.00
CASE	844	4	4	100.00
IF	885	3	3	100.00
CASE	901	6	5	83.33
IF	1028	2	2	100.00
IF	1044	5	4	80.00
IF	1078	2	2	100.00
IF	1725	2	2	100.00
IF	1735	2	2	100.00

539            if (!rst_ni) begin
               -1-  
540              readbuf_addr_busclk <= '0;
                 ==>
541            end else if (sys_csb_deasserted_pulse) begin
                        -2-  
542              readbuf_addr_busclk <= readbuf_addr_sck;
                 ==>
543            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T11,T15,T16
0	0	Covered	T1,T2,T3

828            if (!rst_spi_out_n) io_mode_outclk <= SingleIO;
               -1-  
               ==>
829            else                io_mode_outclk <= io_mode;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T11,T15,T16

844            unique case (cmd_dp_sel)
                      -1-  
845              DpReadCmd, DpReadSFDP: begin
846                // SRAM:: Remember this has glitch
847                // switch should happen only when clock gate is disabled.
848                flash_sram_l2m = sub_sram_l2m[IoModeReadCmd];
                   ==>
849                sub_sram_m2l[IoModeReadCmd] = flash_sram_m2l;
850              end
851        
852              DpUpload: begin
853                flash_sram_l2m = sub_sram_l2m[IoModeUpload];
                   ==>
854                sub_sram_m2l[IoModeUpload] = flash_sram_m2l;
855              end
856        
857              default: begin
858                if (cmd_only_dp_sel == DpUpload) begin
                   -2-  
859                  // Be ready to upload commands on the 8th command bit, when directed
860                  flash_sram_l2m = sub_sram_l2m[IoModeUpload];
                     ==>
861                  sub_sram_m2l[IoModeUpload] = flash_sram_m2l;
862                end else begin
863                  // DpNone, DpReadStatus, DpReadJEDEC
864                  flash_sram_l2m = '{default: '0 };
                     ==>

Branches:

-1-	-2-	Status	Tests
DpReadCmd DpReadSFDP	-	Covered	T15,T16,T22
DpUpload	-	Covered	T41,T46,T49
default	1	Covered	T41,T46,T49
default	0	Covered	T1,T2,T3

885            if (!sck_csb && ((spi_mode == FlashMode) || (spi_mode == PassThrough))) begin
               -1-  
886              mem_b_l2m = flash_sram_l2m;
                 ==>
887              flash_sram_m2l = mem_b_m2l;
888            end else if (cfg_tpm_en) begin
                        -2-  
889              mem_b_l2m = tpm_sram_l2m;
                 ==>
890              tpm_sram_m2l = mem_b_m2l;
891            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T9,T10
0	1	Covered	T4,T5,T13
0	0	Covered	T1,T2,T3

901            unique case (spi_mode)
                      -1-  
902              FlashMode, PassThrough: begin
903                unique case (cmd_dp_sel)
                          -2-  
904                  DpNone: begin
905                    io_mode = sub_iomode[IoModeCmdParse];
                       ==>
906        
907                    sub_p2s_sent[IoModeCmdParse] = p2s_sent;
908        
909                  end
910                  DpReadCmd, DpReadSFDP: begin
911                    io_mode = sub_iomode[IoModeReadCmd];
                       ==>
912        
913                    p2s_valid = sub_p2s_valid[IoModeReadCmd];
914                    p2s_data  = sub_p2s_data[IoModeReadCmd];
915                    sub_p2s_sent[IoModeReadCmd] = p2s_sent;
916                  end
917                  DpReadStatus: begin
918                    io_mode = sub_iomode[IoModeStatus];
                       ==>
919        
920                    p2s_valid = sub_p2s_valid[IoModeStatus];
921                    p2s_data  = sub_p2s_data[IoModeStatus];
922                    sub_p2s_sent[IoModeStatus] = p2s_sent;
923        
924                  end
925        
926                  DpReadJEDEC: begin
927                    io_mode = sub_iomode[IoModeJedec];
                       ==>
928        
929                    p2s_valid = sub_p2s_valid[IoModeJedec];
930                    p2s_data  = sub_p2s_data[IoModeJedec];
931                    sub_p2s_sent[IoModeJedec] = p2s_sent;
932                  end
933        
934                  DpUpload: begin
935                    io_mode = sub_iomode[IoModeUpload];
                       ==>
936        
937                    p2s_valid = sub_p2s_valid[IoModeUpload];
938                    p2s_data  = sub_p2s_data[IoModeUpload];
939                    sub_p2s_sent[IoModeUpload] = p2s_sent;
940                  end
941                  // DpUnknown:
942                  default: begin
943                    io_mode = sub_iomode[IoModeCmdParse];
                       ==> (Excluded)
Exclude Annotation: VC_COV_UNR
944        
945                    sub_p2s_sent[IoModeCmdParse] = p2s_sent;
946                  end
947                endcase
948              end
949        
950              default: begin
951                io_mode = SingleIO;
                   ==>

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
FlashMode PassThrough	DpNone	Covered	T1,T2,T3
FlashMode PassThrough	DpReadCmd DpReadSFDP	Covered	T15,T16,T22
FlashMode PassThrough	DpReadStatus	Covered	T24,T63,T61
FlashMode PassThrough	DpReadJEDEC	Covered	T101,T41,T46
FlashMode PassThrough	DpUpload	Covered	T41,T46,T49
FlashMode PassThrough	default	Excluded		VC_COV_UNR
default	-	Not Covered

1028           if (cmd_read_pipeline_sel) begin
               -1-  
1029             internal_sd_out = internal_sd_stg2_q;
                 ==>
1030             internal_sd_en_out = internal_sd_en_stg2;
1031             intercept_en_out = intercept_en_stg2;
1032           end else begin
1033             internal_sd_out = internal_sd;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T15,T16,T22
0	Covered	T1,T2,T3

1044           if (cfg_tpm_en && !sck_tpm_csb_buf) begin : miso_tpm
               -1-  
1045             // TPM transaction is on-going. MOSI, MISO is being used by TPM
1046             cio_sd_o    = {2'b 00, tpm_miso,    1'b 0};
                 ==>
1047             cio_sd_en_o = {2'b 00, tpm_miso_en, 1'b 0};
1048       
1049           end else begin : spi_out_flash_passthrough
1050             // SPI Flash, Passthrough modes
1051             unique case (spi_mode)
                        -2-  
1052               FlashMode: begin
1053                 cio_sd_o    = internal_sd_out;
                     ==>
1054                 cio_sd_en_o = internal_sd_en_out;
1055               end
1056       
1057               PassThrough: begin
1058                 if (intercept_en_out) begin
                     -3-  
1059                   cio_sd_o    = internal_sd_out;
                       ==>
1060                   cio_sd_en_o = internal_sd_en_out;
1061                 end else begin
1062                   cio_sd_o    = passthrough_sd;
                       ==>
1063                   cio_sd_en_o = passthrough_sd_en;
1064                 end
1065               end
1066       
1067               default: begin
1068                 cio_sd_o    = internal_sd;
                     ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T4,T5,T13
0	FlashMode	-	Covered	T1,T2,T3
0	PassThrough	1	Covered	T24,T58,T63
0	PassThrough	0	Covered	T11,T15,T18
0	default	-	Not Covered

1078           if (!rst_spi_out_n) intercept_en <= 1'b 0;
               -1-  
               ==>
1079           else                intercept_en <= |intercept;
               ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T11,T15,T16

1725             if ((i != SysSramFwEgress) && (i != SysSramFwIngress)) begin
                 -1-  
1726               sys_sram_hw_req |= sys_sram_l2m[i].req;
                   ==>
1727             end
                 MISSING_ELSE
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

1735           if (sys_sram_hw_req) begin
               -1-  
1736             // Fixed low priority. (Discussed in #10065)
1737             // When HW requests the SRAM access, lower the SW requests (and grant)
1738             sys_sram_req[SysSramFwEgress] = 1'b0;
                 ==>
1739             sys_sram_fw_gnt[SPI_DEVICE_EGRESS_BUFFER_IDX] = 1'b0;
1740             sys_sram_req[SysSramFwIngress] = 1'b0;
1741             sys_sram_fw_gnt[SPI_DEVICE_INGRESS_BUFFER_IDX] = 1'b0;
1742           end else begin
1743             sys_sram_fw_gnt[SPI_DEVICE_EGRESS_BUFFER_IDX] = sys_sram_gnt[SysSramFwEgress];
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T5,T14,T26
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	22	22	100.00	21	95.45
Cover properties	0	0		0
Cover sequences	0	0		0
Total	22	22	100.00	21	95.45

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertKnownO_A	505580215	505494102	0	0
CioSdoEnOKnown	505580215	505494102	0	0
CioSdoEnOffWhenInactive	505580215	505494102	0	0
FpvSecCmRegWeOnehotCheck_A	505580215	90	0	0
InterceptLevel_M	150958911	0	0	0
IntrReadbufFlipOKnown	505580215	505494102	0	0
IntrReadbufWatermarkOKnown	505580215	505494102	0	0
IntrTpmHeaderNotEmptyOKnown	505580215	505494102	0	0
IntrTpmRdfifoCmdEndOKnown	505580215	505494102	0	0
IntrTpmRdfifoDropOKnown	505580215	505494102	0	0
IntrUploadCmdfifoNotEmptyOKnown	505580215	505494102	0	0
IntrUploadPayloadNotEmptyOKnown	505580215	505494102	0	0
IntrUploadPayloadOverflowOKnown	505580215	505494102	0	0
PayloadStartIdxWidthMatch_A	955	955	0	0
SpiModeKnown_A	505580215	505494102	0	0
TpmEnableWhenTpmCsbIdle_M	505580215	344	0	0
g_sram_connect[0].ReqAlwaysAccepted_A	505580215	1910848	0	0
g_sram_connect[1].ReqAlwaysAccepted_A	505580215	174368	0	0
g_sram_connect[2].ReqAlwaysAccepted_A	505580215	2388	0	0
g_sram_connect[3].ReqAlwaysAccepted_A	505580215	1816	0	0
g_sram_connect[4].ReqAlwaysAccepted_A	505580215	184894	0	0
scanmodeKnown	505580215	505580215	0	0

AlertKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

CioSdoEnOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

CioSdoEnOffWhenInactive

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	90	0	0
T1	9378	30	0	0
T2	1547	0	0	0
T3	1633	0	0	0
T4	4740	0	0	0
T5	2209	0	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T12	0	10	0	0
T21	0	10	0	0
T33	0	10	0	0
T35	0	30	0	0

InterceptLevel_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	150958911	0	0	0

IntrReadbufFlipOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

IntrReadbufWatermarkOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

IntrTpmHeaderNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

IntrTpmRdfifoCmdEndOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

IntrTpmRdfifoDropOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

IntrUploadCmdfifoNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

IntrUploadPayloadNotEmptyOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

IntrUploadPayloadOverflowOKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

PayloadStartIdxWidthMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

SpiModeKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505494102	0	0
T1	9378	6951	0	0
T2	1547	1484	0	0
T3	1633	1571	0	0
T4	4740	4683	0	0
T5	2209	2135	0	0
T6	1339	1247	0	0
T7	1300	1203	0	0
T8	1043	953	0	0
T9	1754	1657	0	0
T10	2086	2028	0	0

TpmEnableWhenTpmCsbIdle_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	344	0	0
T4	4740	1	0	0
T5	2209	1	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3501	0	0	0
T12	3439	0	0	0
T13	2415	1	0	0
T14	0	1	0	0
T17	0	1	0	0
T26	0	1	0	0
T28	0	1	0	0
T29	0	1	0	0
T30	0	1	0	0
T32	0	1	0	0

g_sram_connect[0].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	1910848	0	0
T11	3501	832	0	0
T13	2415	0	0	0
T14	4756	0	0	0
T15	51882	832	0	0
T16	16407	832	0	0
T17	135126	0	0	0
T18	9552	832	0	0
T19	19411	832	0	0
T20	8263	832	0	0
T21	3098	0	0	0
T22	0	832	0	0
T23	0	832	0	0
T24	0	832	0	0
T25	0	2112	0	0

g_sram_connect[1].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	174368	0	0
T5	2209	14	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3501	0	0	0
T12	3439	0	0	0
T13	2415	0	0	0
T14	4756	1	0	0
T26	0	218	0	0
T41	0	64	0	0
T42	0	715	0	0
T43	0	1014	0	0
T46	0	483	0	0
T47	0	16	0	0
T48	0	386	0	0
T49	0	352	0	0

g_sram_connect[2].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	2388	0	0
T34	5267	0	0	0
T41	169152	1	0	0
T42	243769	0	0	0
T43	551832	0	0	0
T46	0	14	0	0
T47	4500	0	0	0
T49	0	8	0	0
T54	0	8	0	0
T55	0	7	0	0
T56	8151	0	0	0
T64	0	9	0	0
T66	0	3	0	0
T69	0	17	0	0
T81	30165	0	0	0
T82	619815	0	0	0
T83	12712	0	0	0
T96	0	4	0	0
T97	0	3	0	0
T98	8996	0	0	0

g_sram_connect[3].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	1816	0	0
T34	5267	0	0	0
T41	169152	1	0	0
T42	243769	0	0	0
T43	551832	0	0	0
T46	0	11	0	0
T47	4500	0	0	0
T49	0	6	0	0
T54	0	5	0	0
T55	0	5	0	0
T56	8151	0	0	0
T64	0	8	0	0
T66	0	3	0	0
T69	0	17	0	0
T81	30165	0	0	0
T82	619815	0	0	0
T83	12712	0	0	0
T96	0	4	0	0
T97	0	2	0	0
T98	8996	0	0	0

g_sram_connect[4].ReqAlwaysAccepted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	184894	0	0
T5	2209	2	0	0
T6	1339	0	0	0
T7	1300	0	0	0
T8	1043	0	0	0
T9	1754	0	0	0
T10	2086	0	0	0
T11	3501	0	0	0
T12	3439	0	0	0
T13	2415	0	0	0
T14	4756	6	0	0
T26	0	468	0	0
T32	0	1	0	0
T42	0	1519	0	0
T43	0	1718	0	0
T47	0	16	0	0
T48	0	895	0	0
T79	0	2	0	0
T80	0	59	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	505580215	505580215	0	0
T1	9378	9378	0	0
T2	1547	1547	0	0
T3	1633	1633	0	0
T4	4740	4740	0	0
T5	2209	2209	0	0
T6	1339	1339	0	0
T7	1300	1300	0	0
T8	1043	1043	0	0
T9	1754	1754	0	0
T10	2086	2086	0	0