| T432 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.3783940170 |
|
|
Oct 15 06:04:39 AM UTC 24 |
Oct 15 06:04:53 AM UTC 24 |
10145362227 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.1819252074 |
|
|
Oct 15 06:03:56 AM UTC 24 |
Oct 15 06:04:54 AM UTC 24 |
2251891092 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.1791578501 |
|
|
Oct 15 06:04:37 AM UTC 24 |
Oct 15 06:04:57 AM UTC 24 |
8776573630 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3110785362 |
|
|
Oct 15 06:02:19 AM UTC 24 |
Oct 15 06:05:00 AM UTC 24 |
16371033294 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.1167175549 |
|
|
Oct 15 06:04:54 AM UTC 24 |
Oct 15 06:05:01 AM UTC 24 |
141222929 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.3566897698 |
|
|
Oct 15 06:04:09 AM UTC 24 |
Oct 15 06:05:07 AM UTC 24 |
14950240674 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.4023111655 |
|
|
Oct 15 06:01:43 AM UTC 24 |
Oct 15 06:05:08 AM UTC 24 |
12423298228 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.656498379 |
|
|
Oct 15 06:04:33 AM UTC 24 |
Oct 15 06:05:08 AM UTC 24 |
65678325131 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.313912350 |
|
|
Oct 15 06:05:09 AM UTC 24 |
Oct 15 06:05:11 AM UTC 24 |
20717356 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.3471707361 |
|
|
Oct 15 06:05:09 AM UTC 24 |
Oct 15 06:05:11 AM UTC 24 |
14201519 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.1842795171 |
|
|
Oct 15 06:06:40 AM UTC 24 |
Oct 15 06:06:49 AM UTC 24 |
1830206708 ps |
| T64 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.1803671052 |
|
|
Oct 15 06:03:44 AM UTC 24 |
Oct 15 06:05:11 AM UTC 24 |
35852794277 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.3887769415 |
|
|
Oct 15 06:05:12 AM UTC 24 |
Oct 15 06:05:14 AM UTC 24 |
50682518 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.3306345585 |
|
|
Oct 15 06:05:12 AM UTC 24 |
Oct 15 06:05:15 AM UTC 24 |
71441267 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.3836266102 |
|
|
Oct 15 05:56:26 AM UTC 24 |
Oct 15 06:05:21 AM UTC 24 |
52916225625 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.441208467 |
|
|
Oct 15 06:04:52 AM UTC 24 |
Oct 15 06:05:22 AM UTC 24 |
7092519495 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.2498555102 |
|
|
Oct 15 06:04:43 AM UTC 24 |
Oct 15 06:05:25 AM UTC 24 |
23890007415 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2908635148 |
|
|
Oct 15 06:02:48 AM UTC 24 |
Oct 15 06:05:25 AM UTC 24 |
33281732344 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.1800935801 |
|
|
Oct 15 05:59:45 AM UTC 24 |
Oct 15 06:05:26 AM UTC 24 |
144173814104 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.1928009103 |
|
|
Oct 15 06:05:16 AM UTC 24 |
Oct 15 06:05:28 AM UTC 24 |
1970246278 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.3899980026 |
|
|
Oct 15 06:05:22 AM UTC 24 |
Oct 15 06:05:29 AM UTC 24 |
675183948 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.3475561956 |
|
|
Oct 15 06:05:12 AM UTC 24 |
Oct 15 06:05:30 AM UTC 24 |
1701100929 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.3874285882 |
|
|
Oct 15 06:02:47 AM UTC 24 |
Oct 15 06:05:30 AM UTC 24 |
82213817345 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.1072612923 |
|
|
Oct 15 06:04:12 AM UTC 24 |
Oct 15 06:05:34 AM UTC 24 |
11109049717 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.3049895253 |
|
|
Oct 15 06:05:27 AM UTC 24 |
Oct 15 06:05:34 AM UTC 24 |
195011150 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.252855034 |
|
|
Oct 15 06:04:19 AM UTC 24 |
Oct 15 06:05:38 AM UTC 24 |
12675770753 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.3961159721 |
|
|
Oct 15 06:05:31 AM UTC 24 |
Oct 15 06:05:39 AM UTC 24 |
210063218 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.3503233660 |
|
|
Oct 15 06:05:12 AM UTC 24 |
Oct 15 06:05:39 AM UTC 24 |
13542900013 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.2448032991 |
|
|
Oct 15 06:05:38 AM UTC 24 |
Oct 15 06:05:40 AM UTC 24 |
24107735 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.1755714623 |
|
|
Oct 15 06:05:40 AM UTC 24 |
Oct 15 06:05:42 AM UTC 24 |
14881417 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.1463236721 |
|
|
Oct 15 06:05:44 AM UTC 24 |
Oct 15 06:05:46 AM UTC 24 |
50584010 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.4069870813 |
|
|
Oct 15 06:05:26 AM UTC 24 |
Oct 15 06:05:49 AM UTC 24 |
15821289921 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.1754208410 |
|
|
Oct 15 06:05:47 AM UTC 24 |
Oct 15 06:05:50 AM UTC 24 |
67195782 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2299085805 |
|
|
Oct 15 06:05:26 AM UTC 24 |
Oct 15 06:05:51 AM UTC 24 |
5544169123 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.3345741220 |
|
|
Oct 15 06:05:23 AM UTC 24 |
Oct 15 06:05:51 AM UTC 24 |
16769451424 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.2260889595 |
|
|
Oct 15 06:05:50 AM UTC 24 |
Oct 15 06:05:54 AM UTC 24 |
298941999 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.2470223526 |
|
|
Oct 15 06:05:51 AM UTC 24 |
Oct 15 06:05:55 AM UTC 24 |
33843387 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.1659266563 |
|
|
Oct 15 06:05:15 AM UTC 24 |
Oct 15 06:05:56 AM UTC 24 |
37113548055 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.366903227 |
|
|
Oct 15 06:05:52 AM UTC 24 |
Oct 15 06:05:57 AM UTC 24 |
299083659 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.56965077 |
|
|
Oct 15 06:05:41 AM UTC 24 |
Oct 15 06:05:58 AM UTC 24 |
59221796114 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.4161263168 |
|
|
Oct 15 06:02:45 AM UTC 24 |
Oct 15 06:05:58 AM UTC 24 |
87313466212 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.3226028341 |
|
|
Oct 15 06:05:56 AM UTC 24 |
Oct 15 06:06:01 AM UTC 24 |
457003242 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.849919902 |
|
|
Oct 15 06:05:59 AM UTC 24 |
Oct 15 06:06:21 AM UTC 24 |
1316299502 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.585606948 |
|
|
Oct 15 06:05:43 AM UTC 24 |
Oct 15 06:06:22 AM UTC 24 |
11924998315 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.229661469 |
|
|
Oct 15 06:03:13 AM UTC 24 |
Oct 15 06:06:25 AM UTC 24 |
98859195765 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.1492668475 |
|
|
Oct 15 06:05:58 AM UTC 24 |
Oct 15 06:06:26 AM UTC 24 |
1188213600 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.1966452899 |
|
|
Oct 15 06:04:20 AM UTC 24 |
Oct 15 06:06:26 AM UTC 24 |
40284599486 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.1200090799 |
|
|
Oct 15 06:06:27 AM UTC 24 |
Oct 15 06:06:29 AM UTC 24 |
20170221 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.1876345895 |
|
|
Oct 15 06:06:27 AM UTC 24 |
Oct 15 06:06:29 AM UTC 24 |
21386792 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.256890950 |
|
|
Oct 15 06:06:30 AM UTC 24 |
Oct 15 06:06:33 AM UTC 24 |
14337343 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.1938476249 |
|
|
Oct 15 06:06:30 AM UTC 24 |
Oct 15 06:06:33 AM UTC 24 |
114102353 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.3776549485 |
|
|
Oct 15 06:05:35 AM UTC 24 |
Oct 15 06:06:34 AM UTC 24 |
58586423551 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.3645179927 |
|
|
Oct 15 06:06:28 AM UTC 24 |
Oct 15 06:06:38 AM UTC 24 |
685415964 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3859489106 |
|
|
Oct 15 06:03:39 AM UTC 24 |
Oct 15 06:06:39 AM UTC 24 |
13953191397 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.2506816199 |
|
|
Oct 15 06:06:35 AM UTC 24 |
Oct 15 06:06:39 AM UTC 24 |
214264787 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.2417160081 |
|
|
Oct 15 06:05:55 AM UTC 24 |
Oct 15 06:06:40 AM UTC 24 |
15376278248 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.2745933181 |
|
|
Oct 15 06:06:31 AM UTC 24 |
Oct 15 06:06:42 AM UTC 24 |
688180032 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.3806114179 |
|
|
Oct 15 06:06:35 AM UTC 24 |
Oct 15 06:06:43 AM UTC 24 |
8356061417 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.1574608230 |
|
|
Oct 15 06:06:34 AM UTC 24 |
Oct 15 06:06:47 AM UTC 24 |
757983509 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.2817235570 |
|
|
Oct 15 06:06:44 AM UTC 24 |
Oct 15 06:06:50 AM UTC 24 |
145120133 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.1096074291 |
|
|
Oct 15 06:06:41 AM UTC 24 |
Oct 15 06:06:51 AM UTC 24 |
791936236 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.2291390130 |
|
|
Oct 15 06:06:52 AM UTC 24 |
Oct 15 06:06:54 AM UTC 24 |
14408998 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.358413338 |
|
|
Oct 15 06:05:58 AM UTC 24 |
Oct 15 06:06:54 AM UTC 24 |
56016247591 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.4223583416 |
|
|
Oct 15 06:06:52 AM UTC 24 |
Oct 15 06:06:54 AM UTC 24 |
89787372 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.2749265531 |
|
|
Oct 15 06:06:48 AM UTC 24 |
Oct 15 06:06:55 AM UTC 24 |
1462175064 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.3769414899 |
|
|
Oct 15 06:06:53 AM UTC 24 |
Oct 15 06:06:55 AM UTC 24 |
31952211 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.127366241 |
|
|
Oct 15 06:06:38 AM UTC 24 |
Oct 15 06:06:55 AM UTC 24 |
6159943792 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.3110439657 |
|
|
Oct 15 06:06:56 AM UTC 24 |
Oct 15 06:06:59 AM UTC 24 |
278273393 ps |
| T66 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.831243741 |
|
|
Oct 15 06:03:19 AM UTC 24 |
Oct 15 06:06:59 AM UTC 24 |
34149176405 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.1302459701 |
|
|
Oct 15 06:06:57 AM UTC 24 |
Oct 15 06:07:03 AM UTC 24 |
333086802 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.2999657563 |
|
|
Oct 15 06:06:57 AM UTC 24 |
Oct 15 06:07:04 AM UTC 24 |
623905148 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.3762815527 |
|
|
Oct 15 06:05:35 AM UTC 24 |
Oct 15 06:07:05 AM UTC 24 |
13475710316 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.3371489823 |
|
|
Oct 15 06:07:00 AM UTC 24 |
Oct 15 06:07:08 AM UTC 24 |
179001008 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.3212664752 |
|
|
Oct 15 06:06:55 AM UTC 24 |
Oct 15 06:07:10 AM UTC 24 |
6678022242 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.3481612460 |
|
|
Oct 15 06:06:58 AM UTC 24 |
Oct 15 06:07:10 AM UTC 24 |
625885711 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.750710880 |
|
|
Oct 15 06:04:15 AM UTC 24 |
Oct 15 06:07:10 AM UTC 24 |
53913360079 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.3157493898 |
|
|
Oct 15 06:04:53 AM UTC 24 |
Oct 15 06:07:11 AM UTC 24 |
53376589289 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.1197387626 |
|
|
Oct 15 06:07:11 AM UTC 24 |
Oct 15 06:07:17 AM UTC 24 |
437827016 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.922257664 |
|
|
Oct 15 06:07:06 AM UTC 24 |
Oct 15 06:07:18 AM UTC 24 |
1147708899 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.245481301 |
|
|
Oct 15 06:07:03 AM UTC 24 |
Oct 15 06:07:18 AM UTC 24 |
726910661 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.2749765452 |
|
|
Oct 15 06:07:19 AM UTC 24 |
Oct 15 06:07:21 AM UTC 24 |
53565087 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.285570305 |
|
|
Oct 15 06:00:29 AM UTC 24 |
Oct 15 06:07:21 AM UTC 24 |
38027994896 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.3171646164 |
|
|
Oct 15 06:07:20 AM UTC 24 |
Oct 15 06:07:22 AM UTC 24 |
17455861 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.3714998981 |
|
|
Oct 15 06:07:00 AM UTC 24 |
Oct 15 06:07:22 AM UTC 24 |
5253551245 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.3588600753 |
|
|
Oct 15 06:06:50 AM UTC 24 |
Oct 15 06:07:24 AM UTC 24 |
6696747419 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.898433795 |
|
|
Oct 15 06:07:05 AM UTC 24 |
Oct 15 06:07:26 AM UTC 24 |
4401046261 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.949052006 |
|
|
Oct 15 06:07:23 AM UTC 24 |
Oct 15 06:07:26 AM UTC 24 |
179016285 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.1888187802 |
|
|
Oct 15 06:06:55 AM UTC 24 |
Oct 15 06:07:26 AM UTC 24 |
4134676152 ps |
| T90 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.3882409246 |
|
|
Oct 15 06:05:31 AM UTC 24 |
Oct 15 06:07:28 AM UTC 24 |
4925748890 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.930031668 |
|
|
Oct 15 06:07:24 AM UTC 24 |
Oct 15 06:07:29 AM UTC 24 |
2837025115 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.2038025133 |
|
|
Oct 15 06:07:27 AM UTC 24 |
Oct 15 06:07:31 AM UTC 24 |
106911079 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.2427534907 |
|
|
Oct 15 06:07:11 AM UTC 24 |
Oct 15 06:07:32 AM UTC 24 |
1538532769 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.422922332 |
|
|
Oct 15 06:07:26 AM UTC 24 |
Oct 15 06:07:32 AM UTC 24 |
628302953 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.2866322285 |
|
|
Oct 15 06:07:23 AM UTC 24 |
Oct 15 06:07:33 AM UTC 24 |
1852032273 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3514129782 |
|
|
Oct 15 06:03:13 AM UTC 24 |
Oct 15 06:07:33 AM UTC 24 |
26119042106 ps |
| T197 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.3794045623 |
|
|
Oct 15 06:07:29 AM UTC 24 |
Oct 15 06:07:34 AM UTC 24 |
55895400 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.251058070 |
|
|
Oct 15 06:07:30 AM UTC 24 |
Oct 15 06:07:34 AM UTC 24 |
51803374 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.259013699 |
|
|
Oct 15 06:04:55 AM UTC 24 |
Oct 15 06:07:36 AM UTC 24 |
64973670104 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.1734962602 |
|
|
Oct 15 06:07:38 AM UTC 24 |
Oct 15 06:07:40 AM UTC 24 |
120881038 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.2395644453 |
|
|
Oct 15 06:07:38 AM UTC 24 |
Oct 15 06:07:40 AM UTC 24 |
16263640 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.3837264713 |
|
|
Oct 15 06:07:27 AM UTC 24 |
Oct 15 06:07:43 AM UTC 24 |
2383148042 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.3390337395 |
|
|
Oct 15 06:07:44 AM UTC 24 |
Oct 15 06:07:47 AM UTC 24 |
494127392 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.2240468958 |
|
|
Oct 15 06:07:27 AM UTC 24 |
Oct 15 06:07:47 AM UTC 24 |
4679203928 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.1462402646 |
|
|
Oct 15 06:05:01 AM UTC 24 |
Oct 15 06:07:48 AM UTC 24 |
16955308926 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.499056163 |
|
|
Oct 15 06:01:04 AM UTC 24 |
Oct 15 06:07:48 AM UTC 24 |
43323387409 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.2898768036 |
|
|
Oct 15 06:07:34 AM UTC 24 |
Oct 15 06:07:49 AM UTC 24 |
1537488830 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.1940985010 |
|
|
Oct 15 06:07:47 AM UTC 24 |
Oct 15 06:07:50 AM UTC 24 |
65045393 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.3581518185 |
|
|
Oct 15 06:07:23 AM UTC 24 |
Oct 15 06:07:53 AM UTC 24 |
3177534026 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.45103945 |
|
|
Oct 15 06:07:35 AM UTC 24 |
Oct 15 06:07:54 AM UTC 24 |
2305717868 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.3671854158 |
|
|
Oct 15 06:07:41 AM UTC 24 |
Oct 15 06:07:54 AM UTC 24 |
8806435020 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.1568954094 |
|
|
Oct 15 06:07:41 AM UTC 24 |
Oct 15 06:07:57 AM UTC 24 |
1320817075 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.2360934927 |
|
|
Oct 15 06:07:51 AM UTC 24 |
Oct 15 06:07:57 AM UTC 24 |
950362771 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.3586078515 |
|
|
Oct 15 06:05:59 AM UTC 24 |
Oct 15 06:07:57 AM UTC 24 |
11656656275 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.832027363 |
|
|
Oct 15 06:07:49 AM UTC 24 |
Oct 15 06:08:01 AM UTC 24 |
3349498426 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.3516579726 |
|
|
Oct 15 06:07:54 AM UTC 24 |
Oct 15 06:08:05 AM UTC 24 |
1906873884 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.100387065 |
|
|
Oct 15 06:05:53 AM UTC 24 |
Oct 15 06:08:05 AM UTC 24 |
62667710728 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.2445484929 |
|
|
Oct 15 06:07:32 AM UTC 24 |
Oct 15 06:08:06 AM UTC 24 |
13571044312 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.958583790 |
|
|
Oct 15 06:07:55 AM UTC 24 |
Oct 15 06:08:07 AM UTC 24 |
155501061 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.958095672 |
|
|
Oct 15 06:08:06 AM UTC 24 |
Oct 15 06:08:09 AM UTC 24 |
128031304 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.820026618 |
|
|
Oct 15 06:07:47 AM UTC 24 |
Oct 15 06:08:10 AM UTC 24 |
1492429475 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.3397728789 |
|
|
Oct 15 06:08:08 AM UTC 24 |
Oct 15 06:08:10 AM UTC 24 |
69706407 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.4183634488 |
|
|
Oct 15 06:07:59 AM UTC 24 |
Oct 15 06:08:10 AM UTC 24 |
506227440 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.1525666169 |
|
|
Oct 15 06:00:26 AM UTC 24 |
Oct 15 06:08:12 AM UTC 24 |
174469772333 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.981558728 |
|
|
Oct 15 06:08:11 AM UTC 24 |
Oct 15 06:08:13 AM UTC 24 |
27570155 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.1043534186 |
|
|
Oct 15 06:07:49 AM UTC 24 |
Oct 15 06:08:14 AM UTC 24 |
27201383026 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.4007040442 |
|
|
Oct 15 06:08:11 AM UTC 24 |
Oct 15 06:08:14 AM UTC 24 |
132019968 ps |
| T206 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.3591228206 |
|
|
Oct 15 06:07:50 AM UTC 24 |
Oct 15 06:08:15 AM UTC 24 |
3253501176 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.1925320626 |
|
|
Oct 15 06:08:11 AM UTC 24 |
Oct 15 06:08:15 AM UTC 24 |
74812383 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.954925409 |
|
|
Oct 15 06:08:12 AM UTC 24 |
Oct 15 06:08:17 AM UTC 24 |
32449136 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.262430386 |
|
|
Oct 15 06:08:08 AM UTC 24 |
Oct 15 06:08:18 AM UTC 24 |
1252506647 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.2493564864 |
|
|
Oct 15 06:08:15 AM UTC 24 |
Oct 15 06:08:20 AM UTC 24 |
784038440 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.3131423440 |
|
|
Oct 15 06:08:16 AM UTC 24 |
Oct 15 06:08:26 AM UTC 24 |
319043366 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.2667758581 |
|
|
Oct 15 06:08:16 AM UTC 24 |
Oct 15 06:08:26 AM UTC 24 |
858222440 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.494057643 |
|
|
Oct 15 06:07:09 AM UTC 24 |
Oct 15 06:08:29 AM UTC 24 |
4437297003 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.1893619044 |
|
|
Oct 15 06:08:15 AM UTC 24 |
Oct 15 06:08:30 AM UTC 24 |
542698506 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.1648780372 |
|
|
Oct 15 06:03:38 AM UTC 24 |
Oct 15 06:08:31 AM UTC 24 |
92721363542 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.4046858365 |
|
|
Oct 15 06:08:18 AM UTC 24 |
Oct 15 06:08:31 AM UTC 24 |
3125940826 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.2526418034 |
|
|
Oct 15 06:08:10 AM UTC 24 |
Oct 15 06:08:32 AM UTC 24 |
1372591722 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.2709292715 |
|
|
Oct 15 06:08:32 AM UTC 24 |
Oct 15 06:08:34 AM UTC 24 |
43880400 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.1092133848 |
|
|
Oct 15 06:08:32 AM UTC 24 |
Oct 15 06:08:34 AM UTC 24 |
52075949 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.1602592471 |
|
|
Oct 15 06:08:15 AM UTC 24 |
Oct 15 06:08:34 AM UTC 24 |
9444045939 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.2703256054 |
|
|
Oct 15 06:08:34 AM UTC 24 |
Oct 15 06:08:36 AM UTC 24 |
79792984 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.140253422 |
|
|
Oct 15 06:08:34 AM UTC 24 |
Oct 15 06:08:37 AM UTC 24 |
45661656 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.1731800620 |
|
|
Oct 15 06:08:35 AM UTC 24 |
Oct 15 06:08:40 AM UTC 24 |
32565397 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.908029882 |
|
|
Oct 15 06:08:02 AM UTC 24 |
Oct 15 06:08:40 AM UTC 24 |
5257160512 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.2197468081 |
|
|
Oct 15 06:08:38 AM UTC 24 |
Oct 15 06:08:42 AM UTC 24 |
74472490 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.3086045203 |
|
|
Oct 15 06:08:41 AM UTC 24 |
Oct 15 06:08:47 AM UTC 24 |
166129869 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2353658211 |
|
|
Oct 15 06:08:43 AM UTC 24 |
Oct 15 06:08:48 AM UTC 24 |
168009205 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.1091986421 |
|
|
Oct 15 06:08:33 AM UTC 24 |
Oct 15 06:08:50 AM UTC 24 |
4625621135 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.1701873272 |
|
|
Oct 15 06:08:33 AM UTC 24 |
Oct 15 06:08:53 AM UTC 24 |
2766147970 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.2638739703 |
|
|
Oct 15 06:08:47 AM UTC 24 |
Oct 15 06:08:58 AM UTC 24 |
967996653 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.1258538057 |
|
|
Oct 15 06:08:41 AM UTC 24 |
Oct 15 06:08:58 AM UTC 24 |
4352813802 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.429090478 |
|
|
Oct 15 06:08:51 AM UTC 24 |
Oct 15 06:09:07 AM UTC 24 |
2356143170 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2330564725 |
|
|
Oct 15 06:06:22 AM UTC 24 |
Oct 15 06:09:09 AM UTC 24 |
19772437723 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.1415595038 |
|
|
Oct 15 06:09:11 AM UTC 24 |
Oct 15 06:09:13 AM UTC 24 |
79321307 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.2018764266 |
|
|
Oct 15 06:07:34 AM UTC 24 |
Oct 15 06:09:14 AM UTC 24 |
6282959621 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.2460698401 |
|
|
Oct 15 06:09:14 AM UTC 24 |
Oct 15 06:09:16 AM UTC 24 |
21885723 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.1680079279 |
|
|
Oct 15 06:08:38 AM UTC 24 |
Oct 15 06:09:20 AM UTC 24 |
14810306040 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.1224705172 |
|
|
Oct 15 06:09:15 AM UTC 24 |
Oct 15 06:09:20 AM UTC 24 |
389851818 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.3960473647 |
|
|
Oct 15 06:09:21 AM UTC 24 |
Oct 15 06:09:24 AM UTC 24 |
1470797244 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.2690349974 |
|
|
Oct 15 06:09:21 AM UTC 24 |
Oct 15 06:09:26 AM UTC 24 |
75752735 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1299922677 |
|
|
Oct 15 06:05:32 AM UTC 24 |
Oct 15 06:09:27 AM UTC 24 |
30524939545 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.4052519505 |
|
|
Oct 15 06:07:33 AM UTC 24 |
Oct 15 06:09:30 AM UTC 24 |
31799879939 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.1081342874 |
|
|
Oct 15 06:07:34 AM UTC 24 |
Oct 15 06:09:31 AM UTC 24 |
132628939059 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.2967057971 |
|
|
Oct 15 06:09:25 AM UTC 24 |
Oct 15 06:09:37 AM UTC 24 |
2507604824 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.115071640 |
|
|
Oct 15 06:07:12 AM UTC 24 |
Oct 15 06:09:40 AM UTC 24 |
13986627313 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.367834086 |
|
|
Oct 15 06:09:32 AM UTC 24 |
Oct 15 06:09:42 AM UTC 24 |
4060716963 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.3887833274 |
|
|
Oct 15 06:09:17 AM UTC 24 |
Oct 15 06:09:43 AM UTC 24 |
12660861047 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.3557608253 |
|
|
Oct 15 06:09:43 AM UTC 24 |
Oct 15 06:09:46 AM UTC 24 |
13283458 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.159307880 |
|
|
Oct 15 06:07:35 AM UTC 24 |
Oct 15 06:09:49 AM UTC 24 |
6370797854 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.1256870609 |
|
|
Oct 15 06:09:27 AM UTC 24 |
Oct 15 06:09:50 AM UTC 24 |
1905938415 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.3908889755 |
|
|
Oct 15 06:05:28 AM UTC 24 |
Oct 15 06:09:52 AM UTC 24 |
27368503023 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.2807360500 |
|
|
Oct 15 06:09:50 AM UTC 24 |
Oct 15 06:09:52 AM UTC 24 |
271650282 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.4291482616 |
|
|
Oct 15 06:09:51 AM UTC 24 |
Oct 15 06:09:53 AM UTC 24 |
22308548 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.4068654858 |
|
|
Oct 15 06:09:48 AM UTC 24 |
Oct 15 06:09:54 AM UTC 24 |
1039131754 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.2224596256 |
|
|
Oct 15 06:09:52 AM UTC 24 |
Oct 15 06:09:54 AM UTC 24 |
18082898 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.2593781990 |
|
|
Oct 15 06:04:58 AM UTC 24 |
Oct 15 06:09:55 AM UTC 24 |
535037519413 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.90720283 |
|
|
Oct 15 06:09:56 AM UTC 24 |
Oct 15 06:09:58 AM UTC 24 |
240633357 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.897271026 |
|
|
Oct 15 06:09:38 AM UTC 24 |
Oct 15 06:09:59 AM UTC 24 |
852971136 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.2506208160 |
|
|
Oct 15 06:09:56 AM UTC 24 |
Oct 15 06:10:01 AM UTC 24 |
92926472 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.285664600 |
|
|
Oct 15 06:09:59 AM UTC 24 |
Oct 15 06:10:03 AM UTC 24 |
31784324 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.2015453408 |
|
|
Oct 15 06:01:07 AM UTC 24 |
Oct 15 06:10:03 AM UTC 24 |
88153751103 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2725888786 |
|
|
Oct 15 06:09:41 AM UTC 24 |
Oct 15 06:10:04 AM UTC 24 |
2230027598 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.934918190 |
|
|
Oct 15 06:09:30 AM UTC 24 |
Oct 15 06:10:04 AM UTC 24 |
7551709088 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.64935240 |
|
|
Oct 15 06:10:00 AM UTC 24 |
Oct 15 06:10:04 AM UTC 24 |
139053216 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.2365858244 |
|
|
Oct 15 06:10:03 AM UTC 24 |
Oct 15 06:10:08 AM UTC 24 |
136767064 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.361160609 |
|
|
Oct 15 06:04:27 AM UTC 24 |
Oct 15 06:10:10 AM UTC 24 |
155532328992 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.1479938641 |
|
|
Oct 15 06:09:56 AM UTC 24 |
Oct 15 06:10:10 AM UTC 24 |
2426346070 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.2259527452 |
|
|
Oct 15 06:09:28 AM UTC 24 |
Oct 15 06:10:12 AM UTC 24 |
15415244819 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.3228108078 |
|
|
Oct 15 06:10:05 AM UTC 24 |
Oct 15 06:10:13 AM UTC 24 |
694119920 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.1609553604 |
|
|
Oct 15 06:05:02 AM UTC 24 |
Oct 15 06:10:13 AM UTC 24 |
54214935356 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.2435550897 |
|
|
Oct 15 06:10:13 AM UTC 24 |
Oct 15 06:10:15 AM UTC 24 |
12665861 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.4107317559 |
|
|
Oct 15 06:10:13 AM UTC 24 |
Oct 15 06:10:15 AM UTC 24 |
170710928 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.1601526925 |
|
|
Oct 15 06:10:14 AM UTC 24 |
Oct 15 06:10:16 AM UTC 24 |
17840604 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.3601965664 |
|
|
Oct 15 06:09:53 AM UTC 24 |
Oct 15 06:10:17 AM UTC 24 |
7323713135 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.90191774 |
|
|
Oct 15 06:10:18 AM UTC 24 |
Oct 15 06:10:20 AM UTC 24 |
20064258 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.1888464991 |
|
|
Oct 15 06:09:54 AM UTC 24 |
Oct 15 06:10:21 AM UTC 24 |
1446201380 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.3781485676 |
|
|
Oct 15 06:10:18 AM UTC 24 |
Oct 15 06:10:22 AM UTC 24 |
348482000 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.2285068006 |
|
|
Oct 15 06:10:05 AM UTC 24 |
Oct 15 06:10:23 AM UTC 24 |
6564696592 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.3048701898 |
|
|
Oct 15 06:10:17 AM UTC 24 |
Oct 15 06:10:26 AM UTC 24 |
2002515809 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.3936766831 |
|
|
Oct 15 06:10:21 AM UTC 24 |
Oct 15 06:10:27 AM UTC 24 |
223983913 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.3161406033 |
|
|
Oct 15 06:10:24 AM UTC 24 |
Oct 15 06:10:31 AM UTC 24 |
223283138 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.2545784562 |
|
|
Oct 15 06:08:59 AM UTC 24 |
Oct 15 06:10:32 AM UTC 24 |
14363142230 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.4161813276 |
|
|
Oct 15 06:10:18 AM UTC 24 |
Oct 15 06:10:33 AM UTC 24 |
998591809 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.1420919576 |
|
|
Oct 15 06:09:44 AM UTC 24 |
Oct 15 06:10:33 AM UTC 24 |
9636512094 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.3048451137 |
|
|
Oct 15 06:10:27 AM UTC 24 |
Oct 15 06:10:33 AM UTC 24 |
574943913 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.1924854622 |
|
|
Oct 15 06:07:11 AM UTC 24 |
Oct 15 06:10:35 AM UTC 24 |
34237336906 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.295730803 |
|
|
Oct 15 06:10:42 AM UTC 24 |
Oct 15 06:10:44 AM UTC 24 |
41757847 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2601984258 |
|
|
Oct 15 06:10:32 AM UTC 24 |
Oct 15 06:10:45 AM UTC 24 |
292140318 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.91372049 |
|
|
Oct 15 06:02:20 AM UTC 24 |
Oct 15 06:10:46 AM UTC 24 |
293049601645 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2308426645 |
|
|
Oct 15 06:03:58 AM UTC 24 |
Oct 15 06:10:46 AM UTC 24 |
372870888737 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.2388875145 |
|
|
Oct 15 06:10:27 AM UTC 24 |
Oct 15 06:10:46 AM UTC 24 |
5559399284 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.3968104327 |
|
|
Oct 15 06:10:45 AM UTC 24 |
Oct 15 06:10:47 AM UTC 24 |
52233097 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1674585724 |
|
|
Oct 15 06:10:46 AM UTC 24 |
Oct 15 06:10:49 AM UTC 24 |
100352067 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.184437994 |
|
|
Oct 15 06:08:29 AM UTC 24 |
Oct 15 06:10:49 AM UTC 24 |
42982327400 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.2135783821 |
|
|
Oct 15 06:09:29 AM UTC 24 |
Oct 15 06:10:50 AM UTC 24 |
131474430271 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.536382938 |
|
|
Oct 15 06:10:17 AM UTC 24 |
Oct 15 06:10:50 AM UTC 24 |
3360632269 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.2177131168 |
|
|
Oct 15 06:10:48 AM UTC 24 |
Oct 15 06:10:50 AM UTC 24 |
52439585 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.627362023 |
|
|
Oct 15 06:10:02 AM UTC 24 |
Oct 15 06:10:50 AM UTC 24 |
6374269019 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.1181190159 |
|
|
Oct 15 06:10:05 AM UTC 24 |
Oct 15 06:10:51 AM UTC 24 |
2636724329 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.3529352819 |
|
|
Oct 15 06:10:48 AM UTC 24 |
Oct 15 06:10:52 AM UTC 24 |
170036728 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.341709340 |
|
|
Oct 15 06:10:34 AM UTC 24 |
Oct 15 06:10:54 AM UTC 24 |
1095067809 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.2436979141 |
|
|
Oct 15 06:10:53 AM UTC 24 |
Oct 15 06:10:55 AM UTC 24 |
43919672 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.2753452563 |
|
|
Oct 15 06:10:23 AM UTC 24 |
Oct 15 06:10:56 AM UTC 24 |
1987924568 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.1044627752 |
|
|
Oct 15 06:10:21 AM UTC 24 |
Oct 15 06:10:59 AM UTC 24 |
2925406008 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.1327634467 |
|
|
Oct 15 06:10:53 AM UTC 24 |
Oct 15 06:11:00 AM UTC 24 |
519326192 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.3770405873 |
|
|
Oct 15 06:11:00 AM UTC 24 |
Oct 15 06:11:02 AM UTC 24 |
41873130 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.1950334989 |
|
|
Oct 15 06:11:01 AM UTC 24 |
Oct 15 06:11:03 AM UTC 24 |
23256089 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.3126263790 |
|
|
Oct 15 06:10:51 AM UTC 24 |
Oct 15 06:11:04 AM UTC 24 |
1641547404 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.3531735883 |
|
|
Oct 15 06:11:05 AM UTC 24 |
Oct 15 06:11:07 AM UTC 24 |
68275423 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.795180991 |
|
|
Oct 15 06:11:05 AM UTC 24 |
Oct 15 06:11:07 AM UTC 24 |
78679175 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.354622336 |
|
|
Oct 15 06:10:51 AM UTC 24 |
Oct 15 06:11:07 AM UTC 24 |
6376810432 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.4207134754 |
|
|
Oct 15 06:06:02 AM UTC 24 |
Oct 15 06:11:07 AM UTC 24 |
330501543835 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.2096267341 |
|
|
Oct 15 06:07:59 AM UTC 24 |
Oct 15 06:11:07 AM UTC 24 |
49870508044 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.1043737080 |
|
|
Oct 15 06:10:48 AM UTC 24 |
Oct 15 06:11:10 AM UTC 24 |
111265155140 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1448389935 |
|
|
Oct 15 06:10:51 AM UTC 24 |
Oct 15 06:11:11 AM UTC 24 |
1438910835 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.2878797351 |
|
|
Oct 15 06:11:09 AM UTC 24 |
Oct 15 06:11:11 AM UTC 24 |
111739175 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.76915430 |
|
|
Oct 15 06:10:51 AM UTC 24 |
Oct 15 06:11:12 AM UTC 24 |
1578001470 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.2867283980 |
|
|
Oct 15 06:11:09 AM UTC 24 |
Oct 15 06:11:13 AM UTC 24 |
468108822 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.3103468507 |
|
|
Oct 15 06:11:09 AM UTC 24 |
Oct 15 06:11:13 AM UTC 24 |
585876665 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.740286054 |
|
|
Oct 15 06:10:48 AM UTC 24 |
Oct 15 06:11:14 AM UTC 24 |
1619284671 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.420814692 |
|
|
Oct 15 06:10:51 AM UTC 24 |
Oct 15 06:11:16 AM UTC 24 |
7174318624 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.4279626544 |
|
|
Oct 15 06:11:09 AM UTC 24 |
Oct 15 06:11:20 AM UTC 24 |
4449322127 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.2578226812 |
|
|
Oct 15 06:11:14 AM UTC 24 |
Oct 15 06:11:20 AM UTC 24 |
94617579 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.987350882 |
|
|
Oct 15 06:11:21 AM UTC 24 |
Oct 15 06:11:23 AM UTC 24 |
34463420 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.349060951 |
|
|
Oct 15 06:11:12 AM UTC 24 |
Oct 15 06:11:24 AM UTC 24 |
541449938 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.2178940284 |
|
|
Oct 15 06:11:24 AM UTC 24 |
Oct 15 06:11:27 AM UTC 24 |
18100265 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.2508258193 |
|
|
Oct 15 06:10:49 AM UTC 24 |
Oct 15 06:11:30 AM UTC 24 |
27338107881 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.1700213716 |
|
|
Oct 15 06:11:11 AM UTC 24 |
Oct 15 06:11:31 AM UTC 24 |
12676140607 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.2634827141 |
|
|
Oct 15 06:11:12 AM UTC 24 |
Oct 15 06:11:31 AM UTC 24 |
989369981 ps |