| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.74 | 98.65 | 96.80 | 99.01 | 89.36 | 98.51 | 95.57 | 99.26 |
| T162 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.875960176 | Oct 15 03:02:59 AM UTC 24 | Oct 15 03:03:03 AM UTC 24 | 144815576 ps | ||
| T135 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1470230804 | Oct 15 03:02:58 AM UTC 24 | Oct 15 03:03:03 AM UTC 24 | 85885186 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.3972195018 | Oct 15 03:03:01 AM UTC 24 | Oct 15 03:03:03 AM UTC 24 | 24493514 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1667672158 | Oct 15 03:03:01 AM UTC 24 | Oct 15 03:03:04 AM UTC 24 | 71602592 ps | ||
| T188 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.3363586285 | Oct 15 03:02:56 AM UTC 24 | Oct 15 03:03:05 AM UTC 24 | 582000674 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2455312120 | Oct 15 03:03:01 AM UTC 24 | Oct 15 03:03:05 AM UTC 24 | 104113475 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.128853228 | Oct 15 03:03:02 AM UTC 24 | Oct 15 03:03:05 AM UTC 24 | 21034121 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3180290089 | Oct 15 03:03:02 AM UTC 24 | Oct 15 03:03:05 AM UTC 24 | 209538969 ps | ||
| T136 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.3454090913 | Oct 15 03:02:55 AM UTC 24 | Oct 15 03:03:05 AM UTC 24 | 420089853 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2221118496 | Oct 15 03:03:02 AM UTC 24 | Oct 15 03:03:05 AM UTC 24 | 79562066 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1176625020 | Oct 15 03:03:04 AM UTC 24 | Oct 15 03:03:06 AM UTC 24 | 15746214 ps | ||
| T137 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.3035295180 | Oct 15 03:03:04 AM UTC 24 | Oct 15 03:03:07 AM UTC 24 | 38756812 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1921591631 | Oct 15 03:03:06 AM UTC 24 | Oct 15 03:03:09 AM UTC 24 | 16913362 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2954354982 | Oct 15 03:03:05 AM UTC 24 | Oct 15 03:03:10 AM UTC 24 | 50566766 ps | ||
| T138 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.2628015805 | Oct 15 03:03:07 AM UTC 24 | Oct 15 03:03:11 AM UTC 24 | 133144238 ps | ||
| T115 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.2059600006 | Oct 15 03:03:03 AM UTC 24 | Oct 15 03:03:11 AM UTC 24 | 1058585407 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2381286579 | Oct 15 03:03:05 AM UTC 24 | Oct 15 03:03:11 AM UTC 24 | 111204038 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2481906840 | Oct 15 03:03:08 AM UTC 24 | Oct 15 03:03:12 AM UTC 24 | 72377200 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3599867104 | Oct 15 03:02:46 AM UTC 24 | Oct 15 03:03:12 AM UTC 24 | 913208133 ps | ||
| T183 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.3690460384 | Oct 15 03:02:51 AM UTC 24 | Oct 15 03:03:13 AM UTC 24 | 1141189487 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.3056790255 | Oct 15 03:03:11 AM UTC 24 | Oct 15 03:03:13 AM UTC 24 | 49558447 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3648798093 | Oct 15 03:03:07 AM UTC 24 | Oct 15 03:03:14 AM UTC 24 | 212398839 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.2484571692 | Oct 15 03:03:08 AM UTC 24 | Oct 15 03:03:15 AM UTC 24 | 712094227 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.2511189588 | Oct 15 03:03:12 AM UTC 24 | Oct 15 03:03:15 AM UTC 24 | 77245374 ps | ||
| T165 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.4201363855 | Oct 15 03:03:05 AM UTC 24 | Oct 15 03:03:15 AM UTC 24 | 1021932055 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.2584685122 | Oct 15 03:02:59 AM UTC 24 | Oct 15 03:03:16 AM UTC 24 | 615736447 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.272403622 | Oct 15 03:03:14 AM UTC 24 | Oct 15 03:03:17 AM UTC 24 | 42797520 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1389597682 | Oct 15 03:03:12 AM UTC 24 | Oct 15 03:03:17 AM UTC 24 | 190685684 ps | ||
| T163 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1779681606 | Oct 15 03:03:12 AM UTC 24 | Oct 15 03:03:17 AM UTC 24 | 248726163 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.1402509290 | Oct 15 03:03:14 AM UTC 24 | Oct 15 03:03:17 AM UTC 24 | 35781307 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3398814645 | Oct 15 03:02:50 AM UTC 24 | Oct 15 03:03:18 AM UTC 24 | 356477518 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1666498404 | Oct 15 03:03:17 AM UTC 24 | Oct 15 03:03:19 AM UTC 24 | 12082111 ps | ||
| T121 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.2590608335 | Oct 15 03:03:13 AM UTC 24 | Oct 15 03:03:19 AM UTC 24 | 91655545 ps | ||
| T120 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.374876319 | Oct 15 03:03:15 AM UTC 24 | Oct 15 03:03:21 AM UTC 24 | 111666091 ps | ||
| T164 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2981484211 | Oct 15 03:03:15 AM UTC 24 | Oct 15 03:03:19 AM UTC 24 | 226670599 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1822843399 | Oct 15 03:03:15 AM UTC 24 | Oct 15 03:03:20 AM UTC 24 | 44894839 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.4176467095 | Oct 15 03:03:18 AM UTC 24 | Oct 15 03:03:22 AM UTC 24 | 39120979 ps | ||
| T166 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.4257391038 | Oct 15 03:03:05 AM UTC 24 | Oct 15 03:03:22 AM UTC 24 | 4231126414 ps | ||
| T184 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.1024199664 | Oct 15 03:03:13 AM UTC 24 | Oct 15 03:03:22 AM UTC 24 | 291642446 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.4205431707 | Oct 15 03:03:20 AM UTC 24 | Oct 15 03:03:22 AM UTC 24 | 14692654 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2914787312 | Oct 15 03:03:19 AM UTC 24 | Oct 15 03:03:22 AM UTC 24 | 85698451 ps | ||
| T192 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.1563771832 | Oct 15 03:03:26 AM UTC 24 | Oct 15 03:03:43 AM UTC 24 | 4483731920 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.952477741 | Oct 15 03:03:19 AM UTC 24 | Oct 15 03:03:23 AM UTC 24 | 1809563399 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1834355427 | Oct 15 03:03:20 AM UTC 24 | Oct 15 03:03:23 AM UTC 24 | 163781899 ps | ||
| T191 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.938401882 | Oct 15 03:03:01 AM UTC 24 | Oct 15 03:03:23 AM UTC 24 | 289980218 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1624365019 | Oct 15 03:03:18 AM UTC 24 | Oct 15 03:03:24 AM UTC 24 | 63114437 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1061879621 | Oct 15 03:02:45 AM UTC 24 | Oct 15 03:03:24 AM UTC 24 | 7210200753 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3668971228 | Oct 15 03:03:22 AM UTC 24 | Oct 15 03:03:24 AM UTC 24 | 55269028 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.1896202808 | Oct 15 03:03:24 AM UTC 24 | Oct 15 03:03:26 AM UTC 24 | 34359692 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.1472552744 | Oct 15 03:03:21 AM UTC 24 | Oct 15 03:03:26 AM UTC 24 | 694807834 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.134481310 | Oct 15 03:03:20 AM UTC 24 | Oct 15 03:03:26 AM UTC 24 | 153003125 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2409781372 | Oct 15 03:03:24 AM UTC 24 | Oct 15 03:03:27 AM UTC 24 | 111284414 ps | ||
| T189 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.201572424 | Oct 15 03:03:10 AM UTC 24 | Oct 15 03:03:27 AM UTC 24 | 2816437698 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.366493779 | Oct 15 03:03:20 AM UTC 24 | Oct 15 03:03:27 AM UTC 24 | 103545019 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.4201629117 | Oct 15 03:03:22 AM UTC 24 | Oct 15 03:03:27 AM UTC 24 | 391562679 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.1757414288 | Oct 15 03:03:25 AM UTC 24 | Oct 15 03:03:28 AM UTC 24 | 259150690 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.1619317132 | Oct 15 03:03:25 AM UTC 24 | Oct 15 03:03:28 AM UTC 24 | 159302777 ps | ||
| T185 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.405136464 | Oct 15 03:03:04 AM UTC 24 | Oct 15 03:03:28 AM UTC 24 | 3361227955 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3993965959 | Oct 15 03:03:25 AM UTC 24 | Oct 15 03:03:29 AM UTC 24 | 232933020 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.3779660647 | Oct 15 03:03:27 AM UTC 24 | Oct 15 03:03:29 AM UTC 24 | 43261556 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3773403044 | Oct 15 03:03:22 AM UTC 24 | Oct 15 03:03:29 AM UTC 24 | 218416715 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.4058167947 | Oct 15 03:03:21 AM UTC 24 | Oct 15 03:03:29 AM UTC 24 | 1578439435 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.287740961 | Oct 15 03:03:24 AM UTC 24 | Oct 15 03:03:30 AM UTC 24 | 79656619 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2821712384 | Oct 15 03:03:25 AM UTC 24 | Oct 15 03:03:30 AM UTC 24 | 424533410 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.78475374 | Oct 15 03:03:27 AM UTC 24 | Oct 15 03:03:30 AM UTC 24 | 43383696 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.3224987509 | Oct 15 03:03:28 AM UTC 24 | Oct 15 03:03:31 AM UTC 24 | 15930611 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.2257153495 | Oct 15 03:03:28 AM UTC 24 | Oct 15 03:03:31 AM UTC 24 | 29903122 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1525951654 | Oct 15 03:03:29 AM UTC 24 | Oct 15 03:03:32 AM UTC 24 | 63128156 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1678834101 | Oct 15 03:02:58 AM UTC 24 | Oct 15 03:03:33 AM UTC 24 | 18015816531 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2215928568 | Oct 15 03:03:31 AM UTC 24 | Oct 15 03:03:33 AM UTC 24 | 22185598 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1252411474 | Oct 15 03:03:28 AM UTC 24 | Oct 15 03:03:33 AM UTC 24 | 107191855 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.1369953409 | Oct 15 03:03:24 AM UTC 24 | Oct 15 03:03:33 AM UTC 24 | 1285781449 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.326127884 | Oct 15 03:03:30 AM UTC 24 | Oct 15 03:03:33 AM UTC 24 | 51295688 ps | ||
| T186 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.192309652 | Oct 15 03:03:17 AM UTC 24 | Oct 15 03:03:34 AM UTC 24 | 206837020 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.1045837977 | Oct 15 03:03:28 AM UTC 24 | Oct 15 03:03:34 AM UTC 24 | 330913461 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3924232915 | Oct 15 03:03:31 AM UTC 24 | Oct 15 03:03:34 AM UTC 24 | 89862632 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.3311319400 | Oct 15 03:03:32 AM UTC 24 | Oct 15 03:03:34 AM UTC 24 | 14009355 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1830534282 | Oct 15 03:03:31 AM UTC 24 | Oct 15 03:03:34 AM UTC 24 | 89497035 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3847085500 | Oct 15 03:03:28 AM UTC 24 | Oct 15 03:03:34 AM UTC 24 | 156005112 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2299734777 | Oct 15 03:03:32 AM UTC 24 | Oct 15 03:03:36 AM UTC 24 | 112264460 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.2067268881 | Oct 15 03:03:31 AM UTC 24 | Oct 15 03:03:36 AM UTC 24 | 411185163 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.2478262731 | Oct 15 03:03:30 AM UTC 24 | Oct 15 03:03:36 AM UTC 24 | 62596439 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.2226313042 | Oct 15 03:03:35 AM UTC 24 | Oct 15 03:03:36 AM UTC 24 | 12174542 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.3666844910 | Oct 15 03:03:41 AM UTC 24 | Oct 15 03:03:43 AM UTC 24 | 38245962 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.2314198914 | Oct 15 03:03:31 AM UTC 24 | Oct 15 03:03:36 AM UTC 24 | 120684502 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2483473167 | Oct 15 03:03:34 AM UTC 24 | Oct 15 03:03:37 AM UTC 24 | 82948036 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.785999795 | Oct 15 03:03:34 AM UTC 24 | Oct 15 03:03:37 AM UTC 24 | 27471428 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1483897431 | Oct 15 03:03:36 AM UTC 24 | Oct 15 03:03:38 AM UTC 24 | 22454508 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.484863863 | Oct 15 03:03:35 AM UTC 24 | Oct 15 03:03:38 AM UTC 24 | 192050055 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.571873687 | Oct 15 03:03:35 AM UTC 24 | Oct 15 03:03:39 AM UTC 24 | 1532609474 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3211163816 | Oct 15 03:03:33 AM UTC 24 | Oct 15 03:03:39 AM UTC 24 | 287598222 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1596864543 | Oct 15 03:03:37 AM UTC 24 | Oct 15 03:03:39 AM UTC 24 | 16020325 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.3210015912 | Oct 15 03:03:37 AM UTC 24 | Oct 15 03:03:39 AM UTC 24 | 14942515 ps | ||
| T1096 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.2069447886 | Oct 15 03:03:37 AM UTC 24 | Oct 15 03:03:39 AM UTC 24 | 51194415 ps | ||
| T1097 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1268715823 | Oct 15 03:03:35 AM UTC 24 | Oct 15 03:03:40 AM UTC 24 | 1451837526 ps | ||
| T1098 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.2313081317 | Oct 15 03:03:42 AM UTC 24 | Oct 15 03:03:44 AM UTC 24 | 32562405 ps | ||
| T1099 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.833915330 | Oct 15 03:03:28 AM UTC 24 | Oct 15 03:03:40 AM UTC 24 | 1748905229 ps | ||
| T1100 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.3528329020 | Oct 15 03:03:38 AM UTC 24 | Oct 15 03:03:41 AM UTC 24 | 14548035 ps | ||
| T1101 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2283675408 | Oct 15 03:03:38 AM UTC 24 | Oct 15 03:03:41 AM UTC 24 | 14310124 ps | ||
| T1102 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3125808242 | Oct 15 03:03:39 AM UTC 24 | Oct 15 03:03:41 AM UTC 24 | 14068004 ps | ||
| T1103 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.130368486 | Oct 15 03:03:36 AM UTC 24 | Oct 15 03:03:41 AM UTC 24 | 105444601 ps | ||
| T1104 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.243386010 | Oct 15 03:03:37 AM UTC 24 | Oct 15 03:03:41 AM UTC 24 | 130366184 ps | ||
| T1105 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1984775057 | Oct 15 03:03:37 AM UTC 24 | Oct 15 03:03:41 AM UTC 24 | 230833037 ps | ||
| T1106 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.504919948 | Oct 15 03:03:40 AM UTC 24 | Oct 15 03:03:41 AM UTC 24 | 11647353 ps | ||
| T1107 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3343729927 | Oct 15 03:03:40 AM UTC 24 | Oct 15 03:03:42 AM UTC 24 | 41948871 ps | ||
| T1108 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.343402755 | Oct 15 03:03:37 AM UTC 24 | Oct 15 03:03:42 AM UTC 24 | 127166577 ps | ||
| T1109 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.1080232999 | Oct 15 03:03:41 AM UTC 24 | Oct 15 03:03:43 AM UTC 24 | 12948354 ps | ||
| T1110 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.77026224 | Oct 15 03:03:41 AM UTC 24 | Oct 15 03:03:43 AM UTC 24 | 27539885 ps | ||
| T1111 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.4261664278 | Oct 15 03:03:41 AM UTC 24 | Oct 15 03:03:43 AM UTC 24 | 23826820 ps | ||
| T1112 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.580892674 | Oct 15 03:03:41 AM UTC 24 | Oct 15 03:03:43 AM UTC 24 | 12633214 ps | ||
| T1113 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3330642558 | Oct 15 03:03:41 AM UTC 24 | Oct 15 03:03:43 AM UTC 24 | 16133393 ps | ||
| T1114 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.3173202458 | Oct 15 03:03:42 AM UTC 24 | Oct 15 03:03:44 AM UTC 24 | 20719986 ps | ||
| T1115 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3479257990 | Oct 15 03:03:42 AM UTC 24 | Oct 15 03:03:44 AM UTC 24 | 109432171 ps | ||
| T1116 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.3299649392 | Oct 15 03:03:42 AM UTC 24 | Oct 15 03:03:44 AM UTC 24 | 12484573 ps | ||
| T1117 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.115827857 | Oct 15 03:03:42 AM UTC 24 | Oct 15 03:03:45 AM UTC 24 | 121822323 ps | ||
| T1118 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.721811400 | Oct 15 03:03:42 AM UTC 24 | Oct 15 03:03:45 AM UTC 24 | 87679196 ps | ||
| T187 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3571442728 | Oct 15 03:03:19 AM UTC 24 | Oct 15 03:03:45 AM UTC 24 | 1924458212 ps | ||
| T190 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.2925602248 | Oct 15 03:03:30 AM UTC 24 | Oct 15 03:03:45 AM UTC 24 | 600359911 ps | ||
| T1119 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.3098823129 | Oct 15 03:03:42 AM UTC 24 | Oct 15 03:03:45 AM UTC 24 | 15474969 ps | ||
| T1120 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.42876463 | Oct 15 03:03:42 AM UTC 24 | Oct 15 03:03:45 AM UTC 24 | 35314548 ps | ||
| T1121 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2766008215 | Oct 15 03:03:44 AM UTC 24 | Oct 15 03:03:46 AM UTC 24 | 19002144 ps | ||
| T1122 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.493389074 | Oct 15 03:03:44 AM UTC 24 | Oct 15 03:03:46 AM UTC 24 | 57847129 ps | ||
| T1123 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.2955336801 | Oct 15 03:03:44 AM UTC 24 | Oct 15 03:03:46 AM UTC 24 | 20182188 ps | ||
| T1124 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.1752936701 | Oct 15 03:03:44 AM UTC 24 | Oct 15 03:03:46 AM UTC 24 | 59768369 ps | ||
| T1125 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.1164533755 | Oct 15 03:03:44 AM UTC 24 | Oct 15 03:03:46 AM UTC 24 | 12664946 ps | ||
| T1126 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.856979550 | Oct 15 03:03:44 AM UTC 24 | Oct 15 03:03:46 AM UTC 24 | 18208433 ps | ||
| T1127 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.1347712044 | Oct 15 03:03:44 AM UTC 24 | Oct 15 03:03:46 AM UTC 24 | 29294751 ps | ||
| T1128 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.522057658 | Oct 15 03:03:45 AM UTC 24 | Oct 15 03:03:47 AM UTC 24 | 43794783 ps | ||
| T1129 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.517244895 | Oct 15 03:03:34 AM UTC 24 | Oct 15 03:03:48 AM UTC 24 | 192144426 ps | ||
| T1130 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2219757326 | Oct 15 03:03:32 AM UTC 24 | Oct 15 03:03:50 AM UTC 24 | 618440560 ps | ||
| T1131 | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.1003808832 | Oct 15 03:03:36 AM UTC 24 | Oct 15 03:03:57 AM UTC 24 | 653846817 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.2357482345 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 4050200550 ps |
| CPU time | 11.94 seconds |
| Started | Oct 15 05:55:49 AM UTC 24 |
| Finished | Oct 15 05:56:02 AM UTC 24 |
| Peak memory | 245876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357482345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.2357482345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_stress_all.786166724 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 6387000716 ps |
| CPU time | 54.58 seconds |
| Started | Oct 15 05:56:45 AM UTC 24 |
| Finished | Oct 15 05:57:41 AM UTC 24 |
| Peak memory | 248180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786166724 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.786166724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.773218858 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 5045323443 ps |
| CPU time | 88.97 seconds |
| Started | Oct 15 05:57:58 AM UTC 24 |
| Finished | Oct 15 05:59:29 AM UTC 24 |
| Peak memory | 268436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773218858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.773218858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_all.1903094891 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 5180923362 ps |
| CPU time | 61.92 seconds |
| Started | Oct 15 05:55:40 AM UTC 24 |
| Finished | Oct 15 05:56:44 AM UTC 24 |
| Peak memory | 228264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903094891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.1903094891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1120474996 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 101670578 ps |
| CPU time | 3.2 seconds |
| Started | Oct 15 03:02:50 AM UTC 24 |
| Finished | Oct 15 03:02:54 AM UTC 24 |
| Peak memory | 226704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1120474996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 2.spi_device_csr_mem_rw_with_rand_reset.1120474996 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_stress_all.1076213763 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 125582645455 ps |
| CPU time | 210.76 seconds |
| Started | Oct 15 05:58:56 AM UTC 24 |
| Finished | Oct 15 06:02:30 AM UTC 24 |
| Peak memory | 283028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076213763 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.1076213763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.313916303 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 25005155773 ps |
| CPU time | 123.2 seconds |
| Started | Oct 15 05:58:07 AM UTC 24 |
| Finished | Oct 15 06:00:12 AM UTC 24 |
| Peak memory | 264348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313916303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.313916303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_ram_cfg.2753462080 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 72033331 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 05:55:37 AM UTC 24 |
| Finished | Oct 15 05:55:40 AM UTC 24 |
| Peak memory | 227592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753462080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2753462080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.3836266102 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 52916225625 ps |
| CPU time | 529.4 seconds |
| Started | Oct 15 05:56:26 AM UTC 24 |
| Finished | Oct 15 06:05:21 AM UTC 24 |
| Peak memory | 284884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836266102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3836266102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_cfg_cmd.1315468503 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 291210260 ps |
| CPU time | 5.14 seconds |
| Started | Oct 15 05:57:15 AM UTC 24 |
| Finished | Oct 15 05:57:21 AM UTC 24 |
| Peak memory | 235492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1315468503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1315468503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_stress_all.660252095 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 21223212590 ps |
| CPU time | 207.28 seconds |
| Started | Oct 15 05:57:37 AM UTC 24 |
| Finished | Oct 15 06:01:08 AM UTC 24 |
| Peak memory | 278704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=660252095 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.660252095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_stress_all.2015453408 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 88153751103 ps |
| CPU time | 529.56 seconds |
| Started | Oct 15 06:01:07 AM UTC 24 |
| Finished | Oct 15 06:10:03 AM UTC 24 |
| Peak memory | 295068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015453408 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.2015453408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_sec_cm.3446634546 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 328678649 ps |
| CPU time | 1.96 seconds |
| Started | Oct 15 05:56:46 AM UTC 24 |
| Finished | Oct 15 05:56:49 AM UTC 24 |
| Peak memory | 257760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3446634546 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.3446634546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.367624369 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 17465734974 ps |
| CPU time | 108.25 seconds |
| Started | Oct 15 05:58:49 AM UTC 24 |
| Finished | Oct 15 06:00:40 AM UTC 24 |
| Peak memory | 268476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367624369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.367624369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode.1360418388 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 2784915368 ps |
| CPU time | 17.9 seconds |
| Started | Oct 15 05:59:26 AM UTC 24 |
| Finished | Oct 15 05:59:45 AM UTC 24 |
| Peak memory | 245868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360418388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1360418388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.3157493898 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 53376589289 ps |
| CPU time | 134.64 seconds |
| Started | Oct 15 06:04:53 AM UTC 24 |
| Finished | Oct 15 06:07:11 AM UTC 24 |
| Peak memory | 268408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157493898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.3157493898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1496234044 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 13498811877 ps |
| CPU time | 121.83 seconds |
| Started | Oct 15 05:57:36 AM UTC 24 |
| Finished | Oct 15 05:59:40 AM UTC 24 |
| Peak memory | 278636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496234044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.1496234044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_stress_all.361160609 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 155532328992 ps |
| CPU time | 338.43 seconds |
| Started | Oct 15 06:04:27 AM UTC 24 |
| Finished | Oct 15 06:10:10 AM UTC 24 |
| Peak memory | 280732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361160609 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.361160609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.675092746 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 1364604281 ps |
| CPU time | 11.8 seconds |
| Started | Oct 15 03:02:45 AM UTC 24 |
| Finished | Oct 15 03:02:58 AM UTC 24 |
| Peak memory | 224856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=675092746 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.675092746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3540013361 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 407548661 ps |
| CPU time | 3.55 seconds |
| Started | Oct 15 03:02:45 AM UTC 24 |
| Finished | Oct 15 03:02:50 AM UTC 24 |
| Peak memory | 224592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540013361 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3540013361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.2018764266 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 6282959621 ps |
| CPU time | 98.54 seconds |
| Started | Oct 15 06:07:34 AM UTC 24 |
| Finished | Oct 15 06:09:14 AM UTC 24 |
| Peak memory | 278700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018764266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.2018764266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.468179374 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 4875273350 ps |
| CPU time | 58.62 seconds |
| Started | Oct 15 06:03:09 AM UTC 24 |
| Finished | Oct 15 06:04:10 AM UTC 24 |
| Peak memory | 268364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=468179374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.468179374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.1472552744 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 694807834 ps |
| CPU time | 3.58 seconds |
| Started | Oct 15 03:03:21 AM UTC 24 |
| Finished | Oct 15 03:03:26 AM UTC 24 |
| Peak memory | 224988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472552744 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.1472552744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_stress_all.1803671052 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 35852794277 ps |
| CPU time | 85.38 seconds |
| Started | Oct 15 06:03:44 AM UTC 24 |
| Finished | Oct 15 06:05:11 AM UTC 24 |
| Peak memory | 268468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1803671052 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.1803671052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_stress_all.1609553604 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 54214935356 ps |
| CPU time | 306.87 seconds |
| Started | Oct 15 06:05:02 AM UTC 24 |
| Finished | Oct 15 06:10:13 AM UTC 24 |
| Peak memory | 276856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609553604 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.1609553604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.2908635148 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 33281732344 ps |
| CPU time | 154.34 seconds |
| Started | Oct 15 06:02:48 AM UTC 24 |
| Finished | Oct 15 06:05:25 AM UTC 24 |
| Peak memory | 264376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908635148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2908635148 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.3859489106 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 13953191397 ps |
| CPU time | 177 seconds |
| Started | Oct 15 06:03:39 AM UTC 24 |
| Finished | Oct 15 06:06:39 AM UTC 24 |
| Peak memory | 262320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859489106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3859489106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1985386313 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 7020408178 ps |
| CPU time | 148.4 seconds |
| Started | Oct 15 05:56:34 AM UTC 24 |
| Finished | Oct 15 05:59:05 AM UTC 24 |
| Peak memory | 283016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985386313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.1985386313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_all.252855034 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 12675770753 ps |
| CPU time | 77.1 seconds |
| Started | Oct 15 06:04:19 AM UTC 24 |
| Finished | Oct 15 06:05:38 AM UTC 24 |
| Peak memory | 266544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252855034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.252855034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.4161263168 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 87313466212 ps |
| CPU time | 190 seconds |
| Started | Oct 15 06:02:45 AM UTC 24 |
| Finished | Oct 15 06:05:58 AM UTC 24 |
| Peak memory | 266128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161263168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.4161263168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.115071640 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 13986627313 ps |
| CPU time | 145.43 seconds |
| Started | Oct 15 06:07:12 AM UTC 24 |
| Finished | Oct 15 06:09:40 AM UTC 24 |
| Peak memory | 282832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115071640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.115071640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.541392192 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 114113484 ps |
| CPU time | 3.2 seconds |
| Started | Oct 15 03:02:44 AM UTC 24 |
| Finished | Oct 15 03:02:48 AM UTC 24 |
| Peak memory | 224772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541392192 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.541392192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.1439724407 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 6183438686 ps |
| CPU time | 98.96 seconds |
| Started | Oct 15 05:56:11 AM UTC 24 |
| Finished | Oct 15 05:57:52 AM UTC 24 |
| Peak memory | 268420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439724407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.1439724407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_alert_test.2659141861 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 14014411 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 05:57:39 AM UTC 24 |
| Finished | Oct 15 05:57:41 AM UTC 24 |
| Peak memory | 214540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659141861 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2659141861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.193929019 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2447963324 ps |
| CPU time | 10.56 seconds |
| Started | Oct 15 05:55:37 AM UTC 24 |
| Finished | Oct 15 05:55:49 AM UTC 24 |
| Peak memory | 228088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193929019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.193929019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3842754283 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 74203054746 ps |
| CPU time | 687.87 seconds |
| Started | Oct 15 06:14:27 AM UTC 24 |
| Finished | Oct 15 06:26:05 AM UTC 24 |
| Peak memory | 284852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3842754283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.3842754283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.494057643 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 4437297003 ps |
| CPU time | 77.88 seconds |
| Started | Oct 15 06:07:09 AM UTC 24 |
| Finished | Oct 15 06:08:29 AM UTC 24 |
| Peak memory | 268408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494057643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.494057643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1896300757 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 10683135079 ps |
| CPU time | 196.23 seconds |
| Started | Oct 15 06:08:27 AM UTC 24 |
| Finished | Oct 15 06:11:47 AM UTC 24 |
| Peak memory | 278772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896300757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.1896300757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.192309652 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 206837020 ps |
| CPU time | 15.53 seconds |
| Started | Oct 15 03:03:17 AM UTC 24 |
| Finished | Oct 15 03:03:34 AM UTC 24 |
| Peak memory | 224904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192309652 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.192309652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.2925602248 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 600359911 ps |
| CPU time | 13.61 seconds |
| Started | Oct 15 03:03:30 AM UTC 24 |
| Finished | Oct 15 03:03:45 AM UTC 24 |
| Peak memory | 224752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925602248 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.2925602248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_stress_all.831243741 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 34149176405 ps |
| CPU time | 217.09 seconds |
| Started | Oct 15 06:03:19 AM UTC 24 |
| Finished | Oct 15 06:06:59 AM UTC 24 |
| Peak memory | 278876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831243741 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.831243741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode.1492668475 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 1188213600 ps |
| CPU time | 26.75 seconds |
| Started | Oct 15 06:05:58 AM UTC 24 |
| Finished | Oct 15 06:06:26 AM UTC 24 |
| Peak memory | 245756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492668475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1492668475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.159307880 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 6370797854 ps |
| CPU time | 131.69 seconds |
| Started | Oct 15 06:07:35 AM UTC 24 |
| Finished | Oct 15 06:09:49 AM UTC 24 |
| Peak memory | 285024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159307880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.159307880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_all.3274401980 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 78114148772 ps |
| CPU time | 178.04 seconds |
| Started | Oct 15 05:58:02 AM UTC 24 |
| Finished | Oct 15 06:01:04 AM UTC 24 |
| Peak memory | 266352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274401980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.3274401980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.4251693871 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3204994647 ps |
| CPU time | 73.68 seconds |
| Started | Oct 15 06:13:21 AM UTC 24 |
| Finished | Oct 15 06:14:37 AM UTC 24 |
| Peak memory | 278640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251693871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.4251693871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.2478262731 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 62596439 ps |
| CPU time | 5.14 seconds |
| Started | Oct 15 03:03:30 AM UTC 24 |
| Finished | Oct 15 03:03:36 AM UTC 24 |
| Peak memory | 225024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478262731 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.2478262731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_all.1120402146 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 38682008004 ps |
| CPU time | 258.62 seconds |
| Started | Oct 15 05:56:16 AM UTC 24 |
| Finished | Oct 15 06:00:39 AM UTC 24 |
| Peak memory | 266428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120402146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1120402146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode.1072612923 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 11109049717 ps |
| CPU time | 79.94 seconds |
| Started | Oct 15 06:04:12 AM UTC 24 |
| Finished | Oct 15 06:05:34 AM UTC 24 |
| Peak memory | 262288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072612923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1072612923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_upload.1975802113 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 125415032 ps |
| CPU time | 6.51 seconds |
| Started | Oct 15 06:04:44 AM UTC 24 |
| Finished | Oct 15 06:04:52 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975802113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1975802113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_upload.245481301 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 726910661 ps |
| CPU time | 13.88 seconds |
| Started | Oct 15 06:07:03 AM UTC 24 |
| Finished | Oct 15 06:07:18 AM UTC 24 |
| Peak memory | 262352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=245481301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.245481301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.1872330893 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 139576965165 ps |
| CPU time | 584.25 seconds |
| Started | Oct 15 06:08:06 AM UTC 24 |
| Finished | Oct 15 06:17:58 AM UTC 24 |
| Peak memory | 295348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872330893 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.1872330893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.1523514149 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 16320632459 ps |
| CPU time | 132 seconds |
| Started | Oct 15 06:10:12 AM UTC 24 |
| Finished | Oct 15 06:12:26 AM UTC 24 |
| Peak memory | 276852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1523514149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.1523514149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.2448068568 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 7657032730 ps |
| CPU time | 117.04 seconds |
| Started | Oct 15 06:11:43 AM UTC 24 |
| Finished | Oct 15 06:13:42 AM UTC 24 |
| Peak memory | 278988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448068568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.2448068568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_all.1747798974 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 5181340482 ps |
| CPU time | 36.58 seconds |
| Started | Oct 15 06:15:15 AM UTC 24 |
| Finished | Oct 15 06:15:53 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747798974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.1747798974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_intercept.893746429 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 233857766 ps |
| CPU time | 8.55 seconds |
| Started | Oct 15 05:55:50 AM UTC 24 |
| Finished | Oct 15 05:56:00 AM UTC 24 |
| Peak memory | 235516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893746429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.893746429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3280587610 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 83802305 ps |
| CPU time | 2.02 seconds |
| Started | Oct 15 03:02:44 AM UTC 24 |
| Finished | Oct 15 03:02:47 AM UTC 24 |
| Peak memory | 224932 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280587610 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.3280587610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.994360018 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 58920912472 ps |
| CPU time | 731.07 seconds |
| Started | Oct 15 06:03:58 AM UTC 24 |
| Finished | Oct 15 06:16:19 AM UTC 24 |
| Peak memory | 284504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994360018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.994360018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2776883317 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 437552983 ps |
| CPU time | 8.34 seconds |
| Started | Oct 15 03:02:44 AM UTC 24 |
| Finished | Oct 15 03:02:53 AM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776883317 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.2776883317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2378503189 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 188421043 ps |
| CPU time | 12.19 seconds |
| Started | Oct 15 03:02:44 AM UTC 24 |
| Finished | Oct 15 03:02:57 AM UTC 24 |
| Peak memory | 214684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378503189 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.2378503189 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.640525617 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 65460291 ps |
| CPU time | 1.82 seconds |
| Started | Oct 15 03:02:44 AM UTC 24 |
| Finished | Oct 15 03:02:47 AM UTC 24 |
| Peak memory | 225156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=640525617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 0.spi_device_csr_mem_rw_with_rand_reset.640525617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2558261070 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 257313451 ps |
| CPU time | 3.29 seconds |
| Started | Oct 15 03:02:44 AM UTC 24 |
| Finished | Oct 15 03:02:48 AM UTC 24 |
| Peak memory | 214352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558261070 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2558261070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2030634697 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 48949042 ps |
| CPU time | 0.97 seconds |
| Started | Oct 15 03:02:44 AM UTC 24 |
| Finished | Oct 15 03:02:46 AM UTC 24 |
| Peak memory | 212312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030634697 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2030634697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2140667453 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 63479323 ps |
| CPU time | 1.95 seconds |
| Started | Oct 15 03:02:44 AM UTC 24 |
| Finished | Oct 15 03:02:47 AM UTC 24 |
| Peak memory | 223272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140667453 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.2140667453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2290298584 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 13423619 ps |
| CPU time | 0.99 seconds |
| Started | Oct 15 03:02:44 AM UTC 24 |
| Finished | Oct 15 03:02:46 AM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290298584 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.2290298584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.382797254 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 59328152 ps |
| CPU time | 4.62 seconds |
| Started | Oct 15 03:02:44 AM UTC 24 |
| Finished | Oct 15 03:02:50 AM UTC 24 |
| Peak memory | 224920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382797254 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.382797254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.275268290 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 283237913 ps |
| CPU time | 5.14 seconds |
| Started | Oct 15 03:02:43 AM UTC 24 |
| Finished | Oct 15 03:02:49 AM UTC 24 |
| Peak memory | 224928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275268290 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.275268290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.1696938994 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 761890789 ps |
| CPU time | 12.55 seconds |
| Started | Oct 15 03:02:43 AM UTC 24 |
| Finished | Oct 15 03:02:56 AM UTC 24 |
| Peak memory | 224720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696938994 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.1696938994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3599867104 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 913208133 ps |
| CPU time | 24.53 seconds |
| Started | Oct 15 03:02:46 AM UTC 24 |
| Finished | Oct 15 03:03:12 AM UTC 24 |
| Peak memory | 214296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599867104 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.3599867104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1061879621 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 7210200753 ps |
| CPU time | 37.09 seconds |
| Started | Oct 15 03:02:45 AM UTC 24 |
| Finished | Oct 15 03:03:24 AM UTC 24 |
| Peak memory | 224728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061879621 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.1061879621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4219776429 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 43851384 ps |
| CPU time | 1.72 seconds |
| Started | Oct 15 03:02:45 AM UTC 24 |
| Finished | Oct 15 03:02:48 AM UTC 24 |
| Peak memory | 213116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219776429 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.4219776429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3904482466 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 406517673 ps |
| CPU time | 3.65 seconds |
| Started | Oct 15 03:02:48 AM UTC 24 |
| Finished | Oct 15 03:02:52 AM UTC 24 |
| Peak memory | 227024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3904482466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 1.spi_device_csr_mem_rw_with_rand_reset.3904482466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.927936055 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 36785439 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 03:02:45 AM UTC 24 |
| Finished | Oct 15 03:02:47 AM UTC 24 |
| Peak memory | 212680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927936055 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.927936055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1136060874 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 73060403 ps |
| CPU time | 2.64 seconds |
| Started | Oct 15 03:02:45 AM UTC 24 |
| Finished | Oct 15 03:02:49 AM UTC 24 |
| Peak memory | 224936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1136060874 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.1136060874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1537303142 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 18929427 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 03:02:45 AM UTC 24 |
| Finished | Oct 15 03:02:47 AM UTC 24 |
| Peak memory | 212892 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537303142 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.1537303142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3225868190 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 205479857 ps |
| CPU time | 6.4 seconds |
| Started | Oct 15 03:02:47 AM UTC 24 |
| Finished | Oct 15 03:02:54 AM UTC 24 |
| Peak memory | 224592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225868190 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstand ing.3225868190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2914787312 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 85698451 ps |
| CPU time | 2.3 seconds |
| Started | Oct 15 03:03:19 AM UTC 24 |
| Finished | Oct 15 03:03:22 AM UTC 24 |
| Peak memory | 227064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2914787312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 10.spi_device_csr_mem_rw_with_rand_reset.2914787312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.4176467095 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 39120979 ps |
| CPU time | 2.73 seconds |
| Started | Oct 15 03:03:18 AM UTC 24 |
| Finished | Oct 15 03:03:22 AM UTC 24 |
| Peak memory | 224704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176467095 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.4176467095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.1666498404 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 12082111 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 03:03:17 AM UTC 24 |
| Finished | Oct 15 03:03:19 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666498404 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.1666498404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1624365019 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 63114437 ps |
| CPU time | 4.6 seconds |
| Started | Oct 15 03:03:18 AM UTC 24 |
| Finished | Oct 15 03:03:24 AM UTC 24 |
| Peak memory | 224672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624365019 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstan ding.1624365019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.374876319 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 111666091 ps |
| CPU time | 3.98 seconds |
| Started | Oct 15 03:03:15 AM UTC 24 |
| Finished | Oct 15 03:03:21 AM UTC 24 |
| Peak memory | 225092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374876319 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.374876319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.366493779 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 103545019 ps |
| CPU time | 6.22 seconds |
| Started | Oct 15 03:03:20 AM UTC 24 |
| Finished | Oct 15 03:03:27 AM UTC 24 |
| Peak memory | 228688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=366493779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 11.spi_device_csr_mem_rw_with_rand_reset.366493779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1834355427 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 163781899 ps |
| CPU time | 2.21 seconds |
| Started | Oct 15 03:03:20 AM UTC 24 |
| Finished | Oct 15 03:03:23 AM UTC 24 |
| Peak memory | 224644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834355427 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.1834355427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.4205431707 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 14692654 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 03:03:20 AM UTC 24 |
| Finished | Oct 15 03:03:22 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205431707 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.4205431707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.134481310 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 153003125 ps |
| CPU time | 4.94 seconds |
| Started | Oct 15 03:03:20 AM UTC 24 |
| Finished | Oct 15 03:03:26 AM UTC 24 |
| Peak memory | 224660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=134481310 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstand ing.134481310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.952477741 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 1809563399 ps |
| CPU time | 3.17 seconds |
| Started | Oct 15 03:03:19 AM UTC 24 |
| Finished | Oct 15 03:03:23 AM UTC 24 |
| Peak memory | 224704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952477741 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.952477741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.3571442728 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 1924458212 ps |
| CPU time | 24.33 seconds |
| Started | Oct 15 03:03:19 AM UTC 24 |
| Finished | Oct 15 03:03:45 AM UTC 24 |
| Peak memory | 224752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571442728 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.3571442728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.2409781372 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 111284414 ps |
| CPU time | 2.17 seconds |
| Started | Oct 15 03:03:24 AM UTC 24 |
| Finished | Oct 15 03:03:27 AM UTC 24 |
| Peak memory | 226640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2409781372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 12.spi_device_csr_mem_rw_with_rand_reset.2409781372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.4201629117 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 391562679 ps |
| CPU time | 4.03 seconds |
| Started | Oct 15 03:03:22 AM UTC 24 |
| Finished | Oct 15 03:03:27 AM UTC 24 |
| Peak memory | 224656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201629117 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.4201629117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3668971228 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 55269028 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 03:03:22 AM UTC 24 |
| Finished | Oct 15 03:03:24 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668971228 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.3668971228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3773403044 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 218416715 ps |
| CPU time | 5.85 seconds |
| Started | Oct 15 03:03:22 AM UTC 24 |
| Finished | Oct 15 03:03:29 AM UTC 24 |
| Peak memory | 225020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773403044 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstan ding.3773403044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.4058167947 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 1578439435 ps |
| CPU time | 7.12 seconds |
| Started | Oct 15 03:03:21 AM UTC 24 |
| Finished | Oct 15 03:03:29 AM UTC 24 |
| Peak memory | 227016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058167947 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.4058167947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3993965959 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 232933020 ps |
| CPU time | 2.65 seconds |
| Started | Oct 15 03:03:25 AM UTC 24 |
| Finished | Oct 15 03:03:29 AM UTC 24 |
| Peak memory | 226736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3993965959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 13.spi_device_csr_mem_rw_with_rand_reset.3993965959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.1619317132 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 159302777 ps |
| CPU time | 2.04 seconds |
| Started | Oct 15 03:03:25 AM UTC 24 |
| Finished | Oct 15 03:03:28 AM UTC 24 |
| Peak memory | 214464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1619317132 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.1619317132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.1896202808 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 34359692 ps |
| CPU time | 0.88 seconds |
| Started | Oct 15 03:03:24 AM UTC 24 |
| Finished | Oct 15 03:03:26 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896202808 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.1896202808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2821712384 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 424533410 ps |
| CPU time | 4.13 seconds |
| Started | Oct 15 03:03:25 AM UTC 24 |
| Finished | Oct 15 03:03:30 AM UTC 24 |
| Peak memory | 224600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821712384 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstan ding.2821712384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.287740961 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 79656619 ps |
| CPU time | 5.08 seconds |
| Started | Oct 15 03:03:24 AM UTC 24 |
| Finished | Oct 15 03:03:30 AM UTC 24 |
| Peak memory | 224644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287740961 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.287740961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.1369953409 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 1285781449 ps |
| CPU time | 8.44 seconds |
| Started | Oct 15 03:03:24 AM UTC 24 |
| Finished | Oct 15 03:03:33 AM UTC 24 |
| Peak memory | 226732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369953409 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.1369953409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3847085500 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 156005112 ps |
| CPU time | 5.04 seconds |
| Started | Oct 15 03:03:28 AM UTC 24 |
| Finished | Oct 15 03:03:34 AM UTC 24 |
| Peak memory | 228848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3847085500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 14.spi_device_csr_mem_rw_with_rand_reset.3847085500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.78475374 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 43383696 ps |
| CPU time | 1.95 seconds |
| Started | Oct 15 03:03:27 AM UTC 24 |
| Finished | Oct 15 03:03:30 AM UTC 24 |
| Peak memory | 213052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78475374 -assert nopostproc +UVM_TESTNAM E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.78475374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.3779660647 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 43261556 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 03:03:27 AM UTC 24 |
| Finished | Oct 15 03:03:29 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779660647 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.3779660647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.1252411474 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 107191855 ps |
| CPU time | 3.81 seconds |
| Started | Oct 15 03:03:28 AM UTC 24 |
| Finished | Oct 15 03:03:33 AM UTC 24 |
| Peak memory | 224656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252411474 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstan ding.1252411474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.1757414288 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 259150690 ps |
| CPU time | 1.67 seconds |
| Started | Oct 15 03:03:25 AM UTC 24 |
| Finished | Oct 15 03:03:28 AM UTC 24 |
| Peak memory | 223652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757414288 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.1757414288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.1563771832 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4483731920 ps |
| CPU time | 16.28 seconds |
| Started | Oct 15 03:03:26 AM UTC 24 |
| Finished | Oct 15 03:03:43 AM UTC 24 |
| Peak memory | 226888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563771832 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.1563771832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.326127884 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 51295688 ps |
| CPU time | 2.36 seconds |
| Started | Oct 15 03:03:30 AM UTC 24 |
| Finished | Oct 15 03:03:33 AM UTC 24 |
| Peak memory | 226744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=326127884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_n ame 15.spi_device_csr_mem_rw_with_rand_reset.326127884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.2257153495 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 29903122 ps |
| CPU time | 1.81 seconds |
| Started | Oct 15 03:03:28 AM UTC 24 |
| Finished | Oct 15 03:03:31 AM UTC 24 |
| Peak memory | 213052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257153495 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.2257153495 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.3224987509 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 15930611 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 03:03:28 AM UTC 24 |
| Finished | Oct 15 03:03:31 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224987509 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.3224987509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.1525951654 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 63128156 ps |
| CPU time | 2.14 seconds |
| Started | Oct 15 03:03:29 AM UTC 24 |
| Finished | Oct 15 03:03:32 AM UTC 24 |
| Peak memory | 224880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525951654 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstan ding.1525951654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.1045837977 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 330913461 ps |
| CPU time | 4.35 seconds |
| Started | Oct 15 03:03:28 AM UTC 24 |
| Finished | Oct 15 03:03:34 AM UTC 24 |
| Peak memory | 224768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045837977 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.1045837977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.833915330 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 1748905229 ps |
| CPU time | 10.75 seconds |
| Started | Oct 15 03:03:28 AM UTC 24 |
| Finished | Oct 15 03:03:40 AM UTC 24 |
| Peak memory | 226756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833915330 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.833915330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3924232915 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 89862632 ps |
| CPU time | 1.74 seconds |
| Started | Oct 15 03:03:31 AM UTC 24 |
| Finished | Oct 15 03:03:34 AM UTC 24 |
| Peak memory | 223328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3924232915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 16.spi_device_csr_mem_rw_with_rand_reset.3924232915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.2067268881 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 411185163 ps |
| CPU time | 3.69 seconds |
| Started | Oct 15 03:03:31 AM UTC 24 |
| Finished | Oct 15 03:03:36 AM UTC 24 |
| Peak memory | 224696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067268881 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.2067268881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.2215928568 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 22185598 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 03:03:31 AM UTC 24 |
| Finished | Oct 15 03:03:33 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215928568 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.2215928568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.1830534282 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 89497035 ps |
| CPU time | 2.2 seconds |
| Started | Oct 15 03:03:31 AM UTC 24 |
| Finished | Oct 15 03:03:34 AM UTC 24 |
| Peak memory | 224664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830534282 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstan ding.1830534282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2483473167 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 82948036 ps |
| CPU time | 1.75 seconds |
| Started | Oct 15 03:03:34 AM UTC 24 |
| Finished | Oct 15 03:03:37 AM UTC 24 |
| Peak memory | 225376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2483473167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 17.spi_device_csr_mem_rw_with_rand_reset.2483473167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.2299734777 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 112264460 ps |
| CPU time | 2.33 seconds |
| Started | Oct 15 03:03:32 AM UTC 24 |
| Finished | Oct 15 03:03:36 AM UTC 24 |
| Peak memory | 224960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299734777 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.2299734777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.3311319400 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 14009355 ps |
| CPU time | 0.91 seconds |
| Started | Oct 15 03:03:32 AM UTC 24 |
| Finished | Oct 15 03:03:34 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311319400 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.3311319400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3211163816 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 287598222 ps |
| CPU time | 4.72 seconds |
| Started | Oct 15 03:03:33 AM UTC 24 |
| Finished | Oct 15 03:03:39 AM UTC 24 |
| Peak memory | 224916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211163816 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstan ding.3211163816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.2314198914 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 120684502 ps |
| CPU time | 4.18 seconds |
| Started | Oct 15 03:03:31 AM UTC 24 |
| Finished | Oct 15 03:03:36 AM UTC 24 |
| Peak memory | 224640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2314198914 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.2314198914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.2219757326 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 618440560 ps |
| CPU time | 16.53 seconds |
| Started | Oct 15 03:03:32 AM UTC 24 |
| Finished | Oct 15 03:03:50 AM UTC 24 |
| Peak memory | 224644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2219757326 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.2219757326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1268715823 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 1451837526 ps |
| CPU time | 4.04 seconds |
| Started | Oct 15 03:03:35 AM UTC 24 |
| Finished | Oct 15 03:03:40 AM UTC 24 |
| Peak memory | 226704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1268715823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 18.spi_device_csr_mem_rw_with_rand_reset.1268715823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.571873687 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 1532609474 ps |
| CPU time | 3.1 seconds |
| Started | Oct 15 03:03:35 AM UTC 24 |
| Finished | Oct 15 03:03:39 AM UTC 24 |
| Peak memory | 224912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571873687 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.571873687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.2226313042 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 12174542 ps |
| CPU time | 0.82 seconds |
| Started | Oct 15 03:03:35 AM UTC 24 |
| Finished | Oct 15 03:03:36 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226313042 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.2226313042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.484863863 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 192050055 ps |
| CPU time | 2.66 seconds |
| Started | Oct 15 03:03:35 AM UTC 24 |
| Finished | Oct 15 03:03:38 AM UTC 24 |
| Peak memory | 214368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484863863 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstand ing.484863863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.785999795 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 27471428 ps |
| CPU time | 2.05 seconds |
| Started | Oct 15 03:03:34 AM UTC 24 |
| Finished | Oct 15 03:03:37 AM UTC 24 |
| Peak memory | 225020 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785999795 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.785999795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.517244895 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 192144426 ps |
| CPU time | 12.08 seconds |
| Started | Oct 15 03:03:34 AM UTC 24 |
| Finished | Oct 15 03:03:48 AM UTC 24 |
| Peak memory | 227056 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517244895 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.517244895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1984775057 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 230833037 ps |
| CPU time | 3.19 seconds |
| Started | Oct 15 03:03:37 AM UTC 24 |
| Finished | Oct 15 03:03:41 AM UTC 24 |
| Peak memory | 229012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1984775057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 19.spi_device_csr_mem_rw_with_rand_reset.1984775057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.243386010 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 130366184 ps |
| CPU time | 2.95 seconds |
| Started | Oct 15 03:03:37 AM UTC 24 |
| Finished | Oct 15 03:03:41 AM UTC 24 |
| Peak memory | 224596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243386010 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.243386010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1483897431 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 22454508 ps |
| CPU time | 0.81 seconds |
| Started | Oct 15 03:03:36 AM UTC 24 |
| Finished | Oct 15 03:03:38 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483897431 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.1483897431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.343402755 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 127166577 ps |
| CPU time | 4.13 seconds |
| Started | Oct 15 03:03:37 AM UTC 24 |
| Finished | Oct 15 03:03:42 AM UTC 24 |
| Peak memory | 224624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343402755 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstand ing.343402755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.130368486 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 105444601 ps |
| CPU time | 4.22 seconds |
| Started | Oct 15 03:03:36 AM UTC 24 |
| Finished | Oct 15 03:03:41 AM UTC 24 |
| Peak memory | 224676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130368486 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.130368486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.1003808832 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 653846817 ps |
| CPU time | 20.3 seconds |
| Started | Oct 15 03:03:36 AM UTC 24 |
| Finished | Oct 15 03:03:57 AM UTC 24 |
| Peak memory | 226680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003808832 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.1003808832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.4230642250 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 138729834 ps |
| CPU time | 10.1 seconds |
| Started | Oct 15 03:02:50 AM UTC 24 |
| Finished | Oct 15 03:03:01 AM UTC 24 |
| Peak memory | 214356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230642250 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.4230642250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.3398814645 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 356477518 ps |
| CPU time | 26.89 seconds |
| Started | Oct 15 03:02:50 AM UTC 24 |
| Finished | Oct 15 03:03:18 AM UTC 24 |
| Peak memory | 214352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398814645 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.3398814645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3698945754 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 23606935 ps |
| CPU time | 1.52 seconds |
| Started | Oct 15 03:02:49 AM UTC 24 |
| Finished | Oct 15 03:02:51 AM UTC 24 |
| Peak memory | 213116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698945754 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.3698945754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2825569337 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 72136613 ps |
| CPU time | 3.52 seconds |
| Started | Oct 15 03:02:49 AM UTC 24 |
| Finished | Oct 15 03:02:54 AM UTC 24 |
| Peak memory | 224696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825569337 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2825569337 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2580174737 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 12605139 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 03:02:48 AM UTC 24 |
| Finished | Oct 15 03:02:50 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580174737 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2580174737 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.964186793 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 46499230 ps |
| CPU time | 2.25 seconds |
| Started | Oct 15 03:02:49 AM UTC 24 |
| Finished | Oct 15 03:02:52 AM UTC 24 |
| Peak memory | 224896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964186793 -assert nopost proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep o/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.964186793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.203791819 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 29375130 ps |
| CPU time | 0.89 seconds |
| Started | Oct 15 03:02:48 AM UTC 24 |
| Finished | Oct 15 03:02:50 AM UTC 24 |
| Peak memory | 212832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203791819 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.203791819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3919132350 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 53824312 ps |
| CPU time | 2.78 seconds |
| Started | Oct 15 03:02:50 AM UTC 24 |
| Finished | Oct 15 03:02:54 AM UTC 24 |
| Peak memory | 224592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919132350 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstand ing.3919132350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2328495537 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 555011559 ps |
| CPU time | 4.04 seconds |
| Started | Oct 15 03:02:48 AM UTC 24 |
| Finished | Oct 15 03:02:53 AM UTC 24 |
| Peak memory | 224760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328495537 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.2328495537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.3918639894 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 212153785 ps |
| CPU time | 8.11 seconds |
| Started | Oct 15 03:02:48 AM UTC 24 |
| Finished | Oct 15 03:02:57 AM UTC 24 |
| Peak memory | 225068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918639894 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.3918639894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.3210015912 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 14942515 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 03:03:37 AM UTC 24 |
| Finished | Oct 15 03:03:39 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210015912 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.3210015912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.1596864543 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 16020325 ps |
| CPU time | 1 seconds |
| Started | Oct 15 03:03:37 AM UTC 24 |
| Finished | Oct 15 03:03:39 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596864543 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.1596864543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.2069447886 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 51194415 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 03:03:37 AM UTC 24 |
| Finished | Oct 15 03:03:39 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069447886 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.2069447886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.3528329020 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 14548035 ps |
| CPU time | 1.14 seconds |
| Started | Oct 15 03:03:38 AM UTC 24 |
| Finished | Oct 15 03:03:41 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528329020 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.3528329020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2283675408 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 14310124 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 03:03:38 AM UTC 24 |
| Finished | Oct 15 03:03:41 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283675408 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.2283675408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.3125808242 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 14068004 ps |
| CPU time | 1.14 seconds |
| Started | Oct 15 03:03:39 AM UTC 24 |
| Finished | Oct 15 03:03:41 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125808242 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.3125808242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.504919948 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 11647353 ps |
| CPU time | 0.87 seconds |
| Started | Oct 15 03:03:40 AM UTC 24 |
| Finished | Oct 15 03:03:41 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=504919948 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.504919948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.3343729927 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 41948871 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 03:03:40 AM UTC 24 |
| Finished | Oct 15 03:03:42 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343729927 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.3343729927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.77026224 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 27539885 ps |
| CPU time | 0.96 seconds |
| Started | Oct 15 03:03:41 AM UTC 24 |
| Finished | Oct 15 03:03:43 AM UTC 24 |
| Peak memory | 212732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77026224 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.77026224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.580892674 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 12633214 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 03:03:41 AM UTC 24 |
| Finished | Oct 15 03:03:43 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580892674 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.580892674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.3454090913 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 420089853 ps |
| CPU time | 9.57 seconds |
| Started | Oct 15 03:02:55 AM UTC 24 |
| Finished | Oct 15 03:03:05 AM UTC 24 |
| Peak memory | 226640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454090913 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.3454090913 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.403904324 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 517985469 ps |
| CPU time | 23.36 seconds |
| Started | Oct 15 03:02:55 AM UTC 24 |
| Finished | Oct 15 03:03:19 AM UTC 24 |
| Peak memory | 214616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403904324 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.403904324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1928562646 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 122287979 ps |
| CPU time | 1.69 seconds |
| Started | Oct 15 03:02:54 AM UTC 24 |
| Finished | Oct 15 03:02:57 AM UTC 24 |
| Peak memory | 213440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928562646 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.1928562646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2810812002 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 91587631 ps |
| CPU time | 3.53 seconds |
| Started | Oct 15 03:02:55 AM UTC 24 |
| Finished | Oct 15 03:02:59 AM UTC 24 |
| Peak memory | 229108 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2810812002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 3.spi_device_csr_mem_rw_with_rand_reset.2810812002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.1335429261 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 165327324 ps |
| CPU time | 3.32 seconds |
| Started | Oct 15 03:02:55 AM UTC 24 |
| Finished | Oct 15 03:02:59 AM UTC 24 |
| Peak memory | 214388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335429261 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.1335429261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.2751038564 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 13687145 ps |
| CPU time | 0.77 seconds |
| Started | Oct 15 03:02:52 AM UTC 24 |
| Finished | Oct 15 03:02:54 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751038564 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2751038564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.1279210114 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 129878490 ps |
| CPU time | 2.25 seconds |
| Started | Oct 15 03:02:53 AM UTC 24 |
| Finished | Oct 15 03:02:57 AM UTC 24 |
| Peak memory | 224616 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279210114 -assert nopos tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re po/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.1279210114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1350093480 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 13996565 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 03:02:53 AM UTC 24 |
| Finished | Oct 15 03:02:56 AM UTC 24 |
| Peak memory | 212832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350093480 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.1350093480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3102099959 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 353216361 ps |
| CPU time | 4.36 seconds |
| Started | Oct 15 03:02:55 AM UTC 24 |
| Finished | Oct 15 03:03:00 AM UTC 24 |
| Peak memory | 224920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3102099959 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstand ing.3102099959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.427887534 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 315012430 ps |
| CPU time | 2.99 seconds |
| Started | Oct 15 03:02:51 AM UTC 24 |
| Finished | Oct 15 03:02:55 AM UTC 24 |
| Peak memory | 224680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427887534 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.427887534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.3690460384 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 1141189487 ps |
| CPU time | 20.44 seconds |
| Started | Oct 15 03:02:51 AM UTC 24 |
| Finished | Oct 15 03:03:13 AM UTC 24 |
| Peak memory | 224704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690460384 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.3690460384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.1080232999 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 12948354 ps |
| CPU time | 0.92 seconds |
| Started | Oct 15 03:03:41 AM UTC 24 |
| Finished | Oct 15 03:03:43 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080232999 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.1080232999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.4261664278 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 23826820 ps |
| CPU time | 0.94 seconds |
| Started | Oct 15 03:03:41 AM UTC 24 |
| Finished | Oct 15 03:03:43 AM UTC 24 |
| Peak memory | 212736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261664278 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.4261664278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3330642558 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 16133393 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 03:03:41 AM UTC 24 |
| Finished | Oct 15 03:03:43 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330642558 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.3330642558 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.3666844910 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 38245962 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 03:03:41 AM UTC 24 |
| Finished | Oct 15 03:03:43 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666844910 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.3666844910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.3299649392 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 12484573 ps |
| CPU time | 1.2 seconds |
| Started | Oct 15 03:03:42 AM UTC 24 |
| Finished | Oct 15 03:03:44 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299649392 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.3299649392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.3173202458 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 20719986 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 03:03:42 AM UTC 24 |
| Finished | Oct 15 03:03:44 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173202458 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.3173202458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.2313081317 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 32562405 ps |
| CPU time | 0.84 seconds |
| Started | Oct 15 03:03:42 AM UTC 24 |
| Finished | Oct 15 03:03:44 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313081317 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.2313081317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.3479257990 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 109432171 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 03:03:42 AM UTC 24 |
| Finished | Oct 15 03:03:44 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479257990 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.3479257990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.115827857 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 121822323 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 03:03:42 AM UTC 24 |
| Finished | Oct 15 03:03:45 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115827857 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.115827857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.721811400 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 87679196 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 03:03:42 AM UTC 24 |
| Finished | Oct 15 03:03:45 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=721811400 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.721811400 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.2584685122 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 615736447 ps |
| CPU time | 15.01 seconds |
| Started | Oct 15 03:02:59 AM UTC 24 |
| Finished | Oct 15 03:03:16 AM UTC 24 |
| Peak memory | 224660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584685122 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.2584685122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1678834101 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 18015816531 ps |
| CPU time | 31.92 seconds |
| Started | Oct 15 03:02:58 AM UTC 24 |
| Finished | Oct 15 03:03:33 AM UTC 24 |
| Peak memory | 224760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678834101 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.1678834101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1925890289 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 24199469 ps |
| CPU time | 1.94 seconds |
| Started | Oct 15 03:02:58 AM UTC 24 |
| Finished | Oct 15 03:03:02 AM UTC 24 |
| Peak memory | 213116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925890289 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.1925890289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2455312120 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 104113475 ps |
| CPU time | 2.77 seconds |
| Started | Oct 15 03:03:01 AM UTC 24 |
| Finished | Oct 15 03:03:05 AM UTC 24 |
| Peak memory | 226804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2455312120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 4.spi_device_csr_mem_rw_with_rand_reset.2455312120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1470230804 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 85885186 ps |
| CPU time | 2.92 seconds |
| Started | Oct 15 03:02:58 AM UTC 24 |
| Finished | Oct 15 03:03:03 AM UTC 24 |
| Peak memory | 214348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470230804 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1470230804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.2818875176 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 17451332 ps |
| CPU time | 1.06 seconds |
| Started | Oct 15 03:02:57 AM UTC 24 |
| Finished | Oct 15 03:03:00 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818875176 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2818875176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.9325074 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 483827142 ps |
| CPU time | 1.72 seconds |
| Started | Oct 15 03:02:57 AM UTC 24 |
| Finished | Oct 15 03:03:01 AM UTC 24 |
| Peak memory | 223280 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9325074 -assert nopostpr oc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.9325074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_mem_partial_access/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.4112867987 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 11327955 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 03:02:57 AM UTC 24 |
| Finished | Oct 15 03:03:00 AM UTC 24 |
| Peak memory | 212832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112867987 -assert nopostproc +UVM _TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.4112867987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_mem_walk/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.875960176 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 144815576 ps |
| CPU time | 2.13 seconds |
| Started | Oct 15 03:02:59 AM UTC 24 |
| Finished | Oct 15 03:03:03 AM UTC 24 |
| Peak memory | 224856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875960176 -assert nopo stproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r epo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.875960176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.120035417 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 60141690 ps |
| CPU time | 3.95 seconds |
| Started | Oct 15 03:02:56 AM UTC 24 |
| Finished | Oct 15 03:03:01 AM UTC 24 |
| Peak memory | 224732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120035417 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.120035417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.3363586285 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 582000674 ps |
| CPU time | 7.6 seconds |
| Started | Oct 15 03:02:56 AM UTC 24 |
| Finished | Oct 15 03:03:05 AM UTC 24 |
| Peak memory | 224964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3363586285 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.3363586285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.3098823129 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 15474969 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 03:03:42 AM UTC 24 |
| Finished | Oct 15 03:03:45 AM UTC 24 |
| Peak memory | 212764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098823129 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.3098823129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.42876463 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 35314548 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 03:03:42 AM UTC 24 |
| Finished | Oct 15 03:03:45 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42876463 -assert nopostproc +UVM_TESTNAME=s pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.42876463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.493389074 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 57847129 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 03:03:44 AM UTC 24 |
| Finished | Oct 15 03:03:46 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493389074 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.493389074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.2955336801 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 20182188 ps |
| CPU time | 0.9 seconds |
| Started | Oct 15 03:03:44 AM UTC 24 |
| Finished | Oct 15 03:03:46 AM UTC 24 |
| Peak memory | 212632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955336801 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.2955336801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.2766008215 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 19002144 ps |
| CPU time | 0.89 seconds |
| Started | Oct 15 03:03:44 AM UTC 24 |
| Finished | Oct 15 03:03:46 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766008215 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.2766008215 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.1752936701 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 59768369 ps |
| CPU time | 0.9 seconds |
| Started | Oct 15 03:03:44 AM UTC 24 |
| Finished | Oct 15 03:03:46 AM UTC 24 |
| Peak memory | 212640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752936701 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.1752936701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.856979550 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 18208433 ps |
| CPU time | 0.94 seconds |
| Started | Oct 15 03:03:44 AM UTC 24 |
| Finished | Oct 15 03:03:46 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856979550 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.856979550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.1164533755 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 12664946 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 03:03:44 AM UTC 24 |
| Finished | Oct 15 03:03:46 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164533755 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.1164533755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.1347712044 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 29294751 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 03:03:44 AM UTC 24 |
| Finished | Oct 15 03:03:46 AM UTC 24 |
| Peak memory | 212768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347712044 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.1347712044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.522057658 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 43794783 ps |
| CPU time | 0.99 seconds |
| Started | Oct 15 03:03:45 AM UTC 24 |
| Finished | Oct 15 03:03:47 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522057658 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.522057658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3180290089 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 209538969 ps |
| CPU time | 2.1 seconds |
| Started | Oct 15 03:03:02 AM UTC 24 |
| Finished | Oct 15 03:03:05 AM UTC 24 |
| Peak memory | 226700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=3180290089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 5.spi_device_csr_mem_rw_with_rand_reset.3180290089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.128853228 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 21034121 ps |
| CPU time | 1.85 seconds |
| Started | Oct 15 03:03:02 AM UTC 24 |
| Finished | Oct 15 03:03:05 AM UTC 24 |
| Peak memory | 213048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128853228 -assert nopostproc +UVM_TESTNA ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.128853228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.3972195018 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 24493514 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 03:03:01 AM UTC 24 |
| Finished | Oct 15 03:03:03 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972195018 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.3972195018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2221118496 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 79562066 ps |
| CPU time | 2.61 seconds |
| Started | Oct 15 03:03:02 AM UTC 24 |
| Finished | Oct 15 03:03:05 AM UTC 24 |
| Peak memory | 224860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2221118496 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstand ing.2221118496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.1667672158 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 71602592 ps |
| CPU time | 2.39 seconds |
| Started | Oct 15 03:03:01 AM UTC 24 |
| Finished | Oct 15 03:03:04 AM UTC 24 |
| Peak memory | 224692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667672158 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1667672158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.938401882 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 289980218 ps |
| CPU time | 21.24 seconds |
| Started | Oct 15 03:03:01 AM UTC 24 |
| Finished | Oct 15 03:03:23 AM UTC 24 |
| Peak memory | 224648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938401882 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.938401882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2381286579 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 111204038 ps |
| CPU time | 4.86 seconds |
| Started | Oct 15 03:03:05 AM UTC 24 |
| Finished | Oct 15 03:03:11 AM UTC 24 |
| Peak memory | 229048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2381286579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 6.spi_device_csr_mem_rw_with_rand_reset.2381286579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.3035295180 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 38756812 ps |
| CPU time | 1.84 seconds |
| Started | Oct 15 03:03:04 AM UTC 24 |
| Finished | Oct 15 03:03:07 AM UTC 24 |
| Peak memory | 213052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035295180 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.3035295180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1176625020 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 15746214 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 03:03:04 AM UTC 24 |
| Finished | Oct 15 03:03:06 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176625020 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1176625020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2954354982 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 50566766 ps |
| CPU time | 4.05 seconds |
| Started | Oct 15 03:03:05 AM UTC 24 |
| Finished | Oct 15 03:03:10 AM UTC 24 |
| Peak memory | 224656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954354982 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstand ing.2954354982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.2059600006 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 1058585407 ps |
| CPU time | 6.52 seconds |
| Started | Oct 15 03:03:03 AM UTC 24 |
| Finished | Oct 15 03:03:11 AM UTC 24 |
| Peak memory | 224784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059600006 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2059600006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.405136464 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 3361227955 ps |
| CPU time | 23.04 seconds |
| Started | Oct 15 03:03:04 AM UTC 24 |
| Finished | Oct 15 03:03:28 AM UTC 24 |
| Peak memory | 224872 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405136464 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.405136464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2481906840 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 72377200 ps |
| CPU time | 3.11 seconds |
| Started | Oct 15 03:03:08 AM UTC 24 |
| Finished | Oct 15 03:03:12 AM UTC 24 |
| Peak memory | 229072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2481906840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 7.spi_device_csr_mem_rw_with_rand_reset.2481906840 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.2628015805 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 133144238 ps |
| CPU time | 3.03 seconds |
| Started | Oct 15 03:03:07 AM UTC 24 |
| Finished | Oct 15 03:03:11 AM UTC 24 |
| Peak memory | 224592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628015805 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2628015805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.1921591631 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 16913362 ps |
| CPU time | 1.19 seconds |
| Started | Oct 15 03:03:06 AM UTC 24 |
| Finished | Oct 15 03:03:09 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1921591631 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.1921591631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3648798093 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 212398839 ps |
| CPU time | 6.33 seconds |
| Started | Oct 15 03:03:07 AM UTC 24 |
| Finished | Oct 15 03:03:14 AM UTC 24 |
| Peak memory | 224688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648798093 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstand ing.3648798093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.4201363855 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1021932055 ps |
| CPU time | 9 seconds |
| Started | Oct 15 03:03:05 AM UTC 24 |
| Finished | Oct 15 03:03:15 AM UTC 24 |
| Peak memory | 224660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201363855 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.4201363855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.4257391038 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 4231126414 ps |
| CPU time | 15.3 seconds |
| Started | Oct 15 03:03:05 AM UTC 24 |
| Finished | Oct 15 03:03:22 AM UTC 24 |
| Peak memory | 224772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257391038 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.4257391038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1389597682 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 190685684 ps |
| CPU time | 4.06 seconds |
| Started | Oct 15 03:03:12 AM UTC 24 |
| Finished | Oct 15 03:03:17 AM UTC 24 |
| Peak memory | 227004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=1389597682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 8.spi_device_csr_mem_rw_with_rand_reset.1389597682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.2511189588 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 77245374 ps |
| CPU time | 1.83 seconds |
| Started | Oct 15 03:03:12 AM UTC 24 |
| Finished | Oct 15 03:03:15 AM UTC 24 |
| Peak memory | 213052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511189588 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2511189588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.3056790255 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 49558447 ps |
| CPU time | 1.14 seconds |
| Started | Oct 15 03:03:11 AM UTC 24 |
| Finished | Oct 15 03:03:13 AM UTC 24 |
| Peak memory | 212700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3056790255 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3056790255 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1779681606 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 248726163 ps |
| CPU time | 4 seconds |
| Started | Oct 15 03:03:12 AM UTC 24 |
| Finished | Oct 15 03:03:17 AM UTC 24 |
| Peak memory | 224592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779681606 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstand ing.1779681606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.2484571692 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 712094227 ps |
| CPU time | 5.92 seconds |
| Started | Oct 15 03:03:08 AM UTC 24 |
| Finished | Oct 15 03:03:15 AM UTC 24 |
| Peak memory | 226704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484571692 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2484571692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.201572424 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2816437698 ps |
| CPU time | 16.1 seconds |
| Started | Oct 15 03:03:10 AM UTC 24 |
| Finished | Oct 15 03:03:27 AM UTC 24 |
| Peak memory | 226884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201572424 -assert nopostproc +U VM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.201572424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2981484211 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 226670599 ps |
| CPU time | 2.58 seconds |
| Started | Oct 15 03:03:15 AM UTC 24 |
| Finished | Oct 15 03:03:19 AM UTC 24 |
| Peak memory | 224648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000 000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb _random_seed=2981484211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_ name 9.spi_device_csr_mem_rw_with_rand_reset.2981484211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.1402509290 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 35781307 ps |
| CPU time | 1.83 seconds |
| Started | Oct 15 03:03:14 AM UTC 24 |
| Finished | Oct 15 03:03:17 AM UTC 24 |
| Peak memory | 213052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402509290 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.1402509290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.272403622 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 42797520 ps |
| CPU time | 1.08 seconds |
| Started | Oct 15 03:03:14 AM UTC 24 |
| Finished | Oct 15 03:03:17 AM UTC 24 |
| Peak memory | 212708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272403622 -assert nopostproc +UVM_TESTNAME= spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.272403622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.1822843399 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 44894839 ps |
| CPU time | 3.9 seconds |
| Started | Oct 15 03:03:15 AM UTC 24 |
| Finished | Oct 15 03:03:20 AM UTC 24 |
| Peak memory | 224592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822843399 -assert nop ostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/ repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstand ing.1822843399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.2590608335 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 91655545 ps |
| CPU time | 4.48 seconds |
| Started | Oct 15 03:03:13 AM UTC 24 |
| Finished | Oct 15 03:03:19 AM UTC 24 |
| Peak memory | 224664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590608335 -assert nopostproc +UVM_TESTNAME =spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2590608335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.1024199664 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 291642446 ps |
| CPU time | 7.47 seconds |
| Started | Oct 15 03:03:13 AM UTC 24 |
| Finished | Oct 15 03:03:22 AM UTC 24 |
| Peak memory | 224684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024199664 -assert nopostproc + UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.1024199664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_alert_test.2030304395 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 13006056 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 05:56:47 AM UTC 24 |
| Finished | Oct 15 05:56:49 AM UTC 24 |
| Peak memory | 214596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2030304395 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2030304395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_cfg_cmd.295611563 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1068739209 ps |
| CPU time | 5.97 seconds |
| Started | Oct 15 05:56:03 AM UTC 24 |
| Finished | Oct 15 05:56:10 AM UTC 24 |
| Peak memory | 245764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295611563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.295611563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_csb_read.852612089 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 43962763 ps |
| CPU time | 1.24 seconds |
| Started | Oct 15 05:55:31 AM UTC 24 |
| Finished | Oct 15 05:55:33 AM UTC 24 |
| Peak memory | 216408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852612089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.852612089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_flash_mode.743585184 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 217812941 ps |
| CPU time | 4.66 seconds |
| Started | Oct 15 05:56:09 AM UTC 24 |
| Finished | Oct 15 05:56:15 AM UTC 24 |
| Peak memory | 235760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743585184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.743585184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_mailbox.4046627722 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 16301333777 ps |
| CPU time | 32.9 seconds |
| Started | Oct 15 05:55:51 AM UTC 24 |
| Finished | Oct 15 05:56:25 AM UTC 24 |
| Peak memory | 252184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046627722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.4046627722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.4063704814 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 291102237 ps |
| CPU time | 3.42 seconds |
| Started | Oct 15 05:55:44 AM UTC 24 |
| Finished | Oct 15 05:55:48 AM UTC 24 |
| Peak memory | 235568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063704814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.4063704814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.3774072094 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3844561763 ps |
| CPU time | 29.31 seconds |
| Started | Oct 15 05:56:15 AM UTC 24 |
| Finished | Oct 15 05:56:46 AM UTC 24 |
| Peak memory | 232336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774072094 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.3774072094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_rw.612508102 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 213775432 ps |
| CPU time | 6.81 seconds |
| Started | Oct 15 05:55:42 AM UTC 24 |
| Finished | Oct 15 05:55:50 AM UTC 24 |
| Peak memory | 228248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=612508102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.612508102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2235040263 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 32617312 ps |
| CPU time | 1.31 seconds |
| Started | Oct 15 05:55:40 AM UTC 24 |
| Finished | Oct 15 05:55:43 AM UTC 24 |
| Peak memory | 216700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235040263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2235040263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/0.spi_device_upload.42796440 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 7450697224 ps |
| CPU time | 43.17 seconds |
| Started | Oct 15 05:56:00 AM UTC 24 |
| Finished | Oct 15 05:56:45 AM UTC 24 |
| Peak memory | 246128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42796440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.42796440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/0.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_csb_read.993101044 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 20873580 ps |
| CPU time | 1.16 seconds |
| Started | Oct 15 05:56:47 AM UTC 24 |
| Finished | Oct 15 05:56:49 AM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993101044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.993101044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_all.544515834 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 286016235907 ps |
| CPU time | 215.51 seconds |
| Started | Oct 15 05:57:27 AM UTC 24 |
| Finished | Oct 15 06:01:05 AM UTC 24 |
| Peak memory | 268432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544515834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.544515834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2312472207 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 10494329082 ps |
| CPU time | 68.6 seconds |
| Started | Oct 15 05:57:32 AM UTC 24 |
| Finished | Oct 15 05:58:42 AM UTC 24 |
| Peak memory | 268688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2312472207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2312472207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode.1153609767 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 1733374501 ps |
| CPU time | 12.12 seconds |
| Started | Oct 15 05:57:22 AM UTC 24 |
| Finished | Oct 15 05:57:36 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153609767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1153609767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3465499895 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3101607711 ps |
| CPU time | 12.69 seconds |
| Started | Oct 15 05:57:24 AM UTC 24 |
| Finished | Oct 15 05:57:38 AM UTC 24 |
| Peak memory | 235600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3465499895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.3465499895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_intercept.2642073335 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 747431893 ps |
| CPU time | 6.75 seconds |
| Started | Oct 15 05:57:05 AM UTC 24 |
| Finished | Oct 15 05:57:13 AM UTC 24 |
| Peak memory | 235580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642073335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2642073335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_mailbox.866549693 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 2031969338 ps |
| CPU time | 41.06 seconds |
| Started | Oct 15 05:57:10 AM UTC 24 |
| Finished | Oct 15 05:57:53 AM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866549693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.866549693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.3000814977 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 23410548708 ps |
| CPU time | 31.8 seconds |
| Started | Oct 15 05:56:58 AM UTC 24 |
| Finished | Oct 15 05:57:31 AM UTC 24 |
| Peak memory | 245804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000814977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.3000814977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.2705450620 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2092225783 ps |
| CPU time | 5.94 seconds |
| Started | Oct 15 05:56:57 AM UTC 24 |
| Finished | Oct 15 05:57:04 AM UTC 24 |
| Peak memory | 235504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705450620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2705450620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.3667812048 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 613951737 ps |
| CPU time | 8.11 seconds |
| Started | Oct 15 05:57:25 AM UTC 24 |
| Finished | Oct 15 05:57:35 AM UTC 24 |
| Peak memory | 232072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667812048 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.3667812048 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_sec_cm.3092178585 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 733414910 ps |
| CPU time | 1.96 seconds |
| Started | Oct 15 05:57:37 AM UTC 24 |
| Finished | Oct 15 05:57:40 AM UTC 24 |
| Peak memory | 257760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092178585 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3092178585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_all.2616131027 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2072877873 ps |
| CPU time | 23.03 seconds |
| Started | Oct 15 05:56:50 AM UTC 24 |
| Finished | Oct 15 05:57:15 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616131027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.2616131027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1437065833 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 8948424851 ps |
| CPU time | 50.28 seconds |
| Started | Oct 15 05:56:50 AM UTC 24 |
| Finished | Oct 15 05:57:42 AM UTC 24 |
| Peak memory | 228500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437065833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1437065833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_rw.215656118 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 10866247 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 05:56:55 AM UTC 24 |
| Finished | Oct 15 05:56:57 AM UTC 24 |
| Peak memory | 217072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215656118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.215656118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.3513913211 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 37917791 ps |
| CPU time | 1.42 seconds |
| Started | Oct 15 05:56:53 AM UTC 24 |
| Finished | Oct 15 05:56:56 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513913211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3513913211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/1.spi_device_upload.2164617557 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 812358095 ps |
| CPU time | 8.74 seconds |
| Started | Oct 15 05:57:14 AM UTC 24 |
| Finished | Oct 15 05:57:24 AM UTC 24 |
| Peak memory | 245768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164617557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2164617557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/1.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_alert_test.2187430031 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 11897925 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 06:03:22 AM UTC 24 |
| Finished | Oct 15 06:03:24 AM UTC 24 |
| Peak memory | 214544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187430031 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.2187430031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_cfg_cmd.2453849672 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3485951524 ps |
| CPU time | 5.7 seconds |
| Started | Oct 15 06:03:05 AM UTC 24 |
| Finished | Oct 15 06:03:12 AM UTC 24 |
| Peak memory | 235636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453849672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.2453849672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_csb_read.3909679350 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 16042478 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 06:02:55 AM UTC 24 |
| Finished | Oct 15 06:02:58 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909679350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3909679350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_all.3138221939 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 2397479084 ps |
| CPU time | 10.31 seconds |
| Started | Oct 15 06:03:13 AM UTC 24 |
| Finished | Oct 15 06:03:24 AM UTC 24 |
| Peak memory | 235636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138221939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3138221939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.229661469 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 98859195765 ps |
| CPU time | 189.63 seconds |
| Started | Oct 15 06:03:13 AM UTC 24 |
| Finished | Oct 15 06:06:25 AM UTC 24 |
| Peak memory | 266408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229661469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.229661469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3514129782 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 26119042106 ps |
| CPU time | 256.66 seconds |
| Started | Oct 15 06:03:13 AM UTC 24 |
| Finished | Oct 15 06:07:33 AM UTC 24 |
| Peak memory | 264572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514129782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.3514129782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_flash_mode.3325486285 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 953333046 ps |
| CPU time | 28.56 seconds |
| Started | Oct 15 06:03:08 AM UTC 24 |
| Finished | Oct 15 06:03:38 AM UTC 24 |
| Peak memory | 249912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325486285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3325486285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_intercept.3646892390 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 102595211 ps |
| CPU time | 6.26 seconds |
| Started | Oct 15 06:03:04 AM UTC 24 |
| Finished | Oct 15 06:03:12 AM UTC 24 |
| Peak memory | 245844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646892390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3646892390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_mailbox.2224278801 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 56199555 ps |
| CPU time | 3.12 seconds |
| Started | Oct 15 06:03:04 AM UTC 24 |
| Finished | Oct 15 06:03:08 AM UTC 24 |
| Peak memory | 245460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224278801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2224278801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.2340468758 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 9682673671 ps |
| CPU time | 24.11 seconds |
| Started | Oct 15 06:03:03 AM UTC 24 |
| Finished | Oct 15 06:03:29 AM UTC 24 |
| Peak memory | 245884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340468758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.2340468758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.1026831471 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 142734018 ps |
| CPU time | 3.33 seconds |
| Started | Oct 15 06:03:03 AM UTC 24 |
| Finished | Oct 15 06:03:08 AM UTC 24 |
| Peak memory | 246032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026831471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1026831471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.848891782 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 4999118985 ps |
| CPU time | 12.88 seconds |
| Started | Oct 15 06:03:09 AM UTC 24 |
| Finished | Oct 15 06:03:23 AM UTC 24 |
| Peak memory | 232160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848891782 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.848891782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_all.2809653361 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 157201846 ps |
| CPU time | 3.73 seconds |
| Started | Oct 15 06:02:59 AM UTC 24 |
| Finished | Oct 15 06:03:03 AM UTC 24 |
| Peak memory | 228336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809653361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2809653361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.255515959 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 592317003 ps |
| CPU time | 4.82 seconds |
| Started | Oct 15 06:02:56 AM UTC 24 |
| Finished | Oct 15 06:03:03 AM UTC 24 |
| Peak memory | 228232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255515959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.255515959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_rw.2505603533 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 130836495 ps |
| CPU time | 1.8 seconds |
| Started | Oct 15 06:03:01 AM UTC 24 |
| Finished | Oct 15 06:03:04 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505603533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.2505603533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.143466849 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 21962045 ps |
| CPU time | 1.23 seconds |
| Started | Oct 15 06:03:00 AM UTC 24 |
| Finished | Oct 15 06:03:02 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143466849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.143466849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/10.spi_device_upload.3853800983 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 11249334139 ps |
| CPU time | 41.52 seconds |
| Started | Oct 15 06:03:04 AM UTC 24 |
| Finished | Oct 15 06:03:47 AM UTC 24 |
| Peak memory | 262224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853800983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3853800983 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/10.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_alert_test.2853924943 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 116292259 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 06:03:44 AM UTC 24 |
| Finished | Oct 15 06:03:46 AM UTC 24 |
| Peak memory | 214532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853924943 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.2853924943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_cfg_cmd.140144522 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 903254540 ps |
| CPU time | 8.31 seconds |
| Started | Oct 15 06:03:33 AM UTC 24 |
| Finished | Oct 15 06:03:43 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140144522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.140144522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_csb_read.235057265 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 21776772 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 06:03:24 AM UTC 24 |
| Finished | Oct 15 06:03:26 AM UTC 24 |
| Peak memory | 216704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235057265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.235057265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_all.1648780372 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 92721363542 ps |
| CPU time | 288.91 seconds |
| Started | Oct 15 06:03:38 AM UTC 24 |
| Finished | Oct 15 06:08:31 AM UTC 24 |
| Peak memory | 285004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648780372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.1648780372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.1118698711 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 46970194109 ps |
| CPU time | 532.92 seconds |
| Started | Oct 15 06:03:40 AM UTC 24 |
| Finished | Oct 15 06:12:39 AM UTC 24 |
| Peak memory | 278708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118698711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.1118698711 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode.2517196547 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 20514915690 ps |
| CPU time | 29.74 seconds |
| Started | Oct 15 06:03:33 AM UTC 24 |
| Finished | Oct 15 06:04:04 AM UTC 24 |
| Peak memory | 246012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517196547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2517196547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.1581779259 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2166204065 ps |
| CPU time | 14.59 seconds |
| Started | Oct 15 06:03:33 AM UTC 24 |
| Finished | Oct 15 06:03:49 AM UTC 24 |
| Peak memory | 249968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581779259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.1581779259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_intercept.1658188602 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 1534600225 ps |
| CPU time | 18.3 seconds |
| Started | Oct 15 06:03:30 AM UTC 24 |
| Finished | Oct 15 06:03:49 AM UTC 24 |
| Peak memory | 235764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658188602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.1658188602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_mailbox.3978609421 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 5586745702 ps |
| CPU time | 23.23 seconds |
| Started | Oct 15 06:03:31 AM UTC 24 |
| Finished | Oct 15 06:03:55 AM UTC 24 |
| Peak memory | 245820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978609421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.3978609421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.2477686087 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3108833439 ps |
| CPU time | 6.7 seconds |
| Started | Oct 15 06:03:30 AM UTC 24 |
| Finished | Oct 15 06:03:37 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477686087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.2477686087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.1279536095 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 583209882 ps |
| CPU time | 4.37 seconds |
| Started | Oct 15 06:03:30 AM UTC 24 |
| Finished | Oct 15 06:03:35 AM UTC 24 |
| Peak memory | 246096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279536095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.1279536095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.808878437 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 878064829 ps |
| CPU time | 6.72 seconds |
| Started | Oct 15 06:03:36 AM UTC 24 |
| Finished | Oct 15 06:03:44 AM UTC 24 |
| Peak memory | 234184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808878437 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.808878437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_all.3646493080 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 58035708 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 06:03:26 AM UTC 24 |
| Finished | Oct 15 06:03:28 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646493080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.3646493080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.2400252896 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 1732658866 ps |
| CPU time | 6.06 seconds |
| Started | Oct 15 06:03:25 AM UTC 24 |
| Finished | Oct 15 06:03:32 AM UTC 24 |
| Peak memory | 228492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400252896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.2400252896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_rw.899832725 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 194924315 ps |
| CPU time | 2.78 seconds |
| Started | Oct 15 06:03:28 AM UTC 24 |
| Finished | Oct 15 06:03:32 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=899832725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.899832725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.3525722113 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 86289624 ps |
| CPU time | 1.27 seconds |
| Started | Oct 15 06:03:27 AM UTC 24 |
| Finished | Oct 15 06:03:30 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525722113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3525722113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/11.spi_device_upload.2051699863 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 295593945 ps |
| CPU time | 8.93 seconds |
| Started | Oct 15 06:03:33 AM UTC 24 |
| Finished | Oct 15 06:03:43 AM UTC 24 |
| Peak memory | 235704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051699863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.2051699863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/11.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_alert_test.2012300665 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 12538986 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 06:04:02 AM UTC 24 |
| Finished | Oct 15 06:04:04 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012300665 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.2012300665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_cfg_cmd.338086377 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 695554994 ps |
| CPU time | 5.98 seconds |
| Started | Oct 15 06:03:51 AM UTC 24 |
| Finished | Oct 15 06:03:58 AM UTC 24 |
| Peak memory | 245912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338086377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.338086377 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_csb_read.1675211791 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 44874407 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 06:03:44 AM UTC 24 |
| Finished | Oct 15 06:03:46 AM UTC 24 |
| Peak memory | 216628 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675211791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.1675211791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_all.1819252074 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 2251891092 ps |
| CPU time | 56.49 seconds |
| Started | Oct 15 06:03:56 AM UTC 24 |
| Finished | Oct 15 06:04:54 AM UTC 24 |
| Peak memory | 268664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819252074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1819252074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.2308426645 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 372870888737 ps |
| CPU time | 402.96 seconds |
| Started | Oct 15 06:03:58 AM UTC 24 |
| Finished | Oct 15 06:10:46 AM UTC 24 |
| Peak memory | 268032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308426645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.2308426645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode.1461782817 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 1055620178 ps |
| CPU time | 10.71 seconds |
| Started | Oct 15 06:03:54 AM UTC 24 |
| Finished | Oct 15 06:04:06 AM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461782817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.1461782817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.1867470598 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 230856542402 ps |
| CPU time | 452.69 seconds |
| Started | Oct 15 06:03:55 AM UTC 24 |
| Finished | Oct 15 06:11:33 AM UTC 24 |
| Peak memory | 264332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867470598 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.1867470598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_intercept.44934253 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 4683522011 ps |
| CPU time | 8.88 seconds |
| Started | Oct 15 06:03:51 AM UTC 24 |
| Finished | Oct 15 06:04:01 AM UTC 24 |
| Peak memory | 235832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44934253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.44934253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_mailbox.2825251765 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3220799771 ps |
| CPU time | 26.43 seconds |
| Started | Oct 15 06:03:51 AM UTC 24 |
| Finished | Oct 15 06:04:18 AM UTC 24 |
| Peak memory | 245880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825251765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2825251765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.2565394814 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 273532960 ps |
| CPU time | 3.56 seconds |
| Started | Oct 15 06:03:48 AM UTC 24 |
| Finished | Oct 15 06:03:53 AM UTC 24 |
| Peak memory | 246072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565394814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.2565394814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1075097728 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 485659371 ps |
| CPU time | 7.69 seconds |
| Started | Oct 15 06:03:48 AM UTC 24 |
| Finished | Oct 15 06:03:57 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075097728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1075097728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.147377342 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 6815750001 ps |
| CPU time | 7.31 seconds |
| Started | Oct 15 06:03:56 AM UTC 24 |
| Finished | Oct 15 06:04:04 AM UTC 24 |
| Peak memory | 234456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147377342 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.147377342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.2098750646 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 440877132254 ps |
| CPU time | 831.89 seconds |
| Started | Oct 15 06:04:01 AM UTC 24 |
| Finished | Oct 15 06:18:03 AM UTC 24 |
| Peak memory | 295156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098750646 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.2098750646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_all.2021922828 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 1786568545 ps |
| CPU time | 41.75 seconds |
| Started | Oct 15 06:03:47 AM UTC 24 |
| Finished | Oct 15 06:04:30 AM UTC 24 |
| Peak memory | 228240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021922828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2021922828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.649881062 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 1582950257 ps |
| CPU time | 8.49 seconds |
| Started | Oct 15 06:03:45 AM UTC 24 |
| Finished | Oct 15 06:03:55 AM UTC 24 |
| Peak memory | 228344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649881062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.649881062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_rw.4173195692 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 204884344 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 06:03:47 AM UTC 24 |
| Finished | Oct 15 06:03:49 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173195692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.4173195692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.1942472127 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 23356405 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 06:03:47 AM UTC 24 |
| Finished | Oct 15 06:03:49 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942472127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1942472127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_upload.2330381980 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 892910285 ps |
| CPU time | 14.17 seconds |
| Started | Oct 15 06:03:51 AM UTC 24 |
| Finished | Oct 15 06:04:06 AM UTC 24 |
| Peak memory | 251920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330381980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2330381980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/12.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_alert_test.605150438 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 10214653 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 06:04:30 AM UTC 24 |
| Finished | Oct 15 06:04:32 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605150438 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.605150438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_cfg_cmd.2886066868 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 3969665296 ps |
| CPU time | 14.53 seconds |
| Started | Oct 15 06:04:10 AM UTC 24 |
| Finished | Oct 15 06:04:26 AM UTC 24 |
| Peak memory | 245972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2886066868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2886066868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_csb_read.751306322 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 126497165 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 06:04:05 AM UTC 24 |
| Finished | Oct 15 06:04:08 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751306322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.751306322 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1401635357 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 4898130291 ps |
| CPU time | 14.28 seconds |
| Started | Oct 15 06:04:20 AM UTC 24 |
| Finished | Oct 15 06:04:35 AM UTC 24 |
| Peak memory | 230400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401635357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.1401635357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.1966452899 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 40284599486 ps |
| CPU time | 124.17 seconds |
| Started | Oct 15 06:04:20 AM UTC 24 |
| Finished | Oct 15 06:06:26 AM UTC 24 |
| Peak memory | 266448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966452899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.1966452899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.750710880 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 53913360079 ps |
| CPU time | 172.38 seconds |
| Started | Oct 15 06:04:15 AM UTC 24 |
| Finished | Oct 15 06:07:10 AM UTC 24 |
| Peak memory | 268404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=750710880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.750710880 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_intercept.1841140200 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 424273572 ps |
| CPU time | 5.78 seconds |
| Started | Oct 15 06:04:09 AM UTC 24 |
| Finished | Oct 15 06:04:16 AM UTC 24 |
| Peak memory | 245844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841140200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.1841140200 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_mailbox.2382683129 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 146140713 ps |
| CPU time | 2.39 seconds |
| Started | Oct 15 06:04:10 AM UTC 24 |
| Finished | Oct 15 06:04:14 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382683129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2382683129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.1764109380 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 394099641 ps |
| CPU time | 8.57 seconds |
| Started | Oct 15 06:04:09 AM UTC 24 |
| Finished | Oct 15 06:04:19 AM UTC 24 |
| Peak memory | 235516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764109380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.1764109380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.3566897698 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 14950240674 ps |
| CPU time | 57 seconds |
| Started | Oct 15 06:04:09 AM UTC 24 |
| Finished | Oct 15 06:05:07 AM UTC 24 |
| Peak memory | 262260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566897698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3566897698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.844515486 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2849861613 ps |
| CPU time | 11.95 seconds |
| Started | Oct 15 06:04:17 AM UTC 24 |
| Finished | Oct 15 06:04:30 AM UTC 24 |
| Peak memory | 232340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844515486 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.844515486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_all.1310583877 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4555013503 ps |
| CPU time | 10.91 seconds |
| Started | Oct 15 06:04:07 AM UTC 24 |
| Finished | Oct 15 06:04:19 AM UTC 24 |
| Peak memory | 228368 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310583877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1310583877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.3553036972 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 3265484481 ps |
| CPU time | 5.47 seconds |
| Started | Oct 15 06:04:06 AM UTC 24 |
| Finished | Oct 15 06:04:12 AM UTC 24 |
| Peak memory | 228428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553036972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3553036972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_rw.1730838946 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 20037247 ps |
| CPU time | 1.69 seconds |
| Started | Oct 15 06:04:07 AM UTC 24 |
| Finished | Oct 15 06:04:10 AM UTC 24 |
| Peak memory | 228432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730838946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1730838946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.1535329089 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 38242368 ps |
| CPU time | 1.28 seconds |
| Started | Oct 15 06:04:07 AM UTC 24 |
| Finished | Oct 15 06:04:09 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1535329089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1535329089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/13.spi_device_upload.126618022 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 5959267014 ps |
| CPU time | 22.83 seconds |
| Started | Oct 15 06:04:10 AM UTC 24 |
| Finished | Oct 15 06:04:34 AM UTC 24 |
| Peak memory | 235788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126618022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.126618022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/13.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_alert_test.3471707361 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 14201519 ps |
| CPU time | 1.14 seconds |
| Started | Oct 15 06:05:09 AM UTC 24 |
| Finished | Oct 15 06:05:11 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471707361 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.3471707361 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_cfg_cmd.4175561300 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 1385823559 ps |
| CPU time | 6.27 seconds |
| Started | Oct 15 06:04:45 AM UTC 24 |
| Finished | Oct 15 06:04:52 AM UTC 24 |
| Peak memory | 245748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175561300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.4175561300 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_csb_read.1663964147 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 73491272 ps |
| CPU time | 1.27 seconds |
| Started | Oct 15 06:04:31 AM UTC 24 |
| Finished | Oct 15 06:04:34 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663964147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1663964147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_all.259013699 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 64973670104 ps |
| CPU time | 157.9 seconds |
| Started | Oct 15 06:04:55 AM UTC 24 |
| Finished | Oct 15 06:07:36 AM UTC 24 |
| Peak memory | 268624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259013699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.259013699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.2593781990 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 535037519413 ps |
| CPU time | 293.45 seconds |
| Started | Oct 15 06:04:58 AM UTC 24 |
| Finished | Oct 15 06:09:55 AM UTC 24 |
| Peak memory | 268468 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593781990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2593781990 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.1462402646 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 16955308926 ps |
| CPU time | 164.32 seconds |
| Started | Oct 15 06:05:01 AM UTC 24 |
| Finished | Oct 15 06:07:48 AM UTC 24 |
| Peak memory | 262320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462402646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.1462402646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_flash_mode.441208467 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 7092519495 ps |
| CPU time | 28.28 seconds |
| Started | Oct 15 06:04:52 AM UTC 24 |
| Finished | Oct 15 06:05:22 AM UTC 24 |
| Peak memory | 252048 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441208467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.441208467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_intercept.3783940170 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 10145362227 ps |
| CPU time | 13.13 seconds |
| Started | Oct 15 06:04:39 AM UTC 24 |
| Finished | Oct 15 06:04:53 AM UTC 24 |
| Peak memory | 235580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783940170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3783940170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_mailbox.2498555102 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 23890007415 ps |
| CPU time | 40.61 seconds |
| Started | Oct 15 06:04:43 AM UTC 24 |
| Finished | Oct 15 06:05:25 AM UTC 24 |
| Peak memory | 246072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2498555102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2498555102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.3067314589 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 79193673 ps |
| CPU time | 4.16 seconds |
| Started | Oct 15 06:04:38 AM UTC 24 |
| Finished | Oct 15 06:04:43 AM UTC 24 |
| Peak memory | 245808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067314589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.3067314589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.1791578501 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 8776573630 ps |
| CPU time | 19 seconds |
| Started | Oct 15 06:04:37 AM UTC 24 |
| Finished | Oct 15 06:04:57 AM UTC 24 |
| Peak memory | 235636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791578501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1791578501 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.1167175549 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 141222929 ps |
| CPU time | 5.59 seconds |
| Started | Oct 15 06:04:54 AM UTC 24 |
| Finished | Oct 15 06:05:01 AM UTC 24 |
| Peak memory | 232068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167175549 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.1167175549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_all.1560872595 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 680397100 ps |
| CPU time | 6.56 seconds |
| Started | Oct 15 06:04:34 AM UTC 24 |
| Finished | Oct 15 06:04:42 AM UTC 24 |
| Peak memory | 230348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560872595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1560872595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.656498379 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 65678325131 ps |
| CPU time | 32.95 seconds |
| Started | Oct 15 06:04:33 AM UTC 24 |
| Finished | Oct 15 06:05:08 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656498379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.656498379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_rw.598932057 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 18392202 ps |
| CPU time | 0.96 seconds |
| Started | Oct 15 06:04:35 AM UTC 24 |
| Finished | Oct 15 06:04:38 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598932057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.598932057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.3271785976 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 47605007 ps |
| CPU time | 1.4 seconds |
| Started | Oct 15 06:04:34 AM UTC 24 |
| Finished | Oct 15 06:04:37 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271785976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3271785976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/14.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_alert_test.2448032991 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 24107735 ps |
| CPU time | 0.9 seconds |
| Started | Oct 15 06:05:38 AM UTC 24 |
| Finished | Oct 15 06:05:40 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448032991 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.2448032991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2299085805 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 5544169123 ps |
| CPU time | 23.38 seconds |
| Started | Oct 15 06:05:26 AM UTC 24 |
| Finished | Oct 15 06:05:51 AM UTC 24 |
| Peak memory | 235636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299085805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2299085805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_csb_read.313912350 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 20717356 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 06:05:09 AM UTC 24 |
| Finished | Oct 15 06:05:11 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313912350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.313912350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_all.3882409246 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 4925748890 ps |
| CPU time | 114.94 seconds |
| Started | Oct 15 06:05:31 AM UTC 24 |
| Finished | Oct 15 06:07:28 AM UTC 24 |
| Peak memory | 262540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882409246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3882409246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1299922677 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 30524939545 ps |
| CPU time | 231.68 seconds |
| Started | Oct 15 06:05:32 AM UTC 24 |
| Finished | Oct 15 06:09:27 AM UTC 24 |
| Peak memory | 262324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299922677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1299922677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.3776549485 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 58586423551 ps |
| CPU time | 56.96 seconds |
| Started | Oct 15 06:05:35 AM UTC 24 |
| Finished | Oct 15 06:06:34 AM UTC 24 |
| Peak memory | 266384 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776549485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.3776549485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode.3049895253 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 195011150 ps |
| CPU time | 5.93 seconds |
| Started | Oct 15 06:05:27 AM UTC 24 |
| Finished | Oct 15 06:05:34 AM UTC 24 |
| Peak memory | 252112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049895253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3049895253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.3908889755 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 27368503023 ps |
| CPU time | 259.32 seconds |
| Started | Oct 15 06:05:28 AM UTC 24 |
| Finished | Oct 15 06:09:52 AM UTC 24 |
| Peak memory | 262260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908889755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.3908889755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_intercept.3899980026 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 675183948 ps |
| CPU time | 6.68 seconds |
| Started | Oct 15 06:05:22 AM UTC 24 |
| Finished | Oct 15 06:05:29 AM UTC 24 |
| Peak memory | 245784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899980026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3899980026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_mailbox.3345741220 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 16769451424 ps |
| CPU time | 27.37 seconds |
| Started | Oct 15 06:05:23 AM UTC 24 |
| Finished | Oct 15 06:05:51 AM UTC 24 |
| Peak memory | 245876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345741220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3345741220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.1928009103 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 1970246278 ps |
| CPU time | 11.02 seconds |
| Started | Oct 15 06:05:16 AM UTC 24 |
| Finished | Oct 15 06:05:28 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928009103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.1928009103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.1659266563 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 37113548055 ps |
| CPU time | 39.26 seconds |
| Started | Oct 15 06:05:15 AM UTC 24 |
| Finished | Oct 15 06:05:56 AM UTC 24 |
| Peak memory | 235644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659266563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1659266563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.3961159721 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 210063218 ps |
| CPU time | 6.84 seconds |
| Started | Oct 15 06:05:31 AM UTC 24 |
| Finished | Oct 15 06:05:39 AM UTC 24 |
| Peak memory | 231444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961159721 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.3961159721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_stress_all.3762815527 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 13475710316 ps |
| CPU time | 88.19 seconds |
| Started | Oct 15 06:05:35 AM UTC 24 |
| Finished | Oct 15 06:07:05 AM UTC 24 |
| Peak memory | 262320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762815527 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.3762815527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_all.3475561956 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 1701100929 ps |
| CPU time | 16.64 seconds |
| Started | Oct 15 06:05:12 AM UTC 24 |
| Finished | Oct 15 06:05:30 AM UTC 24 |
| Peak memory | 232452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475561956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.3475561956 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.3503233660 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 13542900013 ps |
| CPU time | 26 seconds |
| Started | Oct 15 06:05:12 AM UTC 24 |
| Finished | Oct 15 06:05:39 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503233660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3503233660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_rw.3306345585 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 71441267 ps |
| CPU time | 1.41 seconds |
| Started | Oct 15 06:05:12 AM UTC 24 |
| Finished | Oct 15 06:05:15 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306345585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3306345585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.3887769415 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 50682518 ps |
| CPU time | 1.23 seconds |
| Started | Oct 15 06:05:12 AM UTC 24 |
| Finished | Oct 15 06:05:14 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887769415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3887769415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/15.spi_device_upload.4069870813 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 15821289921 ps |
| CPU time | 21.6 seconds |
| Started | Oct 15 06:05:26 AM UTC 24 |
| Finished | Oct 15 06:05:49 AM UTC 24 |
| Peak memory | 235660 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069870813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.4069870813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/15.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_alert_test.1200090799 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 20170221 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 06:06:27 AM UTC 24 |
| Finished | Oct 15 06:06:29 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200090799 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.1200090799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_cfg_cmd.3226028341 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 457003242 ps |
| CPU time | 4.1 seconds |
| Started | Oct 15 06:05:56 AM UTC 24 |
| Finished | Oct 15 06:06:01 AM UTC 24 |
| Peak memory | 245784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226028341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.3226028341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_csb_read.1755714623 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 14881417 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 06:05:40 AM UTC 24 |
| Finished | Oct 15 06:05:42 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755714623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1755714623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_all.3586078515 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 11656656275 ps |
| CPU time | 116.3 seconds |
| Started | Oct 15 06:05:59 AM UTC 24 |
| Finished | Oct 15 06:07:57 AM UTC 24 |
| Peak memory | 266360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586078515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3586078515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.4207134754 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 330501543835 ps |
| CPU time | 300.71 seconds |
| Started | Oct 15 06:06:02 AM UTC 24 |
| Finished | Oct 15 06:11:07 AM UTC 24 |
| Peak memory | 268460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207134754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4207134754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.2330564725 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 19772437723 ps |
| CPU time | 164.12 seconds |
| Started | Oct 15 06:06:22 AM UTC 24 |
| Finished | Oct 15 06:09:09 AM UTC 24 |
| Peak memory | 262608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330564725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.2330564725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.358413338 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 56016247591 ps |
| CPU time | 54.51 seconds |
| Started | Oct 15 06:05:58 AM UTC 24 |
| Finished | Oct 15 06:06:54 AM UTC 24 |
| Peak memory | 246072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358413338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.358413338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_intercept.366903227 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 299083659 ps |
| CPU time | 4.32 seconds |
| Started | Oct 15 06:05:52 AM UTC 24 |
| Finished | Oct 15 06:05:57 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366903227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.366903227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_mailbox.100387065 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 62667710728 ps |
| CPU time | 130.21 seconds |
| Started | Oct 15 06:05:53 AM UTC 24 |
| Finished | Oct 15 06:08:05 AM UTC 24 |
| Peak memory | 251964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100387065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.100387065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.2470223526 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 33843387 ps |
| CPU time | 3.34 seconds |
| Started | Oct 15 06:05:51 AM UTC 24 |
| Finished | Oct 15 06:05:55 AM UTC 24 |
| Peak memory | 245492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470223526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.2470223526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.2260889595 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 298941999 ps |
| CPU time | 3.33 seconds |
| Started | Oct 15 06:05:50 AM UTC 24 |
| Finished | Oct 15 06:05:54 AM UTC 24 |
| Peak memory | 234876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260889595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2260889595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.849919902 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 1316299502 ps |
| CPU time | 20.89 seconds |
| Started | Oct 15 06:05:59 AM UTC 24 |
| Finished | Oct 15 06:06:21 AM UTC 24 |
| Peak memory | 229992 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849919902 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.849919902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.905663092 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 175907111318 ps |
| CPU time | 1181.69 seconds |
| Started | Oct 15 06:06:23 AM UTC 24 |
| Finished | Oct 15 06:26:20 AM UTC 24 |
| Peak memory | 295088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905663092 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.905663092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_all.585606948 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 11924998315 ps |
| CPU time | 37.32 seconds |
| Started | Oct 15 06:05:43 AM UTC 24 |
| Finished | Oct 15 06:06:22 AM UTC 24 |
| Peak memory | 234536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585606948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.585606948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.56965077 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 59221796114 ps |
| CPU time | 15.7 seconds |
| Started | Oct 15 06:05:41 AM UTC 24 |
| Finished | Oct 15 06:05:58 AM UTC 24 |
| Peak memory | 228336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=56965077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.56965077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_rw.1754208410 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 67195782 ps |
| CPU time | 1.79 seconds |
| Started | Oct 15 06:05:47 AM UTC 24 |
| Finished | Oct 15 06:05:50 AM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754208410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1754208410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.1463236721 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 50584010 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 06:05:44 AM UTC 24 |
| Finished | Oct 15 06:05:46 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463236721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1463236721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_upload.2417160081 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 15376278248 ps |
| CPU time | 43.03 seconds |
| Started | Oct 15 06:05:55 AM UTC 24 |
| Finished | Oct 15 06:06:40 AM UTC 24 |
| Peak memory | 246008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417160081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.2417160081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/16.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_alert_test.2291390130 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 14408998 ps |
| CPU time | 1.14 seconds |
| Started | Oct 15 06:06:52 AM UTC 24 |
| Finished | Oct 15 06:06:54 AM UTC 24 |
| Peak memory | 214544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291390130 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.2291390130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_cfg_cmd.1842795171 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 1830206708 ps |
| CPU time | 7.52 seconds |
| Started | Oct 15 06:06:40 AM UTC 24 |
| Finished | Oct 15 06:06:49 AM UTC 24 |
| Peak memory | 235768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842795171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.1842795171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_csb_read.1876345895 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 21386792 ps |
| CPU time | 1.25 seconds |
| Started | Oct 15 06:06:27 AM UTC 24 |
| Finished | Oct 15 06:06:29 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876345895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1876345895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_all.193207772 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 162197411404 ps |
| CPU time | 328.18 seconds |
| Started | Oct 15 06:06:48 AM UTC 24 |
| Finished | Oct 15 06:12:21 AM UTC 24 |
| Peak memory | 262516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193207772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.193207772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.2749265531 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 1462175064 ps |
| CPU time | 5.61 seconds |
| Started | Oct 15 06:06:48 AM UTC 24 |
| Finished | Oct 15 06:06:55 AM UTC 24 |
| Peak memory | 230344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749265531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.2749265531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.3588600753 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 6696747419 ps |
| CPU time | 32.47 seconds |
| Started | Oct 15 06:06:50 AM UTC 24 |
| Finished | Oct 15 06:07:24 AM UTC 24 |
| Peak memory | 235536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588600753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.3588600753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode.1096074291 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 791936236 ps |
| CPU time | 9.38 seconds |
| Started | Oct 15 06:06:41 AM UTC 24 |
| Finished | Oct 15 06:06:51 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096074291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1096074291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.736458938 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 24290152498 ps |
| CPU time | 291.25 seconds |
| Started | Oct 15 06:06:44 AM UTC 24 |
| Finished | Oct 15 06:11:39 AM UTC 24 |
| Peak memory | 274680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736458938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.736458938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_intercept.2506816199 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 214264787 ps |
| CPU time | 3.36 seconds |
| Started | Oct 15 06:06:35 AM UTC 24 |
| Finished | Oct 15 06:06:39 AM UTC 24 |
| Peak memory | 235340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506816199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2506816199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_mailbox.127366241 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 6159943792 ps |
| CPU time | 15.81 seconds |
| Started | Oct 15 06:06:38 AM UTC 24 |
| Finished | Oct 15 06:06:55 AM UTC 24 |
| Peak memory | 245848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127366241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.127366241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.3806114179 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 8356061417 ps |
| CPU time | 6.87 seconds |
| Started | Oct 15 06:06:35 AM UTC 24 |
| Finished | Oct 15 06:06:43 AM UTC 24 |
| Peak memory | 235676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806114179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.3806114179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.1574608230 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 757983509 ps |
| CPU time | 11.58 seconds |
| Started | Oct 15 06:06:34 AM UTC 24 |
| Finished | Oct 15 06:06:47 AM UTC 24 |
| Peak memory | 245948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574608230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.1574608230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.2817235570 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 145120133 ps |
| CPU time | 5.24 seconds |
| Started | Oct 15 06:06:44 AM UTC 24 |
| Finished | Oct 15 06:06:50 AM UTC 24 |
| Peak memory | 234612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817235570 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.2817235570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_stress_all.4223583416 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 89787372 ps |
| CPU time | 1.59 seconds |
| Started | Oct 15 06:06:52 AM UTC 24 |
| Finished | Oct 15 06:06:54 AM UTC 24 |
| Peak memory | 216904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223583416 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.4223583416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_all.256890950 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 14337343 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 06:06:30 AM UTC 24 |
| Finished | Oct 15 06:06:33 AM UTC 24 |
| Peak memory | 216332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256890950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.256890950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.3645179927 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 685415964 ps |
| CPU time | 8.34 seconds |
| Started | Oct 15 06:06:28 AM UTC 24 |
| Finished | Oct 15 06:06:38 AM UTC 24 |
| Peak memory | 228360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645179927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3645179927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_rw.2745933181 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 688180032 ps |
| CPU time | 10.3 seconds |
| Started | Oct 15 06:06:31 AM UTC 24 |
| Finished | Oct 15 06:06:42 AM UTC 24 |
| Peak memory | 228220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745933181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2745933181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.1938476249 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 114102353 ps |
| CPU time | 1.45 seconds |
| Started | Oct 15 06:06:30 AM UTC 24 |
| Finished | Oct 15 06:06:33 AM UTC 24 |
| Peak memory | 216488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938476249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1938476249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/17.spi_device_upload.1481656734 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 604380497 ps |
| CPU time | 5.97 seconds |
| Started | Oct 15 06:06:40 AM UTC 24 |
| Finished | Oct 15 06:06:47 AM UTC 24 |
| Peak memory | 235740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481656734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1481656734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/17.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_alert_test.2749765452 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 53565087 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 06:07:19 AM UTC 24 |
| Finished | Oct 15 06:07:21 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749765452 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.2749765452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_cfg_cmd.898433795 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 4401046261 ps |
| CPU time | 19.21 seconds |
| Started | Oct 15 06:07:05 AM UTC 24 |
| Finished | Oct 15 06:07:26 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898433795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.898433795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_csb_read.3769414899 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 31952211 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 06:06:53 AM UTC 24 |
| Finished | Oct 15 06:06:55 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769414899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3769414899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_all.2427534907 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 1538532769 ps |
| CPU time | 19.31 seconds |
| Started | Oct 15 06:07:11 AM UTC 24 |
| Finished | Oct 15 06:07:32 AM UTC 24 |
| Peak memory | 247716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427534907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2427534907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.1924854622 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 34237336906 ps |
| CPU time | 200.49 seconds |
| Started | Oct 15 06:07:11 AM UTC 24 |
| Finished | Oct 15 06:10:35 AM UTC 24 |
| Peak memory | 268488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1924854622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.1924854622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_flash_mode.922257664 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 1147708899 ps |
| CPU time | 9.99 seconds |
| Started | Oct 15 06:07:06 AM UTC 24 |
| Finished | Oct 15 06:07:18 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922257664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.922257664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_intercept.3371489823 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 179001008 ps |
| CPU time | 6.78 seconds |
| Started | Oct 15 06:07:00 AM UTC 24 |
| Finished | Oct 15 06:07:08 AM UTC 24 |
| Peak memory | 245816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371489823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3371489823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_mailbox.3714998981 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 5253551245 ps |
| CPU time | 20.96 seconds |
| Started | Oct 15 06:07:00 AM UTC 24 |
| Finished | Oct 15 06:07:22 AM UTC 24 |
| Peak memory | 246096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714998981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3714998981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.3481612460 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 625885711 ps |
| CPU time | 10.65 seconds |
| Started | Oct 15 06:06:58 AM UTC 24 |
| Finished | Oct 15 06:07:10 AM UTC 24 |
| Peak memory | 245820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481612460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.3481612460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.2999657563 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 623905148 ps |
| CPU time | 6.84 seconds |
| Started | Oct 15 06:06:57 AM UTC 24 |
| Finished | Oct 15 06:07:04 AM UTC 24 |
| Peak memory | 235636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2999657563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.2999657563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.1197387626 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 437827016 ps |
| CPU time | 5.45 seconds |
| Started | Oct 15 06:07:11 AM UTC 24 |
| Finished | Oct 15 06:07:17 AM UTC 24 |
| Peak memory | 232060 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197387626 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.1197387626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_stress_all.3950400675 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 44878160851 ps |
| CPU time | 388.84 seconds |
| Started | Oct 15 06:07:18 AM UTC 24 |
| Finished | Oct 15 06:13:53 AM UTC 24 |
| Peak memory | 268456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950400675 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.3950400675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_all.1888187802 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 4134676152 ps |
| CPU time | 29.6 seconds |
| Started | Oct 15 06:06:55 AM UTC 24 |
| Finished | Oct 15 06:07:26 AM UTC 24 |
| Peak memory | 228560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888187802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1888187802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.3212664752 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 6678022242 ps |
| CPU time | 13.25 seconds |
| Started | Oct 15 06:06:55 AM UTC 24 |
| Finished | Oct 15 06:07:10 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212664752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.3212664752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_rw.1302459701 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 333086802 ps |
| CPU time | 5.15 seconds |
| Started | Oct 15 06:06:57 AM UTC 24 |
| Finished | Oct 15 06:07:03 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302459701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1302459701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.3110439657 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 278273393 ps |
| CPU time | 1.53 seconds |
| Started | Oct 15 06:06:56 AM UTC 24 |
| Finished | Oct 15 06:06:59 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110439657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3110439657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/18.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_alert_test.1734962602 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 120881038 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 06:07:38 AM UTC 24 |
| Finished | Oct 15 06:07:40 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734962602 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.1734962602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_cfg_cmd.251058070 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 51803374 ps |
| CPU time | 2.82 seconds |
| Started | Oct 15 06:07:30 AM UTC 24 |
| Finished | Oct 15 06:07:34 AM UTC 24 |
| Peak memory | 235776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251058070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.251058070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_csb_read.3171646164 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 17455861 ps |
| CPU time | 1.2 seconds |
| Started | Oct 15 06:07:20 AM UTC 24 |
| Finished | Oct 15 06:07:22 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171646164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3171646164 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_all.1081342874 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 132628939059 ps |
| CPU time | 114.82 seconds |
| Started | Oct 15 06:07:34 AM UTC 24 |
| Finished | Oct 15 06:09:31 AM UTC 24 |
| Peak memory | 266360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081342874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1081342874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode.2445484929 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 13571044312 ps |
| CPU time | 32.6 seconds |
| Started | Oct 15 06:07:32 AM UTC 24 |
| Finished | Oct 15 06:08:06 AM UTC 24 |
| Peak memory | 235636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445484929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.2445484929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.4052519505 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 31799879939 ps |
| CPU time | 114.92 seconds |
| Started | Oct 15 06:07:33 AM UTC 24 |
| Finished | Oct 15 06:09:30 AM UTC 24 |
| Peak memory | 262264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052519505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.4052519505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_intercept.2038025133 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 106911079 ps |
| CPU time | 3.46 seconds |
| Started | Oct 15 06:07:27 AM UTC 24 |
| Finished | Oct 15 06:07:31 AM UTC 24 |
| Peak memory | 245976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2038025133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2038025133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_mailbox.2240468958 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 4679203928 ps |
| CPU time | 18.48 seconds |
| Started | Oct 15 06:07:27 AM UTC 24 |
| Finished | Oct 15 06:07:47 AM UTC 24 |
| Peak memory | 246012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240468958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2240468958 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.3837264713 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 2383148042 ps |
| CPU time | 15.08 seconds |
| Started | Oct 15 06:07:27 AM UTC 24 |
| Finished | Oct 15 06:07:43 AM UTC 24 |
| Peak memory | 235584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837264713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.3837264713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.422922332 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 628302953 ps |
| CPU time | 5.68 seconds |
| Started | Oct 15 06:07:26 AM UTC 24 |
| Finished | Oct 15 06:07:32 AM UTC 24 |
| Peak memory | 245800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422922332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.422922332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.2898768036 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 1537488830 ps |
| CPU time | 13.7 seconds |
| Started | Oct 15 06:07:34 AM UTC 24 |
| Finished | Oct 15 06:07:49 AM UTC 24 |
| Peak memory | 234248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2898768036 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.2898768036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_stress_all.45103945 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2305717868 ps |
| CPU time | 17.75 seconds |
| Started | Oct 15 06:07:35 AM UTC 24 |
| Finished | Oct 15 06:07:54 AM UTC 24 |
| Peak memory | 235844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45103945 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.45103945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_all.3581518185 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 3177534026 ps |
| CPU time | 28.75 seconds |
| Started | Oct 15 06:07:23 AM UTC 24 |
| Finished | Oct 15 06:07:53 AM UTC 24 |
| Peak memory | 228336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581518185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.3581518185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.2866322285 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 1852032273 ps |
| CPU time | 8.54 seconds |
| Started | Oct 15 06:07:23 AM UTC 24 |
| Finished | Oct 15 06:07:33 AM UTC 24 |
| Peak memory | 228260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866322285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.2866322285 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_rw.930031668 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2837025115 ps |
| CPU time | 3.85 seconds |
| Started | Oct 15 06:07:24 AM UTC 24 |
| Finished | Oct 15 06:07:29 AM UTC 24 |
| Peak memory | 228396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930031668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.930031668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.949052006 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 179016285 ps |
| CPU time | 1.55 seconds |
| Started | Oct 15 06:07:23 AM UTC 24 |
| Finished | Oct 15 06:07:26 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949052006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.949052006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/19.spi_device_upload.3794045623 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 55895400 ps |
| CPU time | 3.49 seconds |
| Started | Oct 15 06:07:29 AM UTC 24 |
| Finished | Oct 15 06:07:34 AM UTC 24 |
| Peak memory | 245748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794045623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3794045623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/19.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_alert_test.1798756643 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 76503591 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 05:58:14 AM UTC 24 |
| Finished | Oct 15 05:58:16 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798756643 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1798756643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_cfg_cmd.1061955641 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 735578364 ps |
| CPU time | 3.65 seconds |
| Started | Oct 15 05:57:53 AM UTC 24 |
| Finished | Oct 15 05:57:58 AM UTC 24 |
| Peak memory | 235640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061955641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1061955641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_csb_read.1362462051 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 15096698 ps |
| CPU time | 1.25 seconds |
| Started | Oct 15 05:57:41 AM UTC 24 |
| Finished | Oct 15 05:57:43 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362462051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1362462051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.1690147335 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 12831014262 ps |
| CPU time | 71.2 seconds |
| Started | Oct 15 05:58:02 AM UTC 24 |
| Finished | Oct 15 05:59:15 AM UTC 24 |
| Peak memory | 245860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690147335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1690147335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_flash_mode.688806804 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 119090715 ps |
| CPU time | 4.31 seconds |
| Started | Oct 15 05:57:56 AM UTC 24 |
| Finished | Oct 15 05:58:01 AM UTC 24 |
| Peak memory | 245836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688806804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.688806804 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_intercept.551401127 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2885273667 ps |
| CPU time | 22.84 seconds |
| Started | Oct 15 05:57:49 AM UTC 24 |
| Finished | Oct 15 05:58:13 AM UTC 24 |
| Peak memory | 235776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551401127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.551401127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_mailbox.3478489351 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 6316689968 ps |
| CPU time | 12.54 seconds |
| Started | Oct 15 05:57:52 AM UTC 24 |
| Finished | Oct 15 05:58:06 AM UTC 24 |
| Peak memory | 235580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478489351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3478489351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.1629265217 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 5462700777 ps |
| CPU time | 18.09 seconds |
| Started | Oct 15 05:57:48 AM UTC 24 |
| Finished | Oct 15 05:58:07 AM UTC 24 |
| Peak memory | 250164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629265217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.1629265217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.2510572328 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 287818674 ps |
| CPU time | 6.08 seconds |
| Started | Oct 15 05:57:48 AM UTC 24 |
| Finished | Oct 15 05:57:55 AM UTC 24 |
| Peak memory | 235704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510572328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2510572328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.2879964779 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 589114811 ps |
| CPU time | 12.95 seconds |
| Started | Oct 15 05:58:01 AM UTC 24 |
| Finished | Oct 15 05:58:15 AM UTC 24 |
| Peak memory | 232072 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879964779 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.2879964779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_sec_cm.915868220 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 132690100 ps |
| CPU time | 1.6 seconds |
| Started | Oct 15 05:58:11 AM UTC 24 |
| Finished | Oct 15 05:58:13 AM UTC 24 |
| Peak memory | 257760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915868220 -assert nopostproc +UVM_TESTN AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.915868220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_stress_all.2931181360 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 116557286085 ps |
| CPU time | 275.59 seconds |
| Started | Oct 15 05:58:08 AM UTC 24 |
| Finished | Oct 15 06:02:47 AM UTC 24 |
| Peak memory | 268448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931181360 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.2931181360 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_all.3509325458 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 3231776337 ps |
| CPU time | 16.87 seconds |
| Started | Oct 15 05:57:43 AM UTC 24 |
| Finished | Oct 15 05:58:02 AM UTC 24 |
| Peak memory | 232596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509325458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3509325458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.2791673246 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 3120123950 ps |
| CPU time | 7.14 seconds |
| Started | Oct 15 05:57:42 AM UTC 24 |
| Finished | Oct 15 05:57:51 AM UTC 24 |
| Peak memory | 230296 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791673246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2791673246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_rw.3122870702 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 155918199 ps |
| CPU time | 1.82 seconds |
| Started | Oct 15 05:57:46 AM UTC 24 |
| Finished | Oct 15 05:57:48 AM UTC 24 |
| Peak memory | 217096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122870702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3122870702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.2767388003 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 39988538 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 05:57:44 AM UTC 24 |
| Finished | Oct 15 05:57:47 AM UTC 24 |
| Peak memory | 217128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767388003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2767388003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/2.spi_device_upload.152993352 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3251979000 ps |
| CPU time | 6.56 seconds |
| Started | Oct 15 05:57:53 AM UTC 24 |
| Finished | Oct 15 05:58:01 AM UTC 24 |
| Peak memory | 246096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152993352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.152993352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/2.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_alert_test.958095672 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 128031304 ps |
| CPU time | 1.16 seconds |
| Started | Oct 15 06:08:06 AM UTC 24 |
| Finished | Oct 15 06:08:09 AM UTC 24 |
| Peak memory | 216708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958095672 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.958095672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_cfg_cmd.3516579726 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 1906873884 ps |
| CPU time | 10.1 seconds |
| Started | Oct 15 06:07:54 AM UTC 24 |
| Finished | Oct 15 06:08:05 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516579726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3516579726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_csb_read.2395644453 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 16263640 ps |
| CPU time | 1.2 seconds |
| Started | Oct 15 06:07:38 AM UTC 24 |
| Finished | Oct 15 06:07:40 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395644453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2395644453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_all.2096267341 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 49870508044 ps |
| CPU time | 185.77 seconds |
| Started | Oct 15 06:07:59 AM UTC 24 |
| Finished | Oct 15 06:11:07 AM UTC 24 |
| Peak memory | 262248 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096267341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.2096267341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.2393836607 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 121754269076 ps |
| CPU time | 739.49 seconds |
| Started | Oct 15 06:07:59 AM UTC 24 |
| Finished | Oct 15 06:20:28 AM UTC 24 |
| Peak memory | 268716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393836607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2393836607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.908029882 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 5257160512 ps |
| CPU time | 36.08 seconds |
| Started | Oct 15 06:08:02 AM UTC 24 |
| Finished | Oct 15 06:08:40 AM UTC 24 |
| Peak memory | 235764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908029882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.908029882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode.958583790 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 155501061 ps |
| CPU time | 10.55 seconds |
| Started | Oct 15 06:07:55 AM UTC 24 |
| Finished | Oct 15 06:08:07 AM UTC 24 |
| Peak memory | 245808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958583790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.958583790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.3589421031 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 109166461432 ps |
| CPU time | 404.33 seconds |
| Started | Oct 15 06:07:55 AM UTC 24 |
| Finished | Oct 15 06:14:45 AM UTC 24 |
| Peak memory | 264504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589421031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.3589421031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_intercept.832027363 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 3349498426 ps |
| CPU time | 11.28 seconds |
| Started | Oct 15 06:07:49 AM UTC 24 |
| Finished | Oct 15 06:08:01 AM UTC 24 |
| Peak memory | 246084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=832027363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.832027363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_mailbox.3591228206 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3253501176 ps |
| CPU time | 23.68 seconds |
| Started | Oct 15 06:07:50 AM UTC 24 |
| Finished | Oct 15 06:08:15 AM UTC 24 |
| Peak memory | 235664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591228206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3591228206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.1043534186 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 27201383026 ps |
| CPU time | 23.72 seconds |
| Started | Oct 15 06:07:49 AM UTC 24 |
| Finished | Oct 15 06:08:14 AM UTC 24 |
| Peak memory | 250164 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043534186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.1043534186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.820026618 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1492429475 ps |
| CPU time | 21.13 seconds |
| Started | Oct 15 06:07:47 AM UTC 24 |
| Finished | Oct 15 06:08:10 AM UTC 24 |
| Peak memory | 251976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820026618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.820026618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.4183634488 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 506227440 ps |
| CPU time | 10.12 seconds |
| Started | Oct 15 06:07:59 AM UTC 24 |
| Finished | Oct 15 06:08:10 AM UTC 24 |
| Peak memory | 234184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183634488 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.4183634488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_all.1568954094 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1320817075 ps |
| CPU time | 15.23 seconds |
| Started | Oct 15 06:07:41 AM UTC 24 |
| Finished | Oct 15 06:07:57 AM UTC 24 |
| Peak memory | 228272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568954094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.1568954094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.3671854158 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 8806435020 ps |
| CPU time | 12.24 seconds |
| Started | Oct 15 06:07:41 AM UTC 24 |
| Finished | Oct 15 06:07:54 AM UTC 24 |
| Peak memory | 227080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3671854158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3671854158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_rw.1940985010 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 65045393 ps |
| CPU time | 1.33 seconds |
| Started | Oct 15 06:07:47 AM UTC 24 |
| Finished | Oct 15 06:07:50 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940985010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1940985010 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.3390337395 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 494127392 ps |
| CPU time | 1.4 seconds |
| Started | Oct 15 06:07:44 AM UTC 24 |
| Finished | Oct 15 06:07:47 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390337395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3390337395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_upload.2360934927 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 950362771 ps |
| CPU time | 5.34 seconds |
| Started | Oct 15 06:07:51 AM UTC 24 |
| Finished | Oct 15 06:07:57 AM UTC 24 |
| Peak memory | 246000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360934927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2360934927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/20.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_alert_test.2709292715 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 43880400 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 06:08:32 AM UTC 24 |
| Finished | Oct 15 06:08:34 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709292715 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.2709292715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_cfg_cmd.2667758581 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 858222440 ps |
| CPU time | 9.14 seconds |
| Started | Oct 15 06:08:16 AM UTC 24 |
| Finished | Oct 15 06:08:26 AM UTC 24 |
| Peak memory | 245776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2667758581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2667758581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_csb_read.3397728789 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 69706407 ps |
| CPU time | 1.24 seconds |
| Started | Oct 15 06:08:08 AM UTC 24 |
| Finished | Oct 15 06:08:10 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397728789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.3397728789 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.4163859660 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 320983120840 ps |
| CPU time | 600.21 seconds |
| Started | Oct 15 06:08:22 AM UTC 24 |
| Finished | Oct 15 06:18:29 AM UTC 24 |
| Peak memory | 284820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163859660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.4163859660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.2103613359 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 43044106225 ps |
| CPU time | 248.38 seconds |
| Started | Oct 15 06:08:27 AM UTC 24 |
| Finished | Oct 15 06:12:39 AM UTC 24 |
| Peak memory | 266636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2103613359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.2103613359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode.3131423440 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 319043366 ps |
| CPU time | 8.78 seconds |
| Started | Oct 15 06:08:16 AM UTC 24 |
| Finished | Oct 15 06:08:26 AM UTC 24 |
| Peak memory | 245832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131423440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3131423440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.3887318942 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 49719033096 ps |
| CPU time | 485.51 seconds |
| Started | Oct 15 06:08:17 AM UTC 24 |
| Finished | Oct 15 06:16:29 AM UTC 24 |
| Peak memory | 268592 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887318942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.3887318942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_intercept.1602592471 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 9444045939 ps |
| CPU time | 18.1 seconds |
| Started | Oct 15 06:08:15 AM UTC 24 |
| Finished | Oct 15 06:08:34 AM UTC 24 |
| Peak memory | 246104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602592471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1602592471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_mailbox.1893619044 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 542698506 ps |
| CPU time | 14.2 seconds |
| Started | Oct 15 06:08:15 AM UTC 24 |
| Finished | Oct 15 06:08:30 AM UTC 24 |
| Peak memory | 262388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893619044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1893619044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.954925409 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 32449136 ps |
| CPU time | 3.08 seconds |
| Started | Oct 15 06:08:12 AM UTC 24 |
| Finished | Oct 15 06:08:17 AM UTC 24 |
| Peak memory | 245452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954925409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.954925409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.1925320626 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 74812383 ps |
| CPU time | 2.94 seconds |
| Started | Oct 15 06:08:11 AM UTC 24 |
| Finished | Oct 15 06:08:15 AM UTC 24 |
| Peak memory | 246012 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925320626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.1925320626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.4046858365 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 3125940826 ps |
| CPU time | 11.35 seconds |
| Started | Oct 15 06:08:18 AM UTC 24 |
| Finished | Oct 15 06:08:31 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046858365 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.4046858365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_stress_all.184437994 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 42982327400 ps |
| CPU time | 137.58 seconds |
| Started | Oct 15 06:08:29 AM UTC 24 |
| Finished | Oct 15 06:10:49 AM UTC 24 |
| Peak memory | 262352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184437994 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.184437994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_all.2526418034 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1372591722 ps |
| CPU time | 21 seconds |
| Started | Oct 15 06:08:10 AM UTC 24 |
| Finished | Oct 15 06:08:32 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526418034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2526418034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.262430386 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 1252506647 ps |
| CPU time | 8.6 seconds |
| Started | Oct 15 06:08:08 AM UTC 24 |
| Finished | Oct 15 06:08:18 AM UTC 24 |
| Peak memory | 228336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262430386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.262430386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_rw.4007040442 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 132019968 ps |
| CPU time | 1.62 seconds |
| Started | Oct 15 06:08:11 AM UTC 24 |
| Finished | Oct 15 06:08:14 AM UTC 24 |
| Peak memory | 216472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007040442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.4007040442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.981558728 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 27570155 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 06:08:11 AM UTC 24 |
| Finished | Oct 15 06:08:13 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981558728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.981558728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_upload.2493564864 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 784038440 ps |
| CPU time | 4.33 seconds |
| Started | Oct 15 06:08:15 AM UTC 24 |
| Finished | Oct 15 06:08:20 AM UTC 24 |
| Peak memory | 245748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493564864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2493564864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/21.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_alert_test.1415595038 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 79321307 ps |
| CPU time | 1.16 seconds |
| Started | Oct 15 06:09:11 AM UTC 24 |
| Finished | Oct 15 06:09:13 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415595038 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.1415595038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_cfg_cmd.2353658211 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 168009205 ps |
| CPU time | 3.9 seconds |
| Started | Oct 15 06:08:43 AM UTC 24 |
| Finished | Oct 15 06:08:48 AM UTC 24 |
| Peak memory | 235516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353658211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2353658211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_csb_read.1092133848 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 52075949 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 06:08:32 AM UTC 24 |
| Finished | Oct 15 06:08:34 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092133848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1092133848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_all.1867612446 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 60864411469 ps |
| CPU time | 219.6 seconds |
| Started | Oct 15 06:08:54 AM UTC 24 |
| Finished | Oct 15 06:12:37 AM UTC 24 |
| Peak memory | 262256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867612446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1867612446 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.1387616891 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 42217667399 ps |
| CPU time | 179.47 seconds |
| Started | Oct 15 06:08:58 AM UTC 24 |
| Finished | Oct 15 06:12:01 AM UTC 24 |
| Peak memory | 268720 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387616891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.1387616891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.2545784562 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 14363142230 ps |
| CPU time | 91.11 seconds |
| Started | Oct 15 06:08:59 AM UTC 24 |
| Finished | Oct 15 06:10:32 AM UTC 24 |
| Peak memory | 266432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545784562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.2545784562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode.2638739703 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 967996653 ps |
| CPU time | 9.19 seconds |
| Started | Oct 15 06:08:47 AM UTC 24 |
| Finished | Oct 15 06:08:58 AM UTC 24 |
| Peak memory | 251984 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638739703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2638739703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.981797277 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 111795697371 ps |
| CPU time | 326.34 seconds |
| Started | Oct 15 06:08:49 AM UTC 24 |
| Finished | Oct 15 06:14:20 AM UTC 24 |
| Peak memory | 268436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=981797277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.981797277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_intercept.2197468081 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 74472490 ps |
| CPU time | 3.49 seconds |
| Started | Oct 15 06:08:38 AM UTC 24 |
| Finished | Oct 15 06:08:42 AM UTC 24 |
| Peak memory | 246040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2197468081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2197468081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_mailbox.1258538057 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 4352813802 ps |
| CPU time | 15.79 seconds |
| Started | Oct 15 06:08:41 AM UTC 24 |
| Finished | Oct 15 06:08:58 AM UTC 24 |
| Peak memory | 245064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258538057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1258538057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.1680079279 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 14810306040 ps |
| CPU time | 40.88 seconds |
| Started | Oct 15 06:08:38 AM UTC 24 |
| Finished | Oct 15 06:09:20 AM UTC 24 |
| Peak memory | 245824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680079279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.1680079279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.1731800620 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 32565397 ps |
| CPU time | 3.1 seconds |
| Started | Oct 15 06:08:35 AM UTC 24 |
| Finished | Oct 15 06:08:40 AM UTC 24 |
| Peak memory | 245488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731800620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1731800620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.429090478 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2356143170 ps |
| CPU time | 14.76 seconds |
| Started | Oct 15 06:08:51 AM UTC 24 |
| Finished | Oct 15 06:09:07 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429090478 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.429090478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_stress_all.3886033028 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 5432875729 ps |
| CPU time | 158.6 seconds |
| Started | Oct 15 06:09:07 AM UTC 24 |
| Finished | Oct 15 06:11:49 AM UTC 24 |
| Peak memory | 278732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886033028 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.3886033028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_all.1701873272 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 2766147970 ps |
| CPU time | 19.1 seconds |
| Started | Oct 15 06:08:33 AM UTC 24 |
| Finished | Oct 15 06:08:53 AM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701873272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.1701873272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.1091986421 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 4625621135 ps |
| CPU time | 16.03 seconds |
| Started | Oct 15 06:08:33 AM UTC 24 |
| Finished | Oct 15 06:08:50 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091986421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1091986421 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_rw.140253422 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 45661656 ps |
| CPU time | 1.47 seconds |
| Started | Oct 15 06:08:34 AM UTC 24 |
| Finished | Oct 15 06:08:37 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140253422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.140253422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.2703256054 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 79792984 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 06:08:34 AM UTC 24 |
| Finished | Oct 15 06:08:36 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703256054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2703256054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/22.spi_device_upload.3086045203 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 166129869 ps |
| CPU time | 4.8 seconds |
| Started | Oct 15 06:08:41 AM UTC 24 |
| Finished | Oct 15 06:08:47 AM UTC 24 |
| Peak memory | 245780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3086045203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3086045203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/22.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_alert_test.4291482616 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 22308548 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 06:09:51 AM UTC 24 |
| Finished | Oct 15 06:09:53 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291482616 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.4291482616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_cfg_cmd.367834086 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 4060716963 ps |
| CPU time | 9.49 seconds |
| Started | Oct 15 06:09:32 AM UTC 24 |
| Finished | Oct 15 06:09:42 AM UTC 24 |
| Peak memory | 246104 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367834086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.367834086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_csb_read.2460698401 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 21885723 ps |
| CPU time | 1.25 seconds |
| Started | Oct 15 06:09:14 AM UTC 24 |
| Finished | Oct 15 06:09:16 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460698401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2460698401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_all.3557608253 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 13283458 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 06:09:43 AM UTC 24 |
| Finished | Oct 15 06:09:46 AM UTC 24 |
| Peak memory | 226264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557608253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.3557608253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.1420919576 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 9636512094 ps |
| CPU time | 46.23 seconds |
| Started | Oct 15 06:09:44 AM UTC 24 |
| Finished | Oct 15 06:10:33 AM UTC 24 |
| Peak memory | 262352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420919576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1420919576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.4068654858 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 1039131754 ps |
| CPU time | 5.37 seconds |
| Started | Oct 15 06:09:48 AM UTC 24 |
| Finished | Oct 15 06:09:54 AM UTC 24 |
| Peak memory | 230436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4068654858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.4068654858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode.897271026 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 852971136 ps |
| CPU time | 19.42 seconds |
| Started | Oct 15 06:09:38 AM UTC 24 |
| Finished | Oct 15 06:09:59 AM UTC 24 |
| Peak memory | 235568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897271026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.897271026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.1859790156 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 396083425383 ps |
| CPU time | 239.52 seconds |
| Started | Oct 15 06:09:41 AM UTC 24 |
| Finished | Oct 15 06:13:44 AM UTC 24 |
| Peak memory | 268408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859790156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.1859790156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_intercept.2259527452 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 15415244819 ps |
| CPU time | 42.46 seconds |
| Started | Oct 15 06:09:28 AM UTC 24 |
| Finished | Oct 15 06:10:12 AM UTC 24 |
| Peak memory | 245900 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259527452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2259527452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_mailbox.2135783821 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 131474430271 ps |
| CPU time | 78.33 seconds |
| Started | Oct 15 06:09:29 AM UTC 24 |
| Finished | Oct 15 06:10:50 AM UTC 24 |
| Peak memory | 249972 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135783821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2135783821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.1256870609 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 1905938415 ps |
| CPU time | 21.66 seconds |
| Started | Oct 15 06:09:27 AM UTC 24 |
| Finished | Oct 15 06:09:50 AM UTC 24 |
| Peak memory | 252116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1256870609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.1256870609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.2967057971 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 2507604824 ps |
| CPU time | 10.91 seconds |
| Started | Oct 15 06:09:25 AM UTC 24 |
| Finished | Oct 15 06:09:37 AM UTC 24 |
| Peak memory | 245880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967057971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.2967057971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2725888786 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 2230027598 ps |
| CPU time | 21.08 seconds |
| Started | Oct 15 06:09:41 AM UTC 24 |
| Finished | Oct 15 06:10:04 AM UTC 24 |
| Peak memory | 232132 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725888786 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.2725888786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_stress_all.2807360500 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 271650282 ps |
| CPU time | 1.7 seconds |
| Started | Oct 15 06:09:50 AM UTC 24 |
| Finished | Oct 15 06:09:52 AM UTC 24 |
| Peak memory | 216672 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807360500 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.2807360500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_all.3887833274 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 12660861047 ps |
| CPU time | 24.81 seconds |
| Started | Oct 15 06:09:17 AM UTC 24 |
| Finished | Oct 15 06:09:43 AM UTC 24 |
| Peak memory | 232596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887833274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.3887833274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.1224705172 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 389851818 ps |
| CPU time | 4.41 seconds |
| Started | Oct 15 06:09:15 AM UTC 24 |
| Finished | Oct 15 06:09:20 AM UTC 24 |
| Peak memory | 228176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224705172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1224705172 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_rw.2690349974 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 75752735 ps |
| CPU time | 3.11 seconds |
| Started | Oct 15 06:09:21 AM UTC 24 |
| Finished | Oct 15 06:09:26 AM UTC 24 |
| Peak memory | 228272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690349974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.2690349974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.3960473647 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 1470797244 ps |
| CPU time | 1.48 seconds |
| Started | Oct 15 06:09:21 AM UTC 24 |
| Finished | Oct 15 06:09:24 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960473647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3960473647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/23.spi_device_upload.934918190 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 7551709088 ps |
| CPU time | 32.11 seconds |
| Started | Oct 15 06:09:30 AM UTC 24 |
| Finished | Oct 15 06:10:04 AM UTC 24 |
| Peak memory | 235632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934918190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.934918190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/23.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_alert_test.2435550897 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 12665861 ps |
| CPU time | 1.01 seconds |
| Started | Oct 15 06:10:13 AM UTC 24 |
| Finished | Oct 15 06:10:15 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435550897 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.2435550897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_cfg_cmd.3228108078 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 694119920 ps |
| CPU time | 6.55 seconds |
| Started | Oct 15 06:10:05 AM UTC 24 |
| Finished | Oct 15 06:10:13 AM UTC 24 |
| Peak memory | 245912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228108078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.3228108078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_csb_read.2224596256 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 18082898 ps |
| CPU time | 1.22 seconds |
| Started | Oct 15 06:09:52 AM UTC 24 |
| Finished | Oct 15 06:09:54 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224596256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2224596256 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.1654339646 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 740893174909 ps |
| CPU time | 477.53 seconds |
| Started | Oct 15 06:10:09 AM UTC 24 |
| Finished | Oct 15 06:18:13 AM UTC 24 |
| Peak memory | 268428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654339646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1654339646 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.2025195074 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 18316396885 ps |
| CPU time | 154.26 seconds |
| Started | Oct 15 06:10:11 AM UTC 24 |
| Finished | Oct 15 06:12:47 AM UTC 24 |
| Peak memory | 249944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025195074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2025195074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode.1181190159 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 2636724329 ps |
| CPU time | 44.18 seconds |
| Started | Oct 15 06:10:05 AM UTC 24 |
| Finished | Oct 15 06:10:51 AM UTC 24 |
| Peak memory | 252052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181190159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1181190159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.1793000786 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 25922481149 ps |
| CPU time | 222.44 seconds |
| Started | Oct 15 06:10:05 AM UTC 24 |
| Finished | Oct 15 06:13:51 AM UTC 24 |
| Peak memory | 276624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793000786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.1793000786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_intercept.64935240 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 139053216 ps |
| CPU time | 2.84 seconds |
| Started | Oct 15 06:10:00 AM UTC 24 |
| Finished | Oct 15 06:10:04 AM UTC 24 |
| Peak memory | 229980 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64935240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.64935240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_mailbox.627362023 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 6374269019 ps |
| CPU time | 46.06 seconds |
| Started | Oct 15 06:10:02 AM UTC 24 |
| Finished | Oct 15 06:10:50 AM UTC 24 |
| Peak memory | 245908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=627362023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.627362023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.285664600 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 31784324 ps |
| CPU time | 2.24 seconds |
| Started | Oct 15 06:09:59 AM UTC 24 |
| Finished | Oct 15 06:10:03 AM UTC 24 |
| Peak memory | 245524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285664600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.285664600 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.1479938641 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 2426346070 ps |
| CPU time | 13.27 seconds |
| Started | Oct 15 06:09:56 AM UTC 24 |
| Finished | Oct 15 06:10:10 AM UTC 24 |
| Peak memory | 234800 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1479938641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.1479938641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.2285068006 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 6564696592 ps |
| CPU time | 16.7 seconds |
| Started | Oct 15 06:10:05 AM UTC 24 |
| Finished | Oct 15 06:10:23 AM UTC 24 |
| Peak memory | 234268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285068006 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.2285068006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_stress_all.4107317559 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 170710928 ps |
| CPU time | 1.46 seconds |
| Started | Oct 15 06:10:13 AM UTC 24 |
| Finished | Oct 15 06:10:15 AM UTC 24 |
| Peak memory | 216792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107317559 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.4107317559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_all.1888464991 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 1446201380 ps |
| CPU time | 24.76 seconds |
| Started | Oct 15 06:09:54 AM UTC 24 |
| Finished | Oct 15 06:10:21 AM UTC 24 |
| Peak memory | 232336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888464991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.1888464991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.3601965664 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 7323713135 ps |
| CPU time | 22.08 seconds |
| Started | Oct 15 06:09:53 AM UTC 24 |
| Finished | Oct 15 06:10:17 AM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601965664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3601965664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_rw.2506208160 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 92926472 ps |
| CPU time | 3.94 seconds |
| Started | Oct 15 06:09:56 AM UTC 24 |
| Finished | Oct 15 06:10:01 AM UTC 24 |
| Peak memory | 227388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506208160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2506208160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.90720283 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 240633357 ps |
| CPU time | 1.46 seconds |
| Started | Oct 15 06:09:56 AM UTC 24 |
| Finished | Oct 15 06:09:58 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90720283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.90720283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_upload.2365858244 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 136767064 ps |
| CPU time | 3.31 seconds |
| Started | Oct 15 06:10:03 AM UTC 24 |
| Finished | Oct 15 06:10:08 AM UTC 24 |
| Peak memory | 235408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365858244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2365858244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/24.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_alert_test.295730803 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 41757847 ps |
| CPU time | 1.07 seconds |
| Started | Oct 15 06:10:42 AM UTC 24 |
| Finished | Oct 15 06:10:44 AM UTC 24 |
| Peak memory | 214664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295730803 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.295730803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_cfg_cmd.2388875145 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 5559399284 ps |
| CPU time | 17.9 seconds |
| Started | Oct 15 06:10:27 AM UTC 24 |
| Finished | Oct 15 06:10:46 AM UTC 24 |
| Peak memory | 245904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388875145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.2388875145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_csb_read.1601526925 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 17840604 ps |
| CPU time | 1.25 seconds |
| Started | Oct 15 06:10:14 AM UTC 24 |
| Finished | Oct 15 06:10:16 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601526925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1601526925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_all.1080390547 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 75412685029 ps |
| CPU time | 134.72 seconds |
| Started | Oct 15 06:10:34 AM UTC 24 |
| Finished | Oct 15 06:12:51 AM UTC 24 |
| Peak memory | 262284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080390547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1080390547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.1811799147 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 7175210532 ps |
| CPU time | 58.74 seconds |
| Started | Oct 15 06:10:34 AM UTC 24 |
| Finished | Oct 15 06:11:34 AM UTC 24 |
| Peak memory | 268444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811799147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1811799147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.2364978775 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 19297902858 ps |
| CPU time | 221.61 seconds |
| Started | Oct 15 06:10:34 AM UTC 24 |
| Finished | Oct 15 06:14:19 AM UTC 24 |
| Peak memory | 262516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364978775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.2364978775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode.3048451137 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 574943913 ps |
| CPU time | 4.47 seconds |
| Started | Oct 15 06:10:27 AM UTC 24 |
| Finished | Oct 15 06:10:33 AM UTC 24 |
| Peak memory | 235768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048451137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3048451137 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.2601984258 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 292140318 ps |
| CPU time | 12 seconds |
| Started | Oct 15 06:10:32 AM UTC 24 |
| Finished | Oct 15 06:10:45 AM UTC 24 |
| Peak memory | 235768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601984258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.2601984258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_intercept.1044627752 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 2925406008 ps |
| CPU time | 36.06 seconds |
| Started | Oct 15 06:10:21 AM UTC 24 |
| Finished | Oct 15 06:10:59 AM UTC 24 |
| Peak memory | 245880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1044627752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1044627752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_mailbox.2753452563 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 1987924568 ps |
| CPU time | 31.55 seconds |
| Started | Oct 15 06:10:23 AM UTC 24 |
| Finished | Oct 15 06:10:56 AM UTC 24 |
| Peak memory | 262200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753452563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2753452563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.3936766831 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 223983913 ps |
| CPU time | 4.07 seconds |
| Started | Oct 15 06:10:21 AM UTC 24 |
| Finished | Oct 15 06:10:27 AM UTC 24 |
| Peak memory | 235712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936766831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.3936766831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.4161813276 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 998591809 ps |
| CPU time | 13.36 seconds |
| Started | Oct 15 06:10:18 AM UTC 24 |
| Finished | Oct 15 06:10:33 AM UTC 24 |
| Peak memory | 252116 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161813276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.4161813276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.341709340 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1095067809 ps |
| CPU time | 18.99 seconds |
| Started | Oct 15 06:10:34 AM UTC 24 |
| Finished | Oct 15 06:10:54 AM UTC 24 |
| Peak memory | 234220 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341709340 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.341709340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_stress_all.1212383067 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 19916815800 ps |
| CPU time | 256.9 seconds |
| Started | Oct 15 06:10:35 AM UTC 24 |
| Finished | Oct 15 06:14:56 AM UTC 24 |
| Peak memory | 284828 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1212383067 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.1212383067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_all.536382938 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 3360632269 ps |
| CPU time | 31.7 seconds |
| Started | Oct 15 06:10:17 AM UTC 24 |
| Finished | Oct 15 06:10:50 AM UTC 24 |
| Peak memory | 228396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536382938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.536382938 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.3048701898 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 2002515809 ps |
| CPU time | 8.79 seconds |
| Started | Oct 15 06:10:17 AM UTC 24 |
| Finished | Oct 15 06:10:26 AM UTC 24 |
| Peak memory | 228140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048701898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3048701898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_rw.3781485676 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 348482000 ps |
| CPU time | 2.52 seconds |
| Started | Oct 15 06:10:18 AM UTC 24 |
| Finished | Oct 15 06:10:22 AM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781485676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3781485676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.90191774 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 20064258 ps |
| CPU time | 1.2 seconds |
| Started | Oct 15 06:10:18 AM UTC 24 |
| Finished | Oct 15 06:10:20 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90191774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.90191774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/25.spi_device_upload.3161406033 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 223283138 ps |
| CPU time | 6.35 seconds |
| Started | Oct 15 06:10:24 AM UTC 24 |
| Finished | Oct 15 06:10:31 AM UTC 24 |
| Peak memory | 245748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161406033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3161406033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/25.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_alert_test.3770405873 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 41873130 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 06:11:00 AM UTC 24 |
| Finished | Oct 15 06:11:02 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770405873 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.3770405873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_cfg_cmd.1448389935 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 1438910835 ps |
| CPU time | 18.56 seconds |
| Started | Oct 15 06:10:51 AM UTC 24 |
| Finished | Oct 15 06:11:11 AM UTC 24 |
| Peak memory | 245784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1448389935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.1448389935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_csb_read.3968104327 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 52233097 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 06:10:45 AM UTC 24 |
| Finished | Oct 15 06:10:47 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968104327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3968104327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_all.2436979141 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 43919672 ps |
| CPU time | 1.53 seconds |
| Started | Oct 15 06:10:53 AM UTC 24 |
| Finished | Oct 15 06:10:55 AM UTC 24 |
| Peak memory | 226264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436979141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2436979141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.915302945 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 4990535325 ps |
| CPU time | 141.93 seconds |
| Started | Oct 15 06:10:55 AM UTC 24 |
| Finished | Oct 15 06:13:20 AM UTC 24 |
| Peak memory | 282824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915302945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.915302945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.4225934521 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 12864173688 ps |
| CPU time | 85.56 seconds |
| Started | Oct 15 06:10:56 AM UTC 24 |
| Finished | Oct 15 06:12:24 AM UTC 24 |
| Peak memory | 262300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4225934521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.4225934521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode.420814692 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 7174318624 ps |
| CPU time | 23.92 seconds |
| Started | Oct 15 06:10:51 AM UTC 24 |
| Finished | Oct 15 06:11:16 AM UTC 24 |
| Peak memory | 235700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420814692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.420814692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.3558073714 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 57907714003 ps |
| CPU time | 162.65 seconds |
| Started | Oct 15 06:10:53 AM UTC 24 |
| Finished | Oct 15 06:13:38 AM UTC 24 |
| Peak memory | 268600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558073714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.3558073714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_intercept.3126263790 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 1641547404 ps |
| CPU time | 11.6 seconds |
| Started | Oct 15 06:10:51 AM UTC 24 |
| Finished | Oct 15 06:11:04 AM UTC 24 |
| Peak memory | 235520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126263790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3126263790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_mailbox.76915430 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 1578001470 ps |
| CPU time | 19.59 seconds |
| Started | Oct 15 06:10:51 AM UTC 24 |
| Finished | Oct 15 06:11:12 AM UTC 24 |
| Peak memory | 235504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76915430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.76915430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.2508258193 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 27338107881 ps |
| CPU time | 39.31 seconds |
| Started | Oct 15 06:10:49 AM UTC 24 |
| Finished | Oct 15 06:11:30 AM UTC 24 |
| Peak memory | 250228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508258193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.2508258193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.1043737080 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 111265155140 ps |
| CPU time | 20.49 seconds |
| Started | Oct 15 06:10:48 AM UTC 24 |
| Finished | Oct 15 06:11:10 AM UTC 24 |
| Peak memory | 235644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1043737080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.1043737080 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.1327634467 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 519326192 ps |
| CPU time | 6.57 seconds |
| Started | Oct 15 06:10:53 AM UTC 24 |
| Finished | Oct 15 06:11:00 AM UTC 24 |
| Peak memory | 234232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327634467 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.1327634467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.2688537347 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 91143039763 ps |
| CPU time | 383.6 seconds |
| Started | Oct 15 06:10:57 AM UTC 24 |
| Finished | Oct 15 06:17:26 AM UTC 24 |
| Peak memory | 295092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2688537347 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.2688537347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_all.740286054 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1619284671 ps |
| CPU time | 25.09 seconds |
| Started | Oct 15 06:10:48 AM UTC 24 |
| Finished | Oct 15 06:11:14 AM UTC 24 |
| Peak memory | 228336 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740286054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.740286054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1674585724 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 100352067 ps |
| CPU time | 1.57 seconds |
| Started | Oct 15 06:10:46 AM UTC 24 |
| Finished | Oct 15 06:10:49 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674585724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1674585724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_rw.3529352819 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 170036728 ps |
| CPU time | 3.06 seconds |
| Started | Oct 15 06:10:48 AM UTC 24 |
| Finished | Oct 15 06:10:52 AM UTC 24 |
| Peak memory | 228224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529352819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.3529352819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.2177131168 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 52439585 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 06:10:48 AM UTC 24 |
| Finished | Oct 15 06:10:50 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177131168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2177131168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_upload.354622336 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 6376810432 ps |
| CPU time | 14.88 seconds |
| Started | Oct 15 06:10:51 AM UTC 24 |
| Finished | Oct 15 06:11:07 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=354622336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.354622336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/26.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_alert_test.987350882 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 34463420 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 06:11:21 AM UTC 24 |
| Finished | Oct 15 06:11:23 AM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987350882 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.987350882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_cfg_cmd.349060951 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 541449938 ps |
| CPU time | 10.82 seconds |
| Started | Oct 15 06:11:12 AM UTC 24 |
| Finished | Oct 15 06:11:24 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349060951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.349060951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_csb_read.1950334989 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 23256089 ps |
| CPU time | 1.25 seconds |
| Started | Oct 15 06:11:01 AM UTC 24 |
| Finished | Oct 15 06:11:03 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950334989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.1950334989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_all.314101679 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 7279956977 ps |
| CPU time | 62.55 seconds |
| Started | Oct 15 06:11:14 AM UTC 24 |
| Finished | Oct 15 06:12:18 AM UTC 24 |
| Peak memory | 262276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314101679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.314101679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.764518479 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 56399961668 ps |
| CPU time | 314.36 seconds |
| Started | Oct 15 06:11:15 AM UTC 24 |
| Finished | Oct 15 06:16:34 AM UTC 24 |
| Peak memory | 268436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764518479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.764518479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.3740436132 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 15056267708 ps |
| CPU time | 86.49 seconds |
| Started | Oct 15 06:11:18 AM UTC 24 |
| Finished | Oct 15 06:12:46 AM UTC 24 |
| Peak memory | 278688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740436132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.3740436132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode.2634827141 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 989369981 ps |
| CPU time | 17.64 seconds |
| Started | Oct 15 06:11:12 AM UTC 24 |
| Finished | Oct 15 06:11:31 AM UTC 24 |
| Peak memory | 235636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634827141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2634827141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.1982692754 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 18392325035 ps |
| CPU time | 69.18 seconds |
| Started | Oct 15 06:11:14 AM UTC 24 |
| Finished | Oct 15 06:12:25 AM UTC 24 |
| Peak memory | 262460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982692754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.1982692754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_intercept.2867283980 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 468108822 ps |
| CPU time | 2.96 seconds |
| Started | Oct 15 06:11:09 AM UTC 24 |
| Finished | Oct 15 06:11:13 AM UTC 24 |
| Peak memory | 235776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867283980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2867283980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_mailbox.1320432188 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 8345203960 ps |
| CPU time | 75.02 seconds |
| Started | Oct 15 06:11:09 AM UTC 24 |
| Finished | Oct 15 06:12:26 AM UTC 24 |
| Peak memory | 245876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320432188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1320432188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.3103468507 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 585876665 ps |
| CPU time | 3.03 seconds |
| Started | Oct 15 06:11:09 AM UTC 24 |
| Finished | Oct 15 06:11:13 AM UTC 24 |
| Peak memory | 245780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103468507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.3103468507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.4279626544 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 4449322127 ps |
| CPU time | 10.35 seconds |
| Started | Oct 15 06:11:09 AM UTC 24 |
| Finished | Oct 15 06:11:20 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279626544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4279626544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.2578226812 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 94617579 ps |
| CPU time | 5.1 seconds |
| Started | Oct 15 06:11:14 AM UTC 24 |
| Finished | Oct 15 06:11:20 AM UTC 24 |
| Peak memory | 232128 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578226812 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.2578226812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_stress_all.2430015578 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 8800789689 ps |
| CPU time | 182.2 seconds |
| Started | Oct 15 06:11:21 AM UTC 24 |
| Finished | Oct 15 06:14:27 AM UTC 24 |
| Peak memory | 278772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430015578 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.2430015578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_all.795180991 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 78679175 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 06:11:05 AM UTC 24 |
| Finished | Oct 15 06:11:07 AM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795180991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.795180991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.2101198454 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 15838139029 ps |
| CPU time | 36.16 seconds |
| Started | Oct 15 06:11:03 AM UTC 24 |
| Finished | Oct 15 06:11:41 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2101198454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2101198454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_rw.2878797351 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 111739175 ps |
| CPU time | 1.87 seconds |
| Started | Oct 15 06:11:09 AM UTC 24 |
| Finished | Oct 15 06:11:11 AM UTC 24 |
| Peak memory | 227520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878797351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2878797351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.3531735883 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 68275423 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 06:11:05 AM UTC 24 |
| Finished | Oct 15 06:11:07 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531735883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3531735883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_upload.1700213716 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 12676140607 ps |
| CPU time | 18.37 seconds |
| Started | Oct 15 06:11:11 AM UTC 24 |
| Finished | Oct 15 06:11:31 AM UTC 24 |
| Peak memory | 245832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700213716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1700213716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/27.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_alert_test.3616454167 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 23587662 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 06:11:48 AM UTC 24 |
| Finished | Oct 15 06:11:50 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616454167 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.3616454167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_cfg_cmd.1158104705 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 698355253 ps |
| CPU time | 4.36 seconds |
| Started | Oct 15 06:11:36 AM UTC 24 |
| Finished | Oct 15 06:11:42 AM UTC 24 |
| Peak memory | 235516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158104705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1158104705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_csb_read.2178940284 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 18100265 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 06:11:24 AM UTC 24 |
| Finished | Oct 15 06:11:27 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2178940284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.2178940284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_all.3215071602 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 3725091588 ps |
| CPU time | 73.17 seconds |
| Started | Oct 15 06:11:43 AM UTC 24 |
| Finished | Oct 15 06:12:58 AM UTC 24 |
| Peak memory | 264528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215071602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3215071602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.3714472477 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 17624494838 ps |
| CPU time | 84.04 seconds |
| Started | Oct 15 06:11:47 AM UTC 24 |
| Finished | Oct 15 06:13:13 AM UTC 24 |
| Peak memory | 278880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714472477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.3714472477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode.638747992 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 179334941 ps |
| CPU time | 6.27 seconds |
| Started | Oct 15 06:11:40 AM UTC 24 |
| Finished | Oct 15 06:11:47 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638747992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.638747992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.1910981049 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 1809711236 ps |
| CPU time | 57.33 seconds |
| Started | Oct 15 06:11:41 AM UTC 24 |
| Finished | Oct 15 06:12:40 AM UTC 24 |
| Peak memory | 266324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1910981049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.1910981049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_intercept.2616763098 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 647697734 ps |
| CPU time | 5.79 seconds |
| Started | Oct 15 06:11:35 AM UTC 24 |
| Finished | Oct 15 06:11:42 AM UTC 24 |
| Peak memory | 230492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616763098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.2616763098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_mailbox.4254199033 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 3266267001 ps |
| CPU time | 38.62 seconds |
| Started | Oct 15 06:11:36 AM UTC 24 |
| Finished | Oct 15 06:12:16 AM UTC 24 |
| Peak memory | 245908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4254199033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4254199033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.2448836685 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 8202957613 ps |
| CPU time | 12.83 seconds |
| Started | Oct 15 06:11:35 AM UTC 24 |
| Finished | Oct 15 06:11:49 AM UTC 24 |
| Peak memory | 245904 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448836685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.2448836685 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.1036924596 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 276263748 ps |
| CPU time | 5.58 seconds |
| Started | Oct 15 06:11:32 AM UTC 24 |
| Finished | Oct 15 06:11:39 AM UTC 24 |
| Peak memory | 235524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036924596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1036924596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.4087275732 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 1311627543 ps |
| CPU time | 22.54 seconds |
| Started | Oct 15 06:11:42 AM UTC 24 |
| Finished | Oct 15 06:12:06 AM UTC 24 |
| Peak memory | 232224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087275732 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.4087275732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_stress_all.3041420245 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 23484515238 ps |
| CPU time | 104.78 seconds |
| Started | Oct 15 06:11:48 AM UTC 24 |
| Finished | Oct 15 06:13:35 AM UTC 24 |
| Peak memory | 268728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041420245 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.3041420245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_all.3540457603 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 22148184802 ps |
| CPU time | 28.33 seconds |
| Started | Oct 15 06:11:28 AM UTC 24 |
| Finished | Oct 15 06:11:57 AM UTC 24 |
| Peak memory | 232464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540457603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3540457603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.227093173 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2624624027 ps |
| CPU time | 8.2 seconds |
| Started | Oct 15 06:11:25 AM UTC 24 |
| Finished | Oct 15 06:11:35 AM UTC 24 |
| Peak memory | 228240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227093173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.227093173 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_rw.2512846132 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 28183249 ps |
| CPU time | 1.29 seconds |
| Started | Oct 15 06:11:32 AM UTC 24 |
| Finished | Oct 15 06:11:35 AM UTC 24 |
| Peak memory | 216512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512846132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2512846132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.3608944474 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 374370731 ps |
| CPU time | 1.36 seconds |
| Started | Oct 15 06:11:31 AM UTC 24 |
| Finished | Oct 15 06:11:33 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608944474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3608944474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/28.spi_device_upload.4017321965 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 1483436496 ps |
| CPU time | 8.18 seconds |
| Started | Oct 15 06:11:36 AM UTC 24 |
| Finished | Oct 15 06:11:46 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017321965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.4017321965 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/28.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_alert_test.2251010075 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 11877391 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 06:12:21 AM UTC 24 |
| Finished | Oct 15 06:12:23 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251010075 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.2251010075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_cfg_cmd.2228772031 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 149883345 ps |
| CPU time | 2.89 seconds |
| Started | Oct 15 06:12:10 AM UTC 24 |
| Finished | Oct 15 06:12:14 AM UTC 24 |
| Peak memory | 235052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228772031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2228772031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_csb_read.3036533858 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 40931228 ps |
| CPU time | 1.16 seconds |
| Started | Oct 15 06:11:50 AM UTC 24 |
| Finished | Oct 15 06:11:52 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036533858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3036533858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_all.3126533463 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 22321820644 ps |
| CPU time | 63.14 seconds |
| Started | Oct 15 06:12:18 AM UTC 24 |
| Finished | Oct 15 06:13:22 AM UTC 24 |
| Peak memory | 262264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126533463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3126533463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1746667805 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 44077635803 ps |
| CPU time | 58.91 seconds |
| Started | Oct 15 06:12:19 AM UTC 24 |
| Finished | Oct 15 06:13:19 AM UTC 24 |
| Peak memory | 246112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746667805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.1746667805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.988871724 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 1768002241 ps |
| CPU time | 34.32 seconds |
| Started | Oct 15 06:12:19 AM UTC 24 |
| Finished | Oct 15 06:12:55 AM UTC 24 |
| Peak memory | 230416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988871724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.988871724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode.3687025786 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1261538237 ps |
| CPU time | 10.9 seconds |
| Started | Oct 15 06:12:14 AM UTC 24 |
| Finished | Oct 15 06:12:26 AM UTC 24 |
| Peak memory | 249936 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687025786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3687025786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.3413460509 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 2044489884 ps |
| CPU time | 33.66 seconds |
| Started | Oct 15 06:12:14 AM UTC 24 |
| Finished | Oct 15 06:12:49 AM UTC 24 |
| Peak memory | 262200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3413460509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.3413460509 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_intercept.3176072116 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 855674423 ps |
| CPU time | 4.64 seconds |
| Started | Oct 15 06:12:02 AM UTC 24 |
| Finished | Oct 15 06:12:08 AM UTC 24 |
| Peak memory | 235700 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176072116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.3176072116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_mailbox.150993812 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 98206574 ps |
| CPU time | 4.26 seconds |
| Started | Oct 15 06:12:07 AM UTC 24 |
| Finished | Oct 15 06:12:13 AM UTC 24 |
| Peak memory | 235520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150993812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.150993812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.1137500009 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 3868430505 ps |
| CPU time | 19.02 seconds |
| Started | Oct 15 06:12:00 AM UTC 24 |
| Finished | Oct 15 06:12:20 AM UTC 24 |
| Peak memory | 262524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137500009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.1137500009 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.3172220468 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 5381715265 ps |
| CPU time | 18.61 seconds |
| Started | Oct 15 06:11:59 AM UTC 24 |
| Finished | Oct 15 06:12:18 AM UTC 24 |
| Peak memory | 246040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172220468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3172220468 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.2048760471 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 1911627292 ps |
| CPU time | 16.2 seconds |
| Started | Oct 15 06:12:16 AM UTC 24 |
| Finished | Oct 15 06:12:34 AM UTC 24 |
| Peak memory | 230092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2048760471 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.2048760471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_stress_all.3211958085 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 9244045956 ps |
| CPU time | 181.01 seconds |
| Started | Oct 15 06:12:21 AM UTC 24 |
| Finished | Oct 15 06:15:25 AM UTC 24 |
| Peak memory | 284848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211958085 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.3211958085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_all.3899645 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 42427055556 ps |
| CPU time | 52.41 seconds |
| Started | Oct 15 06:11:51 AM UTC 24 |
| Finished | Oct 15 06:12:45 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.3899645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.3918003500 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 10682697155 ps |
| CPU time | 17.92 seconds |
| Started | Oct 15 06:11:50 AM UTC 24 |
| Finished | Oct 15 06:12:09 AM UTC 24 |
| Peak memory | 228324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918003500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3918003500 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_rw.1059494783 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 17620333 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 06:11:56 AM UTC 24 |
| Finished | Oct 15 06:11:58 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059494783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.1059494783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.2344832299 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 199610577 ps |
| CPU time | 1.02 seconds |
| Started | Oct 15 06:11:53 AM UTC 24 |
| Finished | Oct 15 06:11:55 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344832299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2344832299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/29.spi_device_upload.2218231313 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 1886240880 ps |
| CPU time | 6.15 seconds |
| Started | Oct 15 06:12:08 AM UTC 24 |
| Finished | Oct 15 06:12:16 AM UTC 24 |
| Peak memory | 246092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218231313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2218231313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/29.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_alert_test.152643354 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 25030662 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 05:59:00 AM UTC 24 |
| Finished | Oct 15 05:59:02 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152643354 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.152643354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_cfg_cmd.1166733510 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 442260197 ps |
| CPU time | 9.4 seconds |
| Started | Oct 15 05:58:37 AM UTC 24 |
| Finished | Oct 15 05:58:48 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166733510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.1166733510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_csb_read.745686860 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 34382273 ps |
| CPU time | 1.24 seconds |
| Started | Oct 15 05:58:14 AM UTC 24 |
| Finished | Oct 15 05:58:16 AM UTC 24 |
| Peak memory | 217124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745686860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.745686860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_all.3070683526 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 14353164263 ps |
| CPU time | 149.35 seconds |
| Started | Oct 15 05:58:47 AM UTC 24 |
| Finished | Oct 15 06:01:20 AM UTC 24 |
| Peak memory | 264316 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070683526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3070683526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.2362054353 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 141404233806 ps |
| CPU time | 303.94 seconds |
| Started | Oct 15 05:58:53 AM UTC 24 |
| Finished | Oct 15 06:04:01 AM UTC 24 |
| Peak memory | 268716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362054353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.2362054353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode.1952107828 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 2012689479 ps |
| CPU time | 6.44 seconds |
| Started | Oct 15 05:58:39 AM UTC 24 |
| Finished | Oct 15 05:58:47 AM UTC 24 |
| Peak memory | 235704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952107828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1952107828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.3871551644 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 61919461331 ps |
| CPU time | 168.4 seconds |
| Started | Oct 15 05:58:43 AM UTC 24 |
| Finished | Oct 15 06:01:35 AM UTC 24 |
| Peak memory | 262448 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871551644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.3871551644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_intercept.824432408 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 65430847 ps |
| CPU time | 3.39 seconds |
| Started | Oct 15 05:58:29 AM UTC 24 |
| Finished | Oct 15 05:58:33 AM UTC 24 |
| Peak memory | 245488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824432408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.824432408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_mailbox.819741072 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 77867195815 ps |
| CPU time | 188.03 seconds |
| Started | Oct 15 05:58:32 AM UTC 24 |
| Finished | Oct 15 06:01:43 AM UTC 24 |
| Peak memory | 246172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819741072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.819741072 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.794863758 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 1717585286 ps |
| CPU time | 10.6 seconds |
| Started | Oct 15 05:58:27 AM UTC 24 |
| Finished | Oct 15 05:58:38 AM UTC 24 |
| Peak memory | 246040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794863758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.794863758 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.2821427854 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 1036323989 ps |
| CPU time | 12.11 seconds |
| Started | Oct 15 05:58:23 AM UTC 24 |
| Finished | Oct 15 05:58:36 AM UTC 24 |
| Peak memory | 262260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821427854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2821427854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.2318751166 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 183078324 ps |
| CPU time | 5.95 seconds |
| Started | Oct 15 05:58:47 AM UTC 24 |
| Finished | Oct 15 05:58:55 AM UTC 24 |
| Peak memory | 234408 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318751166 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.2318751166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_sec_cm.1525275834 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 118289948 ps |
| CPU time | 1.85 seconds |
| Started | Oct 15 05:58:56 AM UTC 24 |
| Finished | Oct 15 05:58:59 AM UTC 24 |
| Peak memory | 257760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525275834 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1525275834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_all.1464424060 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 12181972072 ps |
| CPU time | 27.65 seconds |
| Started | Oct 15 05:58:17 AM UTC 24 |
| Finished | Oct 15 05:58:46 AM UTC 24 |
| Peak memory | 232404 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464424060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1464424060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.3600365976 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 2204679233 ps |
| CPU time | 9.46 seconds |
| Started | Oct 15 05:58:17 AM UTC 24 |
| Finished | Oct 15 05:58:28 AM UTC 24 |
| Peak memory | 228276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600365976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3600365976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_rw.1812085356 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 821657399 ps |
| CPU time | 4.4 seconds |
| Started | Oct 15 05:58:20 AM UTC 24 |
| Finished | Oct 15 05:58:26 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1812085356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1812085356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.484985021 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 51282224 ps |
| CPU time | 1.31 seconds |
| Started | Oct 15 05:58:19 AM UTC 24 |
| Finished | Oct 15 05:58:22 AM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484985021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.484985021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/3.spi_device_upload.101194744 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 2232511615 ps |
| CPU time | 16.7 seconds |
| Started | Oct 15 05:58:34 AM UTC 24 |
| Finished | Oct 15 05:58:52 AM UTC 24 |
| Peak memory | 245844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101194744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.101194744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/3.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_alert_test.351017233 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 12917934 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 06:12:43 AM UTC 24 |
| Finished | Oct 15 06:12:45 AM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351017233 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.351017233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_cfg_cmd.2562215052 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 284501628 ps |
| CPU time | 5.24 seconds |
| Started | Oct 15 06:12:32 AM UTC 24 |
| Finished | Oct 15 06:12:38 AM UTC 24 |
| Peak memory | 235532 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562215052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2562215052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_csb_read.3488027604 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 44201489 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 06:12:25 AM UTC 24 |
| Finished | Oct 15 06:12:27 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488027604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3488027604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_all.331711917 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 2852019254 ps |
| CPU time | 50.63 seconds |
| Started | Oct 15 06:12:38 AM UTC 24 |
| Finished | Oct 15 06:13:30 AM UTC 24 |
| Peak memory | 262444 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331711917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.331711917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.1395250663 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 217444236797 ps |
| CPU time | 551.85 seconds |
| Started | Oct 15 06:12:39 AM UTC 24 |
| Finished | Oct 15 06:21:58 AM UTC 24 |
| Peak memory | 268456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395250663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1395250663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.3423728605 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 22100194180 ps |
| CPU time | 242.5 seconds |
| Started | Oct 15 06:12:40 AM UTC 24 |
| Finished | Oct 15 06:16:47 AM UTC 24 |
| Peak memory | 268696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423728605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.3423728605 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode.3351462079 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 5578567231 ps |
| CPU time | 28.9 seconds |
| Started | Oct 15 06:12:34 AM UTC 24 |
| Finished | Oct 15 06:13:04 AM UTC 24 |
| Peak memory | 246064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351462079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.3351462079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.2571975967 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 46828198311 ps |
| CPU time | 134.87 seconds |
| Started | Oct 15 06:12:34 AM UTC 24 |
| Finished | Oct 15 06:14:52 AM UTC 24 |
| Peak memory | 263600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2571975967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.2571975967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_intercept.3954497861 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 107951849 ps |
| CPU time | 3.29 seconds |
| Started | Oct 15 06:12:29 AM UTC 24 |
| Finished | Oct 15 06:12:34 AM UTC 24 |
| Peak memory | 245516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954497861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.3954497861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_mailbox.728335856 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 7862440367 ps |
| CPU time | 20.45 seconds |
| Started | Oct 15 06:12:32 AM UTC 24 |
| Finished | Oct 15 06:12:54 AM UTC 24 |
| Peak memory | 245948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728335856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.728335856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.1193669908 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 954335928 ps |
| CPU time | 4.61 seconds |
| Started | Oct 15 06:12:28 AM UTC 24 |
| Finished | Oct 15 06:12:34 AM UTC 24 |
| Peak memory | 235732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193669908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.1193669908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.3104780876 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 4673950343 ps |
| CPU time | 22.51 seconds |
| Started | Oct 15 06:12:28 AM UTC 24 |
| Finished | Oct 15 06:12:52 AM UTC 24 |
| Peak memory | 245880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104780876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.3104780876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.108216218 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 450609122 ps |
| CPU time | 6.34 seconds |
| Started | Oct 15 06:12:34 AM UTC 24 |
| Finished | Oct 15 06:12:42 AM UTC 24 |
| Peak memory | 234312 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108216218 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.108216218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_stress_all.3514886230 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 30755847 ps |
| CPU time | 1.31 seconds |
| Started | Oct 15 06:12:40 AM UTC 24 |
| Finished | Oct 15 06:12:43 AM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514886230 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.3514886230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_all.3331812863 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 156360740 ps |
| CPU time | 3.63 seconds |
| Started | Oct 15 06:12:26 AM UTC 24 |
| Finished | Oct 15 06:12:31 AM UTC 24 |
| Peak memory | 230544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331812863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.3331812863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.266395630 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 187603653 ps |
| CPU time | 1.82 seconds |
| Started | Oct 15 06:12:25 AM UTC 24 |
| Finished | Oct 15 06:12:28 AM UTC 24 |
| Peak memory | 217036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266395630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.266395630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_rw.2906791422 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 102111594 ps |
| CPU time | 2 seconds |
| Started | Oct 15 06:12:28 AM UTC 24 |
| Finished | Oct 15 06:12:31 AM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906791422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2906791422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.1118128720 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 516641060 ps |
| CPU time | 1.58 seconds |
| Started | Oct 15 06:12:28 AM UTC 24 |
| Finished | Oct 15 06:12:30 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118128720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1118128720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_upload.2193513363 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 868943341 ps |
| CPU time | 7.63 seconds |
| Started | Oct 15 06:12:32 AM UTC 24 |
| Finished | Oct 15 06:12:41 AM UTC 24 |
| Peak memory | 245608 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193513363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2193513363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/30.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_alert_test.205367484 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 13776568 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 06:12:56 AM UTC 24 |
| Finished | Oct 15 06:12:59 AM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205367484 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.205367484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_cfg_cmd.3285695601 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 771663286 ps |
| CPU time | 4.13 seconds |
| Started | Oct 15 06:12:51 AM UTC 24 |
| Finished | Oct 15 06:12:56 AM UTC 24 |
| Peak memory | 246032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285695601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3285695601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_csb_read.882094487 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 25725520 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 06:12:43 AM UTC 24 |
| Finished | Oct 15 06:12:45 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882094487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.882094487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.4196865101 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 673569910915 ps |
| CPU time | 423.36 seconds |
| Started | Oct 15 06:12:53 AM UTC 24 |
| Finished | Oct 15 06:20:03 AM UTC 24 |
| Peak memory | 266388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196865101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.4196865101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.896734132 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 337123382017 ps |
| CPU time | 504.29 seconds |
| Started | Oct 15 06:12:56 AM UTC 24 |
| Finished | Oct 15 06:21:28 AM UTC 24 |
| Peak memory | 266412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896734132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.896734132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.3772776438 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 95850215969 ps |
| CPU time | 210.58 seconds |
| Started | Oct 15 06:12:56 AM UTC 24 |
| Finished | Oct 15 06:16:30 AM UTC 24 |
| Peak memory | 262496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772776438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.3772776438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode.1248465448 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 1448211501 ps |
| CPU time | 6.99 seconds |
| Started | Oct 15 06:12:53 AM UTC 24 |
| Finished | Oct 15 06:13:02 AM UTC 24 |
| Peak memory | 245868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248465448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1248465448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.4173411413 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 5729360938 ps |
| CPU time | 19.38 seconds |
| Started | Oct 15 06:12:53 AM UTC 24 |
| Finished | Oct 15 06:13:14 AM UTC 24 |
| Peak memory | 245976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173411413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.4173411413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_intercept.92364431 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 570451113 ps |
| CPU time | 6.12 seconds |
| Started | Oct 15 06:12:48 AM UTC 24 |
| Finished | Oct 15 06:12:55 AM UTC 24 |
| Peak memory | 246044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92364431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.92364431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_mailbox.2548318056 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 2757988355 ps |
| CPU time | 21.27 seconds |
| Started | Oct 15 06:12:51 AM UTC 24 |
| Finished | Oct 15 06:13:13 AM UTC 24 |
| Peak memory | 245844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548318056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2548318056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.1993731664 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 1588846123 ps |
| CPU time | 8.73 seconds |
| Started | Oct 15 06:12:48 AM UTC 24 |
| Finished | Oct 15 06:12:58 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993731664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.1993731664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.4075805643 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 46612843278 ps |
| CPU time | 21.87 seconds |
| Started | Oct 15 06:12:48 AM UTC 24 |
| Finished | Oct 15 06:13:11 AM UTC 24 |
| Peak memory | 245816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075805643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.4075805643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.1268519798 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 122477867 ps |
| CPU time | 5.31 seconds |
| Started | Oct 15 06:12:53 AM UTC 24 |
| Finished | Oct 15 06:13:00 AM UTC 24 |
| Peak memory | 234176 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268519798 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.1268519798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_stress_all.477235533 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 5752136522 ps |
| CPU time | 17.81 seconds |
| Started | Oct 15 06:12:56 AM UTC 24 |
| Finished | Oct 15 06:13:16 AM UTC 24 |
| Peak memory | 247908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477235533 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.477235533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_all.2466917358 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 2521746497 ps |
| CPU time | 15.58 seconds |
| Started | Oct 15 06:12:45 AM UTC 24 |
| Finished | Oct 15 06:13:01 AM UTC 24 |
| Peak memory | 228364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2466917358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2466917358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.564272351 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 912329381 ps |
| CPU time | 3.37 seconds |
| Started | Oct 15 06:12:45 AM UTC 24 |
| Finished | Oct 15 06:12:49 AM UTC 24 |
| Peak memory | 228228 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564272351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.564272351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_rw.1658630772 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 1170568737 ps |
| CPU time | 2.72 seconds |
| Started | Oct 15 06:12:48 AM UTC 24 |
| Finished | Oct 15 06:12:51 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658630772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1658630772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.3316214975 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 294878975 ps |
| CPU time | 1.52 seconds |
| Started | Oct 15 06:12:48 AM UTC 24 |
| Finished | Oct 15 06:12:50 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3316214975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.3316214975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_upload.2544945582 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 156269803 ps |
| CPU time | 2.8 seconds |
| Started | Oct 15 06:12:51 AM UTC 24 |
| Finished | Oct 15 06:12:54 AM UTC 24 |
| Peak memory | 234920 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544945582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2544945582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/31.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_alert_test.4089227380 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 12802123 ps |
| CPU time | 0.93 seconds |
| Started | Oct 15 06:13:13 AM UTC 24 |
| Finished | Oct 15 06:13:15 AM UTC 24 |
| Peak memory | 216528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089227380 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.4089227380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_cfg_cmd.2920013037 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 481248719 ps |
| CPU time | 4.61 seconds |
| Started | Oct 15 06:13:06 AM UTC 24 |
| Finished | Oct 15 06:13:12 AM UTC 24 |
| Peak memory | 245760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2920013037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2920013037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_csb_read.740537318 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 68240862 ps |
| CPU time | 1.21 seconds |
| Started | Oct 15 06:12:57 AM UTC 24 |
| Finished | Oct 15 06:12:59 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740537318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.740537318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_all.2587933525 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 43481606 ps |
| CPU time | 1.21 seconds |
| Started | Oct 15 06:13:09 AM UTC 24 |
| Finished | Oct 15 06:13:12 AM UTC 24 |
| Peak memory | 226264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587933525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2587933525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.2605044876 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 4183957823 ps |
| CPU time | 59.99 seconds |
| Started | Oct 15 06:13:12 AM UTC 24 |
| Finished | Oct 15 06:14:14 AM UTC 24 |
| Peak memory | 262304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2605044876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.2605044876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.2006969936 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 6626812691 ps |
| CPU time | 117.79 seconds |
| Started | Oct 15 06:13:13 AM UTC 24 |
| Finished | Oct 15 06:15:14 AM UTC 24 |
| Peak memory | 268452 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006969936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.2006969936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode.2478463332 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 228758777 ps |
| CPU time | 5.44 seconds |
| Started | Oct 15 06:13:06 AM UTC 24 |
| Finished | Oct 15 06:13:13 AM UTC 24 |
| Peak memory | 235760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478463332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2478463332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.1662604052 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 13568167536 ps |
| CPU time | 59.59 seconds |
| Started | Oct 15 06:13:06 AM UTC 24 |
| Finished | Oct 15 06:14:08 AM UTC 24 |
| Peak memory | 262388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662604052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.1662604052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_intercept.3253774974 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 4016683084 ps |
| CPU time | 8.98 seconds |
| Started | Oct 15 06:13:03 AM UTC 24 |
| Finished | Oct 15 06:13:13 AM UTC 24 |
| Peak memory | 242712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3253774974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.3253774974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_mailbox.3643408349 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 1102188180 ps |
| CPU time | 7.56 seconds |
| Started | Oct 15 06:13:03 AM UTC 24 |
| Finished | Oct 15 06:13:12 AM UTC 24 |
| Peak memory | 235732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643408349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3643408349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.4151515974 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 10859414279 ps |
| CPU time | 21.68 seconds |
| Started | Oct 15 06:13:03 AM UTC 24 |
| Finished | Oct 15 06:13:26 AM UTC 24 |
| Peak memory | 252148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4151515974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.4151515974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.2464430296 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 7254288977 ps |
| CPU time | 17.56 seconds |
| Started | Oct 15 06:13:03 AM UTC 24 |
| Finished | Oct 15 06:13:22 AM UTC 24 |
| Peak memory | 246076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464430296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2464430296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.4013257517 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 1443830429 ps |
| CPU time | 13.12 seconds |
| Started | Oct 15 06:13:07 AM UTC 24 |
| Finished | Oct 15 06:13:21 AM UTC 24 |
| Peak memory | 234224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013257517 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.4013257517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.2195213291 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 32801071819 ps |
| CPU time | 289.54 seconds |
| Started | Oct 15 06:13:13 AM UTC 24 |
| Finished | Oct 15 06:18:07 AM UTC 24 |
| Peak memory | 268484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195213291 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.2195213291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_all.94909775 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 33651690 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 06:12:59 AM UTC 24 |
| Finished | Oct 15 06:13:01 AM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=94909775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.94909775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.3377026295 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 889912793 ps |
| CPU time | 3.19 seconds |
| Started | Oct 15 06:12:59 AM UTC 24 |
| Finished | Oct 15 06:13:03 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377026295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3377026295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_rw.3380161831 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 1111733286 ps |
| CPU time | 2.4 seconds |
| Started | Oct 15 06:13:02 AM UTC 24 |
| Finished | Oct 15 06:13:05 AM UTC 24 |
| Peak memory | 228424 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380161831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3380161831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.3636036665 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 25757101 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 06:13:01 AM UTC 24 |
| Finished | Oct 15 06:13:04 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636036665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3636036665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_upload.798608700 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 442222790 ps |
| CPU time | 8.42 seconds |
| Started | Oct 15 06:13:06 AM UTC 24 |
| Finished | Oct 15 06:13:16 AM UTC 24 |
| Peak memory | 246000 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798608700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.798608700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/32.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_alert_test.2398921347 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 13814458 ps |
| CPU time | 1.08 seconds |
| Started | Oct 15 06:13:27 AM UTC 24 |
| Finished | Oct 15 06:13:30 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2398921347 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.2398921347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_cfg_cmd.870932884 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 1162859376 ps |
| CPU time | 6.41 seconds |
| Started | Oct 15 06:13:21 AM UTC 24 |
| Finished | Oct 15 06:13:29 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870932884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.870932884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_csb_read.734934184 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 71644663 ps |
| CPU time | 1.25 seconds |
| Started | Oct 15 06:13:15 AM UTC 24 |
| Finished | Oct 15 06:13:17 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734934184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.734934184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.3860268242 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 20837048171 ps |
| CPU time | 155.29 seconds |
| Started | Oct 15 06:13:24 AM UTC 24 |
| Finished | Oct 15 06:16:02 AM UTC 24 |
| Peak memory | 262328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860268242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3860268242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.2913309962 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 32460321862 ps |
| CPU time | 135.2 seconds |
| Started | Oct 15 06:13:24 AM UTC 24 |
| Finished | Oct 15 06:15:42 AM UTC 24 |
| Peak memory | 272556 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913309962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.2913309962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.132833647 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 10916606692 ps |
| CPU time | 143.87 seconds |
| Started | Oct 15 06:13:25 AM UTC 24 |
| Finished | Oct 15 06:15:51 AM UTC 24 |
| Peak memory | 268476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132833647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.132833647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_mode.2777515601 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 9735752794 ps |
| CPU time | 55.82 seconds |
| Started | Oct 15 06:13:21 AM UTC 24 |
| Finished | Oct 15 06:14:19 AM UTC 24 |
| Peak memory | 262260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777515601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2777515601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_intercept.306328546 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 3748715369 ps |
| CPU time | 5.23 seconds |
| Started | Oct 15 06:13:17 AM UTC 24 |
| Finished | Oct 15 06:13:23 AM UTC 24 |
| Peak memory | 235640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306328546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.306328546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_mailbox.3938974383 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 840033108 ps |
| CPU time | 15.03 seconds |
| Started | Oct 15 06:13:18 AM UTC 24 |
| Finished | Oct 15 06:13:35 AM UTC 24 |
| Peak memory | 251788 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938974383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3938974383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.1103037288 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 451333426 ps |
| CPU time | 10.35 seconds |
| Started | Oct 15 06:13:17 AM UTC 24 |
| Finished | Oct 15 06:13:29 AM UTC 24 |
| Peak memory | 235644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103037288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.1103037288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.1541112947 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 336682778 ps |
| CPU time | 6.82 seconds |
| Started | Oct 15 06:13:17 AM UTC 24 |
| Finished | Oct 15 06:13:25 AM UTC 24 |
| Peak memory | 245844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541112947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1541112947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.2946032506 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 219459509 ps |
| CPU time | 5.52 seconds |
| Started | Oct 15 06:13:22 AM UTC 24 |
| Finished | Oct 15 06:13:29 AM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946032506 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.2946032506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_stress_all.1527028856 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 73585104 ps |
| CPU time | 1.43 seconds |
| Started | Oct 15 06:13:26 AM UTC 24 |
| Finished | Oct 15 06:13:29 AM UTC 24 |
| Peak memory | 216944 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527028856 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.1527028856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_all.927526251 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 11301205870 ps |
| CPU time | 21.72 seconds |
| Started | Oct 15 06:13:15 AM UTC 24 |
| Finished | Oct 15 06:13:38 AM UTC 24 |
| Peak memory | 228204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=927526251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.927526251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.2810014477 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 20773562618 ps |
| CPU time | 33.72 seconds |
| Started | Oct 15 06:13:15 AM UTC 24 |
| Finished | Oct 15 06:13:51 AM UTC 24 |
| Peak memory | 228272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810014477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2810014477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_rw.572391570 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 130749166 ps |
| CPU time | 1.48 seconds |
| Started | Oct 15 06:13:17 AM UTC 24 |
| Finished | Oct 15 06:13:20 AM UTC 24 |
| Peak memory | 216792 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572391570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.572391570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.3757253597 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 138924106 ps |
| CPU time | 1.34 seconds |
| Started | Oct 15 06:13:15 AM UTC 24 |
| Finished | Oct 15 06:13:18 AM UTC 24 |
| Peak memory | 216676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757253597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3757253597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_upload.3497655931 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 10524118066 ps |
| CPU time | 29.82 seconds |
| Started | Oct 15 06:13:18 AM UTC 24 |
| Finished | Oct 15 06:13:50 AM UTC 24 |
| Peak memory | 235416 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497655931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3497655931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/33.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_alert_test.1056824678 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 37809184 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 06:13:46 AM UTC 24 |
| Finished | Oct 15 06:13:48 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056824678 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.1056824678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_cfg_cmd.433188861 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 239553631 ps |
| CPU time | 2.05 seconds |
| Started | Oct 15 06:13:37 AM UTC 24 |
| Finished | Oct 15 06:13:40 AM UTC 24 |
| Peak memory | 235340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433188861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.433188861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_csb_read.2387062599 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 23395891 ps |
| CPU time | 1.16 seconds |
| Started | Oct 15 06:13:29 AM UTC 24 |
| Finished | Oct 15 06:13:31 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387062599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2387062599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_all.2913863351 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 14730718692 ps |
| CPU time | 122.35 seconds |
| Started | Oct 15 06:13:39 AM UTC 24 |
| Finished | Oct 15 06:15:44 AM UTC 24 |
| Peak memory | 268400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913863351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2913863351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.3416245873 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 96675811650 ps |
| CPU time | 212.78 seconds |
| Started | Oct 15 06:13:41 AM UTC 24 |
| Finished | Oct 15 06:17:16 AM UTC 24 |
| Peak memory | 262428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416245873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3416245873 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.2789379485 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 130591937648 ps |
| CPU time | 355.35 seconds |
| Started | Oct 15 06:13:42 AM UTC 24 |
| Finished | Oct 15 06:19:42 AM UTC 24 |
| Peak memory | 276668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789379485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.2789379485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode.1179464744 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 2692470218 ps |
| CPU time | 18.76 seconds |
| Started | Oct 15 06:13:37 AM UTC 24 |
| Finished | Oct 15 06:13:57 AM UTC 24 |
| Peak memory | 251052 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179464744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.1179464744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.3518694694 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 85607014332 ps |
| CPU time | 130.86 seconds |
| Started | Oct 15 06:13:38 AM UTC 24 |
| Finished | Oct 15 06:15:51 AM UTC 24 |
| Peak memory | 266388 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518694694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.3518694694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_intercept.4165801152 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 4859007001 ps |
| CPU time | 14.16 seconds |
| Started | Oct 15 06:13:32 AM UTC 24 |
| Finished | Oct 15 06:13:47 AM UTC 24 |
| Peak memory | 235636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4165801152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.4165801152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_mailbox.593170362 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 6216642471 ps |
| CPU time | 22.02 seconds |
| Started | Oct 15 06:13:33 AM UTC 24 |
| Finished | Oct 15 06:13:56 AM UTC 24 |
| Peak memory | 247928 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593170362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.593170362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.791448327 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 31748952 ps |
| CPU time | 2.9 seconds |
| Started | Oct 15 06:13:32 AM UTC 24 |
| Finished | Oct 15 06:13:36 AM UTC 24 |
| Peak memory | 235356 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791448327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.791448327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.3203788112 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 21317453024 ps |
| CPU time | 20.76 seconds |
| Started | Oct 15 06:13:30 AM UTC 24 |
| Finished | Oct 15 06:13:52 AM UTC 24 |
| Peak memory | 246044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203788112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3203788112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.186652588 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 1106819763 ps |
| CPU time | 14.61 seconds |
| Started | Oct 15 06:13:39 AM UTC 24 |
| Finished | Oct 15 06:13:55 AM UTC 24 |
| Peak memory | 232400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186652588 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.186652588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.72194014 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 123865561501 ps |
| CPU time | 312.86 seconds |
| Started | Oct 15 06:13:43 AM UTC 24 |
| Finished | Oct 15 06:19:00 AM UTC 24 |
| Peak memory | 266652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72194014 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.72194014 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_all.3181490523 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 3023148361 ps |
| CPU time | 9.25 seconds |
| Started | Oct 15 06:13:30 AM UTC 24 |
| Finished | Oct 15 06:13:41 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181490523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3181490523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.1384375263 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 6907557408 ps |
| CPU time | 31.73 seconds |
| Started | Oct 15 06:13:30 AM UTC 24 |
| Finished | Oct 15 06:14:03 AM UTC 24 |
| Peak memory | 228324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384375263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1384375263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_rw.2723752620 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 172695724 ps |
| CPU time | 5.37 seconds |
| Started | Oct 15 06:13:30 AM UTC 24 |
| Finished | Oct 15 06:13:37 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723752620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2723752620 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.3851620320 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 71113992 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 06:13:30 AM UTC 24 |
| Finished | Oct 15 06:13:33 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851620320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.3851620320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_upload.3986228224 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 5491883255 ps |
| CPU time | 8.4 seconds |
| Started | Oct 15 06:13:35 AM UTC 24 |
| Finished | Oct 15 06:13:45 AM UTC 24 |
| Peak memory | 245896 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3986228224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3986228224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/34.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_alert_test.1592325227 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 12282760 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 06:14:03 AM UTC 24 |
| Finished | Oct 15 06:14:05 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592325227 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.1592325227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_cfg_cmd.1704337175 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 109583320 ps |
| CPU time | 3.43 seconds |
| Started | Oct 15 06:13:55 AM UTC 24 |
| Finished | Oct 15 06:13:59 AM UTC 24 |
| Peak memory | 235540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704337175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1704337175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_csb_read.3394663290 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 61144802 ps |
| CPU time | 1.28 seconds |
| Started | Oct 15 06:13:46 AM UTC 24 |
| Finished | Oct 15 06:13:48 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394663290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3394663290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_all.2833880772 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 1518016341 ps |
| CPU time | 19.22 seconds |
| Started | Oct 15 06:13:58 AM UTC 24 |
| Finished | Oct 15 06:14:18 AM UTC 24 |
| Peak memory | 251988 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833880772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2833880772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.1096561051 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 2530853490 ps |
| CPU time | 48.55 seconds |
| Started | Oct 15 06:13:59 AM UTC 24 |
| Finished | Oct 15 06:14:49 AM UTC 24 |
| Peak memory | 264360 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096561051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1096561051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.313307836 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 25884411935 ps |
| CPU time | 134.33 seconds |
| Started | Oct 15 06:14:00 AM UTC 24 |
| Finished | Oct 15 06:16:17 AM UTC 24 |
| Peak memory | 266420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=313307836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.313307836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode.484933134 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 826033792 ps |
| CPU time | 16.88 seconds |
| Started | Oct 15 06:13:56 AM UTC 24 |
| Finished | Oct 15 06:14:14 AM UTC 24 |
| Peak memory | 245816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484933134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.484933134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.767083452 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 89716557790 ps |
| CPU time | 196.63 seconds |
| Started | Oct 15 06:13:58 AM UTC 24 |
| Finished | Oct 15 06:17:17 AM UTC 24 |
| Peak memory | 266584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767083452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.767083452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_intercept.2925895096 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 1201958219 ps |
| CPU time | 7.66 seconds |
| Started | Oct 15 06:13:52 AM UTC 24 |
| Finished | Oct 15 06:14:01 AM UTC 24 |
| Peak memory | 245836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925895096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2925895096 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_mailbox.3398347286 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 2244301549 ps |
| CPU time | 33.47 seconds |
| Started | Oct 15 06:13:54 AM UTC 24 |
| Finished | Oct 15 06:14:28 AM UTC 24 |
| Peak memory | 245816 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398347286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3398347286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.2822113425 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 2491991396 ps |
| CPU time | 8.52 seconds |
| Started | Oct 15 06:13:52 AM UTC 24 |
| Finished | Oct 15 06:14:02 AM UTC 24 |
| Peak memory | 245848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822113425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.2822113425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.3075764029 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 2657568836 ps |
| CPU time | 12.14 seconds |
| Started | Oct 15 06:13:52 AM UTC 24 |
| Finished | Oct 15 06:14:05 AM UTC 24 |
| Peak memory | 246008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075764029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.3075764029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.2941399627 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 465680441 ps |
| CPU time | 7.73 seconds |
| Started | Oct 15 06:13:58 AM UTC 24 |
| Finished | Oct 15 06:14:07 AM UTC 24 |
| Peak memory | 232068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941399627 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.2941399627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_stress_all.2877104222 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 13425204544 ps |
| CPU time | 105.04 seconds |
| Started | Oct 15 06:14:01 AM UTC 24 |
| Finished | Oct 15 06:15:48 AM UTC 24 |
| Peak memory | 246160 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877104222 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.2877104222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_all.1904097252 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 471423100 ps |
| CPU time | 6.22 seconds |
| Started | Oct 15 06:13:49 AM UTC 24 |
| Finished | Oct 15 06:13:56 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904097252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1904097252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.2771051165 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 1044957287 ps |
| CPU time | 8.91 seconds |
| Started | Oct 15 06:13:48 AM UTC 24 |
| Finished | Oct 15 06:13:58 AM UTC 24 |
| Peak memory | 228240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771051165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2771051165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_rw.977035168 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 653845262 ps |
| CPU time | 2.49 seconds |
| Started | Oct 15 06:13:50 AM UTC 24 |
| Finished | Oct 15 06:13:54 AM UTC 24 |
| Peak memory | 228420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977035168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.977035168 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.2122685753 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 34842134 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 06:13:49 AM UTC 24 |
| Finished | Oct 15 06:13:51 AM UTC 24 |
| Peak memory | 216840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2122685753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2122685753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_upload.2278032898 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 26476864621 ps |
| CPU time | 33.83 seconds |
| Started | Oct 15 06:13:54 AM UTC 24 |
| Finished | Oct 15 06:14:29 AM UTC 24 |
| Peak memory | 246092 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278032898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2278032898 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/35.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_alert_test.2043194209 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 13158214 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 06:14:30 AM UTC 24 |
| Finished | Oct 15 06:14:32 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043194209 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.2043194209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_cfg_cmd.1290441754 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 1818223846 ps |
| CPU time | 19.09 seconds |
| Started | Oct 15 06:14:15 AM UTC 24 |
| Finished | Oct 15 06:14:35 AM UTC 24 |
| Peak memory | 245976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290441754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1290441754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_csb_read.3997233962 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 21165733 ps |
| CPU time | 1.27 seconds |
| Started | Oct 15 06:14:05 AM UTC 24 |
| Finished | Oct 15 06:14:07 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997233962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3997233962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_all.2285173250 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 6883364979 ps |
| CPU time | 77.58 seconds |
| Started | Oct 15 06:14:21 AM UTC 24 |
| Finished | Oct 15 06:15:40 AM UTC 24 |
| Peak memory | 264304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285173250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2285173250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2422157768 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 62134490693 ps |
| CPU time | 156.08 seconds |
| Started | Oct 15 06:14:22 AM UTC 24 |
| Finished | Oct 15 06:17:01 AM UTC 24 |
| Peak memory | 262348 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422157768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.2422157768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode.970585199 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 217464829 ps |
| CPU time | 15.01 seconds |
| Started | Oct 15 06:14:19 AM UTC 24 |
| Finished | Oct 15 06:14:36 AM UTC 24 |
| Peak memory | 251924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970585199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.970585199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.4222312002 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 639432471 ps |
| CPU time | 16.04 seconds |
| Started | Oct 15 06:14:19 AM UTC 24 |
| Finished | Oct 15 06:14:37 AM UTC 24 |
| Peak memory | 262200 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222312002 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.4222312002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_intercept.2745656047 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 1247330633 ps |
| CPU time | 23.3 seconds |
| Started | Oct 15 06:14:12 AM UTC 24 |
| Finished | Oct 15 06:14:37 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2745656047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2745656047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_mailbox.1245058941 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 3332415698 ps |
| CPU time | 49.66 seconds |
| Started | Oct 15 06:14:15 AM UTC 24 |
| Finished | Oct 15 06:15:06 AM UTC 24 |
| Peak memory | 235668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245058941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.1245058941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.424985512 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 1115498992 ps |
| CPU time | 15.92 seconds |
| Started | Oct 15 06:14:11 AM UTC 24 |
| Finished | Oct 15 06:14:28 AM UTC 24 |
| Peak memory | 252148 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424985512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.424985512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.732478203 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 1435073013 ps |
| CPU time | 10.86 seconds |
| Started | Oct 15 06:14:09 AM UTC 24 |
| Finished | Oct 15 06:14:21 AM UTC 24 |
| Peak memory | 251948 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732478203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.732478203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.4088088577 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 926018327 ps |
| CPU time | 12.27 seconds |
| Started | Oct 15 06:14:21 AM UTC 24 |
| Finished | Oct 15 06:14:34 AM UTC 24 |
| Peak memory | 234216 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088088577 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.4088088577 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.3667585784 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 8393758171 ps |
| CPU time | 168.92 seconds |
| Started | Oct 15 06:14:30 AM UTC 24 |
| Finished | Oct 15 06:17:22 AM UTC 24 |
| Peak memory | 262324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667585784 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.3667585784 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_all.1860578277 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 7547739859 ps |
| CPU time | 32.65 seconds |
| Started | Oct 15 06:14:06 AM UTC 24 |
| Finished | Oct 15 06:14:40 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860578277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1860578277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.3987224985 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 466515726 ps |
| CPU time | 6.69 seconds |
| Started | Oct 15 06:14:06 AM UTC 24 |
| Finished | Oct 15 06:14:14 AM UTC 24 |
| Peak memory | 228232 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987224985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.3987224985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_rw.2831850964 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 472228387 ps |
| CPU time | 2.2 seconds |
| Started | Oct 15 06:14:08 AM UTC 24 |
| Finished | Oct 15 06:14:11 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831850964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2831850964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.427591795 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 59240100 ps |
| CPU time | 1.09 seconds |
| Started | Oct 15 06:14:08 AM UTC 24 |
| Finished | Oct 15 06:14:10 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427591795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.427591795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_upload.28488079 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 21999194653 ps |
| CPU time | 20.73 seconds |
| Started | Oct 15 06:14:15 AM UTC 24 |
| Finished | Oct 15 06:14:37 AM UTC 24 |
| Peak memory | 235764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28488079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.28488079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/36.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_alert_test.1831588211 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 12809281 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 06:14:53 AM UTC 24 |
| Finished | Oct 15 06:14:55 AM UTC 24 |
| Peak memory | 214600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831588211 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.1831588211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_cfg_cmd.919809687 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 384215672 ps |
| CPU time | 4.62 seconds |
| Started | Oct 15 06:14:39 AM UTC 24 |
| Finished | Oct 15 06:14:45 AM UTC 24 |
| Peak memory | 235764 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919809687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.919809687 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_csb_read.1800063676 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 59845130 ps |
| CPU time | 1.19 seconds |
| Started | Oct 15 06:14:30 AM UTC 24 |
| Finished | Oct 15 06:14:32 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800063676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1800063676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_all.1288469374 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 2081131887 ps |
| CPU time | 49.55 seconds |
| Started | Oct 15 06:14:46 AM UTC 24 |
| Finished | Oct 15 06:15:38 AM UTC 24 |
| Peak memory | 268284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288469374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1288469374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.1468565881 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 115646209709 ps |
| CPU time | 173.39 seconds |
| Started | Oct 15 06:14:46 AM UTC 24 |
| Finished | Oct 15 06:17:43 AM UTC 24 |
| Peak memory | 264560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468565881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1468565881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1674869460 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 4202504707 ps |
| CPU time | 129.37 seconds |
| Started | Oct 15 06:14:48 AM UTC 24 |
| Finished | Oct 15 06:17:00 AM UTC 24 |
| Peak memory | 278880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674869460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.1674869460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode.521303791 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 890303156 ps |
| CPU time | 13.24 seconds |
| Started | Oct 15 06:14:42 AM UTC 24 |
| Finished | Oct 15 06:14:56 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521303791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.521303791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.2499187836 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 3289186527 ps |
| CPU time | 78.35 seconds |
| Started | Oct 15 06:14:42 AM UTC 24 |
| Finished | Oct 15 06:16:02 AM UTC 24 |
| Peak memory | 278860 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499187836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.2499187836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_intercept.1883664691 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 1111733907 ps |
| CPU time | 16.65 seconds |
| Started | Oct 15 06:14:39 AM UTC 24 |
| Finished | Oct 15 06:14:57 AM UTC 24 |
| Peak memory | 235352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883664691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1883664691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_mailbox.1781025149 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 1296821686 ps |
| CPU time | 13.66 seconds |
| Started | Oct 15 06:14:39 AM UTC 24 |
| Finished | Oct 15 06:14:54 AM UTC 24 |
| Peak memory | 245760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781025149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1781025149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.3216904460 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3573042928 ps |
| CPU time | 5.97 seconds |
| Started | Oct 15 06:14:37 AM UTC 24 |
| Finished | Oct 15 06:14:45 AM UTC 24 |
| Peak memory | 235640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216904460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.3216904460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.3361982967 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 33019933409 ps |
| CPU time | 24.09 seconds |
| Started | Oct 15 06:14:37 AM UTC 24 |
| Finished | Oct 15 06:15:03 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361982967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3361982967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.2360188834 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 518829603 ps |
| CPU time | 5.42 seconds |
| Started | Oct 15 06:14:46 AM UTC 24 |
| Finished | Oct 15 06:14:53 AM UTC 24 |
| Peak memory | 229960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360188834 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.2360188834 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.3065405848 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 3983820264 ps |
| CPU time | 82.16 seconds |
| Started | Oct 15 06:14:50 AM UTC 24 |
| Finished | Oct 15 06:16:14 AM UTC 24 |
| Peak memory | 252112 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3065405848 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.3065405848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_all.3106166384 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 16005971023 ps |
| CPU time | 37.19 seconds |
| Started | Oct 15 06:14:33 AM UTC 24 |
| Finished | Oct 15 06:15:12 AM UTC 24 |
| Peak memory | 228340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106166384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3106166384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.2384017067 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 16119845863 ps |
| CPU time | 12.21 seconds |
| Started | Oct 15 06:14:33 AM UTC 24 |
| Finished | Oct 15 06:14:47 AM UTC 24 |
| Peak memory | 228464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2384017067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2384017067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_rw.4053106416 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 213489432 ps |
| CPU time | 1.99 seconds |
| Started | Oct 15 06:14:37 AM UTC 24 |
| Finished | Oct 15 06:14:41 AM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053106416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.4053106416 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.2295684210 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 70032871 ps |
| CPU time | 1.46 seconds |
| Started | Oct 15 06:14:36 AM UTC 24 |
| Finished | Oct 15 06:14:38 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295684210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2295684210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_upload.26446044 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 4746223418 ps |
| CPU time | 11.25 seconds |
| Started | Oct 15 06:14:39 AM UTC 24 |
| Finished | Oct 15 06:14:52 AM UTC 24 |
| Peak memory | 235568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26446044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_de vice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.26446044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/37.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_alert_test.923557555 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 13708535 ps |
| CPU time | 1.14 seconds |
| Started | Oct 15 06:15:13 AM UTC 24 |
| Finished | Oct 15 06:15:15 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923557555 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.923557555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_cfg_cmd.1152884061 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 586864295 ps |
| CPU time | 3.19 seconds |
| Started | Oct 15 06:15:04 AM UTC 24 |
| Finished | Oct 15 06:15:08 AM UTC 24 |
| Peak memory | 245836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152884061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1152884061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_csb_read.3129261282 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 22734665 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 06:14:53 AM UTC 24 |
| Finished | Oct 15 06:14:55 AM UTC 24 |
| Peak memory | 216708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129261282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.3129261282 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_all.293536518 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 1175923228 ps |
| CPU time | 8.12 seconds |
| Started | Oct 15 06:15:09 AM UTC 24 |
| Finished | Oct 15 06:15:18 AM UTC 24 |
| Peak memory | 232596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293536518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.293536518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.1124659617 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 49533162622 ps |
| CPU time | 556.68 seconds |
| Started | Oct 15 06:15:10 AM UTC 24 |
| Finished | Oct 15 06:24:34 AM UTC 24 |
| Peak memory | 262292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124659617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.1124659617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.2643811916 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 62288209826 ps |
| CPU time | 364.96 seconds |
| Started | Oct 15 06:15:10 AM UTC 24 |
| Finished | Oct 15 06:21:20 AM UTC 24 |
| Peak memory | 266612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643811916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.2643811916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode.872952945 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 1121396679 ps |
| CPU time | 14.37 seconds |
| Started | Oct 15 06:15:06 AM UTC 24 |
| Finished | Oct 15 06:15:21 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872952945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.872952945 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.2850257570 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 145826152 ps |
| CPU time | 1.35 seconds |
| Started | Oct 15 06:15:07 AM UTC 24 |
| Finished | Oct 15 06:15:10 AM UTC 24 |
| Peak memory | 226268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850257570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.2850257570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_intercept.447031192 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 848500252 ps |
| CPU time | 5.33 seconds |
| Started | Oct 15 06:14:58 AM UTC 24 |
| Finished | Oct 15 06:15:05 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447031192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.447031192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_mailbox.3642075547 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 755154051 ps |
| CPU time | 14.8 seconds |
| Started | Oct 15 06:14:59 AM UTC 24 |
| Finished | Oct 15 06:15:15 AM UTC 24 |
| Peak memory | 245748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642075547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3642075547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.3493437286 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 2985113881 ps |
| CPU time | 12.8 seconds |
| Started | Oct 15 06:14:58 AM UTC 24 |
| Finished | Oct 15 06:15:12 AM UTC 24 |
| Peak memory | 242716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493437286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.3493437286 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.3803530743 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 585714123 ps |
| CPU time | 9.59 seconds |
| Started | Oct 15 06:14:58 AM UTC 24 |
| Finished | Oct 15 06:15:09 AM UTC 24 |
| Peak memory | 251960 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803530743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3803530743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.791098408 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 277407149 ps |
| CPU time | 5.89 seconds |
| Started | Oct 15 06:15:07 AM UTC 24 |
| Finished | Oct 15 06:15:14 AM UTC 24 |
| Peak memory | 232084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791098408 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.791098408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_stress_all.960253114 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 40758670 ps |
| CPU time | 1.43 seconds |
| Started | Oct 15 06:15:11 AM UTC 24 |
| Finished | Oct 15 06:15:14 AM UTC 24 |
| Peak memory | 216888 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960253114 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.960253114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_all.149042815 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 16237042313 ps |
| CPU time | 29.09 seconds |
| Started | Oct 15 06:14:55 AM UTC 24 |
| Finished | Oct 15 06:15:25 AM UTC 24 |
| Peak memory | 228500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149042815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.149042815 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.1582995458 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 21719410424 ps |
| CPU time | 27.48 seconds |
| Started | Oct 15 06:14:55 AM UTC 24 |
| Finished | Oct 15 06:15:24 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582995458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1582995458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_rw.2480373037 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 105774187 ps |
| CPU time | 1.67 seconds |
| Started | Oct 15 06:14:56 AM UTC 24 |
| Finished | Oct 15 06:14:59 AM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480373037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2480373037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.1408073563 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 65286134 ps |
| CPU time | 1.33 seconds |
| Started | Oct 15 06:14:56 AM UTC 24 |
| Finished | Oct 15 06:14:58 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408073563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.1408073563 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_upload.2951196211 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 1440243865 ps |
| CPU time | 8.23 seconds |
| Started | Oct 15 06:14:59 AM UTC 24 |
| Finished | Oct 15 06:15:09 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951196211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2951196211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/38.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_alert_test.3294940742 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 36471504 ps |
| CPU time | 1.14 seconds |
| Started | Oct 15 06:15:34 AM UTC 24 |
| Finished | Oct 15 06:15:36 AM UTC 24 |
| Peak memory | 214604 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3294940742 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.3294940742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_cfg_cmd.59208676 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 640036450 ps |
| CPU time | 8.75 seconds |
| Started | Oct 15 06:15:22 AM UTC 24 |
| Finished | Oct 15 06:15:32 AM UTC 24 |
| Peak memory | 245752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59208676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.59208676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_csb_read.67409036 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 16892660 ps |
| CPU time | 1.01 seconds |
| Started | Oct 15 06:15:14 AM UTC 24 |
| Finished | Oct 15 06:15:16 AM UTC 24 |
| Peak memory | 216768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67409036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.67409036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_all.1774258302 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 305584709 ps |
| CPU time | 10.53 seconds |
| Started | Oct 15 06:15:27 AM UTC 24 |
| Finished | Oct 15 06:15:39 AM UTC 24 |
| Peak memory | 235668 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774258302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1774258302 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.2254192684 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 3957342405 ps |
| CPU time | 21.73 seconds |
| Started | Oct 15 06:15:27 AM UTC 24 |
| Finished | Oct 15 06:15:50 AM UTC 24 |
| Peak memory | 230740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254192684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.2254192684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.2954542809 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 67757543119 ps |
| CPU time | 178.65 seconds |
| Started | Oct 15 06:15:28 AM UTC 24 |
| Finished | Oct 15 06:18:30 AM UTC 24 |
| Peak memory | 252084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2954542809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.2954542809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode.403237404 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 1797907009 ps |
| CPU time | 18.35 seconds |
| Started | Oct 15 06:15:22 AM UTC 24 |
| Finished | Oct 15 06:15:42 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403237404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.403237404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1064976462 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 5658580434 ps |
| CPU time | 125.02 seconds |
| Started | Oct 15 06:15:24 AM UTC 24 |
| Finished | Oct 15 06:17:32 AM UTC 24 |
| Peak memory | 278648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064976462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.1064976462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_intercept.2034885892 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 1793093315 ps |
| CPU time | 19.94 seconds |
| Started | Oct 15 06:15:20 AM UTC 24 |
| Finished | Oct 15 06:15:41 AM UTC 24 |
| Peak memory | 245848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034885892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.2034885892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_mailbox.1395142155 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 1194294089 ps |
| CPU time | 13.57 seconds |
| Started | Oct 15 06:15:20 AM UTC 24 |
| Finished | Oct 15 06:15:34 AM UTC 24 |
| Peak memory | 246004 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395142155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1395142155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.500968176 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 3105335466 ps |
| CPU time | 3.47 seconds |
| Started | Oct 15 06:15:17 AM UTC 24 |
| Finished | Oct 15 06:15:21 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500968176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.500968176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.2940421176 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 987605157 ps |
| CPU time | 7.69 seconds |
| Started | Oct 15 06:15:17 AM UTC 24 |
| Finished | Oct 15 06:15:26 AM UTC 24 |
| Peak memory | 235768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940421176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2940421176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.348302808 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 1197182829 ps |
| CPU time | 5.38 seconds |
| Started | Oct 15 06:15:27 AM UTC 24 |
| Finished | Oct 15 06:15:34 AM UTC 24 |
| Peak memory | 230084 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348302808 -assert nopostproc +UVM_TESTNAME=spi_device_ base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.348302808 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.606398890 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 5183546546 ps |
| CPU time | 118.92 seconds |
| Started | Oct 15 06:15:34 AM UTC 24 |
| Finished | Oct 15 06:17:35 AM UTC 24 |
| Peak memory | 278704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606398890 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.606398890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.1104228392 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 2754083993 ps |
| CPU time | 15.29 seconds |
| Started | Oct 15 06:15:15 AM UTC 24 |
| Finished | Oct 15 06:15:32 AM UTC 24 |
| Peak memory | 228292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104228392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1104228392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_rw.1334600726 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 58867194 ps |
| CPU time | 1.57 seconds |
| Started | Oct 15 06:15:16 AM UTC 24 |
| Finished | Oct 15 06:15:18 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334600726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.1334600726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.3169964474 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 73896582 ps |
| CPU time | 1.39 seconds |
| Started | Oct 15 06:15:16 AM UTC 24 |
| Finished | Oct 15 06:15:18 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3169964474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3169964474 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_upload.1969429182 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 896284183 ps |
| CPU time | 6.66 seconds |
| Started | Oct 15 06:15:20 AM UTC 24 |
| Finished | Oct 15 06:15:27 AM UTC 24 |
| Peak memory | 245976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969429182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1969429182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/39.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_alert_test.2577385410 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 13774194 ps |
| CPU time | 0.98 seconds |
| Started | Oct 15 05:59:49 AM UTC 24 |
| Finished | Oct 15 05:59:51 AM UTC 24 |
| Peak memory | 214540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577385410 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2577385410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_cfg_cmd.2880272549 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 32399578 ps |
| CPU time | 3.29 seconds |
| Started | Oct 15 05:59:22 AM UTC 24 |
| Finished | Oct 15 05:59:26 AM UTC 24 |
| Peak memory | 245488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880272549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.2880272549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_csb_read.264897266 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 40096680 ps |
| CPU time | 1.14 seconds |
| Started | Oct 15 05:59:00 AM UTC 24 |
| Finished | Oct 15 05:59:02 AM UTC 24 |
| Peak memory | 217064 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264897266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.264897266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_all.2650664562 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 77747934299 ps |
| CPU time | 231.74 seconds |
| Started | Oct 15 05:59:33 AM UTC 24 |
| Finished | Oct 15 06:03:29 AM UTC 24 |
| Peak memory | 262288 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650664562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2650664562 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.4273344279 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 7976140378 ps |
| CPU time | 76.73 seconds |
| Started | Oct 15 05:59:38 AM UTC 24 |
| Finished | Oct 15 06:00:56 AM UTC 24 |
| Peak memory | 262324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273344279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.4273344279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.3373544581 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 145296379021 ps |
| CPU time | 130.13 seconds |
| Started | Oct 15 05:59:41 AM UTC 24 |
| Finished | Oct 15 06:01:53 AM UTC 24 |
| Peak memory | 262508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3373544581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.3373544581 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.156962997 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 12691330233 ps |
| CPU time | 41.92 seconds |
| Started | Oct 15 05:59:27 AM UTC 24 |
| Finished | Oct 15 06:00:11 AM UTC 24 |
| Peak memory | 252300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156962997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.156962997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_intercept.2923095313 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 127366188 ps |
| CPU time | 6.59 seconds |
| Started | Oct 15 05:59:14 AM UTC 24 |
| Finished | Oct 15 05:59:21 AM UTC 24 |
| Peak memory | 245824 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923095313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.2923095313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_mailbox.3631140192 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 11393344952 ps |
| CPU time | 26.69 seconds |
| Started | Oct 15 05:59:16 AM UTC 24 |
| Finished | Oct 15 05:59:44 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631140192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.3631140192 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.2715339539 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 5759226370 ps |
| CPU time | 22.07 seconds |
| Started | Oct 15 05:59:14 AM UTC 24 |
| Finished | Oct 15 05:59:37 AM UTC 24 |
| Peak memory | 245868 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715339539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.2715339539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.3704605531 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 1852543976 ps |
| CPU time | 11.94 seconds |
| Started | Oct 15 05:59:13 AM UTC 24 |
| Finished | Oct 15 05:59:26 AM UTC 24 |
| Peak memory | 245804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704605531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.3704605531 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.3051892607 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 13801556469 ps |
| CPU time | 24.36 seconds |
| Started | Oct 15 05:59:30 AM UTC 24 |
| Finished | Oct 15 05:59:56 AM UTC 24 |
| Peak memory | 232144 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051892607 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.3051892607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_sec_cm.2694234390 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 270819526 ps |
| CPU time | 1.75 seconds |
| Started | Oct 15 05:59:46 AM UTC 24 |
| Finished | Oct 15 05:59:49 AM UTC 24 |
| Peak memory | 257760 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694234390 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2694234390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_stress_all.1800935801 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 144173814104 ps |
| CPU time | 337.1 seconds |
| Started | Oct 15 05:59:45 AM UTC 24 |
| Finished | Oct 15 06:05:26 AM UTC 24 |
| Peak memory | 266644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800935801 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.1800935801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_all.2588184475 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 14922877607 ps |
| CPU time | 49.25 seconds |
| Started | Oct 15 05:59:05 AM UTC 24 |
| Finished | Oct 15 05:59:56 AM UTC 24 |
| Peak memory | 228496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588184475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2588184475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.895114962 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 1630772064 ps |
| CPU time | 7.65 seconds |
| Started | Oct 15 05:59:03 AM UTC 24 |
| Finished | Oct 15 05:59:12 AM UTC 24 |
| Peak memory | 228172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895114962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.895114962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_rw.3607162061 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 77684265 ps |
| CPU time | 2.35 seconds |
| Started | Oct 15 05:59:09 AM UTC 24 |
| Finished | Oct 15 05:59:13 AM UTC 24 |
| Peak memory | 218252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607162061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3607162061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.2807559733 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 199491111 ps |
| CPU time | 1.39 seconds |
| Started | Oct 15 05:59:06 AM UTC 24 |
| Finished | Oct 15 05:59:09 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807559733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.2807559733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/4.spi_device_upload.1343083036 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 962981005 ps |
| CPU time | 14.77 seconds |
| Started | Oct 15 05:59:17 AM UTC 24 |
| Finished | Oct 15 05:59:33 AM UTC 24 |
| Peak memory | 245832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343083036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.1343083036 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/4.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_alert_test.2692373627 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 11926593 ps |
| CPU time | 1.08 seconds |
| Started | Oct 15 06:15:49 AM UTC 24 |
| Finished | Oct 15 06:15:51 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692373627 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.2692373627 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_cfg_cmd.320056381 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 157659191 ps |
| CPU time | 4.61 seconds |
| Started | Oct 15 06:15:42 AM UTC 24 |
| Finished | Oct 15 06:15:48 AM UTC 24 |
| Peak memory | 245748 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320056381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.320056381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_csb_read.2171994746 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 40898102 ps |
| CPU time | 1.29 seconds |
| Started | Oct 15 06:15:35 AM UTC 24 |
| Finished | Oct 15 06:15:38 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171994746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2171994746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.4135952557 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 1135076406 ps |
| CPU time | 33.82 seconds |
| Started | Oct 15 06:15:47 AM UTC 24 |
| Finished | Oct 15 06:16:23 AM UTC 24 |
| Peak memory | 268528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135952557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.4135952557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.153785413 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 133026643318 ps |
| CPU time | 171.29 seconds |
| Started | Oct 15 06:15:48 AM UTC 24 |
| Finished | Oct 15 06:18:41 AM UTC 24 |
| Peak memory | 268460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153785413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.153785413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1100253035 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 8927499637 ps |
| CPU time | 51.54 seconds |
| Started | Oct 15 06:15:48 AM UTC 24 |
| Finished | Oct 15 06:16:41 AM UTC 24 |
| Peak memory | 268460 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100253035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.1100253035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode.2203254174 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 34538476 ps |
| CPU time | 3.55 seconds |
| Started | Oct 15 06:15:44 AM UTC 24 |
| Finished | Oct 15 06:15:48 AM UTC 24 |
| Peak memory | 245752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203254174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2203254174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.234850851 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 39185832022 ps |
| CPU time | 139.71 seconds |
| Started | Oct 15 06:15:44 AM UTC 24 |
| Finished | Oct 15 06:18:06 AM UTC 24 |
| Peak memory | 266224 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234850851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.234850851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_intercept.1437178289 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 574638333 ps |
| CPU time | 5.07 seconds |
| Started | Oct 15 06:15:40 AM UTC 24 |
| Finished | Oct 15 06:15:47 AM UTC 24 |
| Peak memory | 235520 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437178289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1437178289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_mailbox.1021325951 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 3980207012 ps |
| CPU time | 18.09 seconds |
| Started | Oct 15 06:15:42 AM UTC 24 |
| Finished | Oct 15 06:16:01 AM UTC 24 |
| Peak memory | 247952 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021325951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.1021325951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.1857600251 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 8211984528 ps |
| CPU time | 16.72 seconds |
| Started | Oct 15 06:15:40 AM UTC 24 |
| Finished | Oct 15 06:15:58 AM UTC 24 |
| Peak memory | 235644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857600251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.1857600251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.4015002546 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 298177652 ps |
| CPU time | 6.96 seconds |
| Started | Oct 15 06:15:39 AM UTC 24 |
| Finished | Oct 15 06:15:47 AM UTC 24 |
| Peak memory | 235680 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015002546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.4015002546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.2607562414 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1090968403 ps |
| CPU time | 11.07 seconds |
| Started | Oct 15 06:15:45 AM UTC 24 |
| Finished | Oct 15 06:15:57 AM UTC 24 |
| Peak memory | 232068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607562414 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.2607562414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.227974388 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 14237721625 ps |
| CPU time | 19.28 seconds |
| Started | Oct 15 06:15:49 AM UTC 24 |
| Finished | Oct 15 06:16:10 AM UTC 24 |
| Peak memory | 230492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227974388 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.227974388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.55715503 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 4086054900 ps |
| CPU time | 31.91 seconds |
| Started | Oct 15 06:15:35 AM UTC 24 |
| Finished | Oct 15 06:16:09 AM UTC 24 |
| Peak memory | 228328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55715503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.55715503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.695412992 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 1405493733 ps |
| CPU time | 9.47 seconds |
| Started | Oct 15 06:15:35 AM UTC 24 |
| Finished | Oct 15 06:15:46 AM UTC 24 |
| Peak memory | 228180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695412992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.695412992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_rw.3989490 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 207140804 ps |
| CPU time | 1.5 seconds |
| Started | Oct 15 06:15:39 AM UTC 24 |
| Finished | Oct 15 06:15:41 AM UTC 24 |
| Peak memory | 216436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3989490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_dev ice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.3989490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.1925858630 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 220257408 ps |
| CPU time | 1.46 seconds |
| Started | Oct 15 06:15:37 AM UTC 24 |
| Finished | Oct 15 06:15:39 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925858630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1925858630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_upload.2622024550 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 233807626 ps |
| CPU time | 3.72 seconds |
| Started | Oct 15 06:15:42 AM UTC 24 |
| Finished | Oct 15 06:15:47 AM UTC 24 |
| Peak memory | 235568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2622024550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.2622024550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/40.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.1696817381 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 20891415 ps |
| CPU time | 1.12 seconds |
| Started | Oct 15 06:16:05 AM UTC 24 |
| Finished | Oct 15 06:16:08 AM UTC 24 |
| Peak memory | 214544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696817381 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.1696817381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.935989034 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 216678082 ps |
| CPU time | 5.93 seconds |
| Started | Oct 15 06:15:57 AM UTC 24 |
| Finished | Oct 15 06:16:05 AM UTC 24 |
| Peak memory | 235568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935989034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.935989034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_csb_read.3926574831 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 35956651 ps |
| CPU time | 1.23 seconds |
| Started | Oct 15 06:15:49 AM UTC 24 |
| Finished | Oct 15 06:15:51 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926574831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.3926574831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.2727095966 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 934877892 ps |
| CPU time | 10.09 seconds |
| Started | Oct 15 06:16:02 AM UTC 24 |
| Finished | Oct 15 06:16:14 AM UTC 24 |
| Peak memory | 251692 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727095966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.2727095966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.3817429679 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 636096420078 ps |
| CPU time | 435.21 seconds |
| Started | Oct 15 06:16:04 AM UTC 24 |
| Finished | Oct 15 06:23:26 AM UTC 24 |
| Peak memory | 278876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3817429679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3817429679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.1522391476 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 7374477273 ps |
| CPU time | 57.13 seconds |
| Started | Oct 15 06:16:04 AM UTC 24 |
| Finished | Oct 15 06:17:03 AM UTC 24 |
| Peak memory | 264624 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522391476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.1522391476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.2052484439 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 1948830705 ps |
| CPU time | 44.52 seconds |
| Started | Oct 15 06:15:59 AM UTC 24 |
| Finished | Oct 15 06:16:45 AM UTC 24 |
| Peak memory | 235568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052484439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2052484439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2119466899 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 10667521832 ps |
| CPU time | 128.83 seconds |
| Started | Oct 15 06:16:00 AM UTC 24 |
| Finished | Oct 15 06:18:11 AM UTC 24 |
| Peak memory | 268600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2119466899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.2119466899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.3162540684 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 8197770192 ps |
| CPU time | 9.69 seconds |
| Started | Oct 15 06:15:55 AM UTC 24 |
| Finished | Oct 15 06:16:06 AM UTC 24 |
| Peak memory | 235580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162540684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3162540684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.1653046746 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 35374939149 ps |
| CPU time | 27.19 seconds |
| Started | Oct 15 06:15:56 AM UTC 24 |
| Finished | Oct 15 06:16:25 AM UTC 24 |
| Peak memory | 245732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653046746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.1653046746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.3712460439 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 1212726110 ps |
| CPU time | 9.15 seconds |
| Started | Oct 15 06:15:54 AM UTC 24 |
| Finished | Oct 15 06:16:04 AM UTC 24 |
| Peak memory | 245752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712460439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.3712460439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.543560178 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 100208048 ps |
| CPU time | 3.44 seconds |
| Started | Oct 15 06:15:52 AM UTC 24 |
| Finished | Oct 15 06:15:57 AM UTC 24 |
| Peak memory | 245996 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=543560178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.543560178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3108420568 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 128665300 ps |
| CPU time | 5.5 seconds |
| Started | Oct 15 06:16:02 AM UTC 24 |
| Finished | Oct 15 06:16:09 AM UTC 24 |
| Peak memory | 231844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108420568 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.3108420568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.1862036743 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 47074824 ps |
| CPU time | 1.5 seconds |
| Started | Oct 15 06:16:04 AM UTC 24 |
| Finished | Oct 15 06:16:07 AM UTC 24 |
| Peak memory | 216732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1862036743 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.1862036743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.1825255331 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 2505325047 ps |
| CPU time | 17.75 seconds |
| Started | Oct 15 06:15:51 AM UTC 24 |
| Finished | Oct 15 06:16:10 AM UTC 24 |
| Peak memory | 232464 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825255331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1825255331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.99243498 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 883005162 ps |
| CPU time | 10.04 seconds |
| Started | Oct 15 06:15:51 AM UTC 24 |
| Finished | Oct 15 06:16:02 AM UTC 24 |
| Peak memory | 228204 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99243498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.99243498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_rw.3824731591 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 222081068 ps |
| CPU time | 2.07 seconds |
| Started | Oct 15 06:15:52 AM UTC 24 |
| Finished | Oct 15 06:15:55 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824731591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3824731591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.1417536524 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 113925875 ps |
| CPU time | 1.34 seconds |
| Started | Oct 15 06:15:52 AM UTC 24 |
| Finished | Oct 15 06:15:55 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417536524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.1417536524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_upload.2505451586 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 461967645 ps |
| CPU time | 3.34 seconds |
| Started | Oct 15 06:15:56 AM UTC 24 |
| Finished | Oct 15 06:16:01 AM UTC 24 |
| Peak memory | 235488 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505451586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.2505451586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/41.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.4119035404 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 40780423 ps |
| CPU time | 1.08 seconds |
| Started | Oct 15 06:16:24 AM UTC 24 |
| Finished | Oct 15 06:16:26 AM UTC 24 |
| Peak memory | 214456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119035404 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.4119035404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3507335074 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 2665845763 ps |
| CPU time | 12.65 seconds |
| Started | Oct 15 06:16:14 AM UTC 24 |
| Finished | Oct 15 06:16:27 AM UTC 24 |
| Peak memory | 245908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507335074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3507335074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2981434122 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 61162013 ps |
| CPU time | 1.2 seconds |
| Started | Oct 15 06:16:05 AM UTC 24 |
| Finished | Oct 15 06:16:08 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981434122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2981434122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.1690456706 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 7486857578 ps |
| CPU time | 129.55 seconds |
| Started | Oct 15 06:16:20 AM UTC 24 |
| Finished | Oct 15 06:18:32 AM UTC 24 |
| Peak memory | 301268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690456706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1690456706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.3709902504 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 3016076016 ps |
| CPU time | 36.82 seconds |
| Started | Oct 15 06:16:21 AM UTC 24 |
| Finished | Oct 15 06:17:00 AM UTC 24 |
| Peak memory | 252268 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709902504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3709902504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.4246634184 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 7672657646 ps |
| CPU time | 40.54 seconds |
| Started | Oct 15 06:16:21 AM UTC 24 |
| Finished | Oct 15 06:17:04 AM UTC 24 |
| Peak memory | 252040 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246634184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.4246634184 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.1075101672 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 205427522 ps |
| CPU time | 6.58 seconds |
| Started | Oct 15 06:16:15 AM UTC 24 |
| Finished | Oct 15 06:16:23 AM UTC 24 |
| Peak memory | 245836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075101672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1075101672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.4021803149 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 16653702700 ps |
| CPU time | 155.5 seconds |
| Started | Oct 15 06:16:15 AM UTC 24 |
| Finished | Oct 15 06:18:54 AM UTC 24 |
| Peak memory | 262256 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021803149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.4021803149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.2979076943 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 532179170 ps |
| CPU time | 6.81 seconds |
| Started | Oct 15 06:16:11 AM UTC 24 |
| Finished | Oct 15 06:16:19 AM UTC 24 |
| Peak memory | 245784 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979076943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.2979076943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.1726567326 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 515982402 ps |
| CPU time | 6.95 seconds |
| Started | Oct 15 06:16:11 AM UTC 24 |
| Finished | Oct 15 06:16:20 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726567326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1726567326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2288214391 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 1850986109 ps |
| CPU time | 16.14 seconds |
| Started | Oct 15 06:16:11 AM UTC 24 |
| Finished | Oct 15 06:16:29 AM UTC 24 |
| Peak memory | 245752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288214391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.2288214391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.2723355907 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 2133395402 ps |
| CPU time | 15.34 seconds |
| Started | Oct 15 06:16:11 AM UTC 24 |
| Finished | Oct 15 06:16:28 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723355907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2723355907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2342867341 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 1036606894 ps |
| CPU time | 6.83 seconds |
| Started | Oct 15 06:16:18 AM UTC 24 |
| Finished | Oct 15 06:16:26 AM UTC 24 |
| Peak memory | 234212 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342867341 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.2342867341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.374230657 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 136578575955 ps |
| CPU time | 411.9 seconds |
| Started | Oct 15 06:16:22 AM UTC 24 |
| Finished | Oct 15 06:23:21 AM UTC 24 |
| Peak memory | 278736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374230657 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.374230657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.108897639 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 1807080409 ps |
| CPU time | 13.4 seconds |
| Started | Oct 15 06:16:08 AM UTC 24 |
| Finished | Oct 15 06:16:23 AM UTC 24 |
| Peak memory | 228304 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108897639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.108897639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.85552179 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 10752410390 ps |
| CPU time | 13.48 seconds |
| Started | Oct 15 06:16:07 AM UTC 24 |
| Finished | Oct 15 06:16:22 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85552179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.85552179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.2379540592 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 53733417 ps |
| CPU time | 1.92 seconds |
| Started | Oct 15 06:16:09 AM UTC 24 |
| Finished | Oct 15 06:16:12 AM UTC 24 |
| Peak memory | 226964 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379540592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2379540592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.972138287 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 26210240 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 06:16:09 AM UTC 24 |
| Finished | Oct 15 06:16:12 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972138287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.972138287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.1836266564 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 7276877139 ps |
| CPU time | 11.52 seconds |
| Started | Oct 15 06:16:12 AM UTC 24 |
| Finished | Oct 15 06:16:25 AM UTC 24 |
| Peak memory | 235640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836266564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1836266564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/42.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.3011619240 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 257729340 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 06:16:38 AM UTC 24 |
| Finished | Oct 15 06:16:40 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011619240 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.3011619240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1646987843 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 2377359180 ps |
| CPU time | 9.26 seconds |
| Started | Oct 15 06:16:30 AM UTC 24 |
| Finished | Oct 15 06:16:40 AM UTC 24 |
| Peak memory | 245844 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646987843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1646987843 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.2802162114 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 39156712 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 06:16:24 AM UTC 24 |
| Finished | Oct 15 06:16:27 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802162114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.2802162114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.2787442754 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 25960706717 ps |
| CPU time | 113.3 seconds |
| Started | Oct 15 06:16:33 AM UTC 24 |
| Finished | Oct 15 06:18:28 AM UTC 24 |
| Peak memory | 262456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787442754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2787442754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.3196609118 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 33680269052 ps |
| CPU time | 77.71 seconds |
| Started | Oct 15 06:16:33 AM UTC 24 |
| Finished | Oct 15 06:17:52 AM UTC 24 |
| Peak memory | 252076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196609118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3196609118 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.4087417328 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 7186351429 ps |
| CPU time | 92.59 seconds |
| Started | Oct 15 06:16:35 AM UTC 24 |
| Finished | Oct 15 06:18:10 AM UTC 24 |
| Peak memory | 268496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087417328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.4087417328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.2395717655 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 191254041 ps |
| CPU time | 4.31 seconds |
| Started | Oct 15 06:16:31 AM UTC 24 |
| Finished | Oct 15 06:16:37 AM UTC 24 |
| Peak memory | 246028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395717655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2395717655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.3114972251 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 16147120356 ps |
| CPU time | 172.41 seconds |
| Started | Oct 15 06:16:31 AM UTC 24 |
| Finished | Oct 15 06:19:27 AM UTC 24 |
| Peak memory | 264332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3114972251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.3114972251 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.1295870301 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 4018496795 ps |
| CPU time | 6.23 seconds |
| Started | Oct 15 06:16:30 AM UTC 24 |
| Finished | Oct 15 06:16:37 AM UTC 24 |
| Peak memory | 245848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295870301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1295870301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.2064893217 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 15005237991 ps |
| CPU time | 40.87 seconds |
| Started | Oct 15 06:16:30 AM UTC 24 |
| Finished | Oct 15 06:17:12 AM UTC 24 |
| Peak memory | 245848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064893217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2064893217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.1477515797 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 30209147 ps |
| CPU time | 2.43 seconds |
| Started | Oct 15 06:16:28 AM UTC 24 |
| Finished | Oct 15 06:16:31 AM UTC 24 |
| Peak memory | 235352 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477515797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.1477515797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.4047589709 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 1242172945 ps |
| CPU time | 9.89 seconds |
| Started | Oct 15 06:16:28 AM UTC 24 |
| Finished | Oct 15 06:16:39 AM UTC 24 |
| Peak memory | 246008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047589709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.4047589709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.2213529026 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 10421678865 ps |
| CPU time | 17.63 seconds |
| Started | Oct 15 06:16:31 AM UTC 24 |
| Finished | Oct 15 06:16:50 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213529026 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.2213529026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.618313441 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 165473060 ps |
| CPU time | 1.52 seconds |
| Started | Oct 15 06:16:38 AM UTC 24 |
| Finished | Oct 15 06:16:40 AM UTC 24 |
| Peak memory | 216968 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618313441 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.618313441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.368951129 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 889746250 ps |
| CPU time | 3.9 seconds |
| Started | Oct 15 06:16:26 AM UTC 24 |
| Finished | Oct 15 06:16:32 AM UTC 24 |
| Peak memory | 230380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368951129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.368951129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.2521222893 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 7956704531 ps |
| CPU time | 10.98 seconds |
| Started | Oct 15 06:16:24 AM UTC 24 |
| Finished | Oct 15 06:16:36 AM UTC 24 |
| Peak memory | 228124 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521222893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2521222893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.322071505 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 26951957 ps |
| CPU time | 1.2 seconds |
| Started | Oct 15 06:16:28 AM UTC 24 |
| Finished | Oct 15 06:16:30 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322071505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.322071505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1782535310 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 41656982 ps |
| CPU time | 1.3 seconds |
| Started | Oct 15 06:16:26 AM UTC 24 |
| Finished | Oct 15 06:16:29 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782535310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.1782535310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.3967041117 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 935937294 ps |
| CPU time | 7.92 seconds |
| Started | Oct 15 06:16:30 AM UTC 24 |
| Finished | Oct 15 06:16:39 AM UTC 24 |
| Peak memory | 245740 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3967041117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3967041117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/43.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.4193044886 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 37686319 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 06:17:01 AM UTC 24 |
| Finished | Oct 15 06:17:03 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193044886 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.4193044886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.2252595780 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 931952229 ps |
| CPU time | 15.72 seconds |
| Started | Oct 15 06:16:46 AM UTC 24 |
| Finished | Oct 15 06:17:03 AM UTC 24 |
| Peak memory | 235516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2252595780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2252595780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.2484874609 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 33582153 ps |
| CPU time | 1.21 seconds |
| Started | Oct 15 06:16:38 AM UTC 24 |
| Finished | Oct 15 06:16:40 AM UTC 24 |
| Peak memory | 216652 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484874609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2484874609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.879650393 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 6971871552 ps |
| CPU time | 64.28 seconds |
| Started | Oct 15 06:16:51 AM UTC 24 |
| Finished | Oct 15 06:17:57 AM UTC 24 |
| Peak memory | 262252 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879650393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.879650393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1444508673 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 33928191580 ps |
| CPU time | 371.69 seconds |
| Started | Oct 15 06:16:54 AM UTC 24 |
| Finished | Oct 15 06:23:11 AM UTC 24 |
| Peak memory | 262524 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444508673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1444508673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.275896970 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 37834215693 ps |
| CPU time | 77.15 seconds |
| Started | Oct 15 06:16:57 AM UTC 24 |
| Finished | Oct 15 06:18:16 AM UTC 24 |
| Peak memory | 262324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=275896970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.275896970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.3580475850 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 1840963246 ps |
| CPU time | 26.28 seconds |
| Started | Oct 15 06:16:46 AM UTC 24 |
| Finished | Oct 15 06:17:14 AM UTC 24 |
| Peak memory | 247884 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580475850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3580475850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.1352363963 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 43444795306 ps |
| CPU time | 182.37 seconds |
| Started | Oct 15 06:16:47 AM UTC 24 |
| Finished | Oct 15 06:19:53 AM UTC 24 |
| Peak memory | 278648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352363963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.1352363963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.1584825647 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 1296023431 ps |
| CPU time | 19.33 seconds |
| Started | Oct 15 06:16:42 AM UTC 24 |
| Finished | Oct 15 06:17:03 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584825647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1584825647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.3064430835 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 30227684 ps |
| CPU time | 2.8 seconds |
| Started | Oct 15 06:16:44 AM UTC 24 |
| Finished | Oct 15 06:16:47 AM UTC 24 |
| Peak memory | 235272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064430835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3064430835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.1943790007 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 10037722386 ps |
| CPU time | 19.27 seconds |
| Started | Oct 15 06:16:42 AM UTC 24 |
| Finished | Oct 15 06:17:03 AM UTC 24 |
| Peak memory | 250172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943790007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.1943790007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.2093803140 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 1202105566 ps |
| CPU time | 9.47 seconds |
| Started | Oct 15 06:16:42 AM UTC 24 |
| Finished | Oct 15 06:16:53 AM UTC 24 |
| Peak memory | 235704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093803140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2093803140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.3872999387 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 247627741 ps |
| CPU time | 7.01 seconds |
| Started | Oct 15 06:16:49 AM UTC 24 |
| Finished | Oct 15 06:16:57 AM UTC 24 |
| Peak memory | 234492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872999387 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.3872999387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.2953495592 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 162840723826 ps |
| CPU time | 157.08 seconds |
| Started | Oct 15 06:17:01 AM UTC 24 |
| Finished | Oct 15 06:19:41 AM UTC 24 |
| Peak memory | 278640 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953495592 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.2953495592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.1181608838 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 982059323 ps |
| CPU time | 22.19 seconds |
| Started | Oct 15 06:16:40 AM UTC 24 |
| Finished | Oct 15 06:17:04 AM UTC 24 |
| Peak memory | 228240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181608838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1181608838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.731154894 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 32707544 ps |
| CPU time | 0.99 seconds |
| Started | Oct 15 06:16:40 AM UTC 24 |
| Finished | Oct 15 06:16:42 AM UTC 24 |
| Peak memory | 216708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=731154894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.731154894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.718369473 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 32370229 ps |
| CPU time | 1.77 seconds |
| Started | Oct 15 06:16:42 AM UTC 24 |
| Finished | Oct 15 06:16:45 AM UTC 24 |
| Peak memory | 216744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718369473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.718369473 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.4198060669 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 67189894 ps |
| CPU time | 1.34 seconds |
| Started | Oct 15 06:16:40 AM UTC 24 |
| Finished | Oct 15 06:16:43 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198060669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.4198060669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.3045964573 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 6221380973 ps |
| CPU time | 30.04 seconds |
| Started | Oct 15 06:16:44 AM UTC 24 |
| Finished | Oct 15 06:17:15 AM UTC 24 |
| Peak memory | 252044 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045964573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3045964573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/44.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.3520187104 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 14950668 ps |
| CPU time | 0.95 seconds |
| Started | Oct 15 06:17:18 AM UTC 24 |
| Finished | Oct 15 06:17:20 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520187104 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.3520187104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.1826861321 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 169922932 ps |
| CPU time | 4.72 seconds |
| Started | Oct 15 06:17:08 AM UTC 24 |
| Finished | Oct 15 06:17:14 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826861321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1826861321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.962524151 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 34099534 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 06:17:02 AM UTC 24 |
| Finished | Oct 15 06:17:04 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962524151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.962524151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.2303863489 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 18716379962 ps |
| CPU time | 142.23 seconds |
| Started | Oct 15 06:17:15 AM UTC 24 |
| Finished | Oct 15 06:19:40 AM UTC 24 |
| Peak memory | 252156 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2303863489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.2303863489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.2488175899 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 10772694883 ps |
| CPU time | 113.18 seconds |
| Started | Oct 15 06:17:15 AM UTC 24 |
| Finished | Oct 15 06:19:11 AM UTC 24 |
| Peak memory | 252080 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488175899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2488175899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.997592892 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 92273200627 ps |
| CPU time | 311.9 seconds |
| Started | Oct 15 06:17:16 AM UTC 24 |
| Finished | Oct 15 06:22:32 AM UTC 24 |
| Peak memory | 268688 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=997592892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.997592892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.1507441462 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 159737771 ps |
| CPU time | 6.93 seconds |
| Started | Oct 15 06:17:13 AM UTC 24 |
| Finished | Oct 15 06:17:21 AM UTC 24 |
| Peak memory | 245836 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507441462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1507441462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2661455465 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 69088924641 ps |
| CPU time | 314.66 seconds |
| Started | Oct 15 06:17:13 AM UTC 24 |
| Finished | Oct 15 06:22:32 AM UTC 24 |
| Peak memory | 262196 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661455465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.2661455465 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.2435050326 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 758020778 ps |
| CPU time | 4.39 seconds |
| Started | Oct 15 06:17:06 AM UTC 24 |
| Finished | Oct 15 06:17:11 AM UTC 24 |
| Peak memory | 235508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2435050326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.2435050326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.1126294357 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 4399303885 ps |
| CPU time | 27.97 seconds |
| Started | Oct 15 06:17:06 AM UTC 24 |
| Finished | Oct 15 06:17:35 AM UTC 24 |
| Peak memory | 245820 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126294357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.1126294357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.1379626977 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 33647765307 ps |
| CPU time | 36.54 seconds |
| Started | Oct 15 06:17:06 AM UTC 24 |
| Finished | Oct 15 06:17:44 AM UTC 24 |
| Peak memory | 235580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379626977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.1379626977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.3995105525 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 4573991344 ps |
| CPU time | 36.23 seconds |
| Started | Oct 15 06:17:04 AM UTC 24 |
| Finished | Oct 15 06:17:42 AM UTC 24 |
| Peak memory | 262260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995105525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.3995105525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.1639990807 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 457204140 ps |
| CPU time | 4.71 seconds |
| Started | Oct 15 06:17:14 AM UTC 24 |
| Finished | Oct 15 06:17:20 AM UTC 24 |
| Peak memory | 234376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639990807 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.1639990807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.1918671831 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 33135922924 ps |
| CPU time | 271.75 seconds |
| Started | Oct 15 06:17:17 AM UTC 24 |
| Finished | Oct 15 06:21:53 AM UTC 24 |
| Peak memory | 268492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918671831 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.1918671831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3528959786 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 2148334815 ps |
| CPU time | 21.08 seconds |
| Started | Oct 15 06:17:04 AM UTC 24 |
| Finished | Oct 15 06:17:26 AM UTC 24 |
| Peak memory | 228560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528959786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3528959786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.628218541 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 1677711892 ps |
| CPU time | 9.45 seconds |
| Started | Oct 15 06:17:04 AM UTC 24 |
| Finished | Oct 15 06:17:14 AM UTC 24 |
| Peak memory | 228172 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628218541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.628218541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.372216484 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 52799697 ps |
| CPU time | 2.05 seconds |
| Started | Oct 15 06:17:04 AM UTC 24 |
| Finished | Oct 15 06:17:07 AM UTC 24 |
| Peak memory | 228320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=372216484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.372216484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3633649511 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 48455593 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 06:17:04 AM UTC 24 |
| Finished | Oct 15 06:17:06 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633649511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.3633649511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.1592260752 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 88526517 ps |
| CPU time | 4.69 seconds |
| Started | Oct 15 06:17:07 AM UTC 24 |
| Finished | Oct 15 06:17:13 AM UTC 24 |
| Peak memory | 235560 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592260752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1592260752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/45.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.1698591040 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 14201402 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 06:17:43 AM UTC 24 |
| Finished | Oct 15 06:17:45 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1698591040 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.1698591040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2092466644 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 7307485882 ps |
| CPU time | 23.5 seconds |
| Started | Oct 15 06:17:29 AM UTC 24 |
| Finished | Oct 15 06:17:53 AM UTC 24 |
| Peak memory | 246008 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2092466644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.2092466644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.351885484 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 77928179 ps |
| CPU time | 1.05 seconds |
| Started | Oct 15 06:17:18 AM UTC 24 |
| Finished | Oct 15 06:17:20 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351885484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.351885484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.3063528741 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 2704720985 ps |
| CPU time | 69.8 seconds |
| Started | Oct 15 06:17:33 AM UTC 24 |
| Finished | Oct 15 06:18:45 AM UTC 24 |
| Peak memory | 280908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063528741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.3063528741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.1049011992 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 21113898042 ps |
| CPU time | 122.88 seconds |
| Started | Oct 15 06:17:36 AM UTC 24 |
| Finished | Oct 15 06:19:41 AM UTC 24 |
| Peak memory | 280632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049011992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1049011992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.705534800 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 3933828188 ps |
| CPU time | 20.98 seconds |
| Started | Oct 15 06:17:36 AM UTC 24 |
| Finished | Oct 15 06:17:58 AM UTC 24 |
| Peak memory | 249924 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705534800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.705534800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.3645517363 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 82588768 ps |
| CPU time | 3.69 seconds |
| Started | Oct 15 06:17:30 AM UTC 24 |
| Finished | Oct 15 06:17:34 AM UTC 24 |
| Peak memory | 245752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645517363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3645517363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.1516030679 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 84257603261 ps |
| CPU time | 215.49 seconds |
| Started | Oct 15 06:17:32 AM UTC 24 |
| Finished | Oct 15 06:21:11 AM UTC 24 |
| Peak memory | 268428 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516030679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.1516030679 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.2822316730 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 4467210961 ps |
| CPU time | 14.81 seconds |
| Started | Oct 15 06:17:26 AM UTC 24 |
| Finished | Oct 15 06:17:42 AM UTC 24 |
| Peak memory | 245840 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822316730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2822316730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.208427381 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 282618016 ps |
| CPU time | 2.94 seconds |
| Started | Oct 15 06:17:27 AM UTC 24 |
| Finished | Oct 15 06:17:31 AM UTC 24 |
| Peak memory | 235184 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208427381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.208427381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.2639847862 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 184217994 ps |
| CPU time | 3.32 seconds |
| Started | Oct 15 06:17:24 AM UTC 24 |
| Finished | Oct 15 06:17:28 AM UTC 24 |
| Peak memory | 235508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639847862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.2639847862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.4230965690 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 242353099 ps |
| CPU time | 3.99 seconds |
| Started | Oct 15 06:17:24 AM UTC 24 |
| Finished | Oct 15 06:17:29 AM UTC 24 |
| Peak memory | 235432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230965690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4230965690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.2655691064 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 2390728536 ps |
| CPU time | 11.62 seconds |
| Started | Oct 15 06:17:32 AM UTC 24 |
| Finished | Oct 15 06:17:45 AM UTC 24 |
| Peak memory | 232264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655691064 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.2655691064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1994288191 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 37523399945 ps |
| CPU time | 299.06 seconds |
| Started | Oct 15 06:17:36 AM UTC 24 |
| Finished | Oct 15 06:22:40 AM UTC 24 |
| Peak memory | 280744 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994288191 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.1994288191 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.2716501151 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3022343810 ps |
| CPU time | 22.3 seconds |
| Started | Oct 15 06:17:21 AM UTC 24 |
| Finished | Oct 15 06:17:44 AM UTC 24 |
| Peak memory | 228500 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716501151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2716501151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2229154732 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 2930039130 ps |
| CPU time | 9.26 seconds |
| Started | Oct 15 06:17:21 AM UTC 24 |
| Finished | Oct 15 06:17:31 AM UTC 24 |
| Peak memory | 228588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229154732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.2229154732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.191545343 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 150763057 ps |
| CPU time | 1.68 seconds |
| Started | Oct 15 06:17:22 AM UTC 24 |
| Finished | Oct 15 06:17:25 AM UTC 24 |
| Peak memory | 217272 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191545343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.191545343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.1250574494 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 58332383 ps |
| CPU time | 1.27 seconds |
| Started | Oct 15 06:17:21 AM UTC 24 |
| Finished | Oct 15 06:17:23 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250574494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1250574494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.3314674575 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 14173427465 ps |
| CPU time | 33.69 seconds |
| Started | Oct 15 06:17:27 AM UTC 24 |
| Finished | Oct 15 06:18:02 AM UTC 24 |
| Peak memory | 235596 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314674575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3314674575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/46.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.1747757897 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 63720259 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 06:18:02 AM UTC 24 |
| Finished | Oct 15 06:18:04 AM UTC 24 |
| Peak memory | 216588 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747757897 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.1747757897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.163414332 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 142680532 ps |
| CPU time | 3.44 seconds |
| Started | Oct 15 06:17:51 AM UTC 24 |
| Finished | Oct 15 06:17:55 AM UTC 24 |
| Peak memory | 245752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163414332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.163414332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.2945658881 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 68484851 ps |
| CPU time | 1.19 seconds |
| Started | Oct 15 06:17:43 AM UTC 24 |
| Finished | Oct 15 06:17:45 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2945658881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2945658881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.727360463 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 1104777691 ps |
| CPU time | 8.6 seconds |
| Started | Oct 15 06:17:57 AM UTC 24 |
| Finished | Oct 15 06:18:07 AM UTC 24 |
| Peak memory | 249908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727360463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.727360463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.2935115267 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 10811883815 ps |
| CPU time | 82.31 seconds |
| Started | Oct 15 06:17:58 AM UTC 24 |
| Finished | Oct 15 06:19:23 AM UTC 24 |
| Peak memory | 262300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935115267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.2935115267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.546761348 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 87164864984 ps |
| CPU time | 213.35 seconds |
| Started | Oct 15 06:18:00 AM UTC 24 |
| Finished | Oct 15 06:21:37 AM UTC 24 |
| Peak memory | 262324 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546761348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.546761348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.2158084697 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 960440802 ps |
| CPU time | 11.05 seconds |
| Started | Oct 15 06:17:53 AM UTC 24 |
| Finished | Oct 15 06:18:05 AM UTC 24 |
| Peak memory | 235544 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158084697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2158084697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.3593301566 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 3507243413 ps |
| CPU time | 54.2 seconds |
| Started | Oct 15 06:17:55 AM UTC 24 |
| Finished | Oct 15 06:18:51 AM UTC 24 |
| Peak memory | 262284 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593301566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.3593301566 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.3637983927 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 3981066102 ps |
| CPU time | 47.48 seconds |
| Started | Oct 15 06:17:49 AM UTC 24 |
| Finished | Oct 15 06:18:38 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637983927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3637983927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.800840632 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 30539255180 ps |
| CPU time | 120.61 seconds |
| Started | Oct 15 06:17:49 AM UTC 24 |
| Finished | Oct 15 06:19:53 AM UTC 24 |
| Peak memory | 264340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800840632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.800840632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.3394472978 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 48134528 ps |
| CPU time | 3.14 seconds |
| Started | Oct 15 06:17:46 AM UTC 24 |
| Finished | Oct 15 06:17:50 AM UTC 24 |
| Peak memory | 245396 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394472978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.3394472978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.4193761897 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 41431928 ps |
| CPU time | 3.07 seconds |
| Started | Oct 15 06:17:46 AM UTC 24 |
| Finished | Oct 15 06:17:50 AM UTC 24 |
| Peak memory | 245484 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193761897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4193761897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.3034851243 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 240086567 ps |
| CPU time | 4.03 seconds |
| Started | Oct 15 06:17:56 AM UTC 24 |
| Finished | Oct 15 06:18:01 AM UTC 24 |
| Peak memory | 234612 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034851243 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.3034851243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.2194908205 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 112120267 ps |
| CPU time | 1.4 seconds |
| Started | Oct 15 06:18:00 AM UTC 24 |
| Finished | Oct 15 06:18:03 AM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194908205 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.2194908205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.3220434768 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 831740836 ps |
| CPU time | 7.49 seconds |
| Started | Oct 15 06:17:46 AM UTC 24 |
| Finished | Oct 15 06:17:54 AM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220434768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3220434768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2413158250 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 13880580060 ps |
| CPU time | 20.07 seconds |
| Started | Oct 15 06:17:44 AM UTC 24 |
| Finished | Oct 15 06:18:05 AM UTC 24 |
| Peak memory | 230292 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413158250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2413158250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.217644596 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 14673965 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 06:17:46 AM UTC 24 |
| Finished | Oct 15 06:17:48 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217644596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.217644596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.229168218 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 106909188 ps |
| CPU time | 1.38 seconds |
| Started | Oct 15 06:17:46 AM UTC 24 |
| Finished | Oct 15 06:17:48 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229168218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.229168218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.646553887 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 2234306043 ps |
| CPU time | 15.71 seconds |
| Started | Oct 15 06:17:51 AM UTC 24 |
| Finished | Oct 15 06:18:08 AM UTC 24 |
| Peak memory | 235852 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646553887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.646553887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/47.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.3714619078 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 16467551 ps |
| CPU time | 1.14 seconds |
| Started | Oct 15 06:18:14 AM UTC 24 |
| Finished | Oct 15 06:18:16 AM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714619078 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.3714619078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.1154018726 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 75205222 ps |
| CPU time | 2.98 seconds |
| Started | Oct 15 06:18:09 AM UTC 24 |
| Finished | Oct 15 06:18:13 AM UTC 24 |
| Peak memory | 235576 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154018726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1154018726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.3435806091 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 16827621 ps |
| CPU time | 1.18 seconds |
| Started | Oct 15 06:18:04 AM UTC 24 |
| Finished | Oct 15 06:18:06 AM UTC 24 |
| Peak memory | 216712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435806091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3435806091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.2316933943 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 55100261572 ps |
| CPU time | 75.87 seconds |
| Started | Oct 15 06:18:11 AM UTC 24 |
| Finished | Oct 15 06:19:28 AM UTC 24 |
| Peak memory | 252016 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316933943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.2316933943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3651429417 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 36298454965 ps |
| CPU time | 174.6 seconds |
| Started | Oct 15 06:18:12 AM UTC 24 |
| Finished | Oct 15 06:21:10 AM UTC 24 |
| Peak memory | 272684 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651429417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3651429417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.2795891040 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 2380241975 ps |
| CPU time | 84.77 seconds |
| Started | Oct 15 06:18:12 AM UTC 24 |
| Finished | Oct 15 06:19:39 AM UTC 24 |
| Peak memory | 262536 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795891040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.2795891040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.713742596 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 5616664467 ps |
| CPU time | 22.1 seconds |
| Started | Oct 15 06:18:09 AM UTC 24 |
| Finished | Oct 15 06:18:33 AM UTC 24 |
| Peak memory | 235832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=713742596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.713742596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.709673324 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 74675530575 ps |
| CPU time | 306.34 seconds |
| Started | Oct 15 06:18:09 AM UTC 24 |
| Finished | Oct 15 06:23:21 AM UTC 24 |
| Peak memory | 262548 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709673324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.709673324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.2031556367 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 214626665 ps |
| CPU time | 3.97 seconds |
| Started | Oct 15 06:18:07 AM UTC 24 |
| Finished | Oct 15 06:18:12 AM UTC 24 |
| Peak memory | 235572 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031556367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2031556367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.1684349105 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 3860571713 ps |
| CPU time | 50.76 seconds |
| Started | Oct 15 06:18:07 AM UTC 24 |
| Finished | Oct 15 06:19:00 AM UTC 24 |
| Peak memory | 262456 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684349105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1684349105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.4287120489 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 1744965505 ps |
| CPU time | 7.67 seconds |
| Started | Oct 15 06:18:07 AM UTC 24 |
| Finished | Oct 15 06:18:16 AM UTC 24 |
| Peak memory | 235768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287120489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.4287120489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.46418417 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 301551515 ps |
| CPU time | 3.78 seconds |
| Started | Oct 15 06:18:07 AM UTC 24 |
| Finished | Oct 15 06:18:12 AM UTC 24 |
| Peak memory | 235504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46418417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.46418417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1933270910 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 326090674 ps |
| CPU time | 6.96 seconds |
| Started | Oct 15 06:18:11 AM UTC 24 |
| Finished | Oct 15 06:18:19 AM UTC 24 |
| Peak memory | 234276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933270910 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.1933270910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.281459430 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 124516393736 ps |
| CPU time | 603.04 seconds |
| Started | Oct 15 06:18:14 AM UTC 24 |
| Finished | Oct 15 06:28:25 AM UTC 24 |
| Peak memory | 278732 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281459430 -assert nopostproc +UVM_T ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.281459430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.2087796459 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 1746677425 ps |
| CPU time | 6.14 seconds |
| Started | Oct 15 06:18:04 AM UTC 24 |
| Finished | Oct 15 06:18:11 AM UTC 24 |
| Peak memory | 230420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087796459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2087796459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.1986816097 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 8593628273 ps |
| CPU time | 12.1 seconds |
| Started | Oct 15 06:18:04 AM UTC 24 |
| Finished | Oct 15 06:18:17 AM UTC 24 |
| Peak memory | 228400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986816097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1986816097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.110042222 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 796704150 ps |
| CPU time | 3.25 seconds |
| Started | Oct 15 06:18:05 AM UTC 24 |
| Finished | Oct 15 06:18:09 AM UTC 24 |
| Peak memory | 228276 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110042222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.110042222 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.151099886 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 29747446 ps |
| CPU time | 1.29 seconds |
| Started | Oct 15 06:18:05 AM UTC 24 |
| Finished | Oct 15 06:18:07 AM UTC 24 |
| Peak memory | 216776 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151099886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14 /spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.151099886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.497474584 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 771835917 ps |
| CPU time | 6.55 seconds |
| Started | Oct 15 06:18:09 AM UTC 24 |
| Finished | Oct 15 06:18:17 AM UTC 24 |
| Peak memory | 235504 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497474584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.497474584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/48.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.396864515 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 37484959 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 06:18:31 AM UTC 24 |
| Finished | Oct 15 06:18:33 AM UTC 24 |
| Peak memory | 216648 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396864515 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.396864515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.4074219829 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 349748496 ps |
| CPU time | 6.47 seconds |
| Started | Oct 15 06:18:23 AM UTC 24 |
| Finished | Oct 15 06:18:30 AM UTC 24 |
| Peak memory | 245752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074219829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.4074219829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.320930205 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 43640210 ps |
| CPU time | 1.27 seconds |
| Started | Oct 15 06:18:14 AM UTC 24 |
| Finished | Oct 15 06:18:17 AM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320930205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.320930205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.4008496677 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 15186759 ps |
| CPU time | 1.25 seconds |
| Started | Oct 15 06:18:26 AM UTC 24 |
| Finished | Oct 15 06:18:28 AM UTC 24 |
| Peak memory | 226264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008496677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.4008496677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.488731970 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 118046963083 ps |
| CPU time | 376.79 seconds |
| Started | Oct 15 06:18:29 AM UTC 24 |
| Finished | Oct 15 06:24:51 AM UTC 24 |
| Peak memory | 278676 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488731970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.488731970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.4049580345 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 30808893200 ps |
| CPU time | 117.38 seconds |
| Started | Oct 15 06:18:29 AM UTC 24 |
| Finished | Oct 15 06:20:30 AM UTC 24 |
| Peak memory | 262496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049580345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.4049580345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.82457540 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 73278929 ps |
| CPU time | 3.51 seconds |
| Started | Oct 15 06:18:24 AM UTC 24 |
| Finished | Oct 15 06:18:29 AM UTC 24 |
| Peak memory | 235564 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82457540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.82457540 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3326839326 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 7339075915 ps |
| CPU time | 84.63 seconds |
| Started | Oct 15 06:18:24 AM UTC 24 |
| Finished | Oct 15 06:19:51 AM UTC 24 |
| Peak memory | 262264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326839326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.3326839326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.891084770 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 99128564 ps |
| CPU time | 3.83 seconds |
| Started | Oct 15 06:18:19 AM UTC 24 |
| Finished | Oct 15 06:18:24 AM UTC 24 |
| Peak memory | 245976 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891084770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.891084770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.4004245539 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 1608285099 ps |
| CPU time | 18.37 seconds |
| Started | Oct 15 06:18:20 AM UTC 24 |
| Finished | Oct 15 06:18:40 AM UTC 24 |
| Peak memory | 245752 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004245539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4004245539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.465119607 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 34714472 ps |
| CPU time | 2.61 seconds |
| Started | Oct 15 06:18:19 AM UTC 24 |
| Finished | Oct 15 06:18:23 AM UTC 24 |
| Peak memory | 245472 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465119607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.465119607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.1440192249 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 1983194296 ps |
| CPU time | 3.95 seconds |
| Started | Oct 15 06:18:19 AM UTC 24 |
| Finished | Oct 15 06:18:24 AM UTC 24 |
| Peak memory | 235492 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1440192249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1440192249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1433812855 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 1661316808 ps |
| CPU time | 15.87 seconds |
| Started | Oct 15 06:18:25 AM UTC 24 |
| Finished | Oct 15 06:18:42 AM UTC 24 |
| Peak memory | 232076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433812855 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.1433812855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.3555966433 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 95635139388 ps |
| CPU time | 450.97 seconds |
| Started | Oct 15 06:18:31 AM UTC 24 |
| Finished | Oct 15 06:26:09 AM UTC 24 |
| Peak memory | 276568 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555966433 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.3555966433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.2855270549 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 1186899447 ps |
| CPU time | 13.97 seconds |
| Started | Oct 15 06:18:17 AM UTC 24 |
| Finished | Oct 15 06:18:32 AM UTC 24 |
| Peak memory | 228300 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855270549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2855270549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.150999856 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 1811057172 ps |
| CPU time | 7.22 seconds |
| Started | Oct 15 06:18:14 AM UTC 24 |
| Finished | Oct 15 06:18:23 AM UTC 24 |
| Peak memory | 228208 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=150999856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.150999856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.2916860855 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 39340191 ps |
| CPU time | 1.04 seconds |
| Started | Oct 15 06:18:19 AM UTC 24 |
| Finished | Oct 15 06:18:21 AM UTC 24 |
| Peak memory | 217068 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916860855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2916860855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3509500431 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 122040848 ps |
| CPU time | 1.33 seconds |
| Started | Oct 15 06:18:19 AM UTC 24 |
| Finished | Oct 15 06:18:21 AM UTC 24 |
| Peak memory | 216780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509500431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3509500431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1727731004 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 448181543 ps |
| CPU time | 8.59 seconds |
| Started | Oct 15 06:18:21 AM UTC 24 |
| Finished | Oct 15 06:18:31 AM UTC 24 |
| Peak memory | 235540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727731004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1727731004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/49.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_alert_test.2172867817 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 15046350 ps |
| CPU time | 1.1 seconds |
| Started | Oct 15 06:00:39 AM UTC 24 |
| Finished | Oct 15 06:00:41 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2172867817 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2172867817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_cfg_cmd.1206701029 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 183475951 ps |
| CPU time | 7.15 seconds |
| Started | Oct 15 06:00:16 AM UTC 24 |
| Finished | Oct 15 06:00:24 AM UTC 24 |
| Peak memory | 235768 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206701029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.1206701029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_csb_read.3343203017 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 63444846 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 05:59:52 AM UTC 24 |
| Finished | Oct 15 05:59:54 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343203017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3343203017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_all.3022670978 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 11425686423 ps |
| CPU time | 132.01 seconds |
| Started | Oct 15 06:00:23 AM UTC 24 |
| Finished | Oct 15 06:02:38 AM UTC 24 |
| Peak memory | 268412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022670978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3022670978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.1525666169 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 174469772333 ps |
| CPU time | 460.05 seconds |
| Started | Oct 15 06:00:26 AM UTC 24 |
| Finished | Oct 15 06:08:12 AM UTC 24 |
| Peak memory | 278712 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525666169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1525666169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.285570305 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 38027994896 ps |
| CPU time | 406.7 seconds |
| Started | Oct 15 06:00:29 AM UTC 24 |
| Finished | Oct 15 06:07:21 AM UTC 24 |
| Peak memory | 262364 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285570305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.285570305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode.751934247 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 482826074 ps |
| CPU time | 4.2 seconds |
| Started | Oct 15 06:00:17 AM UTC 24 |
| Finished | Oct 15 06:00:23 AM UTC 24 |
| Peak memory | 235512 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751934247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.751934247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.2960448101 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 57439730973 ps |
| CPU time | 152.73 seconds |
| Started | Oct 15 06:00:19 AM UTC 24 |
| Finished | Oct 15 06:02:55 AM UTC 24 |
| Peak memory | 264332 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960448101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.2960448101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_intercept.3167147580 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 298823891 ps |
| CPU time | 4.42 seconds |
| Started | Oct 15 06:00:12 AM UTC 24 |
| Finished | Oct 15 06:00:18 AM UTC 24 |
| Peak memory | 235584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167147580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3167147580 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_mailbox.2223076972 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 52331899134 ps |
| CPU time | 91.22 seconds |
| Started | Oct 15 06:00:13 AM UTC 24 |
| Finished | Oct 15 06:01:46 AM UTC 24 |
| Peak memory | 252024 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223076972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.2223076972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.839678032 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 563481397 ps |
| CPU time | 3.48 seconds |
| Started | Oct 15 06:00:11 AM UTC 24 |
| Finished | Oct 15 06:00:15 AM UTC 24 |
| Peak memory | 245808 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839678032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.839678032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.1206630228 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 8785030221 ps |
| CPU time | 38.73 seconds |
| Started | Oct 15 06:00:09 AM UTC 24 |
| Finished | Oct 15 06:00:49 AM UTC 24 |
| Peak memory | 245876 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206630228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1206630228 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1468978649 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 148007279 ps |
| CPU time | 6.65 seconds |
| Started | Oct 15 06:00:20 AM UTC 24 |
| Finished | Oct 15 06:00:28 AM UTC 24 |
| Peak memory | 234188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468978649 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.1468978649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_stress_all.2634013352 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 43761335 ps |
| CPU time | 1.4 seconds |
| Started | Oct 15 06:00:37 AM UTC 24 |
| Finished | Oct 15 06:00:40 AM UTC 24 |
| Peak memory | 216644 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634013352 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.2634013352 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_all.2846605828 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 1056875039 ps |
| CPU time | 14.85 seconds |
| Started | Oct 15 05:59:57 AM UTC 24 |
| Finished | Oct 15 06:00:13 AM UTC 24 |
| Peak memory | 232656 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846605828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2846605828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2552575891 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 2177830020 ps |
| CPU time | 11.27 seconds |
| Started | Oct 15 05:59:57 AM UTC 24 |
| Finished | Oct 15 06:00:10 AM UTC 24 |
| Peak memory | 228308 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552575891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2552575891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_rw.1124529451 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 33521408 ps |
| CPU time | 1.15 seconds |
| Started | Oct 15 06:00:01 AM UTC 24 |
| Finished | Oct 15 06:00:08 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124529451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1124529451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.4000683141 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 87502714 ps |
| CPU time | 1.63 seconds |
| Started | Oct 15 05:59:58 AM UTC 24 |
| Finished | Oct 15 06:00:01 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000683141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4000683141 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/5.spi_device_upload.218410695 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 248422398 ps |
| CPU time | 3.14 seconds |
| Started | Oct 15 06:00:15 AM UTC 24 |
| Finished | Oct 15 06:00:19 AM UTC 24 |
| Peak memory | 235432 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218410695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_d evice_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.218410695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/5.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_alert_test.4150284995 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 36663121 ps |
| CPU time | 1.11 seconds |
| Started | Oct 15 06:01:09 AM UTC 24 |
| Finished | Oct 15 06:01:11 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150284995 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.4150284995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_cfg_cmd.2936834874 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 244136194 ps |
| CPU time | 6.19 seconds |
| Started | Oct 15 06:00:57 AM UTC 24 |
| Finished | Oct 15 06:01:04 AM UTC 24 |
| Peak memory | 235516 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936834874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.2936834874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_csb_read.3923735295 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 58550778 ps |
| CPU time | 1.23 seconds |
| Started | Oct 15 06:00:40 AM UTC 24 |
| Finished | Oct 15 06:00:43 AM UTC 24 |
| Peak memory | 216528 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923735295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3923735295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_all.3621906312 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 13538106272 ps |
| CPU time | 47.78 seconds |
| Started | Oct 15 06:01:04 AM UTC 24 |
| Finished | Oct 15 06:01:54 AM UTC 24 |
| Peak memory | 264340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621906312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.3621906312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.499056163 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 43323387409 ps |
| CPU time | 398.26 seconds |
| Started | Oct 15 06:01:04 AM UTC 24 |
| Finished | Oct 15 06:07:48 AM UTC 24 |
| Peak memory | 268496 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499056163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.499056163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.2052056812 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 6817885759 ps |
| CPU time | 114.08 seconds |
| Started | Oct 15 06:01:06 AM UTC 24 |
| Finished | Oct 15 06:03:02 AM UTC 24 |
| Peak memory | 268632 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052056812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.2052056812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode.1629290664 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 507275682 ps |
| CPU time | 6.29 seconds |
| Started | Oct 15 06:01:00 AM UTC 24 |
| Finished | Oct 15 06:01:08 AM UTC 24 |
| Peak memory | 232600 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629290664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1629290664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.2275045022 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 21462867 ps |
| CPU time | 1.29 seconds |
| Started | Oct 15 06:01:00 AM UTC 24 |
| Finished | Oct 15 06:01:02 AM UTC 24 |
| Peak memory | 226264 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275045022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.2275045022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_intercept.3053341550 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 293044522 ps |
| CPU time | 7.89 seconds |
| Started | Oct 15 06:00:50 AM UTC 24 |
| Finished | Oct 15 06:00:59 AM UTC 24 |
| Peak memory | 245848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053341550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3053341550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_mailbox.4204165977 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 868498448 ps |
| CPU time | 18.4 seconds |
| Started | Oct 15 06:00:53 AM UTC 24 |
| Finished | Oct 15 06:01:13 AM UTC 24 |
| Peak memory | 246032 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204165977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.4204165977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1357316304 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 445164755 ps |
| CPU time | 12.38 seconds |
| Started | Oct 15 06:00:50 AM UTC 24 |
| Finished | Oct 15 06:01:03 AM UTC 24 |
| Peak memory | 235508 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357316304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.1357316304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.1471351597 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 12252415646 ps |
| CPU time | 8.8 seconds |
| Started | Oct 15 06:00:50 AM UTC 24 |
| Finished | Oct 15 06:01:00 AM UTC 24 |
| Peak memory | 246036 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471351597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1471351597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.3909010806 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 5392657607 ps |
| CPU time | 15.76 seconds |
| Started | Oct 15 06:01:03 AM UTC 24 |
| Finished | Oct 15 06:01:20 AM UTC 24 |
| Peak memory | 234476 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909010806 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.3909010806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_all.1607367334 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 866563166 ps |
| CPU time | 12.05 seconds |
| Started | Oct 15 06:00:43 AM UTC 24 |
| Finished | Oct 15 06:00:57 AM UTC 24 |
| Peak memory | 232340 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607367334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1607367334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2742567275 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 412731592 ps |
| CPU time | 5.73 seconds |
| Started | Oct 15 06:00:42 AM UTC 24 |
| Finished | Oct 15 06:00:49 AM UTC 24 |
| Peak memory | 228180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2742567275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2742567275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_rw.2882379134 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 23339842 ps |
| CPU time | 1.67 seconds |
| Started | Oct 15 06:00:47 AM UTC 24 |
| Finished | Oct 15 06:00:49 AM UTC 24 |
| Peak memory | 228436 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882379134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.2882379134 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.1382338824 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 68341714 ps |
| CPU time | 1.51 seconds |
| Started | Oct 15 06:00:43 AM UTC 24 |
| Finished | Oct 15 06:00:46 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382338824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.1382338824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/6.spi_device_upload.1124660484 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 1828027628 ps |
| CPU time | 11.83 seconds |
| Started | Oct 15 06:00:57 AM UTC 24 |
| Finished | Oct 15 06:01:10 AM UTC 24 |
| Peak memory | 245804 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124660484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1124660484 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/6.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_alert_test.2627592549 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 18093217 ps |
| CPU time | 1.13 seconds |
| Started | Oct 15 06:01:48 AM UTC 24 |
| Finished | Oct 15 06:01:50 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627592549 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.2627592549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_cfg_cmd.952880229 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 57824357 ps |
| CPU time | 4.17 seconds |
| Started | Oct 15 06:01:24 AM UTC 24 |
| Finished | Oct 15 06:01:29 AM UTC 24 |
| Peak memory | 235584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952880229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.952880229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_csb_read.1346765319 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 64364562 ps |
| CPU time | 1.17 seconds |
| Started | Oct 15 06:01:09 AM UTC 24 |
| Finished | Oct 15 06:01:11 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1346765319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.1346765319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_all.905344520 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 10251422108 ps |
| CPU time | 190.5 seconds |
| Started | Oct 15 06:01:30 AM UTC 24 |
| Finished | Oct 15 06:04:44 AM UTC 24 |
| Peak memory | 268440 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905344520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.905344520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1464129113 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 5912268945 ps |
| CPU time | 89.69 seconds |
| Started | Oct 15 06:01:36 AM UTC 24 |
| Finished | Oct 15 06:03:08 AM UTC 24 |
| Peak memory | 262328 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464129113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1464129113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.3010877021 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 23543267463 ps |
| CPU time | 129.32 seconds |
| Started | Oct 15 06:01:43 AM UTC 24 |
| Finished | Oct 15 06:03:55 AM UTC 24 |
| Peak memory | 262344 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010877021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.3010877021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode.2698169927 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 1275283097 ps |
| CPU time | 19.3 seconds |
| Started | Oct 15 06:01:27 AM UTC 24 |
| Finished | Oct 15 06:01:48 AM UTC 24 |
| Peak memory | 252088 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698169927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2698169927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.20605565 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 93874940972 ps |
| CPU time | 178.45 seconds |
| Started | Oct 15 06:01:29 AM UTC 24 |
| Finished | Oct 15 06:04:30 AM UTC 24 |
| Peak memory | 268400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20605565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.20605565 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_intercept.258445551 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 1403859931 ps |
| CPU time | 9.91 seconds |
| Started | Oct 15 06:01:17 AM UTC 24 |
| Finished | Oct 15 06:01:28 AM UTC 24 |
| Peak memory | 235580 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258445551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.258445551 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_mailbox.240413525 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 6373984741 ps |
| CPU time | 24.76 seconds |
| Started | Oct 15 06:01:21 AM UTC 24 |
| Finished | Oct 15 06:01:47 AM UTC 24 |
| Peak memory | 245908 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240413525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.240413525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.2831645851 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 135981515 ps |
| CPU time | 4.83 seconds |
| Started | Oct 15 06:01:17 AM UTC 24 |
| Finished | Oct 15 06:01:23 AM UTC 24 |
| Peak memory | 245812 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831645851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.2831645851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.571696483 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 8403766593 ps |
| CPU time | 48.79 seconds |
| Started | Oct 15 06:01:16 AM UTC 24 |
| Finished | Oct 15 06:02:07 AM UTC 24 |
| Peak memory | 245880 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571696483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.571696483 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.1238255028 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 864410006 ps |
| CPU time | 12.28 seconds |
| Started | Oct 15 06:01:29 AM UTC 24 |
| Finished | Oct 15 06:01:43 AM UTC 24 |
| Peak memory | 234180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238255028 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.1238255028 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_stress_all.4023111655 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 12423298228 ps |
| CPU time | 200.76 seconds |
| Started | Oct 15 06:01:43 AM UTC 24 |
| Finished | Oct 15 06:05:08 AM UTC 24 |
| Peak memory | 262320 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023111655 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.4023111655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_all.723887380 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 1514534983 ps |
| CPU time | 12.53 seconds |
| Started | Oct 15 06:01:12 AM UTC 24 |
| Finished | Oct 15 06:01:26 AM UTC 24 |
| Peak memory | 230584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723887380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.723887380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.553563519 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 173790436 ps |
| CPU time | 3.52 seconds |
| Started | Oct 15 06:01:12 AM UTC 24 |
| Finished | Oct 15 06:01:17 AM UTC 24 |
| Peak memory | 227956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553563519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.553563519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_rw.2036994011 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 34315985 ps |
| CPU time | 1.24 seconds |
| Started | Oct 15 06:01:14 AM UTC 24 |
| Finished | Oct 15 06:01:16 AM UTC 24 |
| Peak memory | 216832 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036994011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2036994011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.3530001235 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 24990555 ps |
| CPU time | 1.14 seconds |
| Started | Oct 15 06:01:13 AM UTC 24 |
| Finished | Oct 15 06:01:15 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3530001235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3530001235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/7.spi_device_upload.2912017433 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 3169988043 ps |
| CPU time | 6.68 seconds |
| Started | Oct 15 06:01:21 AM UTC 24 |
| Finished | Oct 15 06:01:28 AM UTC 24 |
| Peak memory | 235916 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912017433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2912017433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/7.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_alert_test.768329127 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 24049888 ps |
| CPU time | 1.16 seconds |
| Started | Oct 15 06:02:20 AM UTC 24 |
| Finished | Oct 15 06:02:22 AM UTC 24 |
| Peak memory | 214664 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768329127 -assert nopostproc +UVM_TEST NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.768329127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_cfg_cmd.1411904374 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 10826521490 ps |
| CPU time | 18.05 seconds |
| Started | Oct 15 06:02:01 AM UTC 24 |
| Finished | Oct 15 06:02:20 AM UTC 24 |
| Peak memory | 245848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411904374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1411904374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_csb_read.710262480 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 22290838 ps |
| CPU time | 1.21 seconds |
| Started | Oct 15 06:01:48 AM UTC 24 |
| Finished | Oct 15 06:01:50 AM UTC 24 |
| Peak memory | 216708 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710262480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.710262480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_all.2573486026 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 5485016511 ps |
| CPU time | 87.87 seconds |
| Started | Oct 15 06:02:14 AM UTC 24 |
| Finished | Oct 15 06:03:44 AM UTC 24 |
| Peak memory | 268636 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573486026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2573486026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.1348578603 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 43489320034 ps |
| CPU time | 74.41 seconds |
| Started | Oct 15 06:02:16 AM UTC 24 |
| Finished | Oct 15 06:03:32 AM UTC 24 |
| Peak memory | 235696 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348578603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_ 14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.1348578603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3110785362 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 16371033294 ps |
| CPU time | 158.09 seconds |
| Started | Oct 15 06:02:19 AM UTC 24 |
| Finished | Oct 15 06:05:00 AM UTC 24 |
| Peak memory | 278728 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110785362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.3110785362 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode.711356800 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 6744886930 ps |
| CPU time | 54.33 seconds |
| Started | Oct 15 06:02:07 AM UTC 24 |
| Finished | Oct 15 06:03:03 AM UTC 24 |
| Peak memory | 245864 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711356800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.711356800 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.48311365 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 14923354616 ps |
| CPU time | 75.55 seconds |
| Started | Oct 15 06:02:08 AM UTC 24 |
| Finished | Oct 15 06:03:25 AM UTC 24 |
| Peak memory | 266380 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48311365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.48311365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_intercept.2538022713 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 2013058813 ps |
| CPU time | 15.97 seconds |
| Started | Oct 15 06:01:55 AM UTC 24 |
| Finished | Oct 15 06:02:13 AM UTC 24 |
| Peak memory | 245848 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538022713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.2538022713 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_mailbox.3697964502 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 7398385795 ps |
| CPU time | 79.89 seconds |
| Started | Oct 15 06:01:56 AM UTC 24 |
| Finished | Oct 15 06:03:18 AM UTC 24 |
| Peak memory | 262420 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3697964502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3697964502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.47751932 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 8030572157 ps |
| CPU time | 34.18 seconds |
| Started | Oct 15 06:01:55 AM UTC 24 |
| Finished | Oct 15 06:02:31 AM UTC 24 |
| Peak memory | 245856 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47751932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test + UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.47751932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.1227760786 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 568493948 ps |
| CPU time | 12.44 seconds |
| Started | Oct 15 06:01:55 AM UTC 24 |
| Finished | Oct 15 06:02:09 AM UTC 24 |
| Peak memory | 251956 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227760786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1227760786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.3194765459 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 484909434 ps |
| CPU time | 8.77 seconds |
| Started | Oct 15 06:02:10 AM UTC 24 |
| Finished | Oct 15 06:02:20 AM UTC 24 |
| Peak memory | 234188 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194765459 -assert nopostproc +UVM_TESTNAME=spi_device _base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.3194765459 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_stress_all.91372049 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 293049601645 ps |
| CPU time | 499.37 seconds |
| Started | Oct 15 06:02:20 AM UTC 24 |
| Finished | Oct 15 06:10:46 AM UTC 24 |
| Peak memory | 285076 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=91372049 -assert nopostproc +UVM_TE STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.91372049 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_all.316734310 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 142836189 ps |
| CPU time | 3.74 seconds |
| Started | Oct 15 06:01:51 AM UTC 24 |
| Finished | Oct 15 06:01:56 AM UTC 24 |
| Peak memory | 228376 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316734310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.316734310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.3617224229 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 11306042884 ps |
| CPU time | 14.04 seconds |
| Started | Oct 15 06:01:51 AM UTC 24 |
| Finished | Oct 15 06:02:06 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617224229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_1 0_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3617224229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_rw.1971520351 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 69085238 ps |
| CPU time | 1.31 seconds |
| Started | Oct 15 06:01:54 AM UTC 24 |
| Finished | Oct 15 06:01:56 AM UTC 24 |
| Peak memory | 228400 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971520351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.1971520351 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.3838464861 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 22696237 ps |
| CPU time | 1.19 seconds |
| Started | Oct 15 06:01:52 AM UTC 24 |
| Finished | Oct 15 06:01:54 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838464861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.3838464861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/8.spi_device_upload.2704349841 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 10135875582 ps |
| CPU time | 15.89 seconds |
| Started | Oct 15 06:01:57 AM UTC 24 |
| Finished | Oct 15 06:02:15 AM UTC 24 |
| Peak memory | 246096 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704349841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2704349841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/8.spi_device_upload/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_alert_test.3360817569 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 18279512 ps |
| CPU time | 1.16 seconds |
| Started | Oct 15 06:02:53 AM UTC 24 |
| Finished | Oct 15 06:02:55 AM UTC 24 |
| Peak memory | 216584 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360817569 -assert nopostproc +UVM_TES TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3360817569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_cfg_cmd.2480580000 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 686107301 ps |
| CPU time | 8.69 seconds |
| Started | Oct 15 06:02:39 AM UTC 24 |
| Finished | Oct 15 06:02:49 AM UTC 24 |
| Peak memory | 235540 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2480580000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.2480580000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_cfg_cmd/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_csb_read.4087348739 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 19813775 ps |
| CPU time | 1.23 seconds |
| Started | Oct 15 06:02:23 AM UTC 24 |
| Finished | Oct 15 06:02:26 AM UTC 24 |
| Peak memory | 216704 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087348739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/sp i_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.4087348739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_csb_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_all.3874285882 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 82213817345 ps |
| CPU time | 160.52 seconds |
| Started | Oct 15 06:02:47 AM UTC 24 |
| Finished | Oct 15 06:05:30 AM UTC 24 |
| Peak memory | 262260 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874285882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3874285882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_flash_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.1055418330 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 38464118879 ps |
| CPU time | 76.35 seconds |
| Started | Oct 15 06:02:50 AM UTC 24 |
| Finished | Oct 15 06:04:08 AM UTC 24 |
| Peak memory | 266412 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055418330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.1055418330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_flash_mode.3779755785 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 8271075155 ps |
| CPU time | 27.07 seconds |
| Started | Oct 15 06:02:44 AM UTC 24 |
| Finished | Oct 15 06:03:12 AM UTC 24 |
| Peak memory | 252240 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779755785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/ spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3779755785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_flash_mode/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_intercept.3006493375 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 525872821 ps |
| CPU time | 6.54 seconds |
| Started | Oct 15 06:02:36 AM UTC 24 |
| Finished | Oct 15 06:02:44 AM UTC 24 |
| Peak memory | 235716 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3006493375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/s pi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3006493375 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_intercept/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_mailbox.4039979179 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 355684652 ps |
| CPU time | 4.23 seconds |
| Started | Oct 15 06:02:37 AM UTC 24 |
| Finished | Oct 15 06:02:42 AM UTC 24 |
| Peak memory | 245912 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039979179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.4039979179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_mailbox/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.2753991947 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3499174281 ps |
| CPU time | 14.23 seconds |
| Started | Oct 15 06:02:34 AM UTC 24 |
| Finished | Oct 15 06:02:49 AM UTC 24 |
| Peak memory | 246028 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753991947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.2753991947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_pass_addr_payload_swap/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.1764601467 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 1143294284 ps |
| CPU time | 11.26 seconds |
| Started | Oct 15 06:02:34 AM UTC 24 |
| Finished | Oct 15 06:02:46 AM UTC 24 |
| Peak memory | 235756 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764601467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1764601467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_pass_cmd_filtering/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.78346705 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 219919189 ps |
| CPU time | 6.17 seconds |
| Started | Oct 15 06:02:45 AM UTC 24 |
| Finished | Oct 15 06:02:52 AM UTC 24 |
| Peak memory | 232140 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78346705 -assert nopostproc +UVM_TESTNAME=spi_device_b ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.78346705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_read_buffer_direct/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_stress_all.3301783680 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 28932809041 ps |
| CPU time | 54.49 seconds |
| Started | Oct 15 06:02:50 AM UTC 24 |
| Finished | Oct 15 06:03:46 AM UTC 24 |
| Peak memory | 235736 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UV M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301783680 -assert nopostproc +UVM_ TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.3301783680 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_all.3548745964 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 1930500431 ps |
| CPU time | 5.29 seconds |
| Started | Oct 15 06:02:30 AM UTC 24 |
| Finished | Oct 15 06:02:36 AM UTC 24 |
| Peak memory | 228236 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548745964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi _device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3548745964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_tpm_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.785764595 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 570473041 ps |
| CPU time | 4.67 seconds |
| Started | Oct 15 06:02:28 AM UTC 24 |
| Finished | Oct 15 06:02:33 AM UTC 24 |
| Peak memory | 228180 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785764595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10 _14/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.785764595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_tpm_read_hw_reg/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_rw.1877111543 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 111286774 ps |
| CPU time | 3.4 seconds |
| Started | Oct 15 06:02:32 AM UTC 24 |
| Finished | Oct 15 06:02:36 AM UTC 24 |
| Peak memory | 228244 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877111543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1877111543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_tpm_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.1964951181 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 81139292 ps |
| CPU time | 1.38 seconds |
| Started | Oct 15 06:02:31 AM UTC 24 |
| Finished | Oct 15 06:02:33 AM UTC 24 |
| Peak memory | 216772 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1964951181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_1 4/spi_device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1964951181 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_tpm_sts_read/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/9.spi_device_upload.1804413846 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 983605504 ps |
| CPU time | 17.2 seconds |
| Started | Oct 15 06:02:37 AM UTC 24 |
| Finished | Oct 15 06:02:56 AM UTC 24 |
| Peak memory | 245780 kb |
| Host | riverbear.us-west1-a.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY= UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804413846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_14/spi_ device_1r1w-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1804413846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/9.spi_device_upload/latest |
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |