| T832 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/33.spi_device_flash_all.3860268242 |
|
|
Oct 15 06:13:24 AM UTC 24 |
Oct 15 06:16:02 AM UTC 24 |
20837048171 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.99243498 |
|
|
Oct 15 06:15:51 AM UTC 24 |
Oct 15 06:16:02 AM UTC 24 |
883005162 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.2499187836 |
|
|
Oct 15 06:14:42 AM UTC 24 |
Oct 15 06:16:02 AM UTC 24 |
3289186527 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.3712460439 |
|
|
Oct 15 06:15:54 AM UTC 24 |
Oct 15 06:16:04 AM UTC 24 |
1212726110 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_cfg_cmd.935989034 |
|
|
Oct 15 06:15:57 AM UTC 24 |
Oct 15 06:16:05 AM UTC 24 |
216678082 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_intercept.3162540684 |
|
|
Oct 15 06:15:55 AM UTC 24 |
Oct 15 06:16:06 AM UTC 24 |
8197770192 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_stress_all.1862036743 |
|
|
Oct 15 06:16:04 AM UTC 24 |
Oct 15 06:16:07 AM UTC 24 |
47074824 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_alert_test.1696817381 |
|
|
Oct 15 06:16:05 AM UTC 24 |
Oct 15 06:16:08 AM UTC 24 |
20891415 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_csb_read.2981434122 |
|
|
Oct 15 06:16:05 AM UTC 24 |
Oct 15 06:16:08 AM UTC 24 |
61162013 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_tpm_all.55715503 |
|
|
Oct 15 06:15:35 AM UTC 24 |
Oct 15 06:16:09 AM UTC 24 |
4086054900 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3108420568 |
|
|
Oct 15 06:16:02 AM UTC 24 |
Oct 15 06:16:09 AM UTC 24 |
128665300 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_stress_all.227974388 |
|
|
Oct 15 06:15:49 AM UTC 24 |
Oct 15 06:16:10 AM UTC 24 |
14237721625 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_tpm_all.1825255331 |
|
|
Oct 15 06:15:51 AM UTC 24 |
Oct 15 06:16:10 AM UTC 24 |
2505325047 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.972138287 |
|
|
Oct 15 06:16:09 AM UTC 24 |
Oct 15 06:16:12 AM UTC 24 |
26210240 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_rw.2379540592 |
|
|
Oct 15 06:16:09 AM UTC 24 |
Oct 15 06:16:12 AM UTC 24 |
53733417 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_all.2727095966 |
|
|
Oct 15 06:16:02 AM UTC 24 |
Oct 15 06:16:14 AM UTC 24 |
934877892 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_stress_all.3065405848 |
|
|
Oct 15 06:14:50 AM UTC 24 |
Oct 15 06:16:14 AM UTC 24 |
3983820264 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.313307836 |
|
|
Oct 15 06:14:00 AM UTC 24 |
Oct 15 06:16:17 AM UTC 24 |
25884411935 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.994360018 |
|
|
Oct 15 06:03:58 AM UTC 24 |
Oct 15 06:16:19 AM UTC 24 |
58920912472 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_intercept.2979076943 |
|
|
Oct 15 06:16:11 AM UTC 24 |
Oct 15 06:16:19 AM UTC 24 |
532179170 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_mailbox.1726567326 |
|
|
Oct 15 06:16:11 AM UTC 24 |
Oct 15 06:16:20 AM UTC 24 |
515982402 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.85552179 |
|
|
Oct 15 06:16:07 AM UTC 24 |
Oct 15 06:16:22 AM UTC 24 |
10752410390 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_all.4135952557 |
|
|
Oct 15 06:15:47 AM UTC 24 |
Oct 15 06:16:23 AM UTC 24 |
1135076406 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_tpm_all.108897639 |
|
|
Oct 15 06:16:08 AM UTC 24 |
Oct 15 06:16:23 AM UTC 24 |
1807080409 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode.1075101672 |
|
|
Oct 15 06:16:15 AM UTC 24 |
Oct 15 06:16:23 AM UTC 24 |
205427522 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_mailbox.1653046746 |
|
|
Oct 15 06:15:56 AM UTC 24 |
Oct 15 06:16:25 AM UTC 24 |
35374939149 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_upload.1836266564 |
|
|
Oct 15 06:16:12 AM UTC 24 |
Oct 15 06:16:25 AM UTC 24 |
7276877139 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_alert_test.4119035404 |
|
|
Oct 15 06:16:24 AM UTC 24 |
Oct 15 06:16:26 AM UTC 24 |
40780423 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2342867341 |
|
|
Oct 15 06:16:18 AM UTC 24 |
Oct 15 06:16:26 AM UTC 24 |
1036606894 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_csb_read.2802162114 |
|
|
Oct 15 06:16:24 AM UTC 24 |
Oct 15 06:16:27 AM UTC 24 |
39156712 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3507335074 |
|
|
Oct 15 06:16:14 AM UTC 24 |
Oct 15 06:16:27 AM UTC 24 |
2665845763 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.2723355907 |
|
|
Oct 15 06:16:11 AM UTC 24 |
Oct 15 06:16:28 AM UTC 24 |
2133395402 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.2288214391 |
|
|
Oct 15 06:16:11 AM UTC 24 |
Oct 15 06:16:29 AM UTC 24 |
1850986109 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1782535310 |
|
|
Oct 15 06:16:26 AM UTC 24 |
Oct 15 06:16:29 AM UTC 24 |
41656982 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.3887318942 |
|
|
Oct 15 06:08:17 AM UTC 24 |
Oct 15 06:16:29 AM UTC 24 |
49719033096 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_rw.322071505 |
|
|
Oct 15 06:16:28 AM UTC 24 |
Oct 15 06:16:30 AM UTC 24 |
26951957 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.3772776438 |
|
|
Oct 15 06:12:56 AM UTC 24 |
Oct 15 06:16:30 AM UTC 24 |
95850215969 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.1477515797 |
|
|
Oct 15 06:16:28 AM UTC 24 |
Oct 15 06:16:31 AM UTC 24 |
30209147 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_mailbox.208427381 |
|
|
Oct 15 06:17:27 AM UTC 24 |
Oct 15 06:17:31 AM UTC 24 |
282618016 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_all.368951129 |
|
|
Oct 15 06:16:26 AM UTC 24 |
Oct 15 06:16:32 AM UTC 24 |
889746250 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.764518479 |
|
|
Oct 15 06:11:15 AM UTC 24 |
Oct 15 06:16:34 AM UTC 24 |
56399961668 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.2521222893 |
|
|
Oct 15 06:16:24 AM UTC 24 |
Oct 15 06:16:36 AM UTC 24 |
7956704531 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode.2395717655 |
|
|
Oct 15 06:16:31 AM UTC 24 |
Oct 15 06:16:37 AM UTC 24 |
191254041 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_intercept.1295870301 |
|
|
Oct 15 06:16:30 AM UTC 24 |
Oct 15 06:16:37 AM UTC 24 |
4018496795 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_upload.3967041117 |
|
|
Oct 15 06:16:30 AM UTC 24 |
Oct 15 06:16:39 AM UTC 24 |
935937294 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.4047589709 |
|
|
Oct 15 06:16:28 AM UTC 24 |
Oct 15 06:16:39 AM UTC 24 |
1242172945 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_alert_test.3011619240 |
|
|
Oct 15 06:16:38 AM UTC 24 |
Oct 15 06:16:40 AM UTC 24 |
257729340 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_csb_read.2484874609 |
|
|
Oct 15 06:16:38 AM UTC 24 |
Oct 15 06:16:40 AM UTC 24 |
33582153 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_cfg_cmd.1646987843 |
|
|
Oct 15 06:16:30 AM UTC 24 |
Oct 15 06:16:40 AM UTC 24 |
2377359180 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_stress_all.618313441 |
|
|
Oct 15 06:16:38 AM UTC 24 |
Oct 15 06:16:40 AM UTC 24 |
165473060 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.1100253035 |
|
|
Oct 15 06:15:48 AM UTC 24 |
Oct 15 06:16:41 AM UTC 24 |
8927499637 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.731154894 |
|
|
Oct 15 06:16:40 AM UTC 24 |
Oct 15 06:16:42 AM UTC 24 |
32707544 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.4198060669 |
|
|
Oct 15 06:16:40 AM UTC 24 |
Oct 15 06:16:43 AM UTC 24 |
67189894 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode.2052484439 |
|
|
Oct 15 06:15:59 AM UTC 24 |
Oct 15 06:16:45 AM UTC 24 |
1948830705 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_rw.718369473 |
|
|
Oct 15 06:16:42 AM UTC 24 |
Oct 15 06:16:45 AM UTC 24 |
32370229 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.3423728605 |
|
|
Oct 15 06:12:40 AM UTC 24 |
Oct 15 06:16:47 AM UTC 24 |
22100194180 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_mailbox.3064430835 |
|
|
Oct 15 06:16:44 AM UTC 24 |
Oct 15 06:16:47 AM UTC 24 |
30227684 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.2213529026 |
|
|
Oct 15 06:16:31 AM UTC 24 |
Oct 15 06:16:50 AM UTC 24 |
10421678865 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.2093803140 |
|
|
Oct 15 06:16:42 AM UTC 24 |
Oct 15 06:16:53 AM UTC 24 |
1202105566 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.3872999387 |
|
|
Oct 15 06:16:49 AM UTC 24 |
Oct 15 06:16:57 AM UTC 24 |
247627741 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.3709902504 |
|
|
Oct 15 06:16:21 AM UTC 24 |
Oct 15 06:17:00 AM UTC 24 |
3016076016 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1674869460 |
|
|
Oct 15 06:14:48 AM UTC 24 |
Oct 15 06:17:00 AM UTC 24 |
4202504707 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2422157768 |
|
|
Oct 15 06:14:22 AM UTC 24 |
Oct 15 06:17:01 AM UTC 24 |
62134490693 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.1943790007 |
|
|
Oct 15 06:16:42 AM UTC 24 |
Oct 15 06:17:03 AM UTC 24 |
10037722386 ps |
| T67 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.1522391476 |
|
|
Oct 15 06:16:04 AM UTC 24 |
Oct 15 06:17:03 AM UTC 24 |
7374477273 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_intercept.1584825647 |
|
|
Oct 15 06:16:42 AM UTC 24 |
Oct 15 06:17:03 AM UTC 24 |
1296023431 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_alert_test.4193044886 |
|
|
Oct 15 06:17:01 AM UTC 24 |
Oct 15 06:17:03 AM UTC 24 |
37686319 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_cfg_cmd.2252595780 |
|
|
Oct 15 06:16:46 AM UTC 24 |
Oct 15 06:17:03 AM UTC 24 |
931952229 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.4246634184 |
|
|
Oct 15 06:16:21 AM UTC 24 |
Oct 15 06:17:04 AM UTC 24 |
7672657646 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_tpm_all.1181608838 |
|
|
Oct 15 06:16:40 AM UTC 24 |
Oct 15 06:17:04 AM UTC 24 |
982059323 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_csb_read.962524151 |
|
|
Oct 15 06:17:02 AM UTC 24 |
Oct 15 06:17:04 AM UTC 24 |
34099534 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3633649511 |
|
|
Oct 15 06:17:04 AM UTC 24 |
Oct 15 06:17:06 AM UTC 24 |
48455593 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_rw.372216484 |
|
|
Oct 15 06:17:04 AM UTC 24 |
Oct 15 06:17:07 AM UTC 24 |
52799697 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_intercept.2435050326 |
|
|
Oct 15 06:17:06 AM UTC 24 |
Oct 15 06:17:11 AM UTC 24 |
758020778 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_mailbox.2064893217 |
|
|
Oct 15 06:16:30 AM UTC 24 |
Oct 15 06:17:12 AM UTC 24 |
15005237991 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_upload.1592260752 |
|
|
Oct 15 06:17:07 AM UTC 24 |
Oct 15 06:17:13 AM UTC 24 |
88526517 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode.3580475850 |
|
|
Oct 15 06:16:46 AM UTC 24 |
Oct 15 06:17:14 AM UTC 24 |
1840963246 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_cfg_cmd.1826861321 |
|
|
Oct 15 06:17:08 AM UTC 24 |
Oct 15 06:17:14 AM UTC 24 |
169922932 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.628218541 |
|
|
Oct 15 06:17:04 AM UTC 24 |
Oct 15 06:17:14 AM UTC 24 |
1677711892 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_upload.3045964573 |
|
|
Oct 15 06:16:44 AM UTC 24 |
Oct 15 06:17:15 AM UTC 24 |
6221380973 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.3416245873 |
|
|
Oct 15 06:13:41 AM UTC 24 |
Oct 15 06:17:16 AM UTC 24 |
96675811650 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.767083452 |
|
|
Oct 15 06:13:58 AM UTC 24 |
Oct 15 06:17:17 AM UTC 24 |
89716557790 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.1639990807 |
|
|
Oct 15 06:17:14 AM UTC 24 |
Oct 15 06:17:20 AM UTC 24 |
457204140 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_alert_test.3520187104 |
|
|
Oct 15 06:17:18 AM UTC 24 |
Oct 15 06:17:20 AM UTC 24 |
14950668 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_csb_read.351885484 |
|
|
Oct 15 06:17:18 AM UTC 24 |
Oct 15 06:17:20 AM UTC 24 |
77928179 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode.1507441462 |
|
|
Oct 15 06:17:13 AM UTC 24 |
Oct 15 06:17:21 AM UTC 24 |
159737771 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_stress_all.3667585784 |
|
|
Oct 15 06:14:30 AM UTC 24 |
Oct 15 06:17:22 AM UTC 24 |
8393758171 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.1250574494 |
|
|
Oct 15 06:17:21 AM UTC 24 |
Oct 15 06:17:23 AM UTC 24 |
58332383 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_rw.191545343 |
|
|
Oct 15 06:17:22 AM UTC 24 |
Oct 15 06:17:25 AM UTC 24 |
150763057 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_tpm_all.3528959786 |
|
|
Oct 15 06:17:04 AM UTC 24 |
Oct 15 06:17:26 AM UTC 24 |
2148334815 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/26.spi_device_stress_all.2688537347 |
|
|
Oct 15 06:10:57 AM UTC 24 |
Oct 15 06:17:26 AM UTC 24 |
91143039763 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.2639847862 |
|
|
Oct 15 06:17:24 AM UTC 24 |
Oct 15 06:17:28 AM UTC 24 |
184217994 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.4230965690 |
|
|
Oct 15 06:17:24 AM UTC 24 |
Oct 15 06:17:29 AM UTC 24 |
242353099 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2229154732 |
|
|
Oct 15 06:17:21 AM UTC 24 |
Oct 15 06:17:31 AM UTC 24 |
2930039130 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1064976462 |
|
|
Oct 15 06:15:24 AM UTC 24 |
Oct 15 06:17:32 AM UTC 24 |
5658580434 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode.3645517363 |
|
|
Oct 15 06:17:30 AM UTC 24 |
Oct 15 06:17:34 AM UTC 24 |
82588768 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_stress_all.606398890 |
|
|
Oct 15 06:15:34 AM UTC 24 |
Oct 15 06:17:35 AM UTC 24 |
5183546546 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_mailbox.1126294357 |
|
|
Oct 15 06:17:06 AM UTC 24 |
Oct 15 06:17:35 AM UTC 24 |
4399303885 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.3995105525 |
|
|
Oct 15 06:17:04 AM UTC 24 |
Oct 15 06:17:42 AM UTC 24 |
4573991344 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_intercept.2822316730 |
|
|
Oct 15 06:17:26 AM UTC 24 |
Oct 15 06:17:42 AM UTC 24 |
4467210961 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.1468565881 |
|
|
Oct 15 06:14:46 AM UTC 24 |
Oct 15 06:17:43 AM UTC 24 |
115646209709 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.1379626977 |
|
|
Oct 15 06:17:06 AM UTC 24 |
Oct 15 06:17:44 AM UTC 24 |
33647765307 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_tpm_all.2716501151 |
|
|
Oct 15 06:17:21 AM UTC 24 |
Oct 15 06:17:44 AM UTC 24 |
3022343810 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_alert_test.1698591040 |
|
|
Oct 15 06:17:43 AM UTC 24 |
Oct 15 06:17:45 AM UTC 24 |
14201402 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_csb_read.2945658881 |
|
|
Oct 15 06:17:43 AM UTC 24 |
Oct 15 06:17:45 AM UTC 24 |
68484851 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.2655691064 |
|
|
Oct 15 06:17:32 AM UTC 24 |
Oct 15 06:17:45 AM UTC 24 |
2390728536 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_rw.217644596 |
|
|
Oct 15 06:17:46 AM UTC 24 |
Oct 15 06:17:48 AM UTC 24 |
14673965 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.229168218 |
|
|
Oct 15 06:17:46 AM UTC 24 |
Oct 15 06:17:48 AM UTC 24 |
106909188 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.4193761897 |
|
|
Oct 15 06:17:46 AM UTC 24 |
Oct 15 06:17:50 AM UTC 24 |
41431928 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.3394472978 |
|
|
Oct 15 06:17:46 AM UTC 24 |
Oct 15 06:17:50 AM UTC 24 |
48134528 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.3196609118 |
|
|
Oct 15 06:16:33 AM UTC 24 |
Oct 15 06:17:52 AM UTC 24 |
33680269052 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2092466644 |
|
|
Oct 15 06:17:29 AM UTC 24 |
Oct 15 06:17:53 AM UTC 24 |
7307485882 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_all.3220434768 |
|
|
Oct 15 06:17:46 AM UTC 24 |
Oct 15 06:17:54 AM UTC 24 |
831740836 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_cfg_cmd.163414332 |
|
|
Oct 15 06:17:51 AM UTC 24 |
Oct 15 06:17:55 AM UTC 24 |
142680532 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_all.879650393 |
|
|
Oct 15 06:16:51 AM UTC 24 |
Oct 15 06:17:57 AM UTC 24 |
6971871552 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_stress_all.1872330893 |
|
|
Oct 15 06:08:06 AM UTC 24 |
Oct 15 06:17:58 AM UTC 24 |
139576965165 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.705534800 |
|
|
Oct 15 06:17:36 AM UTC 24 |
Oct 15 06:17:58 AM UTC 24 |
3933828188 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.3034851243 |
|
|
Oct 15 06:17:56 AM UTC 24 |
Oct 15 06:18:01 AM UTC 24 |
240086567 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_upload.3314674575 |
|
|
Oct 15 06:17:27 AM UTC 24 |
Oct 15 06:18:02 AM UTC 24 |
14173427465 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_stress_all.2194908205 |
|
|
Oct 15 06:18:00 AM UTC 24 |
Oct 15 06:18:03 AM UTC 24 |
112120267 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/12.spi_device_stress_all.2098750646 |
|
|
Oct 15 06:04:01 AM UTC 24 |
Oct 15 06:18:03 AM UTC 24 |
440877132254 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_alert_test.1747757897 |
|
|
Oct 15 06:18:02 AM UTC 24 |
Oct 15 06:18:04 AM UTC 24 |
63720259 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2413158250 |
|
|
Oct 15 06:17:44 AM UTC 24 |
Oct 15 06:18:05 AM UTC 24 |
13880580060 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode.2158084697 |
|
|
Oct 15 06:17:53 AM UTC 24 |
Oct 15 06:18:05 AM UTC 24 |
960440802 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.234850851 |
|
|
Oct 15 06:15:44 AM UTC 24 |
Oct 15 06:18:06 AM UTC 24 |
39185832022 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_csb_read.3435806091 |
|
|
Oct 15 06:18:04 AM UTC 24 |
Oct 15 06:18:06 AM UTC 24 |
16827621 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_all.727360463 |
|
|
Oct 15 06:17:57 AM UTC 24 |
Oct 15 06:18:07 AM UTC 24 |
1104777691 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/32.spi_device_stress_all.2195213291 |
|
|
Oct 15 06:13:13 AM UTC 24 |
Oct 15 06:18:07 AM UTC 24 |
32801071819 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.151099886 |
|
|
Oct 15 06:18:05 AM UTC 24 |
Oct 15 06:18:07 AM UTC 24 |
29747446 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_upload.646553887 |
|
|
Oct 15 06:17:51 AM UTC 24 |
Oct 15 06:18:08 AM UTC 24 |
2234306043 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_rw.110042222 |
|
|
Oct 15 06:18:05 AM UTC 24 |
Oct 15 06:18:09 AM UTC 24 |
796704150 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.4087417328 |
|
|
Oct 15 06:16:35 AM UTC 24 |
Oct 15 06:18:10 AM UTC 24 |
7186351429 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_all.2087796459 |
|
|
Oct 15 06:18:04 AM UTC 24 |
Oct 15 06:18:11 AM UTC 24 |
1746677425 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2119466899 |
|
|
Oct 15 06:16:00 AM UTC 24 |
Oct 15 06:18:11 AM UTC 24 |
10667521832 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.46418417 |
|
|
Oct 15 06:18:07 AM UTC 24 |
Oct 15 06:18:12 AM UTC 24 |
301551515 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_intercept.2031556367 |
|
|
Oct 15 06:18:07 AM UTC 24 |
Oct 15 06:18:12 AM UTC 24 |
214626665 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/24.spi_device_flash_all.1654339646 |
|
|
Oct 15 06:10:09 AM UTC 24 |
Oct 15 06:18:13 AM UTC 24 |
740893174909 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_cfg_cmd.1154018726 |
|
|
Oct 15 06:18:09 AM UTC 24 |
Oct 15 06:18:13 AM UTC 24 |
75205222 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.4287120489 |
|
|
Oct 15 06:18:07 AM UTC 24 |
Oct 15 06:18:16 AM UTC 24 |
1744965505 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.275896970 |
|
|
Oct 15 06:16:57 AM UTC 24 |
Oct 15 06:18:16 AM UTC 24 |
37834215693 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_alert_test.3714619078 |
|
|
Oct 15 06:18:14 AM UTC 24 |
Oct 15 06:18:16 AM UTC 24 |
16467551 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_csb_read.320930205 |
|
|
Oct 15 06:18:14 AM UTC 24 |
Oct 15 06:18:17 AM UTC 24 |
43640210 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_upload.497474584 |
|
|
Oct 15 06:18:09 AM UTC 24 |
Oct 15 06:18:17 AM UTC 24 |
771835917 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.1986816097 |
|
|
Oct 15 06:18:04 AM UTC 24 |
Oct 15 06:18:17 AM UTC 24 |
8593628273 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.1933270910 |
|
|
Oct 15 06:18:11 AM UTC 24 |
Oct 15 06:18:19 AM UTC 24 |
326090674 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_rw.2916860855 |
|
|
Oct 15 06:18:19 AM UTC 24 |
Oct 15 06:18:21 AM UTC 24 |
39340191 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3509500431 |
|
|
Oct 15 06:18:19 AM UTC 24 |
Oct 15 06:18:21 AM UTC 24 |
122040848 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.465119607 |
|
|
Oct 15 06:18:19 AM UTC 24 |
Oct 15 06:18:23 AM UTC 24 |
34714472 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.150999856 |
|
|
Oct 15 06:18:14 AM UTC 24 |
Oct 15 06:18:23 AM UTC 24 |
1811057172 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.1440192249 |
|
|
Oct 15 06:18:19 AM UTC 24 |
Oct 15 06:18:24 AM UTC 24 |
1983194296 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_intercept.891084770 |
|
|
Oct 15 06:18:19 AM UTC 24 |
Oct 15 06:18:24 AM UTC 24 |
99128564 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_all.4008496677 |
|
|
Oct 15 06:18:26 AM UTC 24 |
Oct 15 06:18:28 AM UTC 24 |
15186759 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_all.2787442754 |
|
|
Oct 15 06:16:33 AM UTC 24 |
Oct 15 06:18:28 AM UTC 24 |
25960706717 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode.82457540 |
|
|
Oct 15 06:18:24 AM UTC 24 |
Oct 15 06:18:29 AM UTC 24 |
73278929 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/21.spi_device_flash_all.4163859660 |
|
|
Oct 15 06:08:22 AM UTC 24 |
Oct 15 06:18:29 AM UTC 24 |
320983120840 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.2954542809 |
|
|
Oct 15 06:15:28 AM UTC 24 |
Oct 15 06:18:30 AM UTC 24 |
67757543119 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_cfg_cmd.4074219829 |
|
|
Oct 15 06:18:23 AM UTC 24 |
Oct 15 06:18:30 AM UTC 24 |
349748496 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_upload.1727731004 |
|
|
Oct 15 06:18:21 AM UTC 24 |
Oct 15 06:18:31 AM UTC 24 |
448181543 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_tpm_all.2855270549 |
|
|
Oct 15 06:18:17 AM UTC 24 |
Oct 15 06:18:32 AM UTC 24 |
1186899447 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_all.1690456706 |
|
|
Oct 15 06:16:20 AM UTC 24 |
Oct 15 06:18:32 AM UTC 24 |
7486857578 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode.713742596 |
|
|
Oct 15 06:18:09 AM UTC 24 |
Oct 15 06:18:33 AM UTC 24 |
5616664467 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_alert_test.396864515 |
|
|
Oct 15 06:18:31 AM UTC 24 |
Oct 15 06:18:33 AM UTC 24 |
37484959 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_intercept.3637983927 |
|
|
Oct 15 06:17:49 AM UTC 24 |
Oct 15 06:18:38 AM UTC 24 |
3981066102 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_mailbox.4004245539 |
|
|
Oct 15 06:18:20 AM UTC 24 |
Oct 15 06:18:40 AM UTC 24 |
1608285099 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.153785413 |
|
|
Oct 15 06:15:48 AM UTC 24 |
Oct 15 06:18:41 AM UTC 24 |
133026643318 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1433812855 |
|
|
Oct 15 06:18:25 AM UTC 24 |
Oct 15 06:18:42 AM UTC 24 |
1661316808 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_all.3063528741 |
|
|
Oct 15 06:17:33 AM UTC 24 |
Oct 15 06:18:45 AM UTC 24 |
2704720985 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.3593301566 |
|
|
Oct 15 06:17:55 AM UTC 24 |
Oct 15 06:18:51 AM UTC 24 |
3507243413 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.4021803149 |
|
|
Oct 15 06:16:15 AM UTC 24 |
Oct 15 06:18:54 AM UTC 24 |
16653702700 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_mailbox.1684349105 |
|
|
Oct 15 06:18:07 AM UTC 24 |
Oct 15 06:19:00 AM UTC 24 |
3860571713 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_stress_all.72194014 |
|
|
Oct 15 06:13:43 AM UTC 24 |
Oct 15 06:19:00 AM UTC 24 |
123865561501 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.2488175899 |
|
|
Oct 15 06:17:15 AM UTC 24 |
Oct 15 06:19:11 AM UTC 24 |
10772694883 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.2935115267 |
|
|
Oct 15 06:17:58 AM UTC 24 |
Oct 15 06:19:23 AM UTC 24 |
10811883815 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.3114972251 |
|
|
Oct 15 06:16:31 AM UTC 24 |
Oct 15 06:19:27 AM UTC 24 |
16147120356 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_all.2316933943 |
|
|
Oct 15 06:18:11 AM UTC 24 |
Oct 15 06:19:28 AM UTC 24 |
55100261572 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.2795891040 |
|
|
Oct 15 06:18:12 AM UTC 24 |
Oct 15 06:19:39 AM UTC 24 |
2380241975 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_all.2303863489 |
|
|
Oct 15 06:17:15 AM UTC 24 |
Oct 15 06:19:40 AM UTC 24 |
18716379962 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_stress_all.2953495592 |
|
|
Oct 15 06:17:01 AM UTC 24 |
Oct 15 06:19:41 AM UTC 24 |
162840723826 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.1049011992 |
|
|
Oct 15 06:17:36 AM UTC 24 |
Oct 15 06:19:41 AM UTC 24 |
21113898042 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.2789379485 |
|
|
Oct 15 06:13:42 AM UTC 24 |
Oct 15 06:19:42 AM UTC 24 |
130591937648 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3326839326 |
|
|
Oct 15 06:18:24 AM UTC 24 |
Oct 15 06:19:51 AM UTC 24 |
7339075915 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_mailbox.800840632 |
|
|
Oct 15 06:17:49 AM UTC 24 |
Oct 15 06:19:53 AM UTC 24 |
30539255180 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.1352363963 |
|
|
Oct 15 06:16:47 AM UTC 24 |
Oct 15 06:19:53 AM UTC 24 |
43444795306 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_all.4196865101 |
|
|
Oct 15 06:12:53 AM UTC 24 |
Oct 15 06:20:03 AM UTC 24 |
673569910915 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.2393836607 |
|
|
Oct 15 06:07:59 AM UTC 24 |
Oct 15 06:20:28 AM UTC 24 |
121754269076 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.4049580345 |
|
|
Oct 15 06:18:29 AM UTC 24 |
Oct 15 06:20:30 AM UTC 24 |
30808893200 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3651429417 |
|
|
Oct 15 06:18:12 AM UTC 24 |
Oct 15 06:21:10 AM UTC 24 |
36298454965 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.1516030679 |
|
|
Oct 15 06:17:32 AM UTC 24 |
Oct 15 06:21:11 AM UTC 24 |
84257603261 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.2643811916 |
|
|
Oct 15 06:15:10 AM UTC 24 |
Oct 15 06:21:20 AM UTC 24 |
62288209826 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.896734132 |
|
|
Oct 15 06:12:56 AM UTC 24 |
Oct 15 06:21:28 AM UTC 24 |
337123382017 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.546761348 |
|
|
Oct 15 06:18:00 AM UTC 24 |
Oct 15 06:21:37 AM UTC 24 |
87164864984 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_stress_all.1918671831 |
|
|
Oct 15 06:17:17 AM UTC 24 |
Oct 15 06:21:53 AM UTC 24 |
33135922924 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.1395250663 |
|
|
Oct 15 06:12:39 AM UTC 24 |
Oct 15 06:21:58 AM UTC 24 |
217444236797 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2661455465 |
|
|
Oct 15 06:17:13 AM UTC 24 |
Oct 15 06:22:32 AM UTC 24 |
69088924641 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.997592892 |
|
|
Oct 15 06:17:16 AM UTC 24 |
Oct 15 06:22:32 AM UTC 24 |
92273200627 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/46.spi_device_stress_all.1994288191 |
|
|
Oct 15 06:17:36 AM UTC 24 |
Oct 15 06:22:40 AM UTC 24 |
37523399945 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.1444508673 |
|
|
Oct 15 06:16:54 AM UTC 24 |
Oct 15 06:23:11 AM UTC 24 |
33928191580 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.709673324 |
|
|
Oct 15 06:18:09 AM UTC 24 |
Oct 15 06:23:21 AM UTC 24 |
74675530575 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/42.spi_device_stress_all.374230657 |
|
|
Oct 15 06:16:22 AM UTC 24 |
Oct 15 06:23:21 AM UTC 24 |
136578575955 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.3817429679 |
|
|
Oct 15 06:16:04 AM UTC 24 |
Oct 15 06:23:26 AM UTC 24 |
636096420078 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.1124659617 |
|
|
Oct 15 06:15:10 AM UTC 24 |
Oct 15 06:24:34 AM UTC 24 |
49533162622 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.488731970 |
|
|
Oct 15 06:18:29 AM UTC 24 |
Oct 15 06:24:51 AM UTC 24 |
118046963083 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3842754283 |
|
|
Oct 15 06:14:27 AM UTC 24 |
Oct 15 06:26:05 AM UTC 24 |
74203054746 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/49.spi_device_stress_all.3555966433 |
|
|
Oct 15 06:18:31 AM UTC 24 |
Oct 15 06:26:09 AM UTC 24 |
95635139388 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/16.spi_device_stress_all.905663092 |
|
|
Oct 15 06:06:23 AM UTC 24 |
Oct 15 06:26:20 AM UTC 24 |
175907111318 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/default/48.spi_device_stress_all.281459430 |
|
|
Oct 15 06:18:14 AM UTC 24 |
Oct 15 06:28:25 AM UTC 24 |
124516393736 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.403904324 |
|
|
Oct 15 03:02:55 AM UTC 24 |
Oct 15 03:03:19 AM UTC 24 |
517985469 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2030634697 |
|
|
Oct 15 03:02:44 AM UTC 24 |
Oct 15 03:02:46 AM UTC 24 |
48949042 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2290298584 |
|
|
Oct 15 03:02:44 AM UTC 24 |
Oct 15 03:02:46 AM UTC 24 |
13423619 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.2140667453 |
|
|
Oct 15 03:02:44 AM UTC 24 |
Oct 15 03:02:47 AM UTC 24 |
63479323 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3280587610 |
|
|
Oct 15 03:02:44 AM UTC 24 |
Oct 15 03:02:47 AM UTC 24 |
83802305 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.640525617 |
|
|
Oct 15 03:02:44 AM UTC 24 |
Oct 15 03:02:47 AM UTC 24 |
65460291 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.927936055 |
|
|
Oct 15 03:02:45 AM UTC 24 |
Oct 15 03:02:47 AM UTC 24 |
36785439 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.1537303142 |
|
|
Oct 15 03:02:45 AM UTC 24 |
Oct 15 03:02:47 AM UTC 24 |
18929427 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.4219776429 |
|
|
Oct 15 03:02:45 AM UTC 24 |
Oct 15 03:02:48 AM UTC 24 |
43851384 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2558261070 |
|
|
Oct 15 03:02:44 AM UTC 24 |
Oct 15 03:02:48 AM UTC 24 |
257313451 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.541392192 |
|
|
Oct 15 03:02:44 AM UTC 24 |
Oct 15 03:02:48 AM UTC 24 |
114113484 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.275268290 |
|
|
Oct 15 03:02:43 AM UTC 24 |
Oct 15 03:02:49 AM UTC 24 |
283237913 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1136060874 |
|
|
Oct 15 03:02:45 AM UTC 24 |
Oct 15 03:02:49 AM UTC 24 |
73060403 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.382797254 |
|
|
Oct 15 03:02:44 AM UTC 24 |
Oct 15 03:02:50 AM UTC 24 |
59328152 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.203791819 |
|
|
Oct 15 03:02:48 AM UTC 24 |
Oct 15 03:02:50 AM UTC 24 |
29375130 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2580174737 |
|
|
Oct 15 03:02:48 AM UTC 24 |
Oct 15 03:02:50 AM UTC 24 |
12605139 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.3540013361 |
|
|
Oct 15 03:02:45 AM UTC 24 |
Oct 15 03:02:50 AM UTC 24 |
407548661 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3698945754 |
|
|
Oct 15 03:02:49 AM UTC 24 |
Oct 15 03:02:51 AM UTC 24 |
23606935 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.964186793 |
|
|
Oct 15 03:02:49 AM UTC 24 |
Oct 15 03:02:52 AM UTC 24 |
46499230 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3904482466 |
|
|
Oct 15 03:02:48 AM UTC 24 |
Oct 15 03:02:52 AM UTC 24 |
406517673 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2328495537 |
|
|
Oct 15 03:02:48 AM UTC 24 |
Oct 15 03:02:53 AM UTC 24 |
555011559 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2776883317 |
|
|
Oct 15 03:02:44 AM UTC 24 |
Oct 15 03:02:53 AM UTC 24 |
437552983 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.2825569337 |
|
|
Oct 15 03:02:49 AM UTC 24 |
Oct 15 03:02:54 AM UTC 24 |
72136613 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3919132350 |
|
|
Oct 15 03:02:50 AM UTC 24 |
Oct 15 03:02:54 AM UTC 24 |
53824312 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3225868190 |
|
|
Oct 15 03:02:47 AM UTC 24 |
Oct 15 03:02:54 AM UTC 24 |
205479857 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.2751038564 |
|
|
Oct 15 03:02:52 AM UTC 24 |
Oct 15 03:02:54 AM UTC 24 |
13687145 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1120474996 |
|
|
Oct 15 03:02:50 AM UTC 24 |
Oct 15 03:02:54 AM UTC 24 |
101670578 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.427887534 |
|
|
Oct 15 03:02:51 AM UTC 24 |
Oct 15 03:02:55 AM UTC 24 |
315012430 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1350093480 |
|
|
Oct 15 03:02:53 AM UTC 24 |
Oct 15 03:02:56 AM UTC 24 |
13996565 ps |
| T105 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.1696938994 |
|
|
Oct 15 03:02:43 AM UTC 24 |
Oct 15 03:02:56 AM UTC 24 |
761890789 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1928562646 |
|
|
Oct 15 03:02:54 AM UTC 24 |
Oct 15 03:02:57 AM UTC 24 |
122287979 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.3918639894 |
|
|
Oct 15 03:02:48 AM UTC 24 |
Oct 15 03:02:57 AM UTC 24 |
212153785 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.1279210114 |
|
|
Oct 15 03:02:53 AM UTC 24 |
Oct 15 03:02:57 AM UTC 24 |
129878490 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2378503189 |
|
|
Oct 15 03:02:44 AM UTC 24 |
Oct 15 03:02:57 AM UTC 24 |
188421043 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.675092746 |
|
|
Oct 15 03:02:45 AM UTC 24 |
Oct 15 03:02:58 AM UTC 24 |
1364604281 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.1335429261 |
|
|
Oct 15 03:02:55 AM UTC 24 |
Oct 15 03:02:59 AM UTC 24 |
165327324 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2810812002 |
|
|
Oct 15 03:02:55 AM UTC 24 |
Oct 15 03:02:59 AM UTC 24 |
91587631 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.3102099959 |
|
|
Oct 15 03:02:55 AM UTC 24 |
Oct 15 03:03:00 AM UTC 24 |
353216361 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.2818875176 |
|
|
Oct 15 03:02:57 AM UTC 24 |
Oct 15 03:03:00 AM UTC 24 |
17451332 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.4112867987 |
|
|
Oct 15 03:02:57 AM UTC 24 |
Oct 15 03:03:00 AM UTC 24 |
11327955 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.120035417 |
|
|
Oct 15 03:02:56 AM UTC 24 |
Oct 15 03:03:01 AM UTC 24 |
60141690 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.9325074 |
|
|
Oct 15 03:02:57 AM UTC 24 |
Oct 15 03:03:01 AM UTC 24 |
483827142 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.4230642250 |
|
|
Oct 15 03:02:50 AM UTC 24 |
Oct 15 03:03:01 AM UTC 24 |
138729834 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1925890289 |
|
|
Oct 15 03:02:58 AM UTC 24 |
Oct 15 03:03:02 AM UTC 24 |
24199469 ps |