Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3636839	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4344464

1

T1

1861

T3

1

T4

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4428387	1			T1	1638		T2	1		T3	79
values[0x0]	1776022	1			T1	874		T4	4		T5	21
values[0x1]	1776894	1			T1	832		T4	5		T5	22

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2587604	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5393699

1

T1

2257

T3

26

T4

10

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	28416	1			T1	17		T10	8		T16	8
valid_sources[0x01]	31919	1			T1	10		T10	21		T16	1
valid_sources[0x02]	28735	1			T1	16		T10	8		T12	3
valid_sources[0x03]	28640	1			T1	13		T10	39		T14	455
valid_sources[0x04]	34729	1			T1	15		T10	1		T12	1
valid_sources[0x05]	76236	1			T1	15		T10	14		T16	12
valid_sources[0x06]	29055	1			T1	18		T3	1		T10	23
valid_sources[0x07]	26743	1			T1	16		T3	3		T10	33
valid_sources[0x08]	30880	1			T1	14		T10	26		T16	8
valid_sources[0x09]	32826	1			T1	10		T5	1		T10	5
valid_sources[0x0a]	46108	1			T1	9		T10	32		T16	1
valid_sources[0x0b]	27677	1			T1	14		T10	4		T16	3
valid_sources[0x0c]	29314	1			T1	12		T5	1		T10	10
valid_sources[0x0d]	28167	1			T1	18		T5	1		T10	29
valid_sources[0x0e]	30871	1			T1	9		T5	1		T10	9
valid_sources[0x0f]	29108	1			T1	6		T3	2		T5	1
valid_sources[0x10]	27374	1			T1	12		T3	2		T5	1
valid_sources[0x11]	28837	1			T1	18		T10	31		T12	5
valid_sources[0x12]	29199	1			T1	14		T5	1		T10	16
valid_sources[0x13]	28862	1			T1	7		T10	67		T16	4
valid_sources[0x14]	29067	1			T1	9		T10	29		T12	1
valid_sources[0x15]	27147	1			T1	9		T3	1		T10	20
valid_sources[0x16]	30875	1			T1	11		T10	69		T16	5
valid_sources[0x17]	29524	1			T1	17		T9	7		T10	47
valid_sources[0x18]	27253	1			T1	13		T10	16		T16	1
valid_sources[0x19]	27871	1			T1	13		T5	1		T10	30
valid_sources[0x1a]	29771	1			T1	14		T5	1		T10	26
valid_sources[0x1b]	29355	1			T1	17		T5	1		T8	2
valid_sources[0x1c]	28177	1			T1	8		T10	26		T12	1
valid_sources[0x1d]	28619	1			T1	11		T10	39		T16	8
valid_sources[0x1e]	28956	1			T1	11		T5	1		T10	5
valid_sources[0x1f]	35192	1			T1	11		T10	32		T16	3
valid_sources[0x20]	30943	1			T1	12		T3	2		T10	54
valid_sources[0x21]	33113	1			T1	11		T10	24		T12	1
valid_sources[0x22]	27999	1			T1	10		T8	2		T10	46
valid_sources[0x23]	29953	1			T1	13		T8	1		T10	16
valid_sources[0x24]	32793	1			T1	14		T10	85		T16	5
valid_sources[0x25]	30332	1			T1	22		T10	15		T16	2
valid_sources[0x26]	34808	1			T1	16		T10	27		T16	3
valid_sources[0x27]	29671	1			T1	9		T3	1		T5	1
valid_sources[0x28]	38346	1			T1	14		T10	47		T12	1
valid_sources[0x29]	40491	1			T1	18		T10	51		T16	1
valid_sources[0x2a]	41612	1			T1	12		T3	3		T10	15
valid_sources[0x2b]	27142	1			T1	20		T10	30		T12	1
valid_sources[0x2c]	33806	1			T1	10		T16	4		T41	1
valid_sources[0x2d]	29623	1			T1	13		T10	36		T16	4
valid_sources[0x2e]	30482	1			T1	7		T10	20		T12	1
valid_sources[0x2f]	29907	1			T1	23		T5	1		T16	1
valid_sources[0x30]	27510	1			T1	8		T10	7		T16	8
valid_sources[0x31]	29928	1			T1	11		T10	11		T12	5
valid_sources[0x32]	28713	1			T1	20		T10	16		T16	5
valid_sources[0x33]	27214	1			T1	11		T10	25		T16	4
valid_sources[0x34]	30232	1			T1	10		T5	2		T10	59
valid_sources[0x35]	28353	1			T1	9		T10	24		T41	3
valid_sources[0x36]	29083	1			T1	13		T3	1		T10	17
valid_sources[0x37]	27874	1			T1	13		T10	13		T16	19
valid_sources[0x38]	28451	1			T1	13		T10	3		T16	5
valid_sources[0x39]	28955	1			T1	20		T3	1		T10	30
valid_sources[0x3a]	34586	1			T1	17		T10	6		T16	2
valid_sources[0x3b]	33968	1			T1	30		T3	2		T10	77
valid_sources[0x3c]	27094	1			T1	12		T8	1		T10	39
valid_sources[0x3d]	29805	1			T1	17		T10	56		T16	6
valid_sources[0x3e]	28751	1			T1	13		T10	26		T16	2
valid_sources[0x3f]	33994	1			T1	16		T5	1		T10	54
valid_sources[0x40]	28756	1			T1	12		T10	34		T16	10
valid_sources[0x41]	29094	1			T1	9		T10	1		T16	3
valid_sources[0x42]	28351	1			T1	15		T3	1		T10	18
valid_sources[0x43]	28614	1			T1	7		T10	9		T16	1
valid_sources[0x44]	29995	1			T1	17		T10	33		T16	4
valid_sources[0x45]	28948	1			T1	11		T10	3		T16	5
valid_sources[0x46]	28304	1			T1	11		T10	26		T16	4
valid_sources[0x47]	28751	1			T1	19		T3	1		T10	38
valid_sources[0x48]	31323	1			T1	7		T10	1		T11	20
valid_sources[0x49]	27959	1			T1	9		T10	43		T16	7
valid_sources[0x4a]	28693	1			T1	20		T10	15		T16	5
valid_sources[0x4b]	30499	1			T1	9		T10	38		T16	3
valid_sources[0x4c]	29599	1			T1	15		T10	21		T16	4
valid_sources[0x4d]	28418	1			T1	13		T8	1		T10	70
valid_sources[0x4e]	29742	1			T1	13		T10	23		T14	184
valid_sources[0x4f]	29973	1			T1	15		T5	2		T10	31
valid_sources[0x50]	27798	1			T1	15		T10	10		T16	7
valid_sources[0x51]	30617	1			T1	21		T10	17		T16	3
valid_sources[0x52]	30431	1			T1	9		T8	4		T10	19
valid_sources[0x53]	32839	1			T1	12		T10	27		T16	11
valid_sources[0x54]	28078	1			T1	21		T3	1		T10	5
valid_sources[0x55]	35581	1			T1	15		T10	7		T12	1
valid_sources[0x56]	28757	1			T1	15		T3	1		T8	1
valid_sources[0x57]	32001	1			T1	10		T5	2		T10	18
valid_sources[0x58]	27829	1			T1	15		T3	6		T10	91
valid_sources[0x59]	28961	1			T1	13		T10	7		T15	1
valid_sources[0x5a]	29824	1			T1	14		T10	23		T16	4
valid_sources[0x5b]	30543	1			T1	10		T8	1		T10	10
valid_sources[0x5c]	32085	1			T1	11		T10	10		T16	7
valid_sources[0x5d]	31056	1			T1	5		T10	21		T16	5
valid_sources[0x5e]	29154	1			T1	11		T8	1		T10	3
valid_sources[0x5f]	36883	1			T1	16		T10	19		T16	4
valid_sources[0x60]	30674	1			T1	11		T3	1		T10	21
valid_sources[0x61]	27473	1			T1	17		T5	1		T10	17
valid_sources[0x62]	30750	1			T1	18		T10	12		T16	15
valid_sources[0x63]	32063	1			T1	15		T10	31		T16	4
valid_sources[0x64]	28491	1			T1	16		T10	9		T16	5
valid_sources[0x65]	28204	1			T1	9		T10	2		T12	1
valid_sources[0x66]	27833	1			T1	13		T10	9		T16	6
valid_sources[0x67]	28195	1			T1	15		T10	46		T16	6
valid_sources[0x68]	31519	1			T1	10		T10	15		T12	3
valid_sources[0x69]	29456	1			T1	10		T10	31		T16	6
valid_sources[0x6a]	30619	1			T1	10		T10	15		T16	10
valid_sources[0x6b]	32150	1			T1	13		T10	1		T12	2
valid_sources[0x6c]	35122	1			T1	10		T10	43		T16	5
valid_sources[0x6d]	29029	1			T1	16		T10	21		T16	2
valid_sources[0x6e]	29639	1			T1	16		T10	34		T12	6
valid_sources[0x6f]	26626	1			T1	20		T10	3		T16	5
valid_sources[0x70]	26938	1			T1	13		T3	2		T10	5
valid_sources[0x71]	31106	1			T1	5		T8	5		T10	19
valid_sources[0x72]	33697	1			T1	7		T8	1		T10	42
valid_sources[0x73]	29550	1			T1	12		T10	21		T16	14
valid_sources[0x74]	26954	1			T1	14		T10	24		T16	3
valid_sources[0x75]	30233	1			T1	10		T8	1		T10	32
valid_sources[0x76]	29882	1			T1	8		T10	17		T16	2
valid_sources[0x77]	28706	1			T1	16		T3	5		T6	3
valid_sources[0x78]	28729	1			T1	18		T3	2		T8	1
valid_sources[0x79]	70029	1			T1	8		T10	4		T16	3
valid_sources[0x7a]	29651	1			T1	11		T10	10		T16	4
valid_sources[0x7b]	35106	1			T1	12		T10	19		T16	5
valid_sources[0x7c]	26996	1			T1	10		T10	20		T16	1
valid_sources[0x7d]	30983	1			T1	17		T5	3		T10	36
valid_sources[0x7e]	44435	1			T1	10		T5	1		T10	28
valid_sources[0x7f]	29157	1			T1	12		T3	2		T8	2
valid_sources[0x80]	29681	1			T1	13		T10	13		T16	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1119546

1

T1

666

T3

1

T4

1

values[0x0]

all_enables

biggest_size

1624685

1

T1

651

T4

3

T5

19

values[0x1]

all_enables

biggest_size

1600233

1

T1

544

T4

4

T5

16