Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_spi_device_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3670393	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4398219

1

T3

20

T4

873

T5

201

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	4399378	1			T1	45		T2	1		T3	1
values[0x0]	1832891	1			T3	15		T4	434		T5	130
values[0x1]	1836343	1			T3	10		T4	441		T5	119

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2604761	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5463851

1

T1

15

T2

1

T3

21

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	30555	1			T4	2		T7	1		T8	7
valid_sources[0x01]	29953	1			T4	1		T7	2		T8	6
valid_sources[0x02]	30039	1			T1	1		T4	9		T7	9
valid_sources[0x03]	29971	1			T1	1		T4	5		T7	4
valid_sources[0x04]	29327	1			T4	3		T7	13		T9	5
valid_sources[0x05]	36199	1			T4	5		T7	1		T8	2
valid_sources[0x06]	31961	1			T4	6		T5	2		T7	7
valid_sources[0x07]	29760	1			T4	1		T5	3		T7	3
valid_sources[0x08]	45729	1			T5	1		T7	9		T8	1
valid_sources[0x09]	29382	1			T5	1		T7	6		T9	6
valid_sources[0x0a]	31466	1			T4	3		T7	10		T8	4
valid_sources[0x0b]	28672	1			T4	7		T7	4		T8	2
valid_sources[0x0c]	30766	1			T5	1		T7	4		T8	2
valid_sources[0x0d]	32427	1			T4	4		T5	1		T8	14
valid_sources[0x0e]	32858	1			T4	2		T7	7		T8	2
valid_sources[0x0f]	35395	1			T2	1		T4	2		T7	1
valid_sources[0x10]	29427	1			T1	1		T4	1		T7	3
valid_sources[0x11]	31030	1			T4	7		T5	1		T7	4
valid_sources[0x12]	29295	1			T4	2		T7	4		T9	5
valid_sources[0x13]	27647	1			T4	4		T5	1		T7	1
valid_sources[0x14]	36777	1			T4	4		T7	13		T9	3
valid_sources[0x15]	30611	1			T4	3		T7	11		T8	4
valid_sources[0x16]	30465	1			T4	1		T5	2		T7	17
valid_sources[0x17]	32498	1			T1	2		T4	4		T5	2
valid_sources[0x18]	28638	1			T4	1		T7	12		T8	2
valid_sources[0x19]	32771	1			T1	1		T4	1		T5	1
valid_sources[0x1a]	29199	1			T4	4		T5	1		T7	7
valid_sources[0x1b]	30086	1			T1	2		T5	1		T7	13
valid_sources[0x1c]	31636	1			T4	8		T5	1		T7	11
valid_sources[0x1d]	31468	1			T1	2		T4	2		T5	3
valid_sources[0x1e]	32684	1			T5	1		T7	15		T8	4
valid_sources[0x1f]	35739	1			T4	5		T5	1		T7	7
valid_sources[0x20]	32130	1			T4	9		T5	1		T7	8
valid_sources[0x21]	29339	1			T5	1		T7	10		T8	3
valid_sources[0x22]	34166	1			T5	1		T8	4		T9	2
valid_sources[0x23]	31330	1			T4	4		T7	13		T8	2
valid_sources[0x24]	29870	1			T4	7		T5	1		T8	4
valid_sources[0x25]	34491	1			T4	2		T5	1		T8	4
valid_sources[0x26]	30922	1			T4	6		T5	2		T8	4
valid_sources[0x27]	31661	1			T4	1		T7	10		T9	4
valid_sources[0x28]	32016	1			T4	2		T8	1		T9	2
valid_sources[0x29]	30538	1			T4	2		T5	2		T8	1
valid_sources[0x2a]	28931	1			T4	1		T7	11		T9	3
valid_sources[0x2b]	29158	1			T4	3		T5	2		T7	14
valid_sources[0x2c]	31665	1			T1	1		T4	5		T7	1
valid_sources[0x2d]	30731	1			T4	5		T5	1		T8	1
valid_sources[0x2e]	28424	1			T1	1		T4	5		T8	5
valid_sources[0x2f]	28525	1			T4	3		T5	2		T7	16
valid_sources[0x30]	31289	1			T1	1		T4	1		T5	1
valid_sources[0x31]	32266	1			T7	1		T8	1		T9	4
valid_sources[0x32]	28294	1			T1	3		T4	1		T5	2
valid_sources[0x33]	29113	1			T1	1		T4	1		T7	3
valid_sources[0x34]	37010	1			T4	1		T5	1		T7	1
valid_sources[0x35]	28536	1			T7	4		T8	5		T9	3
valid_sources[0x36]	30958	1			T5	1		T7	6		T8	8
valid_sources[0x37]	33630	1			T4	2		T7	6		T8	10
valid_sources[0x38]	29458	1			T3	26		T7	18		T8	3
valid_sources[0x39]	29265	1			T4	1		T5	1		T7	4
valid_sources[0x3a]	32050	1			T4	2		T5	3		T7	2
valid_sources[0x3b]	31185	1			T4	2		T5	2		T7	5
valid_sources[0x3c]	29174	1			T4	4		T5	1		T7	21
valid_sources[0x3d]	30502	1			T4	7		T5	2		T7	3
valid_sources[0x3e]	31037	1			T4	2		T5	1		T7	1
valid_sources[0x3f]	29698	1			T4	2		T5	3		T7	2
valid_sources[0x40]	31505	1			T1	1		T4	4		T5	1
valid_sources[0x41]	30093	1			T4	1		T8	10		T9	2
valid_sources[0x42]	32316	1			T4	2		T7	8		T8	7
valid_sources[0x43]	32194	1			T4	1		T5	3		T7	5
valid_sources[0x44]	30734	1			T4	3		T7	7		T8	2
valid_sources[0x45]	29909	1			T4	5		T5	1		T7	9
valid_sources[0x46]	28648	1			T7	2		T8	7		T9	1
valid_sources[0x47]	29210	1			T1	1		T4	5		T5	4
valid_sources[0x48]	30673	1			T1	1		T4	8		T5	1
valid_sources[0x49]	29349	1			T5	2		T7	1		T8	2
valid_sources[0x4a]	30558	1			T4	4		T5	1		T7	3
valid_sources[0x4b]	27951	1			T4	1		T5	1		T8	1
valid_sources[0x4c]	33789	1			T4	7		T5	2		T7	11
valid_sources[0x4d]	30854	1			T4	3		T7	1		T8	4
valid_sources[0x4e]	31721	1			T4	9		T5	1		T7	12
valid_sources[0x4f]	28581	1			T1	1		T4	7		T8	2
valid_sources[0x50]	30395	1			T4	13		T7	11		T8	5
valid_sources[0x51]	35367	1			T4	6		T5	1		T8	1
valid_sources[0x52]	30306	1			T5	1		T7	7		T8	10
valid_sources[0x53]	30984	1			T4	4		T5	1		T7	1
valid_sources[0x54]	29818	1			T4	4		T5	2		T7	1
valid_sources[0x55]	28753	1			T4	1		T5	8		T7	5
valid_sources[0x56]	38329	1			T1	1		T4	2		T5	1
valid_sources[0x57]	29846	1			T1	1		T4	1		T5	1
valid_sources[0x58]	30484	1			T4	1		T5	1		T8	3
valid_sources[0x59]	34523	1			T1	1		T4	2		T5	1
valid_sources[0x5a]	35953	1			T4	2		T5	1		T7	4
valid_sources[0x5b]	30335	1			T4	2		T5	1		T7	1
valid_sources[0x5c]	30702	1			T4	5		T5	2		T7	7
valid_sources[0x5d]	29237	1			T4	4		T5	1		T8	3
valid_sources[0x5e]	33747	1			T8	5		T9	5		T11	40
valid_sources[0x5f]	30795	1			T1	1		T4	6		T5	1
valid_sources[0x60]	29599	1			T4	1		T5	1		T7	8
valid_sources[0x61]	32651	1			T4	2		T7	5		T9	1
valid_sources[0x62]	30100	1			T1	1		T4	4		T5	1
valid_sources[0x63]	30398	1			T5	3		T7	7		T8	6
valid_sources[0x64]	32748	1			T4	3		T5	1		T9	8
valid_sources[0x65]	30250	1			T4	3		T5	3		T7	5
valid_sources[0x66]	31491	1			T4	3		T7	4		T8	12
valid_sources[0x67]	30095	1			T4	1		T7	30		T9	10
valid_sources[0x68]	29156	1			T1	1		T4	4		T5	1
valid_sources[0x69]	29413	1			T4	5		T7	4		T9	1
valid_sources[0x6a]	29453	1			T4	4		T7	4		T8	7
valid_sources[0x6b]	30043	1			T4	4		T7	2		T8	8
valid_sources[0x6c]	29741	1			T4	4		T7	1		T8	4
valid_sources[0x6d]	33792	1			T4	9		T7	8		T8	1
valid_sources[0x6e]	29797	1			T4	1		T5	1		T7	3
valid_sources[0x6f]	29969	1			T4	2		T7	1		T8	8
valid_sources[0x70]	29133	1			T4	3		T7	6		T8	1
valid_sources[0x71]	29507	1			T1	1		T4	5		T5	1
valid_sources[0x72]	31480	1			T4	4		T5	1		T7	11
valid_sources[0x73]	28919	1			T4	2		T9	4		T11	10
valid_sources[0x74]	32299	1			T4	5		T5	1		T7	6
valid_sources[0x75]	32810	1			T4	1		T8	1		T9	6
valid_sources[0x76]	31332	1			T4	1		T5	1		T7	1
valid_sources[0x77]	30678	1			T1	1		T7	10		T8	2
valid_sources[0x78]	36595	1			T4	1		T8	2		T9	5
valid_sources[0x79]	30144	1			T5	1		T7	4		T8	5
valid_sources[0x7a]	30447	1			T4	7		T5	3		T7	3
valid_sources[0x7b]	29111	1			T4	2		T7	12		T8	6
valid_sources[0x7c]	32351	1			T4	4		T5	1		T7	3
valid_sources[0x7d]	33497	1			T4	3		T5	1		T7	3
valid_sources[0x7e]	31689	1			T4	2		T5	1		T7	7
valid_sources[0x7f]	29591	1			T4	4		T7	5		T8	2
valid_sources[0x80]	28994	1			T5	2		T7	15		T9	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1072990

1

T4

1

T6

26

T7

199

values[0x0]

all_enables

biggest_size

1674361

1

T3

11

T4

432

T5

109

values[0x1]

all_enables

biggest_size

1650868

1

T3

9

T4

440

T5

92