Unified Coverage Report :: Group :: cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

Group : cip_base_pkg::tl_intg_err_mem_subword_cg_wrap::tl_intg_err_mem_subword_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]	100.00	1	100	1	64	64

---

Group Instance : tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_num_enable_bytes	2	0	2	100.00	100	1	1	0
cp_tl_intg_err_type	4	0	4	100.00	100	1	1	0
cp_write	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tl_intg_err_mem_subword_cgs_wrap[spi_device_reg_block]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	16	0	16	100.00	100	1	1	0

Summary for Variable cp_num_num_enable_bytes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_num_enable_bytes

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

partial

3660404

1

T1

1483

T2

1

T3

78

full_word

4345849

1

T1

1861

T3

1

T4

8

---

Summary for Variable cp_tl_intg_err_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_tl_intg_err_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	8005843	1			T1	3344		T2	1		T3	79
auto[TlIntgErrCmd]	131	1			T99	5		T126	4		T127	11
auto[TlIntgErrData]	130	1			T99	2		T126	3		T127	9
auto[TlIntgErrBoth]	149	1			T99	3		T126	3		T127	10

---

Summary for Variable cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4433227

1

T1

1638

T2

1

T3

79

auto[1]

3573026

1

T1

1706

T4

9

T5

43

---

Summary for Cross cr_all

Samples crossed: cp_tl_intg_err_type cp_num_num_enable_bytes cp_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_tl_intg_err_type	cp_num_num_enable_bytes	cp_write	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[TlIntgErrNone]	partial	auto[0]	3313143	1			T1	972		T2	1		T3	78
auto[TlIntgErrNone]	partial	auto[1]	346883	1			T1	511		T4	2		T5	8
auto[TlIntgErrNone]	full_word	auto[0]	1119897	1			T1	666		T3	1		T4	1
auto[TlIntgErrNone]	full_word	auto[1]	3225920	1			T1	1195		T4	7		T5	35
auto[TlIntgErrCmd]	partial	auto[0]	58	1			T99	1		T126	2		T127	3
auto[TlIntgErrCmd]	partial	auto[1]	62	1			T99	4		T126	2		T127	6
auto[TlIntgErrCmd]	full_word	auto[0]	8	1			T211	1		T214	1		T215	1
auto[TlIntgErrCmd]	full_word	auto[1]	3	1			T127	2		T210	1		-	-
auto[TlIntgErrData]	partial	auto[0]	68	1			T99	1		T126	1		T127	5
auto[TlIntgErrData]	partial	auto[1]	53	1			T99	1		T126	2		T127	3
auto[TlIntgErrData]	full_word	auto[0]	3	1			T216	1		T217	1		T218	1
auto[TlIntgErrData]	full_word	auto[1]	6	1			T127	1		T212	1		T219	1
auto[TlIntgErrBoth]	partial	auto[0]	46	1			T99	2		T126	2		T127	3
auto[TlIntgErrBoth]	partial	auto[1]	91	1			T99	1		T126	1		T127	7
auto[TlIntgErrBoth]	full_word	auto[0]	4	1			T211	1		T220	1		T215	1
auto[TlIntgErrBoth]	full_word	auto[1]	8	1			T212	1		T211	2		T221	1