Module : prim_flop
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_prim_abstract_flop_0/prim_flop.sv
Module self-instances :
Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_flash_readbuf_watermark_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
Instance :
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_flash_readbuf_flip_pulse_sync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
Instance :
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_rst_spi_out_sync
Instance :
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| 95.10 | 95.20 | 93.48 | 97.84 | 93.55 | 95.45 | dut |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_tpm_rst_out_sync
Instance :
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| 95.10 | 95.20 | 93.48 | 97.84 | 93.55 | 95.45 | dut |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_1
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_tpm_csb_rst_sync.u_sync.gen_generic.u_impl_generic.u_sync_2
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spid_csb_sync.u_count_sync.gen_generic.u_impl_generic.u_sync_1
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spid_csb_sync.u_count_sync.gen_generic.u_impl_generic.u_sync_2
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_sys_csb_syncd.gen_generic.u_impl_generic.u_sync_1
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_sys_csb_syncd.gen_generic.u_impl_generic.u_sync_2
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_sys_tpm_csb_sync.gen_generic.u_impl_generic.u_sync_1
Instance :
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_sys_tpm_csb_sync.gen_generic.u_impl_generic.u_sync_2
Instance :
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_read_pipe_stg1
Instance :
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| 95.10 | 95.20 | 93.48 | 97.84 | 93.55 | 95.45 | dut |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_read_pipe_stg2
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| 95.10 | 95.20 | 93.48 | 97.84 | 93.55 | 95.45 | dut |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_read_en_pipe_stg1
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| 95.10 | 95.20 | 93.48 | 97.84 | 93.55 | 95.45 | dut |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_read_en_pipe_stg2
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| 95.10 | 95.20 | 93.48 | 97.84 | 93.55 | 95.45 | dut |
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| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_read_intercept_pipe_stg1
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| 95.10 | 95.20 | 93.48 | 97.84 | 93.55 | 95.45 | dut |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_read_intercept_pipe_stg2
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| 95.10 | 95.20 | 93.48 | 97.84 | 93.55 | 95.45 | dut |
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| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1
Instance :
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2
Instance :
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1
Instance :
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_readcmd.u_readbuffer.u_sys2spi_clr.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spid_status.u_sck2csb_status
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| 100.00 | 100.00 | 100.00 | 100.00 | 100.00 | u_spid_status |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.gen_generic.u_impl_generic.u_sync_1
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_wptr.gen_generic.u_impl_generic.u_sync_2
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.gen_generic.u_impl_generic.u_sync_1
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spid_status.u_sw_status_update_sync.sync_rptr.gen_generic.u_impl_generic.u_sync_2
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.gen_generic.u_impl_generic.u_sync_1
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_upload.u_sys_cmdfifo_set.u_count_sync.gen_generic.u_impl_generic.u_sync_2
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_1
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_upload.u_payloadptr_clr_psync.prim_flop_2sync.gen_generic.u_impl_generic.u_sync_2
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_1
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_upload.u_cmdfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_2
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_1
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| gen_generic.u_impl_generic |
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| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_upload.u_cmdfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_2
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| gen_generic.u_impl_generic |
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| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_1
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_upload.u_addrfifo.u_sync_wptr_gray.gen_generic.u_impl_generic.u_sync_2
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_1
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_upload.u_addrfifo.u_sync_rptr_gray.gen_generic.u_impl_generic.u_sync_2
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spid_addr_4b.u_sys2spi_sync.u_prim_sync_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.gen_generic.u_impl_generic.u_sync_1
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spid_addr_4b.u_spi2sys_sync.gen_generic.u_impl_generic.u_sync_2
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_passthrough.u_read_half_cycle
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 90.74 | 94.50 | 91.49 | 75.00 | 92.71 | 100.00 | u_passthrough |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_passthrough.u_read_pipe_stg1
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 90.74 | 94.50 | 91.49 | 75.00 | 92.71 | 100.00 | u_passthrough |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_passthrough.u_read_pipe_stg2
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 90.74 | 94.50 | 91.49 | 75.00 | 92.71 | 100.00 | u_passthrough |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_passthrough.u_read_pipe_oe_stg1
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 90.74 | 94.50 | 91.49 | 75.00 | 92.71 | 100.00 | u_passthrough |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_passthrough.u_read_pipe_oe_stg2
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| 90.74 | 94.50 | 91.49 | 75.00 | 92.71 | 100.00 | u_passthrough |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_1
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spi_tpm.u_csb_sync_rst.g_sync.u_sync.gen_generic.u_impl_generic.u_sync_2
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spi_tpm.u_wrfifo_busy_sync.gen_generic.u_impl_generic.u_sync_1
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spi_tpm.u_wrfifo_busy_sync.gen_generic.u_impl_generic.u_sync_2
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_1
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_sync_2
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_1
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spi_tpm.u_wrfifo_release_reqack.gen_nrz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_sync_2
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spi_tpm.u_rdfifo_ready.gen_generic.u_impl_generic.u_sync_1
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spi_tpm.u_rdfifo_ready.gen_generic.u_impl_generic.u_sync_2
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.gen_generic.u_impl_generic.u_sync_1
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_wptr.gen_generic.u_impl_generic.u_sync_2
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.gen_generic.u_impl_generic.u_sync_1
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |
Module Instance : tb.dut.u_spi_tpm.u_cmdaddr_buffer.sync_rptr.gen_generic.u_impl_generic.u_sync_2
Instance :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
Instance's subtree :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| 100.00 | 100.00 | 100.00 |
Parent :
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
| gen_generic.u_impl_generic |
Subtrees :
| NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
| gen_generic.u_impl_generic | 100.00 | 100.00 | 100.00 |