Module Definition
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Module : prim_generic_ram_1r1w
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/spi_device_1r1w-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_ram_1r1w_0/rtl/prim_generic_ram_1r1w.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00
tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_mem


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_generic_ram_1r1w
Line No.TotalCoveredPercent
TOTAL1111100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
ALWAYS6644100.00
ALWAYS7722100.00


44                        logic unused_cfg;
45         1/1            assign unused_cfg = ^cfg_i;
           Tests:       T2 
46                      
47                        // Width of internal write mask. Note *_wmask_i input into the module is always assumed
48                        // to be the full bit mask.
49                        localparam int MaskWidth = Width / DataBitsPerMask;
50                      
51                        logic [Width-1:0]     mem [Depth];
52                        logic [MaskWidth-1:0] a_wmask;
53                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
54         4/4              assign a_wmask[k] = &a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
55                      
56                          // Ensure that all mask bits within a group have the same value for a write
57                          `ASSERT(MaskCheckPortA_A, a_req_i |->
58                              a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
59                              clk_a_i, '0)
60                        end
61                      
62                        // Xilinx FPGA specific Two-port RAM coding style
63                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
64                        // thrown due to 'mem' being driven by two always processes below
65                        always @(posedge clk_a_i) begin
66         1/1              if (a_req_i) begin
           Tests:       T1 T2 T3 
67         1/1                for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T1 T7 T10 
68         1/1                  if (a_wmask[i]) begin
           Tests:       T1 T7 T10 
69         1/1                    mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T1 T7 T10 
70                                  a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                              end
                        MISSING_ELSE
72                            end
73                          end
                        MISSING_ELSE
74                        end
75                      
76                        always @(posedge clk_b_i) begin
77         1/1              if (b_req_i) begin
           Tests:       T1 T2 T3 
78         1/1                b_rdata_o <= mem[b_addr_i];
           Tests:       T1 T10 T15 
79                          end
                        MISSING_ELSE
Branch Coverage for Module : prim_generic_ram_1r1w
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 66 2 2 100.00
IF 77 2 2 100.00 



66             if (a_req_i) begin
               -1-  
67               for (int i=0; i < MaskWidth; i = i + 1) begin
                 ==>
68                 if (a_wmask[i]) begin
69                   mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
70                     a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                 end
72               end
73             end
               MISSING_ELSE
               ==>

Branches:
-1-StatusTests
1 Covered T1,T7,T10
0 Covered T1,T2,T3 



77             if (b_req_i) begin
               -1-  
78               b_rdata_o <= mem[b_addr_i];
                 ==>
79             end
               MISSING_ELSE
               ==>

Branches:
-1-StatusTests
1 Covered T1,T10,T15
0 Covered T1,T2,T3

Assert Coverage for Module : prim_generic_ram_1r1w
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
gen_wmask[0].MaskCheckPortA_A 640744831 3563060 0 0
gen_wmask[1].MaskCheckPortA_A 640744831 3563060 0 0
gen_wmask[2].MaskCheckPortA_A 640744831 3563060 0 0
gen_wmask[3].MaskCheckPortA_A 640744831 3563060 0 0


gen_wmask[0].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 640744831 3563060 0 0
T1 279717 2811 0 0
T2 872 0 0 0
T3 1244 0 0 0
T4 1146 0 0 0
T5 4521 0 0 0
T6 935 0 0 0
T7 3029 832 0 0
T8 1074 0 0 0
T9 922 0 0 0
T10 588309 5118 0 0
T11 432 0 0 0
T12 31436 0 0 0
T14 779 832 0 0
T15 734 832 0 0
T16 14034 832 0 0
T18 512 832 0 0
T19 9285 832 0 0
T22 0 4 0 0
T25 0 3628 0 0
T27 0 69 0 0
T28 0 65 0 0
T30 0 156 0 0
T35 0 1751 0 0
T41 0 832 0 0
T49 0 110 0 0
T52 0 6 0 0

gen_wmask[1].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 640744831 3563060 0 0
T1 279717 2811 0 0
T2 872 0 0 0
T3 1244 0 0 0
T4 1146 0 0 0
T5 4521 0 0 0
T6 935 0 0 0
T7 3029 832 0 0
T8 1074 0 0 0
T9 922 0 0 0
T10 588309 5118 0 0
T11 432 0 0 0
T12 31436 0 0 0
T14 779 832 0 0
T15 734 832 0 0
T16 14034 832 0 0
T18 512 832 0 0
T19 9285 832 0 0
T22 0 4 0 0
T25 0 3628 0 0
T27 0 69 0 0
T28 0 65 0 0
T30 0 156 0 0
T35 0 1751 0 0
T41 0 832 0 0
T49 0 110 0 0
T52 0 6 0 0

gen_wmask[2].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 640744831 3563060 0 0
T1 279717 2811 0 0
T2 872 0 0 0
T3 1244 0 0 0
T4 1146 0 0 0
T5 4521 0 0 0
T6 935 0 0 0
T7 3029 832 0 0
T8 1074 0 0 0
T9 922 0 0 0
T10 588309 5118 0 0
T11 432 0 0 0
T12 31436 0 0 0
T14 779 832 0 0
T15 734 832 0 0
T16 14034 832 0 0
T18 512 832 0 0
T19 9285 832 0 0
T22 0 4 0 0
T25 0 3628 0 0
T27 0 69 0 0
T28 0 65 0 0
T30 0 156 0 0
T35 0 1751 0 0
T41 0 832 0 0
T49 0 110 0 0
T52 0 6 0 0

gen_wmask[3].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 640744831 3563060 0 0
T1 279717 2811 0 0
T2 872 0 0 0
T3 1244 0 0 0
T4 1146 0 0 0
T5 4521 0 0 0
T6 935 0 0 0
T7 3029 832 0 0
T8 1074 0 0 0
T9 922 0 0 0
T10 588309 5118 0 0
T11 432 0 0 0
T12 31436 0 0 0
T14 779 832 0 0
T15 734 832 0 0
T16 14034 832 0 0
T18 512 832 0 0
T19 9285 832 0 0
T22 0 4 0 0
T25 0 3628 0 0
T27 0 69 0 0
T28 0 65 0 0
T30 0 156 0 0
T35 0 1751 0 0
T41 0 832 0 0
T49 0 110 0 0
T52 0 6 0 0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL1111100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
ALWAYS6644100.00
ALWAYS7722100.00


44                        logic unused_cfg;
45         1/1            assign unused_cfg = ^cfg_i;
           Tests:       T2 
46                      
47                        // Width of internal write mask. Note *_wmask_i input into the module is always assumed
48                        // to be the full bit mask.
49                        localparam int MaskWidth = Width / DataBitsPerMask;
50                      
51                        logic [Width-1:0]     mem [Depth];
52                        logic [MaskWidth-1:0] a_wmask;
53                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
54         4/4              assign a_wmask[k] = &a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
55                      
56                          // Ensure that all mask bits within a group have the same value for a write
57                          `ASSERT(MaskCheckPortA_A, a_req_i |->
58                              a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
59                              clk_a_i, '0)
60                        end
61                      
62                        // Xilinx FPGA specific Two-port RAM coding style
63                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
64                        // thrown due to 'mem' being driven by two always processes below
65                        always @(posedge clk_a_i) begin
66         1/1              if (a_req_i) begin
           Tests:       T1 T2 T3 
67         1/1                for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T1 T7 T10 
68         1/1                  if (a_wmask[i]) begin
           Tests:       T1 T7 T10 
69         1/1                    mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T1 T7 T10 
70                                  a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                              end
                   ==>  MISSING_ELSE
72                            end
73                          end
                        MISSING_ELSE
74                        end
75                      
76                        always @(posedge clk_b_i) begin
77         1/1              if (b_req_i) begin
           Tests:       T1 T5 T10 
78         1/1                b_rdata_o <= mem[b_addr_i];
           Tests:       T1 T10 T15 
79                          end
                        MISSING_ELSE
Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 66 2 2 100.00
IF 77 2 2 100.00 



66             if (a_req_i) begin
               -1-  
67               for (int i=0; i < MaskWidth; i = i + 1) begin
                 ==>
68                 if (a_wmask[i]) begin
69                   mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
70                     a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                 end
72               end
73             end
               MISSING_ELSE
               ==>

Branches:
-1-StatusTests
1 Covered T1,T7,T10
0 Covered T1,T2,T3 



77             if (b_req_i) begin
               -1-  
78               b_rdata_o <= mem[b_addr_i];
                 ==>
79             end
               MISSING_ELSE
               ==>

Branches:
-1-StatusTests
1 Covered T1,T10,T15
0 Covered T1,T5,T10

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_sys2spi_mem.u_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
gen_wmask[0].MaskCheckPortA_A 485027186 2136017 0 0
gen_wmask[1].MaskCheckPortA_A 485027186 2136017 0 0
gen_wmask[2].MaskCheckPortA_A 485027186 2136017 0 0
gen_wmask[3].MaskCheckPortA_A 485027186 2136017 0 0


gen_wmask[0].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 485027186 2136017 0 0
T1 62559 732 0 0
T2 872 0 0 0
T3 1244 0 0 0
T4 1146 0 0 0
T5 3363 0 0 0
T6 935 0 0 0
T7 3029 832 0 0
T8 1074 0 0 0
T9 922 0 0 0
T10 166106 1785 0 0
T14 0 832 0 0
T15 0 832 0 0
T16 0 832 0 0
T18 0 832 0 0
T19 0 832 0 0
T27 0 33 0 0
T41 0 832 0 0

gen_wmask[1].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 485027186 2136017 0 0
T1 62559 732 0 0
T2 872 0 0 0
T3 1244 0 0 0
T4 1146 0 0 0
T5 3363 0 0 0
T6 935 0 0 0
T7 3029 832 0 0
T8 1074 0 0 0
T9 922 0 0 0
T10 166106 1785 0 0
T14 0 832 0 0
T15 0 832 0 0
T16 0 832 0 0
T18 0 832 0 0
T19 0 832 0 0
T27 0 33 0 0
T41 0 832 0 0

gen_wmask[2].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 485027186 2136017 0 0
T1 62559 732 0 0
T2 872 0 0 0
T3 1244 0 0 0
T4 1146 0 0 0
T5 3363 0 0 0
T6 935 0 0 0
T7 3029 832 0 0
T8 1074 0 0 0
T9 922 0 0 0
T10 166106 1785 0 0
T14 0 832 0 0
T15 0 832 0 0
T16 0 832 0 0
T18 0 832 0 0
T19 0 832 0 0
T27 0 33 0 0
T41 0 832 0 0

gen_wmask[3].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 485027186 2136017 0 0
T1 62559 732 0 0
T2 872 0 0 0
T3 1244 0 0 0
T4 1146 0 0 0
T5 3363 0 0 0
T6 935 0 0 0
T7 3029 832 0 0
T8 1074 0 0 0
T9 922 0 0 0
T10 166106 1785 0 0
T14 0 832 0 0
T15 0 832 0 0
T16 0 832 0 0
T18 0 832 0 0
T19 0 832 0 0
T27 0 33 0 0
T41 0 832 0 0

Line Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
TOTAL1111100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
CONT_ASSIGN5411100.00
ALWAYS6644100.00
ALWAYS7722100.00


44                        logic unused_cfg;
45         1/1            assign unused_cfg = ^cfg_i;
           Tests:       T2 
46                      
47                        // Width of internal write mask. Note *_wmask_i input into the module is always assumed
48                        // to be the full bit mask.
49                        localparam int MaskWidth = Width / DataBitsPerMask;
50                      
51                        logic [Width-1:0]     mem [Depth];
52                        logic [MaskWidth-1:0] a_wmask;
53                        for (genvar k = 0; k < MaskWidth; k++) begin : gen_wmask
54         4/4              assign a_wmask[k] = &a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
55                      
56                          // Ensure that all mask bits within a group have the same value for a write
57                          `ASSERT(MaskCheckPortA_A, a_req_i |->
58                              a_wmask_i[k*DataBitsPerMask +: DataBitsPerMask] inside {{DataBitsPerMask{1'b1}}, '0},
59                              clk_a_i, '0)
60                        end
61                      
62                        // Xilinx FPGA specific Two-port RAM coding style
63                        // using always instead of always_ff to avoid 'ICPD  - illegal combination of drivers' error
64                        // thrown due to 'mem' being driven by two always processes below
65                        always @(posedge clk_a_i) begin
66         1/1              if (a_req_i) begin
           Tests:       T1 T5 T10 
67         1/1                for (int i=0; i < MaskWidth; i = i + 1) begin
           Tests:       T1 T10 T27 
68         1/1                  if (a_wmask[i]) begin
           Tests:       T1 T10 T27 
69         1/1                    mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
           Tests:       T1 T10 T27 
70                                  a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                              end
                        MISSING_ELSE
72                            end
73                          end
                        MISSING_ELSE
74                        end
75                      
76                        always @(posedge clk_b_i) begin
77         1/1              if (b_req_i) begin
           Tests:       T1 T2 T3 
78         1/1                b_rdata_o <= mem[b_addr_i];
           Tests:       T1 T10 T27 
79                          end
                        MISSING_ELSE
Branch Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic
Line No.TotalCoveredPercent
Branches 4 4 100.00
IF 66 2 2 100.00
IF 77 2 2 100.00 



66             if (a_req_i) begin
               -1-  
67               for (int i=0; i < MaskWidth; i = i + 1) begin
                 ==>
68                 if (a_wmask[i]) begin
69                   mem[a_addr_i][i*DataBitsPerMask +: DataBitsPerMask] <=
70                     a_wdata_i[i*DataBitsPerMask +: DataBitsPerMask];
71                 end
72               end
73             end
               MISSING_ELSE
               ==>

Branches:
-1-StatusTests
1 Covered T1,T10,T27
0 Covered T1,T5,T10 



77             if (b_req_i) begin
               -1-  
78               b_rdata_o <= mem[b_addr_i];
                 ==>
79             end
               MISSING_ELSE
               ==>

Branches:
-1-StatusTests
1 Covered T1,T10,T27
0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_spid_dpram.gen_ram1r1w.u_spi2sys_mem.u_mem.gen_generic.u_impl_generic
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
gen_wmask[0].MaskCheckPortA_A 155717645 1427043 0 0
gen_wmask[1].MaskCheckPortA_A 155717645 1427043 0 0
gen_wmask[2].MaskCheckPortA_A 155717645 1427043 0 0
gen_wmask[3].MaskCheckPortA_A 155717645 1427043 0 0


gen_wmask[0].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155717645 1427043 0 0
T1 217158 2079 0 0
T5 1158 0 0 0
T10 422203 3333 0 0
T11 432 0 0 0
T12 31436 0 0 0
T14 779 0 0 0
T15 734 0 0 0
T16 14034 0 0 0
T18 512 0 0 0
T19 9285 0 0 0
T22 0 4 0 0
T25 0 3628 0 0
T27 0 36 0 0
T28 0 65 0 0
T30 0 156 0 0
T35 0 1751 0 0
T49 0 110 0 0
T52 0 6 0 0

gen_wmask[1].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155717645 1427043 0 0
T1 217158 2079 0 0
T5 1158 0 0 0
T10 422203 3333 0 0
T11 432 0 0 0
T12 31436 0 0 0
T14 779 0 0 0
T15 734 0 0 0
T16 14034 0 0 0
T18 512 0 0 0
T19 9285 0 0 0
T22 0 4 0 0
T25 0 3628 0 0
T27 0 36 0 0
T28 0 65 0 0
T30 0 156 0 0
T35 0 1751 0 0
T49 0 110 0 0
T52 0 6 0 0

gen_wmask[2].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155717645 1427043 0 0
T1 217158 2079 0 0
T5 1158 0 0 0
T10 422203 3333 0 0
T11 432 0 0 0
T12 31436 0 0 0
T14 779 0 0 0
T15 734 0 0 0
T16 14034 0 0 0
T18 512 0 0 0
T19 9285 0 0 0
T22 0 4 0 0
T25 0 3628 0 0
T27 0 36 0 0
T28 0 65 0 0
T30 0 156 0 0
T35 0 1751 0 0
T49 0 110 0 0
T52 0 6 0 0

gen_wmask[3].MaskCheckPortA_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 155717645 1427043 0 0
T1 217158 2079 0 0
T5 1158 0 0 0
T10 422203 3333 0 0
T11 432 0 0 0
T12 31436 0 0 0
T14 779 0 0 0
T15 734 0 0 0
T16 14034 0 0 0
T18 512 0 0 0
T19 9285 0 0 0
T22 0 4 0 0
T25 0 3628 0 0
T27 0 36 0 0
T28 0 65 0 0
T30 0 156 0 0
T35 0 1751 0 0
T49 0 110 0 0
T52 0 6 0 0