Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	487100895	2980511	0	0
DepthKnown_A	487100895	486965968	0	0
RvalidKnown_A	487100895	486965968	0	0
WreadyKnown_A	487100895	486965968	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	2980511	0	0
T7	3029	832	0	0
T8	1074	0	0	0
T9	922	0	0	0
T10	166106	0	0	0
T11	4482	0	0	0
T12	33130	0	0	0
T13	8472	0	0	0
T14	7214	1670	0	0
T15	6649	1664	0	0
T16	10668	832	0	0
T18	0	832	0	0
T19	0	1663	0	0
T21	0	832	0	0
T22	0	832	0	0
T23	0	1663	0	0
T41	0	1665	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	487100895	3251292	0	0
DepthKnown_A	487100895	486965968	0	0
RvalidKnown_A	487100895	486965968	0	0
WreadyKnown_A	487100895	486965968	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	3251292	0	0
T7	3029	832	0	0
T8	1074	0	0	0
T9	922	0	0	0
T10	166106	0	0	0
T11	4482	0	0	0
T12	33130	0	0	0
T13	8472	0	0	0
T14	7214	839	0	0
T15	6649	834	0	0
T16	10668	832	0	0
T18	0	832	0	0
T19	0	832	0	0
T21	0	832	0	0
T22	0	832	0	0
T23	0	832	0	0
T41	0	834	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	487100895	200889	0	0
DepthKnown_A	487100895	486965968	0	0
RvalidKnown_A	487100895	486965968	0	0
WreadyKnown_A	487100895	486965968	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	200889	0	0
T1	62559	537	0	0
T2	872	0	0	0
T3	1244	0	0	0
T4	1146	0	0	0
T5	3363	0	0	0
T6	935	0	0	0
T7	3029	0	0	0
T8	1074	0	0	0
T9	922	0	0	0
T10	166106	865	0	0
T25	0	258	0	0
T27	0	10	0	0
T28	0	17	0	0
T30	0	41	0	0
T35	0	454	0	0
T49	0	28	0	0
T50	0	1	0	0
T51	0	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	487100895	476139	0	0
DepthKnown_A	487100895	486965968	0	0
RvalidKnown_A	487100895	486965968	0	0
WreadyKnown_A	487100895	486965968	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	476139	0	0
T1	62559	537	0	0
T2	872	0	0	0
T3	1244	0	0	0
T4	1146	0	0	0
T5	3363	0	0	0
T6	935	0	0	0
T7	3029	0	0	0
T8	1074	0	0	0
T9	922	0	0	0
T10	166106	3870	0	0
T25	0	258	0	0
T27	0	10	0	0
T28	0	17	0	0
T30	0	41	0	0
T35	0	454	0	0
T49	0	28	0	0
T50	0	1	0	0
T51	0	54	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	487100895	6254429	0	0
DepthKnown_A	487100895	486965968	0	0
RvalidKnown_A	487100895	486965968	0	0
WreadyKnown_A	487100895	486965968	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	6254429	0	0
T1	62559	2829	0	0
T2	872	1	0	0
T3	1244	79	0	0
T4	1146	13	0	0
T5	3363	44	0	0
T6	935	3	0	0
T7	3029	44	0	0
T8	1074	51	0	0
T9	922	7	0	0
T10	166106	6730	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	487100895	12772942	0	0
DepthKnown_A	487100895	486965968	0	0
RvalidKnown_A	487100895	486965968	0	0
WreadyKnown_A	487100895	486965968	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	12772942	0	0
T1	62559	2807	0	0
T2	872	1	0	0
T3	1244	79	0	0
T4	1146	12	0	0
T5	3363	44	0	0
T6	935	18	0	0
T7	3029	44	0	0
T8	1074	51	0	0
T9	922	21	0	0
T10	166106	26808	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	487100895	486965968	0	0
T1	62559	62473	0	0
T2	872	789	0	0
T3	1244	1165	0	0
T4	1146	1069	0	0
T5	3363	3278	0	0
T6	935	876	0	0
T7	3029	2950	0	0
T8	1074	993	0	0
T9	922	850	0	0
T10	166106	166033	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0