Unified Coverage Report :: Module Instance :: tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[2].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455154969	3037858	0	0
DataKnown_AKnownEnable	455154969	455022920	0	0
DepthKnown_A	455154969	455022920	0	0
RvalidKnown_A	455154969	455022920	0	0
WreadyKnown_A	455154969	455022920	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3037858	0	0
T4	7275	832	0	0
T5	46509	0	0	0
T6	10474	0	0	0
T7	22916	832	0	0
T8	109355	1663	0	0
T9	24581	1664	0	0
T10	10889	832	0	0
T11	407531	1663	0	0
T12	253866	0	0	0
T13	707836	1663	0	0
T14	0	832	0	0
T17	0	832	0	0
T18	0	832	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455154969	3305392	0	0
DataKnown_AKnownEnable	455154969	455022920	0	0
DepthKnown_A	455154969	455022920	0	0
RvalidKnown_A	455154969	455022920	0	0
WreadyKnown_A	455154969	455022920	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	3305392	0	0
T4	7275	832	0	0
T5	46509	0	0	0
T6	10474	0	0	0
T7	22916	3776	0	0
T8	109355	832	0	0
T9	24581	833	0	0
T10	10889	3770	0	0
T11	407531	832	0	0
T12	253866	0	0	0
T13	707836	832	0	0
T14	0	3778	0	0
T17	0	832	0	0
T18	0	3566	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455154969	202461	0	0
DataKnown_AKnownEnable	455154969	455022920	0	0
DepthKnown_A	455154969	455022920	0	0
RvalidKnown_A	455154969	455022920	0	0
WreadyKnown_A	455154969	455022920	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	202461	0	0
T6	10474	25	0	0
T7	22916	0	0	0
T8	109355	0	0	0
T9	24581	0	0	0
T10	10889	0	0	0
T11	407531	0	0	0
T12	253866	1211	0	0
T13	707836	0	0	0
T14	184541	0	0	0
T15	7886	0	0	0
T21	0	748	0	0
T26	0	321	0	0
T28	0	28	0	0
T36	0	128	0	0
T38	0	128	0	0
T42	0	405	0	0
T43	0	98	0	0
T44	0	63	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455154969	471915	0	0
DataKnown_AKnownEnable	455154969	455022920	0	0
DepthKnown_A	455154969	455022920	0	0
RvalidKnown_A	455154969	455022920	0	0
WreadyKnown_A	455154969	455022920	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	471915	0	0
T6	10474	25	0	0
T7	22916	0	0	0
T8	109355	0	0	0
T9	24581	0	0	0
T10	10889	0	0	0
T11	407531	0	0	0
T12	253866	5551	0	0
T13	707836	0	0	0
T14	184541	0	0	0
T15	7886	0	0	0
T21	0	748	0	0
T26	0	321	0	0
T28	0	28	0	0
T36	0	626	0	0
T38	0	128	0	0
T42	0	1731	0	0
T43	0	98	0	0
T44	0	269	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455154969	6339261	0	0
DataKnown_AKnownEnable	455154969	455022920	0	0
DepthKnown_A	455154969	455022920	0	0
RvalidKnown_A	455154969	455022920	0	0
WreadyKnown_A	455154969	455022920	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	6339261	0	0
T1	1098	45	0	0
T2	718	1	0	0
T3	2934	26	0	0
T4	7275	46	0	0
T5	46509	250	0	0
T6	10474	4019	0	0
T7	22916	465	0	0
T8	109355	63	0	0
T9	24581	552	0	0
T10	10889	79	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0

Line Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.u_reg.u_socket.gen_dfifo[2].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	455154969	13972854	0	0
DataKnown_AKnownEnable	455154969	455022920	0	0
DepthKnown_A	455154969	455022920	0	0
RvalidKnown_A	455154969	455022920	0	0
WreadyKnown_A	455154969	455022920	0	0
gen_passthru_fifo.paramCheckPass	1131	1131	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	13972854	0	0
T1	1098	45	0	0
T2	718	9	0	0
T3	2934	117	0	0
T4	7275	46	0	0
T5	46509	250	0	0
T6	10474	4019	0	0
T7	22916	2076	0	0
T8	109355	63	0	0
T9	24581	2357	0	0
T10	10889	329	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	455154969	455022920	0	0
T1	1098	1022	0	0
T2	718	619	0	0
T3	2934	2843	0	0
T4	7275	7211	0	0
T5	46509	46422	0	0
T6	10474	10394	0	0
T7	22916	22862	0	0
T8	109355	109264	0	0
T9	24581	24485	0	0
T10	10889	10792	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1131	1131	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T8	1	1	0	0
T9	1	1	0	0
T10	1	1	0	0