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Module Instance : tb.dut.u_reg.u_intr_state_upload_cmdfifo_not_empty.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_state_upload_cmdfifo_not_empty


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_state_upload_payload_not_empty.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_state_upload_payload_not_empty


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_state_upload_payload_overflow.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_state_upload_payload_overflow


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_state_readbuf_watermark.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_state_readbuf_watermark


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_state_readbuf_flip.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_state_readbuf_flip


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_state_tpm_header_not_empty.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
50.00 50.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.24 85.71 100.00 100.00 u_intr_state_tpm_header_not_empty


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_state_tpm_rdfifo_cmd_end.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_state_tpm_rdfifo_cmd_end


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_state_tpm_rdfifo_drop.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_state_tpm_rdfifo_drop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable_upload_cmdfifo_not_empty.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable_upload_cmdfifo_not_empty


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable_upload_payload_not_empty.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable_upload_payload_not_empty


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable_upload_payload_overflow.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable_upload_payload_overflow


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable_readbuf_watermark.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable_readbuf_watermark


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable_readbuf_flip.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable_readbuf_flip


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable_tpm_header_not_empty.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable_tpm_header_not_empty


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable_tpm_rdfifo_cmd_end.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable_tpm_rdfifo_cmd_end


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_intr_enable_tpm_rdfifo_drop.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_intr_enable_tpm_rdfifo_drop


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_control_flash_status_fifo_clr.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.24 85.71 100.00 100.00 u_control_flash_status_fifo_clr


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_intr_state_upload_cmdfifo_not_empty.wr_en_data_arb
tb.dut.u_reg.u_intr_state_upload_payload_not_empty.wr_en_data_arb
tb.dut.u_reg.u_intr_state_upload_payload_overflow.wr_en_data_arb
tb.dut.u_reg.u_intr_state_readbuf_watermark.wr_en_data_arb
tb.dut.u_reg.u_intr_state_readbuf_flip.wr_en_data_arb
tb.dut.u_reg.u_intr_state_tpm_header_not_empty.wr_en_data_arb
tb.dut.u_reg.u_intr_state_tpm_rdfifo_cmd_end.wr_en_data_arb
tb.dut.u_reg.u_intr_state_tpm_rdfifo_drop.wr_en_data_arb
tb.dut.u_reg.u_intr_enable_upload_cmdfifo_not_empty.wr_en_data_arb
tb.dut.u_reg.u_intr_enable_upload_payload_not_empty.wr_en_data_arb
tb.dut.u_reg.u_intr_enable_upload_payload_overflow.wr_en_data_arb
tb.dut.u_reg.u_intr_enable_readbuf_watermark.wr_en_data_arb
tb.dut.u_reg.u_intr_enable_readbuf_flip.wr_en_data_arb
tb.dut.u_reg.u_intr_enable_tpm_header_not_empty.wr_en_data_arb
tb.dut.u_reg.u_intr_enable_tpm_rdfifo_cmd_end.wr_en_data_arb
tb.dut.u_reg.u_intr_enable_tpm_rdfifo_drop.wr_en_data_arb
tb.dut.u_reg.u_control_flash_status_fifo_clr.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_upload_cmdfifo_not_empty.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00

87 // If both try to set/clr at the same bit pos, SW wins. 88 1/1 assign wr_en = we | de; Tests: T1 T2 T3  89 if (Mubi) begin : gen_mubi 90 if (DW == 4) begin : gen_mubi4 91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 92 (we ? prim_mubi_pkg::mubi4_t'(~wd) : 93 prim_mubi_pkg::MuBi4True)); 94 end else if (DW == 8) begin : gen_mubi8 95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 96 (we ? prim_mubi_pkg::mubi8_t'(~wd) : 97 prim_mubi_pkg::MuBi8True)); 98 end else if (DW == 12) begin : gen_mubi12 99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 100 (we ? prim_mubi_pkg::mubi12_t'(~wd) : 101 prim_mubi_pkg::MuBi12True)); 102 end else if (DW == 16) begin : gen_mubi16 103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 104 (we ? prim_mubi_pkg::mubi16_t'(~wd) : 105 prim_mubi_pkg::MuBi16True)); 106 end else begin : gen_invalid_mubi 107 $error("%m: Invalid width for MuBi"); 108 end 109 end else begin : gen_non_mubi 110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_upload_cmdfifo_not_empty.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT13,T36,T38
10CoveredT6,T12,T13

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT13,T36,T38
11CoveredT13,T36,T38

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT13,T36,T38

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T12,T13
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_upload_payload_not_empty.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00

87 // If both try to set/clr at the same bit pos, SW wins. 88 1/1 assign wr_en = we | de; Tests: T1 T2 T3  89 if (Mubi) begin : gen_mubi 90 if (DW == 4) begin : gen_mubi4 91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 92 (we ? prim_mubi_pkg::mubi4_t'(~wd) : 93 prim_mubi_pkg::MuBi4True)); 94 end else if (DW == 8) begin : gen_mubi8 95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 96 (we ? prim_mubi_pkg::mubi8_t'(~wd) : 97 prim_mubi_pkg::MuBi8True)); 98 end else if (DW == 12) begin : gen_mubi12 99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 100 (we ? prim_mubi_pkg::mubi12_t'(~wd) : 101 prim_mubi_pkg::MuBi12True)); 102 end else if (DW == 16) begin : gen_mubi16 103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 104 (we ? prim_mubi_pkg::mubi16_t'(~wd) : 105 prim_mubi_pkg::MuBi16True)); 106 end else begin : gen_invalid_mubi 107 $error("%m: Invalid width for MuBi"); 108 end 109 end else begin : gen_non_mubi 110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_upload_payload_not_empty.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT36,T38,T21
10CoveredT6,T12,T13

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT36,T38,T21
11CoveredT36,T38,T21

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT36,T38,T21

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T12,T13
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_upload_payload_overflow.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00

87 // If both try to set/clr at the same bit pos, SW wins. 88 1/1 assign wr_en = we | de; Tests: T1 T2 T3  89 if (Mubi) begin : gen_mubi 90 if (DW == 4) begin : gen_mubi4 91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 92 (we ? prim_mubi_pkg::mubi4_t'(~wd) : 93 prim_mubi_pkg::MuBi4True)); 94 end else if (DW == 8) begin : gen_mubi8 95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 96 (we ? prim_mubi_pkg::mubi8_t'(~wd) : 97 prim_mubi_pkg::MuBi8True)); 98 end else if (DW == 12) begin : gen_mubi12 99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 100 (we ? prim_mubi_pkg::mubi12_t'(~wd) : 101 prim_mubi_pkg::MuBi12True)); 102 end else if (DW == 16) begin : gen_mubi16 103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 104 (we ? prim_mubi_pkg::mubi16_t'(~wd) : 105 prim_mubi_pkg::MuBi16True)); 106 end else begin : gen_invalid_mubi 107 $error("%m: Invalid width for MuBi"); 108 end 109 end else begin : gen_non_mubi 110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_upload_payload_overflow.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT38,T21,T43
10CoveredT6,T12,T13

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT38,T21,T43
11CoveredT38,T21,T43

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT38,T21,T43

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T12,T13
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_readbuf_watermark.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00

87 // If both try to set/clr at the same bit pos, SW wins. 88 1/1 assign wr_en = we | de; Tests: T1 T2 T3  89 if (Mubi) begin : gen_mubi 90 if (DW == 4) begin : gen_mubi4 91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 92 (we ? prim_mubi_pkg::mubi4_t'(~wd) : 93 prim_mubi_pkg::MuBi4True)); 94 end else if (DW == 8) begin : gen_mubi8 95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 96 (we ? prim_mubi_pkg::mubi8_t'(~wd) : 97 prim_mubi_pkg::MuBi8True)); 98 end else if (DW == 12) begin : gen_mubi12 99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 100 (we ? prim_mubi_pkg::mubi12_t'(~wd) : 101 prim_mubi_pkg::MuBi12True)); 102 end else if (DW == 16) begin : gen_mubi16 103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 104 (we ? prim_mubi_pkg::mubi16_t'(~wd) : 105 prim_mubi_pkg::MuBi16True)); 106 end else begin : gen_invalid_mubi 107 $error("%m: Invalid width for MuBi"); 108 end 109 end else begin : gen_non_mubi 110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_readbuf_watermark.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T37,T21
10CoveredT6,T12,T13

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T37,T21
11CoveredT14,T37,T21

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T37,T21

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T12,T13
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_readbuf_flip.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00

87 // If both try to set/clr at the same bit pos, SW wins. 88 1/1 assign wr_en = we | de; Tests: T1 T2 T3  89 if (Mubi) begin : gen_mubi 90 if (DW == 4) begin : gen_mubi4 91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 92 (we ? prim_mubi_pkg::mubi4_t'(~wd) : 93 prim_mubi_pkg::MuBi4True)); 94 end else if (DW == 8) begin : gen_mubi8 95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 96 (we ? prim_mubi_pkg::mubi8_t'(~wd) : 97 prim_mubi_pkg::MuBi8True)); 98 end else if (DW == 12) begin : gen_mubi12 99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 100 (we ? prim_mubi_pkg::mubi12_t'(~wd) : 101 prim_mubi_pkg::MuBi12True)); 102 end else if (DW == 16) begin : gen_mubi16 103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 104 (we ? prim_mubi_pkg::mubi16_t'(~wd) : 105 prim_mubi_pkg::MuBi16True)); 106 end else begin : gen_invalid_mubi 107 $error("%m: Invalid width for MuBi"); 108 end 109 end else begin : gen_non_mubi 110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_readbuf_flip.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T37,T21
10CoveredT6,T12,T13

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT14,T37,T21
11CoveredT14,T37,T21

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT14,T37,T21

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T12,T13
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_tpm_header_not_empty.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL2150.00
CONT_ASSIGN43100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN5100
CONT_ASSIGN5200
CONT_ASSIGN5300

42 end else if (SwAccess == SwAccessRO) begin : gen_ro 43 0/1 ==> assign wr_en = de; 44 1/1 assign wr_data = d; Tests: T1 T2 T3  45 // Unused we, wd, q - Prevent lint errors. 46 logic unused_we; 47 logic [DW-1:0] unused_wd; 48 logic [DW-1:0] unused_q; 49 //VCS coverage off 50 // pragma coverage off 51 unreachable assign unused_we = we; 52 unreachable assign unused_wd = wd; 53 unreachable assign unused_q = q;
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_tpm_rdfifo_cmd_end.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00

87 // If both try to set/clr at the same bit pos, SW wins. 88 1/1 assign wr_en = we | de; Tests: T1 T2 T3  89 if (Mubi) begin : gen_mubi 90 if (DW == 4) begin : gen_mubi4 91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 92 (we ? prim_mubi_pkg::mubi4_t'(~wd) : 93 prim_mubi_pkg::MuBi4True)); 94 end else if (DW == 8) begin : gen_mubi8 95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 96 (we ? prim_mubi_pkg::mubi8_t'(~wd) : 97 prim_mubi_pkg::MuBi8True)); 98 end else if (DW == 12) begin : gen_mubi12 99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 100 (we ? prim_mubi_pkg::mubi12_t'(~wd) : 101 prim_mubi_pkg::MuBi12True)); 102 end else if (DW == 16) begin : gen_mubi16 103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 104 (we ? prim_mubi_pkg::mubi16_t'(~wd) : 105 prim_mubi_pkg::MuBi16True)); 106 end else begin : gen_invalid_mubi 107 $error("%m: Invalid width for MuBi"); 108 end 109 end else begin : gen_non_mubi 110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_tpm_rdfifo_cmd_end.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT6,T12,T26
10CoveredT6,T12,T13

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT6,T12,T26
11CoveredT6,T12,T26

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T12,T26

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T12,T13
Line Coverage for Instance : tb.dut.u_reg.u_intr_state_tpm_rdfifo_drop.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN11011100.00

87 // If both try to set/clr at the same bit pos, SW wins. 88 1/1 assign wr_en = we | de; Tests: T6 T12 T13  89 if (Mubi) begin : gen_mubi 90 if (DW == 4) begin : gen_mubi4 91 assign wr_data = prim_mubi_pkg::mubi4_and_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 92 (we ? prim_mubi_pkg::mubi4_t'(~wd) : 93 prim_mubi_pkg::MuBi4True)); 94 end else if (DW == 8) begin : gen_mubi8 95 assign wr_data = prim_mubi_pkg::mubi8_and_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 96 (we ? prim_mubi_pkg::mubi8_t'(~wd) : 97 prim_mubi_pkg::MuBi8True)); 98 end else if (DW == 12) begin : gen_mubi12 99 assign wr_data = prim_mubi_pkg::mubi12_and_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 100 (we ? prim_mubi_pkg::mubi12_t'(~wd) : 101 prim_mubi_pkg::MuBi12True)); 102 end else if (DW == 16) begin : gen_mubi16 103 assign wr_data = prim_mubi_pkg::mubi16_and_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 104 (we ? prim_mubi_pkg::mubi16_t'(~wd) : 105 prim_mubi_pkg::MuBi16True)); 106 end else begin : gen_invalid_mubi 107 $error("%m: Invalid width for MuBi"); 108 end 109 end else begin : gen_non_mubi 110 1/1 assign wr_data = (de ? d : q) & (we ? ~wd : '1); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_intr_state_tpm_rdfifo_drop.wr_en_data_arb
TotalCoveredPercent
Conditions1010100.00
Logical1010100.00
Non-Logical00
Event00

 LINE       88
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT21,T87,T33
10CoveredT6,T12,T13

 LINE       110
 EXPRESSION ((de ? d : q) & (we ? ((~wd)) : '1))
             ------1-----   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT21,T87,T33
11CoveredT21,T87,T33

 LINE       110
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

 LINE       110
 SUB-EXPRESSION (we ? ((~wd)) : '1)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T12,T13
Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_upload_cmdfifo_not_empty.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T21 T87 T33  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_upload_cmdfifo_not_empty.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT21,T87,T33

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_upload_cmdfifo_not_empty.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T21,T87,T33
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_upload_payload_not_empty.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T21 T87 T33  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_upload_payload_not_empty.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT21,T87,T33

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_upload_payload_not_empty.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T21,T87,T33
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_upload_payload_overflow.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T21 T87 T33  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_upload_payload_overflow.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT21,T87,T33

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_upload_payload_overflow.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T21,T87,T33
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_readbuf_watermark.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T21 T87 T33  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_readbuf_watermark.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT21,T87,T33

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_readbuf_watermark.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T21,T87,T33
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_readbuf_flip.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T21 T87 T33  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_readbuf_flip.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT21,T87,T33

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_readbuf_flip.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T21,T87,T33
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_tpm_header_not_empty.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T21 T87 T33  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_tpm_header_not_empty.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT21,T87,T33

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_tpm_header_not_empty.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T21,T87,T33
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_tpm_rdfifo_cmd_end.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T21 T87 T33  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_tpm_rdfifo_cmd_end.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT21,T87,T33

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_tpm_rdfifo_cmd_end.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T21,T87,T33
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_intr_enable_tpm_rdfifo_drop.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900

32 if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w 33 1/1 assign wr_en = we | de; Tests: T21 T87 T33  34 1/1 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority Tests: T1 T2 T3  35 // Unused q - Prevent lint errors. 36 logic [DW-1:0] unused_q; 37 //VCS coverage off 38 // pragma coverage off 39 unreachable assign unused_q = q;

Cond Coverage for Instance : tb.dut.u_reg.u_intr_enable_tpm_rdfifo_drop.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT21,T87,T33

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT21,T87,T33

Branch Coverage for Instance : tb.dut.u_reg.u_intr_enable_tpm_rdfifo_drop.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00


34 assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T21,T87,T33
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_control_flash_status_fifo_clr.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN6011100.00
CONT_ASSIGN8211100.00

59 // If both try to set/clr at the same bit pos, SW wins. 60 1/1 assign wr_en = we | de; Tests: T4 T7 T8  61 if (Mubi) begin : gen_mubi 62 if (DW == 4) begin : gen_mubi4 63 assign wr_data = prim_mubi_pkg::mubi4_or_hi(prim_mubi_pkg::mubi4_t'(de ? d : q), 64 (we ? prim_mubi_pkg::mubi4_t'(wd) : 65 prim_mubi_pkg::MuBi4False)); 66 end else if (DW == 8) begin : gen_mubi8 67 assign wr_data = prim_mubi_pkg::mubi8_or_hi(prim_mubi_pkg::mubi8_t'(de ? d : q), 68 (we ? prim_mubi_pkg::mubi8_t'(wd) : 69 prim_mubi_pkg::MuBi8False)); 70 end else if (DW == 12) begin : gen_mubi12 71 assign wr_data = prim_mubi_pkg::mubi12_or_hi(prim_mubi_pkg::mubi12_t'(de ? d : q), 72 (we ? prim_mubi_pkg::mubi12_t'(wd) : 73 prim_mubi_pkg::MuBi12False)); 74 end else if (DW == 16) begin : gen_mubi16 75 assign wr_data = prim_mubi_pkg::mubi16_or_hi(prim_mubi_pkg::mubi16_t'(de ? d : q), 76 (we ? prim_mubi_pkg::mubi16_t'(wd) : 77 prim_mubi_pkg::MuBi16False)); 78 end else begin : gen_invalid_mubi 79 $error("%m: Invalid width for MuBi"); 80 end 81 end else begin : gen_non_mubi 82 1/1 assign wr_data = (de ? d : q) | (we ? wd : '0); Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg.u_control_flash_status_fifo_clr.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       60
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTestsExclude Annotation
00Excluded VC_COV_UNR
01CoveredT1,T2,T3
10Excluded VC_COV_UNR

 LINE       82
 EXPRESSION ((de ? d : q) | (we ? wd : '0))
             ------1-----   -------2------
-1--2-StatusTestsExclude Annotation
00CoveredT1,T2,T3
01CoveredT91,T92,T93
10Excluded VC_COV_UNR

 LINE       82
 SUB-EXPRESSION (de ? d : q)
                 -1
-1-StatusTestsExclude Annotation
0Excluded VC_COV_UNR
1CoveredT1,T2,T3

 LINE       82
 SUB-EXPRESSION (we ? wd : '0)
                 -1
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%