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Module Instance : tb.dut.u_reg.u_cmd_info_13_read_pipeline_mode_13.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_13_read_pipeline_mode_13


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_13_upload_13.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_13_upload_13


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_13_busy_13.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_13_busy_13


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_13_valid_13.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_13_valid_13


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_14_opcode_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_14_opcode_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_14_addr_mode_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_14_addr_mode_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_14_addr_swap_en_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_14_addr_swap_en_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_14_mbyte_en_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_14_mbyte_en_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_14_dummy_size_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_14_dummy_size_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_14_dummy_en_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_14_dummy_en_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_14_payload_en_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_14_payload_en_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_14_payload_dir_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_14_payload_dir_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_14_payload_swap_en_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_14_payload_swap_en_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_14_read_pipeline_mode_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_14_read_pipeline_mode_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_14_upload_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_14_upload_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_14_busy_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_14_busy_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_reg.u_cmd_info_14_valid_14.wr_en_data_arb

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 100.00 100.00 u_cmd_info_14_valid_14


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Go back
Module Instances:
tb.dut.u_reg.u_cmd_info_13_read_pipeline_mode_13.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_13_upload_13.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_13_busy_13.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_13_valid_13.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_14_opcode_14.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_14_addr_mode_14.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_14_addr_swap_en_14.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_14_mbyte_en_14.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_14_dummy_size_14.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_14_dummy_en_14.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_14_payload_en_14.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_14_payload_dir_14.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_14_payload_swap_en_14.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_14_read_pipeline_mode_14.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_14_upload_14.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_14_busy_14.wr_en_data_arb
tb.dut.u_reg.u_cmd_info_14_valid_14.wr_en_data_arb
Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_13_read_pipeline_mode_13.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_13_read_pipeline_mode_13.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_13_read_pipeline_mode_13.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_13_upload_13.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_13_upload_13.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_13_upload_13.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_13_busy_13.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_13_busy_13.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_13_busy_13.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_13_valid_13.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_13_valid_13.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_13_valid_13.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_opcode_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_opcode_14.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_opcode_14.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_addr_mode_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_addr_mode_14.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_addr_mode_14.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_addr_swap_en_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_addr_swap_en_14.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_addr_swap_en_14.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_mbyte_en_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_mbyte_en_14.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_mbyte_en_14.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_dummy_size_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_dummy_size_14.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_dummy_size_14.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_dummy_en_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_dummy_en_14.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_dummy_en_14.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_payload_en_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_payload_en_14.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_payload_en_14.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_payload_dir_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_payload_dir_14.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_payload_dir_14.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_payload_swap_en_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_payload_swap_en_14.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_payload_swap_en_14.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_read_pipeline_mode_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_read_pipeline_mode_14.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_read_pipeline_mode_14.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_upload_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_upload_14.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_upload_14.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_busy_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_busy_14.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_busy_14.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_valid_14.wr_en_data_arb
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN3311100.00
CONT_ASSIGN3411100.00
CONT_ASSIGN3900


32                        if (SwAccess inside {SwAccessRW, SwAccessWO}) begin : gen_w
33         1/1              assign wr_en   = we | de;
           Tests:       T4 T7 T8 
34         1/1              assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
           Tests:       T1 T2 T3 
35                          // Unused q - Prevent lint errors.
36                          logic [DW-1:0] unused_q;
37                          //VCS coverage off
38                          // pragma coverage off
39         unreachable      assign unused_q = q;
Cond Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_valid_14.wr_en_data_arb
TotalCoveredPercent
Conditions66100.00
Logical66100.00
Non-Logical00
Event00

 LINE       33
 EXPRESSION (we | de)
             -1   -2
-1--2-StatusTests
00CoveredT1,T2,T3
01Unreachable
10CoveredT4,T7,T8 

 LINE       34
 EXPRESSION ((we == 1'b1) ? wd : d)
             ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8 

 LINE       34
 SUB-EXPRESSION (we == 1'b1)
                ------1-----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T7,T8
Branch Coverage for Instance : tb.dut.u_reg.u_cmd_info_14_valid_14.wr_en_data_arb
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 34 2 2 100.00 



34             assign wr_data = (we == 1'b1) ? wd : d; // SW higher priority
                                             -1-  
                                             ==>  
                                             ==>

Branches:
-1-StatusTests
1 Covered T4,T7,T8
0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%