SPI_DEVICE/2P Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: `70ad420931`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	13.129m	488.337ms	49	50	98.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.430s	162.797us	5	5	100.00
V1	csr_rw	spi_device_csr_rw	2.790s	221.764us	20	20	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	32.590s	7.432ms	5	5	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.190s	792.463us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	4.170s	269.337us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	2.790s	221.764us	20	20	100.00
		spi_device_csr_aliasing	16.190s	792.463us	5	5	100.00
V1	mem_walk	spi_device_mem_walk	0.660s	52.723us	5	5	100.00
V1	mem_partial_access	spi_device_mem_partial_access	2.230s	79.002us	5	5	100.00
V1		TOTAL			114	115	99.13
V2	csb_read	spi_device_csb_read	0.880s	43.191us	50	50	100.00
V2	mem_parity	spi_device_mem_parity	1.140s	25.541us	20	20	100.00
V2	mem_cfg	spi_device_ram_cfg	0.800s	29.714us	20	20	100.00
V2	tpm_read	spi_device_tpm_rw	14.360s	1.704ms	50	50	100.00
V2	tpm_write	spi_device_tpm_rw	14.360s	1.704ms	50	50	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	30.060s	23.745ms	50	50	100.00
		spi_device_tpm_sts_read	1.130s	145.295us	50	50	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	1.326m	50.483ms	50	50	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	40.440s	31.061ms	50	50	100.00
		spi_device_flash_all	6.551m	77.227ms	48	50	96.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	52.840s	67.067ms	50	50	100.00
		spi_device_flash_all	6.551m	77.227ms	48	50	96.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	52.840s	67.067ms	50	50	100.00
		spi_device_flash_all	6.551m	77.227ms	48	50	96.00
V2	cmd_info_slots	spi_device_flash_all	6.551m	77.227ms	48	50	96.00
V2	cmd_read_status	spi_device_intercept	14.880s	21.633ms	50	50	100.00
		spi_device_flash_all	6.551m	77.227ms	48	50	96.00
V2	cmd_read_jedec	spi_device_intercept	14.880s	21.633ms	50	50	100.00
		spi_device_flash_all	6.551m	77.227ms	48	50	96.00
V2	cmd_read_sfdp	spi_device_intercept	14.880s	21.633ms	50	50	100.00
		spi_device_flash_all	6.551m	77.227ms	48	50	96.00
V2	cmd_fast_read	spi_device_intercept	14.880s	21.633ms	50	50	100.00
		spi_device_flash_all	6.551m	77.227ms	48	50	96.00
V2	cmd_read_pipeline	spi_device_intercept	14.880s	21.633ms	50	50	100.00
		spi_device_flash_all	6.551m	77.227ms	48	50	96.00
V2	flash_cmd_upload	spi_device_upload	26.960s	17.774ms	50	50	100.00
V2	mailbox_command	spi_device_mailbox	1.241m	25.810ms	50	50	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	1.241m	25.810ms	50	50	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	1.241m	25.810ms	50	50	100.00
V2	cmd_read_buffer	spi_device_flash_mode	1.182m	22.922ms	49	50	98.00
		spi_device_read_buffer_direct	7.280s	2.115ms	50	50	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	1.241m	25.810ms	50	50	100.00
		spi_device_flash_all	6.551m	77.227ms	48	50	96.00
V2	quad_spi	spi_device_flash_all	6.551m	77.227ms	48	50	96.00
V2	dual_spi	spi_device_flash_all	6.551m	77.227ms	48	50	96.00
V2	4b_3b_feature	spi_device_cfg_cmd	9.830s	9.642ms	50	50	100.00
V2	write_enable_disable	spi_device_cfg_cmd	9.830s	9.642ms	50	50	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	13.129m	488.337ms	49	50	98.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	11.503m	197.565ms	49	50	98.00
V2	stress_all	spi_device_stress_all	11.555m	766.815ms	50	50	100.00
V2	alert_test	spi_device_alert_test	0.800s	35.081us	50	50	100.00
V2	intr_test	spi_device_intr_test	0.800s	42.728us	50	50	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	4.790s	121.194us	20	20	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	4.790s	121.194us	20	20	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.430s	162.797us	5	5	100.00
		spi_device_csr_rw	2.790s	221.764us	20	20	100.00
		spi_device_csr_aliasing	16.190s	792.463us	5	5	100.00
		spi_device_same_csr_outstanding	4.290s	1.982ms	20	20	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.430s	162.797us	5	5	100.00
		spi_device_csr_rw	2.790s	221.764us	20	20	100.00
		spi_device_csr_aliasing	16.190s	792.463us	5	5	100.00
		spi_device_same_csr_outstanding	4.290s	1.982ms	20	20	100.00
V2		TOTAL			976	980	99.59
V2S	tl_intg_err	spi_device_sec_cm	1.210s	111.647us	5	5	100.00
		spi_device_tl_intg_err	24.110s	4.293ms	20	20	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	24.110s	4.293ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	spi_device_stress_all_with_rand_reset			0	0	--
V3		TOTAL			0	0	--
		TOTAL			1115	1120	99.55

Testplan Progress

Items	Total	Written	Passing	Progress
V1	8	8	7	87.50
V2	22	22	19	86.36
V2S	2	2	2	100.00
V3	1	0	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.98	98.36	94.43	98.61	89.36	97.09	95.82	98.22

Failure Buckets

UVM_ERROR (spi_device_scoreboard.sv:478) [scoreboard] Check failed flash_status_q.size <= * (* [*] vs * [*]) has 2 failures:

Test spi_device_flash_all has 2 failures.

20.spi_device_flash_all.59937466624859219681554189948544156590269778168053739381275745941151120554746
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 7028527981 ps: (spi_device_scoreboard.sv:478) [uvm_test_top.env.scoreboard] Check failed flash_status_q.size <= 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 8137312981 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/13
  UVM_INFO @ 9374620981 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/13
  UVM_INFO @ 14314862981 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/13
  UVM_INFO @ 16285443981 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 6/13

28.spi_device_flash_all.75352001400414592798046536291176847497807063135499129230776333404207761397574
Line 251, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/28.spi_device_flash_all/latest/run.log

  UVM_ERROR @ 26538842074 ps: (spi_device_scoreboard.sv:478) [uvm_test_top.env.scoreboard] Check failed flash_status_q.size <= 1 (2 [0x2] vs 1 [0x1])
  UVM_INFO @ 26963610820 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 2/15
  UVM_INFO @ 34454428322 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 3/15
  UVM_INFO @ 41973129313 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 4/15
  UVM_INFO @ 53752570791 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_all_vseq] running iteration 5/15

UVM_FATAL (spi_device_scoreboard.sv:921) [scoreboard] timeout occurred! has 1 failures:
- Test spi_device_flash_mode has 1 failures.
  - 20.spi_device_flash_mode.21970183484807009992297849588989980214803153211488217323072634948957142451566
    Line 249, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/20.spi_device_flash_mode/latest/run.log
```
  UVM_FATAL @ 22560025500 ps: (spi_device_scoreboard.sv:921) [uvm_test_top.env.scoreboard] timeout occurred!
  UVM_INFO @ 22560025500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (spi_device_scoreboard.sv:1070) [scoreboard] Check failed (item.d_data inside {exp_data_q}) act (*) != exp '{'{other_status:*, wel:*, busy:*}} has 1 failures:

Test spi_device_flash_and_tpm has 1 failures.

21.spi_device_flash_and_tpm.47773237956782699049991956072818345928030663188618215740575501613106938252217
Line 252, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm/latest/run.log

  UVM_ERROR @ 2220696043 ps: (spi_device_scoreboard.sv:1070) [uvm_test_top.env.scoreboard] Check failed (item.d_data inside {exp_data_q}) act (0x9abbc6) != exp '{'{other_status:'ha2b44, wel:'h1, busy:'h0}}
  UVM_INFO @ 2733156043 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 2/5
  UVM_INFO @ 2741623043 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 2/4
  UVM_INFO @ 5060844043 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.flash_vseq] running iteration 3/4
  UVM_INFO @ 8232326043 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_vseq.tpm_vseq] starting sequence 3/5

UVM_ERROR (spi_device_scoreboard.sv:1101) [scoreboard] Check failed item.d_data[i] == intr_exp[i] (* [*] vs * [*]) Compare CmdFifoNotEmpty mismatch, act (*) != exp * has 1 failures:

Test spi_device_flash_and_tpm_min_idle has 1 failures.

41.spi_device_flash_and_tpm_min_idle.107164095059753409589415093002163438823845015317078052074098692497298083684274
Line 263, in log /container/opentitan-public/scratch/os_regression/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest/run.log

  UVM_ERROR @ 766039836635 ps: (spi_device_scoreboard.sv:1101) [uvm_test_top.env.scoreboard] Check failed item.d_data[i] == intr_exp[i] (0 [0x0] vs 1 [0x1]) Compare CmdFifoNotEmpty mismatch, act (0x0) != exp 1
  UVM_INFO @ 771682357179 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 8/13
  UVM_INFO @ 785942543107 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 7/10
  UVM_INFO @ 822663594995 ps: (spi_device_flash_all_vseq.sv:46) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.flash_vseq] running iteration 9/13
  UVM_INFO @ 885636909162 ps: (spi_device_tpm_read_hw_reg_vseq.sv:48) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.spi_device_flash_and_tpm_min_idle_vseq.tpm_vseq] starting sequence 8/10