Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
3740 | 
0 | 
0 | 
| T117 | 
6033 | 
102 | 
0 | 
0 | 
| T118 | 
9875 | 
1 | 
0 | 
0 | 
| T119 | 
10950 | 
6 | 
0 | 
0 | 
| T120 | 
6703 | 
302 | 
0 | 
0 | 
| T121 | 
8740 | 
129 | 
0 | 
0 | 
| T122 | 
67699 | 
4 | 
0 | 
0 | 
| T127 | 
18345 | 
193 | 
0 | 
0 | 
| T141 | 
12070 | 
8 | 
0 | 
0 | 
| T142 | 
5143 | 
2 | 
0 | 
0 | 
| T143 | 
3224 | 
6 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1872 | 
0 | 
0 | 
| T122 | 
67699 | 
78 | 
0 | 
0 | 
| T142 | 
5143 | 
13 | 
0 | 
0 | 
| T145 | 
10643 | 
11 | 
0 | 
0 | 
| T148 | 
7514 | 
11 | 
0 | 
0 | 
| T153 | 
4474 | 
5 | 
0 | 
0 | 
| T168 | 
13268 | 
36 | 
0 | 
0 | 
| T169 | 
235180 | 
455 | 
0 | 
0 | 
| T170 | 
17537 | 
12 | 
0 | 
0 | 
| T171 | 
155457 | 
299 | 
0 | 
0 | 
| T172 | 
90546 | 
217 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1746 | 
0 | 
0 | 
| T122 | 
67699 | 
79 | 
0 | 
0 | 
| T142 | 
5143 | 
10 | 
0 | 
0 | 
| T145 | 
10643 | 
10 | 
0 | 
0 | 
| T148 | 
7514 | 
6 | 
0 | 
0 | 
| T151 | 
10045 | 
7 | 
0 | 
0 | 
| T153 | 
4474 | 
11 | 
0 | 
0 | 
| T168 | 
13268 | 
21 | 
0 | 
0 | 
| T169 | 
235180 | 
421 | 
0 | 
0 | 
| T170 | 
17537 | 
40 | 
0 | 
0 | 
| T173 | 
6436 | 
23 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
2078 | 
0 | 
0 | 
| T122 | 
67699 | 
150 | 
0 | 
0 | 
| T142 | 
5143 | 
5 | 
0 | 
0 | 
| T145 | 
10643 | 
26 | 
0 | 
0 | 
| T148 | 
7514 | 
13 | 
0 | 
0 | 
| T151 | 
10045 | 
5 | 
0 | 
0 | 
| T153 | 
4474 | 
11 | 
0 | 
0 | 
| T168 | 
13268 | 
33 | 
0 | 
0 | 
| T169 | 
235180 | 
403 | 
0 | 
0 | 
| T170 | 
17537 | 
27 | 
0 | 
0 | 
| T173 | 
6436 | 
26 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
7108 | 
0 | 
0 | 
| T122 | 
67699 | 
1324 | 
0 | 
0 | 
| T142 | 
5143 | 
117 | 
0 | 
0 | 
| T145 | 
10643 | 
375 | 
0 | 
0 | 
| T148 | 
7514 | 
87 | 
0 | 
0 | 
| T151 | 
10045 | 
183 | 
0 | 
0 | 
| T153 | 
4474 | 
17 | 
0 | 
0 | 
| T168 | 
13268 | 
53 | 
0 | 
0 | 
| T169 | 
235180 | 
406 | 
0 | 
0 | 
| T170 | 
17537 | 
31 | 
0 | 
0 | 
| T173 | 
6436 | 
33 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
7334 | 
0 | 
0 | 
| T122 | 
67699 | 
1438 | 
0 | 
0 | 
| T142 | 
5143 | 
9 | 
0 | 
0 | 
| T145 | 
10643 | 
138 | 
0 | 
0 | 
| T148 | 
7514 | 
112 | 
0 | 
0 | 
| T151 | 
10045 | 
3 | 
0 | 
0 | 
| T153 | 
4474 | 
22 | 
0 | 
0 | 
| T168 | 
13268 | 
69 | 
0 | 
0 | 
| T169 | 
235180 | 
389 | 
0 | 
0 | 
| T170 | 
17537 | 
19 | 
0 | 
0 | 
| T173 | 
6436 | 
24 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
6640 | 
0 | 
0 | 
| T122 | 
67699 | 
764 | 
0 | 
0 | 
| T142 | 
5143 | 
8 | 
0 | 
0 | 
| T145 | 
10643 | 
124 | 
0 | 
0 | 
| T148 | 
7514 | 
128 | 
0 | 
0 | 
| T151 | 
10045 | 
1 | 
0 | 
0 | 
| T153 | 
4474 | 
18 | 
0 | 
0 | 
| T168 | 
13268 | 
35 | 
0 | 
0 | 
| T169 | 
235180 | 
493 | 
0 | 
0 | 
| T170 | 
17537 | 
25 | 
0 | 
0 | 
| T173 | 
6436 | 
17 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
8207 | 
0 | 
0 | 
| T122 | 
67699 | 
1355 | 
0 | 
0 | 
| T142 | 
5143 | 
127 | 
0 | 
0 | 
| T145 | 
10643 | 
248 | 
0 | 
0 | 
| T148 | 
7514 | 
63 | 
0 | 
0 | 
| T151 | 
10045 | 
114 | 
0 | 
0 | 
| T153 | 
4474 | 
6 | 
0 | 
0 | 
| T168 | 
13268 | 
39 | 
0 | 
0 | 
| T169 | 
235180 | 
415 | 
0 | 
0 | 
| T170 | 
17537 | 
39 | 
0 | 
0 | 
| T173 | 
6436 | 
21 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
8373 | 
0 | 
0 | 
| T122 | 
67699 | 
1852 | 
0 | 
0 | 
| T142 | 
5143 | 
4 | 
0 | 
0 | 
| T145 | 
10643 | 
236 | 
0 | 
0 | 
| T148 | 
7514 | 
66 | 
0 | 
0 | 
| T151 | 
10045 | 
122 | 
0 | 
0 | 
| T153 | 
4474 | 
6 | 
0 | 
0 | 
| T168 | 
13268 | 
22 | 
0 | 
0 | 
| T169 | 
235180 | 
486 | 
0 | 
0 | 
| T170 | 
17537 | 
70 | 
0 | 
0 | 
| T173 | 
6436 | 
8 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
7879 | 
0 | 
0 | 
| T122 | 
67699 | 
1531 | 
0 | 
0 | 
| T142 | 
5143 | 
156 | 
0 | 
0 | 
| T145 | 
10643 | 
134 | 
0 | 
0 | 
| T148 | 
7514 | 
10 | 
0 | 
0 | 
| T151 | 
10045 | 
56 | 
0 | 
0 | 
| T153 | 
4474 | 
5 | 
0 | 
0 | 
| T168 | 
13268 | 
44 | 
0 | 
0 | 
| T169 | 
235180 | 
381 | 
0 | 
0 | 
| T170 | 
17537 | 
26 | 
0 | 
0 | 
| T173 | 
6436 | 
18 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
8066 | 
0 | 
0 | 
| T122 | 
67699 | 
1196 | 
0 | 
0 | 
| T142 | 
5143 | 
5 | 
0 | 
0 | 
| T145 | 
10643 | 
129 | 
0 | 
0 | 
| T148 | 
7514 | 
133 | 
0 | 
0 | 
| T151 | 
10045 | 
88 | 
0 | 
0 | 
| T153 | 
4474 | 
16 | 
0 | 
0 | 
| T168 | 
13268 | 
38 | 
0 | 
0 | 
| T169 | 
235180 | 
402 | 
0 | 
0 | 
| T170 | 
17537 | 
23 | 
0 | 
0 | 
| T173 | 
6436 | 
43 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
6665 | 
0 | 
0 | 
| T122 | 
67699 | 
819 | 
0 | 
0 | 
| T142 | 
5143 | 
133 | 
0 | 
0 | 
| T145 | 
10643 | 
3 | 
0 | 
0 | 
| T148 | 
7514 | 
63 | 
0 | 
0 | 
| T151 | 
10045 | 
120 | 
0 | 
0 | 
| T153 | 
4474 | 
19 | 
0 | 
0 | 
| T168 | 
13268 | 
36 | 
0 | 
0 | 
| T169 | 
235180 | 
352 | 
0 | 
0 | 
| T170 | 
17537 | 
43 | 
0 | 
0 | 
| T173 | 
6436 | 
1 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
3993 | 
0 | 
0 | 
| T122 | 
67699 | 
636 | 
0 | 
0 | 
| T142 | 
5143 | 
2 | 
0 | 
0 | 
| T145 | 
10643 | 
49 | 
0 | 
0 | 
| T148 | 
7514 | 
41 | 
0 | 
0 | 
| T151 | 
10045 | 
66 | 
0 | 
0 | 
| T153 | 
4474 | 
20 | 
0 | 
0 | 
| T168 | 
13268 | 
55 | 
0 | 
0 | 
| T169 | 
235180 | 
437 | 
0 | 
0 | 
| T170 | 
17537 | 
12 | 
0 | 
0 | 
| T173 | 
6436 | 
50 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4475 | 
0 | 
0 | 
| T122 | 
67699 | 
526 | 
0 | 
0 | 
| T142 | 
5143 | 
56 | 
0 | 
0 | 
| T145 | 
10643 | 
96 | 
0 | 
0 | 
| T148 | 
7514 | 
39 | 
0 | 
0 | 
| T151 | 
10045 | 
22 | 
0 | 
0 | 
| T153 | 
4474 | 
18 | 
0 | 
0 | 
| T168 | 
13268 | 
33 | 
0 | 
0 | 
| T169 | 
235180 | 
413 | 
0 | 
0 | 
| T170 | 
17537 | 
17 | 
0 | 
0 | 
| T173 | 
6436 | 
16 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4238 | 
0 | 
0 | 
| T122 | 
67699 | 
361 | 
0 | 
0 | 
| T142 | 
5143 | 
11 | 
0 | 
0 | 
| T145 | 
10643 | 
44 | 
0 | 
0 | 
| T148 | 
7514 | 
30 | 
0 | 
0 | 
| T151 | 
10045 | 
73 | 
0 | 
0 | 
| T153 | 
4474 | 
10 | 
0 | 
0 | 
| T168 | 
13268 | 
66 | 
0 | 
0 | 
| T169 | 
235180 | 
395 | 
0 | 
0 | 
| T170 | 
17537 | 
58 | 
0 | 
0 | 
| T173 | 
6436 | 
33 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4343 | 
0 | 
0 | 
| T122 | 
67699 | 
536 | 
0 | 
0 | 
| T142 | 
5143 | 
71 | 
0 | 
0 | 
| T145 | 
10643 | 
145 | 
0 | 
0 | 
| T148 | 
7514 | 
6 | 
0 | 
0 | 
| T151 | 
10045 | 
25 | 
0 | 
0 | 
| T153 | 
4474 | 
13 | 
0 | 
0 | 
| T168 | 
13268 | 
43 | 
0 | 
0 | 
| T169 | 
235180 | 
452 | 
0 | 
0 | 
| T170 | 
17537 | 
60 | 
0 | 
0 | 
| T173 | 
6436 | 
43 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4179 | 
0 | 
0 | 
| T122 | 
67699 | 
546 | 
0 | 
0 | 
| T142 | 
5143 | 
10 | 
0 | 
0 | 
| T145 | 
10643 | 
109 | 
0 | 
0 | 
| T148 | 
7514 | 
4 | 
0 | 
0 | 
| T151 | 
10045 | 
60 | 
0 | 
0 | 
| T153 | 
4474 | 
13 | 
0 | 
0 | 
| T168 | 
13268 | 
43 | 
0 | 
0 | 
| T169 | 
235180 | 
397 | 
0 | 
0 | 
| T170 | 
17537 | 
42 | 
0 | 
0 | 
| T173 | 
6436 | 
25 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
3847 | 
0 | 
0 | 
| T122 | 
67699 | 
521 | 
0 | 
0 | 
| T142 | 
5143 | 
46 | 
0 | 
0 | 
| T145 | 
10643 | 
60 | 
0 | 
0 | 
| T148 | 
7514 | 
49 | 
0 | 
0 | 
| T151 | 
10045 | 
71 | 
0 | 
0 | 
| T153 | 
4474 | 
14 | 
0 | 
0 | 
| T168 | 
13268 | 
23 | 
0 | 
0 | 
| T169 | 
235180 | 
456 | 
0 | 
0 | 
| T170 | 
17537 | 
36 | 
0 | 
0 | 
| T173 | 
6436 | 
1 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4178 | 
0 | 
0 | 
| T122 | 
67699 | 
560 | 
0 | 
0 | 
| T142 | 
5143 | 
10 | 
0 | 
0 | 
| T145 | 
10643 | 
152 | 
0 | 
0 | 
| T148 | 
7514 | 
25 | 
0 | 
0 | 
| T151 | 
10045 | 
45 | 
0 | 
0 | 
| T153 | 
4474 | 
12 | 
0 | 
0 | 
| T168 | 
13268 | 
54 | 
0 | 
0 | 
| T169 | 
235180 | 
401 | 
0 | 
0 | 
| T170 | 
17537 | 
27 | 
0 | 
0 | 
| T173 | 
6436 | 
14 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4234 | 
0 | 
0 | 
| T122 | 
67699 | 
489 | 
0 | 
0 | 
| T142 | 
5143 | 
74 | 
0 | 
0 | 
| T145 | 
10643 | 
67 | 
0 | 
0 | 
| T148 | 
7514 | 
28 | 
0 | 
0 | 
| T151 | 
10045 | 
5 | 
0 | 
0 | 
| T153 | 
4474 | 
13 | 
0 | 
0 | 
| T168 | 
13268 | 
56 | 
0 | 
0 | 
| T169 | 
235180 | 
359 | 
0 | 
0 | 
| T170 | 
17537 | 
13 | 
0 | 
0 | 
| T173 | 
6436 | 
12 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4059 | 
0 | 
0 | 
| T122 | 
67699 | 
538 | 
0 | 
0 | 
| T142 | 
5143 | 
60 | 
0 | 
0 | 
| T145 | 
10643 | 
16 | 
0 | 
0 | 
| T148 | 
7514 | 
44 | 
0 | 
0 | 
| T153 | 
4474 | 
9 | 
0 | 
0 | 
| T168 | 
13268 | 
47 | 
0 | 
0 | 
| T169 | 
235180 | 
490 | 
0 | 
0 | 
| T170 | 
17537 | 
17 | 
0 | 
0 | 
| T171 | 
155457 | 
242 | 
0 | 
0 | 
| T173 | 
6436 | 
20 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4095 | 
0 | 
0 | 
| T122 | 
67699 | 
371 | 
0 | 
0 | 
| T142 | 
5143 | 
58 | 
0 | 
0 | 
| T145 | 
10643 | 
155 | 
0 | 
0 | 
| T148 | 
7514 | 
32 | 
0 | 
0 | 
| T151 | 
10045 | 
96 | 
0 | 
0 | 
| T153 | 
4474 | 
7 | 
0 | 
0 | 
| T168 | 
13268 | 
43 | 
0 | 
0 | 
| T169 | 
235180 | 
452 | 
0 | 
0 | 
| T170 | 
17537 | 
53 | 
0 | 
0 | 
| T173 | 
6436 | 
15 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4076 | 
0 | 
0 | 
| T122 | 
67699 | 
515 | 
0 | 
0 | 
| T142 | 
5143 | 
8 | 
0 | 
0 | 
| T145 | 
10643 | 
89 | 
0 | 
0 | 
| T148 | 
7514 | 
17 | 
0 | 
0 | 
| T151 | 
10045 | 
47 | 
0 | 
0 | 
| T153 | 
4474 | 
12 | 
0 | 
0 | 
| T168 | 
13268 | 
14 | 
0 | 
0 | 
| T169 | 
235180 | 
444 | 
0 | 
0 | 
| T170 | 
17537 | 
21 | 
0 | 
0 | 
| T173 | 
6436 | 
1 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4277 | 
0 | 
0 | 
| T122 | 
67699 | 
655 | 
0 | 
0 | 
| T142 | 
5143 | 
9 | 
0 | 
0 | 
| T145 | 
10643 | 
103 | 
0 | 
0 | 
| T151 | 
10045 | 
67 | 
0 | 
0 | 
| T153 | 
4474 | 
13 | 
0 | 
0 | 
| T168 | 
13268 | 
15 | 
0 | 
0 | 
| T169 | 
235180 | 
392 | 
0 | 
0 | 
| T170 | 
17537 | 
30 | 
0 | 
0 | 
| T171 | 
155457 | 
259 | 
0 | 
0 | 
| T173 | 
6436 | 
38 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
3808 | 
0 | 
0 | 
| T122 | 
67699 | 
395 | 
0 | 
0 | 
| T142 | 
5143 | 
8 | 
0 | 
0 | 
| T145 | 
10643 | 
15 | 
0 | 
0 | 
| T148 | 
7514 | 
40 | 
0 | 
0 | 
| T151 | 
10045 | 
21 | 
0 | 
0 | 
| T153 | 
4474 | 
16 | 
0 | 
0 | 
| T168 | 
13268 | 
18 | 
0 | 
0 | 
| T169 | 
235180 | 
343 | 
0 | 
0 | 
| T170 | 
17537 | 
32 | 
0 | 
0 | 
| T173 | 
6436 | 
1 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
3773 | 
0 | 
0 | 
| T122 | 
67699 | 
450 | 
0 | 
0 | 
| T142 | 
5143 | 
8 | 
0 | 
0 | 
| T145 | 
10643 | 
54 | 
0 | 
0 | 
| T148 | 
7514 | 
17 | 
0 | 
0 | 
| T151 | 
10045 | 
50 | 
0 | 
0 | 
| T153 | 
4474 | 
6 | 
0 | 
0 | 
| T168 | 
13268 | 
50 | 
0 | 
0 | 
| T169 | 
235180 | 
402 | 
0 | 
0 | 
| T170 | 
17537 | 
45 | 
0 | 
0 | 
| T173 | 
6436 | 
20 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4166 | 
0 | 
0 | 
| T122 | 
67699 | 
496 | 
0 | 
0 | 
| T142 | 
5143 | 
3 | 
0 | 
0 | 
| T145 | 
10643 | 
43 | 
0 | 
0 | 
| T148 | 
7514 | 
21 | 
0 | 
0 | 
| T151 | 
10045 | 
83 | 
0 | 
0 | 
| T153 | 
4474 | 
11 | 
0 | 
0 | 
| T168 | 
13268 | 
75 | 
0 | 
0 | 
| T169 | 
235180 | 
390 | 
0 | 
0 | 
| T170 | 
17537 | 
31 | 
0 | 
0 | 
| T173 | 
6436 | 
9 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4371 | 
0 | 
0 | 
| T122 | 
67699 | 
489 | 
0 | 
0 | 
| T142 | 
5143 | 
44 | 
0 | 
0 | 
| T145 | 
10643 | 
46 | 
0 | 
0 | 
| T148 | 
7514 | 
3 | 
0 | 
0 | 
| T151 | 
10045 | 
60 | 
0 | 
0 | 
| T153 | 
4474 | 
10 | 
0 | 
0 | 
| T168 | 
13268 | 
16 | 
0 | 
0 | 
| T169 | 
235180 | 
410 | 
0 | 
0 | 
| T170 | 
17537 | 
20 | 
0 | 
0 | 
| T173 | 
6436 | 
17 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4024 | 
0 | 
0 | 
| T122 | 
67699 | 
823 | 
0 | 
0 | 
| T142 | 
5143 | 
42 | 
0 | 
0 | 
| T145 | 
10643 | 
15 | 
0 | 
0 | 
| T148 | 
7514 | 
29 | 
0 | 
0 | 
| T151 | 
10045 | 
48 | 
0 | 
0 | 
| T153 | 
4474 | 
12 | 
0 | 
0 | 
| T168 | 
13268 | 
75 | 
0 | 
0 | 
| T169 | 
235180 | 
341 | 
0 | 
0 | 
| T170 | 
17537 | 
11 | 
0 | 
0 | 
| T173 | 
6436 | 
7 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4598 | 
0 | 
0 | 
| T122 | 
67699 | 
554 | 
0 | 
0 | 
| T142 | 
5143 | 
78 | 
0 | 
0 | 
| T145 | 
10643 | 
120 | 
0 | 
0 | 
| T148 | 
7514 | 
5 | 
0 | 
0 | 
| T151 | 
10045 | 
39 | 
0 | 
0 | 
| T153 | 
4474 | 
19 | 
0 | 
0 | 
| T168 | 
13268 | 
51 | 
0 | 
0 | 
| T169 | 
235180 | 
431 | 
0 | 
0 | 
| T170 | 
17537 | 
51 | 
0 | 
0 | 
| T173 | 
6436 | 
36 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
3936 | 
0 | 
0 | 
| T122 | 
67699 | 
601 | 
0 | 
0 | 
| T142 | 
5143 | 
43 | 
0 | 
0 | 
| T145 | 
10643 | 
85 | 
0 | 
0 | 
| T148 | 
7514 | 
67 | 
0 | 
0 | 
| T151 | 
10045 | 
35 | 
0 | 
0 | 
| T153 | 
4474 | 
4 | 
0 | 
0 | 
| T168 | 
13268 | 
50 | 
0 | 
0 | 
| T169 | 
235180 | 
420 | 
0 | 
0 | 
| T170 | 
17537 | 
34 | 
0 | 
0 | 
| T173 | 
6436 | 
28 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
3798 | 
0 | 
0 | 
| T122 | 
67699 | 
626 | 
0 | 
0 | 
| T142 | 
5143 | 
10 | 
0 | 
0 | 
| T145 | 
10643 | 
92 | 
0 | 
0 | 
| T148 | 
7514 | 
18 | 
0 | 
0 | 
| T151 | 
10045 | 
46 | 
0 | 
0 | 
| T153 | 
4474 | 
7 | 
0 | 
0 | 
| T168 | 
13268 | 
109 | 
0 | 
0 | 
| T169 | 
235180 | 
400 | 
0 | 
0 | 
| T170 | 
17537 | 
21 | 
0 | 
0 | 
| T173 | 
6436 | 
38 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4066 | 
0 | 
0 | 
| T122 | 
67699 | 
739 | 
0 | 
0 | 
| T142 | 
5143 | 
6 | 
0 | 
0 | 
| T145 | 
10643 | 
139 | 
0 | 
0 | 
| T148 | 
7514 | 
18 | 
0 | 
0 | 
| T151 | 
10045 | 
55 | 
0 | 
0 | 
| T153 | 
4474 | 
20 | 
0 | 
0 | 
| T168 | 
13268 | 
8 | 
0 | 
0 | 
| T169 | 
235180 | 
444 | 
0 | 
0 | 
| T170 | 
17537 | 
13 | 
0 | 
0 | 
| T173 | 
6436 | 
2 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4355 | 
0 | 
0 | 
| T122 | 
67699 | 
506 | 
0 | 
0 | 
| T142 | 
5143 | 
6 | 
0 | 
0 | 
| T145 | 
10643 | 
112 | 
0 | 
0 | 
| T148 | 
7514 | 
40 | 
0 | 
0 | 
| T151 | 
10045 | 
37 | 
0 | 
0 | 
| T153 | 
4474 | 
18 | 
0 | 
0 | 
| T168 | 
13268 | 
30 | 
0 | 
0 | 
| T169 | 
235180 | 
426 | 
0 | 
0 | 
| T170 | 
17537 | 
22 | 
0 | 
0 | 
| T173 | 
6436 | 
28 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4111 | 
0 | 
0 | 
| T122 | 
67699 | 
612 | 
0 | 
0 | 
| T142 | 
5143 | 
16 | 
0 | 
0 | 
| T145 | 
10643 | 
44 | 
0 | 
0 | 
| T148 | 
7514 | 
32 | 
0 | 
0 | 
| T151 | 
10045 | 
13 | 
0 | 
0 | 
| T153 | 
4474 | 
10 | 
0 | 
0 | 
| T168 | 
13268 | 
17 | 
0 | 
0 | 
| T169 | 
235180 | 
459 | 
0 | 
0 | 
| T170 | 
17537 | 
12 | 
0 | 
0 | 
| T173 | 
6436 | 
22 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
4001 | 
0 | 
0 | 
| T122 | 
67699 | 
585 | 
0 | 
0 | 
| T142 | 
5143 | 
40 | 
0 | 
0 | 
| T145 | 
10643 | 
91 | 
0 | 
0 | 
| T151 | 
10045 | 
48 | 
0 | 
0 | 
| T153 | 
4474 | 
13 | 
0 | 
0 | 
| T168 | 
13268 | 
26 | 
0 | 
0 | 
| T169 | 
235180 | 
347 | 
0 | 
0 | 
| T170 | 
17537 | 
38 | 
0 | 
0 | 
| T171 | 
155457 | 
256 | 
0 | 
0 | 
| T173 | 
6436 | 
7 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
2242 | 
0 | 
0 | 
| T122 | 
67699 | 
149 | 
0 | 
0 | 
| T142 | 
5143 | 
17 | 
0 | 
0 | 
| T145 | 
10643 | 
19 | 
0 | 
0 | 
| T151 | 
10045 | 
2 | 
0 | 
0 | 
| T153 | 
4474 | 
12 | 
0 | 
0 | 
| T168 | 
13268 | 
44 | 
0 | 
0 | 
| T169 | 
235180 | 
462 | 
0 | 
0 | 
| T170 | 
17537 | 
35 | 
0 | 
0 | 
| T171 | 
155457 | 
303 | 
0 | 
0 | 
| T173 | 
6436 | 
56 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
2068 | 
0 | 
0 | 
| T122 | 
67699 | 
97 | 
0 | 
0 | 
| T142 | 
5143 | 
18 | 
0 | 
0 | 
| T145 | 
10643 | 
18 | 
0 | 
0 | 
| T148 | 
7514 | 
15 | 
0 | 
0 | 
| T151 | 
10045 | 
18 | 
0 | 
0 | 
| T153 | 
4474 | 
5 | 
0 | 
0 | 
| T168 | 
13268 | 
41 | 
0 | 
0 | 
| T169 | 
235180 | 
414 | 
0 | 
0 | 
| T170 | 
17537 | 
44 | 
0 | 
0 | 
| T173 | 
6436 | 
40 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
2108 | 
0 | 
0 | 
| T122 | 
67699 | 
140 | 
0 | 
0 | 
| T142 | 
5143 | 
5 | 
0 | 
0 | 
| T145 | 
10643 | 
13 | 
0 | 
0 | 
| T148 | 
7514 | 
16 | 
0 | 
0 | 
| T151 | 
10045 | 
6 | 
0 | 
0 | 
| T153 | 
4474 | 
7 | 
0 | 
0 | 
| T168 | 
13268 | 
31 | 
0 | 
0 | 
| T169 | 
235180 | 
426 | 
0 | 
0 | 
| T170 | 
17537 | 
24 | 
0 | 
0 | 
| T173 | 
6436 | 
8 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1900 | 
0 | 
0 | 
| T122 | 
67699 | 
122 | 
0 | 
0 | 
| T142 | 
5143 | 
2 | 
0 | 
0 | 
| T145 | 
10643 | 
17 | 
0 | 
0 | 
| T148 | 
7514 | 
12 | 
0 | 
0 | 
| T151 | 
10045 | 
21 | 
0 | 
0 | 
| T153 | 
4474 | 
1 | 
0 | 
0 | 
| T168 | 
13268 | 
57 | 
0 | 
0 | 
| T169 | 
235180 | 
291 | 
0 | 
0 | 
| T170 | 
17537 | 
19 | 
0 | 
0 | 
| T171 | 
155457 | 
278 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
2244 | 
0 | 
0 | 
| T122 | 
67699 | 
203 | 
0 | 
0 | 
| T142 | 
5143 | 
10 | 
0 | 
0 | 
| T145 | 
10643 | 
24 | 
0 | 
0 | 
| T148 | 
7514 | 
11 | 
0 | 
0 | 
| T153 | 
4474 | 
17 | 
0 | 
0 | 
| T168 | 
13268 | 
55 | 
0 | 
0 | 
| T169 | 
235180 | 
310 | 
0 | 
0 | 
| T170 | 
17537 | 
48 | 
0 | 
0 | 
| T171 | 
155457 | 
264 | 
0 | 
0 | 
| T173 | 
6436 | 
31 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
3803 | 
0 | 
0 | 
| T32 | 
6583 | 
85 | 
0 | 
0 | 
| T33 | 
5740 | 
0 | 
0 | 
0 | 
| T35 | 
0 | 
56 | 
0 | 
0 | 
| T36 | 
0 | 
63 | 
0 | 
0 | 
| T37 | 
0 | 
29 | 
0 | 
0 | 
| T62 | 
682915 | 
0 | 
0 | 
0 | 
| T95 | 
0 | 
10 | 
0 | 
0 | 
| T111 | 
4050 | 
0 | 
0 | 
0 | 
| T174 | 
0 | 
22 | 
0 | 
0 | 
| T175 | 
0 | 
56 | 
0 | 
0 | 
| T176 | 
0 | 
13 | 
0 | 
0 | 
| T177 | 
0 | 
17 | 
0 | 
0 | 
| T178 | 
0 | 
21 | 
0 | 
0 | 
| T179 | 
1273 | 
0 | 
0 | 
0 | 
| T180 | 
981 | 
0 | 
0 | 
0 | 
| T181 | 
1166 | 
0 | 
0 | 
0 | 
| T182 | 
1051 | 
0 | 
0 | 
0 | 
| T183 | 
2349 | 
0 | 
0 | 
0 | 
| T184 | 
951344 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1909 | 
0 | 
0 | 
| T122 | 
67699 | 
106 | 
0 | 
0 | 
| T142 | 
5143 | 
6 | 
0 | 
0 | 
| T145 | 
10643 | 
12 | 
0 | 
0 | 
| T148 | 
7514 | 
4 | 
0 | 
0 | 
| T151 | 
10045 | 
5 | 
0 | 
0 | 
| T153 | 
4474 | 
15 | 
0 | 
0 | 
| T168 | 
13268 | 
31 | 
0 | 
0 | 
| T169 | 
235180 | 
377 | 
0 | 
0 | 
| T170 | 
17537 | 
28 | 
0 | 
0 | 
| T173 | 
6436 | 
5 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1949 | 
0 | 
0 | 
| T122 | 
67699 | 
112 | 
0 | 
0 | 
| T142 | 
5143 | 
15 | 
0 | 
0 | 
| T145 | 
10643 | 
13 | 
0 | 
0 | 
| T148 | 
7514 | 
5 | 
0 | 
0 | 
| T151 | 
10045 | 
18 | 
0 | 
0 | 
| T153 | 
4474 | 
15 | 
0 | 
0 | 
| T168 | 
13268 | 
29 | 
0 | 
0 | 
| T169 | 
235180 | 
405 | 
0 | 
0 | 
| T170 | 
17537 | 
7 | 
0 | 
0 | 
| T173 | 
6436 | 
35 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1856 | 
0 | 
0 | 
| T122 | 
67699 | 
68 | 
0 | 
0 | 
| T142 | 
5143 | 
14 | 
0 | 
0 | 
| T145 | 
10643 | 
17 | 
0 | 
0 | 
| T148 | 
7514 | 
2 | 
0 | 
0 | 
| T151 | 
10045 | 
20 | 
0 | 
0 | 
| T153 | 
4474 | 
15 | 
0 | 
0 | 
| T168 | 
13268 | 
25 | 
0 | 
0 | 
| T169 | 
235180 | 
371 | 
0 | 
0 | 
| T170 | 
17537 | 
52 | 
0 | 
0 | 
| T173 | 
6436 | 
11 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1910 | 
0 | 
0 | 
| T122 | 
67699 | 
90 | 
0 | 
0 | 
| T142 | 
5143 | 
9 | 
0 | 
0 | 
| T145 | 
10643 | 
10 | 
0 | 
0 | 
| T153 | 
4474 | 
14 | 
0 | 
0 | 
| T168 | 
13268 | 
19 | 
0 | 
0 | 
| T169 | 
235180 | 
436 | 
0 | 
0 | 
| T170 | 
17537 | 
52 | 
0 | 
0 | 
| T171 | 
155457 | 
253 | 
0 | 
0 | 
| T172 | 
90546 | 
234 | 
0 | 
0 | 
| T173 | 
6436 | 
12 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1885 | 
0 | 
0 | 
| T122 | 
67699 | 
66 | 
0 | 
0 | 
| T127 | 
18345 | 
1 | 
0 | 
0 | 
| T142 | 
5143 | 
3 | 
0 | 
0 | 
| T145 | 
10643 | 
3 | 
0 | 
0 | 
| T148 | 
7514 | 
9 | 
0 | 
0 | 
| T151 | 
10045 | 
11 | 
0 | 
0 | 
| T153 | 
4474 | 
6 | 
0 | 
0 | 
| T168 | 
13268 | 
42 | 
0 | 
0 | 
| T169 | 
235180 | 
413 | 
0 | 
0 | 
| T173 | 
6436 | 
5 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1940 | 
0 | 
0 | 
| T122 | 
67699 | 
54 | 
0 | 
0 | 
| T142 | 
5143 | 
14 | 
0 | 
0 | 
| T145 | 
10643 | 
15 | 
0 | 
0 | 
| T151 | 
10045 | 
5 | 
0 | 
0 | 
| T153 | 
4474 | 
9 | 
0 | 
0 | 
| T168 | 
13268 | 
18 | 
0 | 
0 | 
| T169 | 
235180 | 
439 | 
0 | 
0 | 
| T170 | 
17537 | 
36 | 
0 | 
0 | 
| T171 | 
155457 | 
305 | 
0 | 
0 | 
| T173 | 
6436 | 
31 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
2315 | 
0 | 
0 | 
| T122 | 
67699 | 
173 | 
0 | 
0 | 
| T142 | 
5143 | 
28 | 
0 | 
0 | 
| T145 | 
10643 | 
44 | 
0 | 
0 | 
| T148 | 
7514 | 
7 | 
0 | 
0 | 
| T151 | 
10045 | 
26 | 
0 | 
0 | 
| T153 | 
4474 | 
9 | 
0 | 
0 | 
| T168 | 
13268 | 
49 | 
0 | 
0 | 
| T169 | 
235180 | 
400 | 
0 | 
0 | 
| T170 | 
17537 | 
42 | 
0 | 
0 | 
| T173 | 
6436 | 
8 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1926 | 
0 | 
0 | 
| T122 | 
67699 | 
64 | 
0 | 
0 | 
| T142 | 
5143 | 
6 | 
0 | 
0 | 
| T145 | 
10643 | 
16 | 
0 | 
0 | 
| T151 | 
10045 | 
7 | 
0 | 
0 | 
| T153 | 
4474 | 
13 | 
0 | 
0 | 
| T168 | 
13268 | 
37 | 
0 | 
0 | 
| T169 | 
235180 | 
411 | 
0 | 
0 | 
| T170 | 
17537 | 
61 | 
0 | 
0 | 
| T171 | 
155457 | 
224 | 
0 | 
0 | 
| T173 | 
6436 | 
28 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
2448 | 
0 | 
0 | 
| T122 | 
67699 | 
215 | 
0 | 
0 | 
| T127 | 
18345 | 
5 | 
0 | 
0 | 
| T142 | 
5143 | 
9 | 
0 | 
0 | 
| T145 | 
10643 | 
26 | 
0 | 
0 | 
| T148 | 
7514 | 
5 | 
0 | 
0 | 
| T151 | 
10045 | 
23 | 
0 | 
0 | 
| T153 | 
4474 | 
4 | 
0 | 
0 | 
| T168 | 
13268 | 
60 | 
0 | 
0 | 
| T169 | 
235180 | 
409 | 
0 | 
0 | 
| T173 | 
6436 | 
15 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1889 | 
0 | 
0 | 
| T122 | 
67699 | 
97 | 
0 | 
0 | 
| T142 | 
5143 | 
16 | 
0 | 
0 | 
| T145 | 
10643 | 
12 | 
0 | 
0 | 
| T151 | 
10045 | 
8 | 
0 | 
0 | 
| T153 | 
4474 | 
16 | 
0 | 
0 | 
| T168 | 
13268 | 
24 | 
0 | 
0 | 
| T169 | 
235180 | 
366 | 
0 | 
0 | 
| T170 | 
17537 | 
31 | 
0 | 
0 | 
| T171 | 
155457 | 
236 | 
0 | 
0 | 
| T173 | 
6436 | 
41 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1809 | 
0 | 
0 | 
| T122 | 
67699 | 
82 | 
0 | 
0 | 
| T142 | 
5143 | 
7 | 
0 | 
0 | 
| T145 | 
10643 | 
9 | 
0 | 
0 | 
| T148 | 
7514 | 
3 | 
0 | 
0 | 
| T153 | 
4474 | 
13 | 
0 | 
0 | 
| T168 | 
13268 | 
37 | 
0 | 
0 | 
| T169 | 
235180 | 
409 | 
0 | 
0 | 
| T170 | 
17537 | 
22 | 
0 | 
0 | 
| T171 | 
155457 | 
260 | 
0 | 
0 | 
| T173 | 
6436 | 
5 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1784 | 
0 | 
0 | 
| T122 | 
67699 | 
104 | 
0 | 
0 | 
| T142 | 
5143 | 
8 | 
0 | 
0 | 
| T145 | 
10643 | 
14 | 
0 | 
0 | 
| T148 | 
7514 | 
3 | 
0 | 
0 | 
| T151 | 
10045 | 
4 | 
0 | 
0 | 
| T153 | 
4474 | 
17 | 
0 | 
0 | 
| T168 | 
13268 | 
5 | 
0 | 
0 | 
| T169 | 
235180 | 
352 | 
0 | 
0 | 
| T170 | 
17537 | 
23 | 
0 | 
0 | 
| T173 | 
6436 | 
21 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1859 | 
0 | 
0 | 
| T122 | 
67699 | 
66 | 
0 | 
0 | 
| T142 | 
5143 | 
6 | 
0 | 
0 | 
| T145 | 
10643 | 
12 | 
0 | 
0 | 
| T151 | 
10045 | 
9 | 
0 | 
0 | 
| T153 | 
4474 | 
12 | 
0 | 
0 | 
| T168 | 
13268 | 
14 | 
0 | 
0 | 
| T169 | 
235180 | 
392 | 
0 | 
0 | 
| T170 | 
17537 | 
4 | 
0 | 
0 | 
| T171 | 
155457 | 
273 | 
0 | 
0 | 
| T173 | 
6436 | 
59 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1739 | 
0 | 
0 | 
| T122 | 
67699 | 
64 | 
0 | 
0 | 
| T142 | 
5143 | 
6 | 
0 | 
0 | 
| T145 | 
10643 | 
11 | 
0 | 
0 | 
| T148 | 
7514 | 
9 | 
0 | 
0 | 
| T151 | 
10045 | 
8 | 
0 | 
0 | 
| T153 | 
4474 | 
3 | 
0 | 
0 | 
| T168 | 
13268 | 
60 | 
0 | 
0 | 
| T169 | 
235180 | 
420 | 
0 | 
0 | 
| T170 | 
17537 | 
57 | 
0 | 
0 | 
| T173 | 
6436 | 
23 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1950 | 
0 | 
0 | 
| T122 | 
67699 | 
60 | 
0 | 
0 | 
| T142 | 
5143 | 
4 | 
0 | 
0 | 
| T145 | 
10643 | 
18 | 
0 | 
0 | 
| T148 | 
7514 | 
1 | 
0 | 
0 | 
| T151 | 
10045 | 
13 | 
0 | 
0 | 
| T153 | 
4474 | 
17 | 
0 | 
0 | 
| T168 | 
13268 | 
61 | 
0 | 
0 | 
| T169 | 
235180 | 
509 | 
0 | 
0 | 
| T170 | 
17537 | 
24 | 
0 | 
0 | 
| T173 | 
6436 | 
33 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
472825360 | 
1852 | 
0 | 
0 | 
| T122 | 
67699 | 
51 | 
0 | 
0 | 
| T142 | 
5143 | 
11 | 
0 | 
0 | 
| T145 | 
10643 | 
12 | 
0 | 
0 | 
| T148 | 
7514 | 
17 | 
0 | 
0 | 
| T151 | 
10045 | 
4 | 
0 | 
0 | 
| T153 | 
4474 | 
12 | 
0 | 
0 | 
| T168 | 
13268 | 
79 | 
0 | 
0 | 
| T169 | 
235180 | 
396 | 
0 | 
0 | 
| T170 | 
17537 | 
14 | 
0 | 
0 | 
| T173 | 
6436 | 
28 | 
0 | 
0 |