| T837 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.1014861469 |
|
|
Aug 25 11:08:08 AM UTC 24 |
Aug 25 11:08:47 AM UTC 24 |
58226756620 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.2920962153 |
|
|
Aug 25 11:06:47 AM UTC 24 |
Aug 25 11:08:48 AM UTC 24 |
21722493116 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.2138767081 |
|
|
Aug 25 11:08:43 AM UTC 24 |
Aug 25 11:08:49 AM UTC 24 |
824396670 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.2231142328 |
|
|
Aug 25 11:08:40 AM UTC 24 |
Aug 25 11:08:49 AM UTC 24 |
554865507 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.2448814392 |
|
|
Aug 25 11:08:39 AM UTC 24 |
Aug 25 11:08:50 AM UTC 24 |
1038097421 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1741403846 |
|
|
Aug 25 11:08:39 AM UTC 24 |
Aug 25 11:08:50 AM UTC 24 |
5399075496 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.3678463259 |
|
|
Aug 25 11:05:24 AM UTC 24 |
Aug 25 11:08:51 AM UTC 24 |
175519569793 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.3101419489 |
|
|
Aug 25 11:08:04 AM UTC 24 |
Aug 25 11:08:54 AM UTC 24 |
22411847860 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.1913186682 |
|
|
Aug 25 11:08:52 AM UTC 24 |
Aug 25 11:08:54 AM UTC 24 |
11396328 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.3278639660 |
|
|
Aug 25 11:08:43 AM UTC 24 |
Aug 25 11:08:54 AM UTC 24 |
3779713283 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.4270104208 |
|
|
Aug 25 11:08:52 AM UTC 24 |
Aug 25 11:08:54 AM UTC 24 |
23677651 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.1339682747 |
|
|
Aug 25 11:06:51 AM UTC 24 |
Aug 25 11:08:56 AM UTC 24 |
24251333257 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.2920447857 |
|
|
Aug 25 11:08:55 AM UTC 24 |
Aug 25 11:08:58 AM UTC 24 |
95501081 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2224649190 |
|
|
Aug 25 11:07:16 AM UTC 24 |
Aug 25 11:08:59 AM UTC 24 |
9054172735 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.2328418005 |
|
|
Aug 25 11:08:48 AM UTC 24 |
Aug 25 11:08:59 AM UTC 24 |
1168263275 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.1989144908 |
|
|
Aug 25 11:08:56 AM UTC 24 |
Aug 25 11:09:02 AM UTC 24 |
1760835682 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.159828917 |
|
|
Aug 25 11:08:46 AM UTC 24 |
Aug 25 11:09:04 AM UTC 24 |
1254757607 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.574521950 |
|
|
Aug 25 11:05:37 AM UTC 24 |
Aug 25 11:09:05 AM UTC 24 |
9829670555 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.1885706303 |
|
|
Aug 25 11:06:16 AM UTC 24 |
Aug 25 11:09:06 AM UTC 24 |
20100053101 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.125751904 |
|
|
Aug 25 11:05:03 AM UTC 24 |
Aug 25 11:09:06 AM UTC 24 |
153588727382 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.3868855907 |
|
|
Aug 25 11:08:25 AM UTC 24 |
Aug 25 11:09:06 AM UTC 24 |
2160625200 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.1164426998 |
|
|
Aug 25 11:08:55 AM UTC 24 |
Aug 25 11:09:12 AM UTC 24 |
1884115406 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.3494329063 |
|
|
Aug 25 11:08:50 AM UTC 24 |
Aug 25 11:09:12 AM UTC 24 |
4833320623 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.792808586 |
|
|
Aug 25 11:08:40 AM UTC 24 |
Aug 25 11:09:12 AM UTC 24 |
18384944692 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.2318105161 |
|
|
Aug 25 11:07:18 AM UTC 24 |
Aug 25 11:09:12 AM UTC 24 |
3193193539 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.2556760030 |
|
|
Aug 25 11:07:59 AM UTC 24 |
Aug 25 11:09:13 AM UTC 24 |
3803963665 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.4095727949 |
|
|
Aug 25 11:09:11 AM UTC 24 |
Aug 25 11:09:14 AM UTC 24 |
15540076 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.107052336 |
|
|
Aug 25 11:04:48 AM UTC 24 |
Aug 25 11:09:14 AM UTC 24 |
8422802385 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.1013932555 |
|
|
Aug 25 11:09:13 AM UTC 24 |
Aug 25 11:09:16 AM UTC 24 |
13406201 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.1054489479 |
|
|
Aug 25 11:09:13 AM UTC 24 |
Aug 25 11:09:16 AM UTC 24 |
155915494 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.3916205916 |
|
|
Aug 25 11:08:31 AM UTC 24 |
Aug 25 11:09:17 AM UTC 24 |
4813701531 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.4256343182 |
|
|
Aug 25 11:09:13 AM UTC 24 |
Aug 25 11:09:17 AM UTC 24 |
93304914 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3256897099 |
|
|
Aug 25 11:09:02 AM UTC 24 |
Aug 25 11:09:18 AM UTC 24 |
3227791298 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1310953161 |
|
|
Aug 25 11:08:59 AM UTC 24 |
Aug 25 11:09:19 AM UTC 24 |
947801741 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.77909271 |
|
|
Aug 25 11:09:15 AM UTC 24 |
Aug 25 11:09:24 AM UTC 24 |
427016063 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.777874722 |
|
|
Aug 25 11:09:16 AM UTC 24 |
Aug 25 11:09:24 AM UTC 24 |
154136005 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.472805539 |
|
|
Aug 25 11:09:07 AM UTC 24 |
Aug 25 11:09:25 AM UTC 24 |
907020858 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.3534494755 |
|
|
Aug 25 11:09:18 AM UTC 24 |
Aug 25 11:09:26 AM UTC 24 |
352692927 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.896518771 |
|
|
Aug 25 11:09:18 AM UTC 24 |
Aug 25 11:09:27 AM UTC 24 |
1455376953 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.1000499444 |
|
|
Aug 25 11:09:13 AM UTC 24 |
Aug 25 11:09:27 AM UTC 24 |
2274326244 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.3912122178 |
|
|
Aug 25 11:09:13 AM UTC 24 |
Aug 25 11:09:27 AM UTC 24 |
1207145310 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.3720906156 |
|
|
Aug 25 11:09:17 AM UTC 24 |
Aug 25 11:09:28 AM UTC 24 |
1124635880 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.2183448967 |
|
|
Aug 25 11:08:13 AM UTC 24 |
Aug 25 11:09:28 AM UTC 24 |
10862063844 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.2718645395 |
|
|
Aug 25 11:09:27 AM UTC 24 |
Aug 25 11:09:29 AM UTC 24 |
43844555 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.2766292087 |
|
|
Aug 25 11:04:44 AM UTC 24 |
Aug 25 11:09:30 AM UTC 24 |
72384957132 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.2993364743 |
|
|
Aug 25 11:09:28 AM UTC 24 |
Aug 25 11:09:31 AM UTC 24 |
18122145 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.2951716308 |
|
|
Aug 25 11:09:28 AM UTC 24 |
Aug 25 11:09:31 AM UTC 24 |
157715500 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1233870191 |
|
|
Aug 25 11:09:20 AM UTC 24 |
Aug 25 11:09:31 AM UTC 24 |
2625639538 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1572747327 |
|
|
Aug 25 11:09:30 AM UTC 24 |
Aug 25 11:09:32 AM UTC 24 |
15217025 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.3906234941 |
|
|
Aug 25 11:08:23 AM UTC 24 |
Aug 25 11:09:32 AM UTC 24 |
12012007662 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.50938888 |
|
|
Aug 25 11:08:58 AM UTC 24 |
Aug 25 11:09:33 AM UTC 24 |
10602094226 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.35982774 |
|
|
Aug 25 11:09:31 AM UTC 24 |
Aug 25 11:09:33 AM UTC 24 |
20700215 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.89254118 |
|
|
Aug 25 11:09:13 AM UTC 24 |
Aug 25 11:09:35 AM UTC 24 |
1610404805 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3037304231 |
|
|
Aug 25 11:09:06 AM UTC 24 |
Aug 25 11:09:36 AM UTC 24 |
5493250306 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.1816264 |
|
|
Aug 25 11:02:50 AM UTC 24 |
Aug 25 11:09:36 AM UTC 24 |
26784040526 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.2110914471 |
|
|
Aug 25 11:08:55 AM UTC 24 |
Aug 25 11:09:37 AM UTC 24 |
2899703093 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.388017000 |
|
|
Aug 25 11:09:34 AM UTC 24 |
Aug 25 11:09:38 AM UTC 24 |
120647509 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.679852168 |
|
|
Aug 25 10:58:15 AM UTC 24 |
Aug 25 11:09:38 AM UTC 24 |
83906050994 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.694104581 |
|
|
Aug 25 11:09:32 AM UTC 24 |
Aug 25 11:09:39 AM UTC 24 |
444353578 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.419431227 |
|
|
Aug 25 11:09:28 AM UTC 24 |
Aug 25 11:09:40 AM UTC 24 |
789502220 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.152681193 |
|
|
Aug 25 11:09:40 AM UTC 24 |
Aug 25 11:09:42 AM UTC 24 |
22127295 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.828300414 |
|
|
Aug 25 11:09:40 AM UTC 24 |
Aug 25 11:09:42 AM UTC 24 |
43628214 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.4111871982 |
|
|
Aug 25 11:09:01 AM UTC 24 |
Aug 25 11:09:43 AM UTC 24 |
25567049642 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.3331343355 |
|
|
Aug 25 11:09:32 AM UTC 24 |
Aug 25 11:09:44 AM UTC 24 |
283318429 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.315077817 |
|
|
Aug 25 11:09:43 AM UTC 24 |
Aug 25 11:09:45 AM UTC 24 |
17677947 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.3686691405 |
|
|
Aug 25 11:08:34 AM UTC 24 |
Aug 25 11:09:46 AM UTC 24 |
129499913038 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.3283580480 |
|
|
Aug 25 11:09:31 AM UTC 24 |
Aug 25 11:09:49 AM UTC 24 |
7401140221 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.4139484022 |
|
|
Aug 25 11:09:44 AM UTC 24 |
Aug 25 11:09:50 AM UTC 24 |
704066780 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.600248140 |
|
|
Aug 25 11:09:19 AM UTC 24 |
Aug 25 11:09:51 AM UTC 24 |
1875579981 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.1370713356 |
|
|
Aug 25 11:09:46 AM UTC 24 |
Aug 25 11:09:51 AM UTC 24 |
102994036 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.3316684749 |
|
|
Aug 25 11:09:04 AM UTC 24 |
Aug 25 11:09:51 AM UTC 24 |
3345146913 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.182343157 |
|
|
Aug 25 11:09:34 AM UTC 24 |
Aug 25 11:09:53 AM UTC 24 |
2702883637 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.1574253959 |
|
|
Aug 25 11:08:37 AM UTC 24 |
Aug 25 11:09:55 AM UTC 24 |
23142342757 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.977010489 |
|
|
Aug 25 11:09:31 AM UTC 24 |
Aug 25 11:09:55 AM UTC 24 |
10765753914 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.4074761921 |
|
|
Aug 25 11:09:52 AM UTC 24 |
Aug 25 11:09:56 AM UTC 24 |
109801299 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.4187204446 |
|
|
Aug 25 11:09:51 AM UTC 24 |
Aug 25 11:09:57 AM UTC 24 |
258202878 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.48167264 |
|
|
Aug 25 11:09:36 AM UTC 24 |
Aug 25 11:09:57 AM UTC 24 |
5682272352 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.2158110815 |
|
|
Aug 25 11:09:29 AM UTC 24 |
Aug 25 11:09:57 AM UTC 24 |
6645186616 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.2506497103 |
|
|
Aug 25 11:09:48 AM UTC 24 |
Aug 25 11:09:58 AM UTC 24 |
385295461 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.546609253 |
|
|
Aug 25 11:09:58 AM UTC 24 |
Aug 25 11:10:00 AM UTC 24 |
48828079 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.2971591225 |
|
|
Aug 25 11:09:58 AM UTC 24 |
Aug 25 11:10:00 AM UTC 24 |
48468038 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2828497130 |
|
|
Aug 25 11:09:54 AM UTC 24 |
Aug 25 11:10:02 AM UTC 24 |
754516753 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1872721608 |
|
|
Aug 25 11:09:44 AM UTC 24 |
Aug 25 11:10:04 AM UTC 24 |
4519451421 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.223733429 |
|
|
Aug 25 11:09:41 AM UTC 24 |
Aug 25 11:10:04 AM UTC 24 |
4038294429 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.1646278628 |
|
|
Aug 25 11:10:02 AM UTC 24 |
Aug 25 11:10:04 AM UTC 24 |
36214336 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.33463305 |
|
|
Aug 25 11:09:07 AM UTC 24 |
Aug 25 11:10:04 AM UTC 24 |
4438210931 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.2075185559 |
|
|
Aug 25 11:10:03 AM UTC 24 |
Aug 25 11:10:07 AM UTC 24 |
56116989 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.1911874501 |
|
|
Aug 25 11:09:50 AM UTC 24 |
Aug 25 11:10:07 AM UTC 24 |
497755477 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.1464886370 |
|
|
Aug 25 11:09:52 AM UTC 24 |
Aug 25 11:10:09 AM UTC 24 |
2658100672 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.376051368 |
|
|
Aug 25 11:10:08 AM UTC 24 |
Aug 25 11:10:13 AM UTC 24 |
1238115551 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.3470185436 |
|
|
Aug 25 11:09:37 AM UTC 24 |
Aug 25 11:10:13 AM UTC 24 |
7527641616 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.3871768375 |
|
|
Aug 25 11:10:07 AM UTC 24 |
Aug 25 11:10:13 AM UTC 24 |
1848708023 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.1576553238 |
|
|
Aug 25 11:02:46 AM UTC 24 |
Aug 25 11:10:15 AM UTC 24 |
26720916699 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.438143717 |
|
|
Aug 25 11:10:05 AM UTC 24 |
Aug 25 11:10:15 AM UTC 24 |
287217765 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.2944129973 |
|
|
Aug 25 11:09:32 AM UTC 24 |
Aug 25 11:10:16 AM UTC 24 |
7079050260 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.2444398937 |
|
|
Aug 25 11:10:16 AM UTC 24 |
Aug 25 11:10:19 AM UTC 24 |
119168998 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.2048167080 |
|
|
Aug 25 11:09:59 AM UTC 24 |
Aug 25 11:10:19 AM UTC 24 |
11732613539 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.248438333 |
|
|
Aug 25 11:10:14 AM UTC 24 |
Aug 25 11:10:20 AM UTC 24 |
264820690 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3820500391 |
|
|
Aug 25 11:10:05 AM UTC 24 |
Aug 25 11:10:22 AM UTC 24 |
10545968548 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.1801811650 |
|
|
Aug 25 11:10:05 AM UTC 24 |
Aug 25 11:10:24 AM UTC 24 |
2969414681 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3029052750 |
|
|
Aug 25 11:10:21 AM UTC 24 |
Aug 25 11:10:24 AM UTC 24 |
170415871 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.1027995595 |
|
|
Aug 25 11:10:21 AM UTC 24 |
Aug 25 11:10:25 AM UTC 24 |
177592378 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.857721741 |
|
|
Aug 25 11:10:23 AM UTC 24 |
Aug 25 11:10:27 AM UTC 24 |
470873784 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.602405016 |
|
|
Aug 25 11:10:23 AM UTC 24 |
Aug 25 11:10:28 AM UTC 24 |
170670989 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.3294221729 |
|
|
Aug 25 11:04:26 AM UTC 24 |
Aug 25 11:10:34 AM UTC 24 |
55916599374 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.3856125970 |
|
|
Aug 25 11:09:10 AM UTC 24 |
Aug 25 11:10:35 AM UTC 24 |
6514622146 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3177239190 |
|
|
Aug 25 11:08:04 AM UTC 24 |
Aug 25 11:10:38 AM UTC 24 |
14248775893 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.282945224 |
|
|
Aug 25 11:09:43 AM UTC 24 |
Aug 25 11:10:39 AM UTC 24 |
49923421797 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.1915064831 |
|
|
Aug 25 11:10:26 AM UTC 24 |
Aug 25 11:10:41 AM UTC 24 |
3109797002 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.3412059893 |
|
|
Aug 25 11:06:38 AM UTC 24 |
Aug 25 11:10:41 AM UTC 24 |
78106548600 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2552582351 |
|
|
Aug 25 11:10:20 AM UTC 24 |
Aug 25 11:10:43 AM UTC 24 |
4218161259 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.166118692 |
|
|
Aug 25 11:10:37 AM UTC 24 |
Aug 25 11:10:43 AM UTC 24 |
526872097 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.4055129904 |
|
|
Aug 25 11:10:02 AM UTC 24 |
Aug 25 11:10:45 AM UTC 24 |
5427270476 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.1496513721 |
|
|
Aug 25 11:10:10 AM UTC 24 |
Aug 25 11:10:46 AM UTC 24 |
4922019962 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.153602981 |
|
|
Aug 25 11:10:44 AM UTC 24 |
Aug 25 11:10:47 AM UTC 24 |
42591699 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.295971412 |
|
|
Aug 25 11:10:44 AM UTC 24 |
Aug 25 11:10:47 AM UTC 24 |
57146454 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.495150148 |
|
|
Aug 25 11:10:25 AM UTC 24 |
Aug 25 11:10:47 AM UTC 24 |
1747594414 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.2278270727 |
|
|
Aug 25 11:10:46 AM UTC 24 |
Aug 25 11:10:50 AM UTC 24 |
739069823 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.2988034235 |
|
|
Aug 25 11:10:48 AM UTC 24 |
Aug 25 11:10:50 AM UTC 24 |
30949761 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3536822115 |
|
|
Aug 25 11:10:28 AM UTC 24 |
Aug 25 11:10:51 AM UTC 24 |
1573060061 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.450221186 |
|
|
Aug 25 11:10:48 AM UTC 24 |
Aug 25 11:10:52 AM UTC 24 |
884015737 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.2456074124 |
|
|
Aug 25 11:10:35 AM UTC 24 |
Aug 25 11:10:58 AM UTC 24 |
3895656522 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.496615506 |
|
|
Aug 25 11:10:21 AM UTC 24 |
Aug 25 11:10:58 AM UTC 24 |
4674768943 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.90483069 |
|
|
Aug 25 11:10:50 AM UTC 24 |
Aug 25 11:10:59 AM UTC 24 |
1433988370 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.3974033514 |
|
|
Aug 25 11:01:20 AM UTC 24 |
Aug 25 11:10:59 AM UTC 24 |
647823386978 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.2426298342 |
|
|
Aug 25 11:09:58 AM UTC 24 |
Aug 25 11:11:00 AM UTC 24 |
2200751206 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.2364480531 |
|
|
Aug 25 11:10:28 AM UTC 24 |
Aug 25 11:11:01 AM UTC 24 |
1337514333 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.1729154332 |
|
|
Aug 25 11:10:51 AM UTC 24 |
Aug 25 11:11:02 AM UTC 24 |
1096139571 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.4074981971 |
|
|
Aug 25 11:10:16 AM UTC 24 |
Aug 25 11:11:02 AM UTC 24 |
15385493335 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.998702410 |
|
|
Aug 25 11:05:41 AM UTC 24 |
Aug 25 11:11:03 AM UTC 24 |
120060844703 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.612029485 |
|
|
Aug 25 11:10:53 AM UTC 24 |
Aug 25 11:11:05 AM UTC 24 |
852967903 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.1787935010 |
|
|
Aug 25 11:11:04 AM UTC 24 |
Aug 25 11:11:06 AM UTC 24 |
45913763 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.3152002628 |
|
|
Aug 25 11:10:48 AM UTC 24 |
Aug 25 11:11:07 AM UTC 24 |
1488305731 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.3749353088 |
|
|
Aug 25 11:11:06 AM UTC 24 |
Aug 25 11:11:08 AM UTC 24 |
17233330 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.19605457 |
|
|
Aug 25 11:10:59 AM UTC 24 |
Aug 25 11:11:10 AM UTC 24 |
1897211083 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3421818320 |
|
|
Aug 25 11:11:10 AM UTC 24 |
Aug 25 11:11:12 AM UTC 24 |
117898711 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.2635614333 |
|
|
Aug 25 11:10:41 AM UTC 24 |
Aug 25 11:11:12 AM UTC 24 |
1372505502 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2549720265 |
|
|
Aug 25 11:11:00 AM UTC 24 |
Aug 25 11:11:13 AM UTC 24 |
796259251 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.2585967389 |
|
|
Aug 25 11:06:13 AM UTC 24 |
Aug 25 11:11:15 AM UTC 24 |
19953552672 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.897263400 |
|
|
Aug 25 11:10:47 AM UTC 24 |
Aug 25 11:11:15 AM UTC 24 |
3620500812 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.778781827 |
|
|
Aug 25 11:11:13 AM UTC 24 |
Aug 25 11:11:18 AM UTC 24 |
142622294 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.3831623004 |
|
|
Aug 25 11:11:14 AM UTC 24 |
Aug 25 11:11:19 AM UTC 24 |
575094018 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.828175611 |
|
|
Aug 25 11:11:11 AM UTC 24 |
Aug 25 11:11:21 AM UTC 24 |
3791586568 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.2698272047 |
|
|
Aug 25 11:10:25 AM UTC 24 |
Aug 25 11:11:23 AM UTC 24 |
25515112330 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.482885042 |
|
|
Aug 25 11:11:07 AM UTC 24 |
Aug 25 11:11:25 AM UTC 24 |
10632178556 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.1017076335 |
|
|
Aug 25 11:11:13 AM UTC 24 |
Aug 25 11:11:27 AM UTC 24 |
1489577792 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.1681247992 |
|
|
Aug 25 11:11:23 AM UTC 24 |
Aug 25 11:11:30 AM UTC 24 |
311444851 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.1321454242 |
|
|
Aug 25 11:11:19 AM UTC 24 |
Aug 25 11:11:30 AM UTC 24 |
443745353 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.1995698643 |
|
|
Aug 25 11:09:17 AM UTC 24 |
Aug 25 11:11:31 AM UTC 24 |
11401717691 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.2298844190 |
|
|
Aug 25 11:11:16 AM UTC 24 |
Aug 25 11:11:33 AM UTC 24 |
2328850413 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.2421439190 |
|
|
Aug 25 11:11:32 AM UTC 24 |
Aug 25 11:11:34 AM UTC 24 |
30174813 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.2959848256 |
|
|
Aug 25 11:11:32 AM UTC 24 |
Aug 25 11:11:34 AM UTC 24 |
185010427 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.3824982877 |
|
|
Aug 25 11:11:21 AM UTC 24 |
Aug 25 11:11:35 AM UTC 24 |
450035834 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.4077754973 |
|
|
Aug 25 11:08:14 AM UTC 24 |
Aug 25 11:11:36 AM UTC 24 |
11514167417 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.304170485 |
|
|
Aug 25 11:10:53 AM UTC 24 |
Aug 25 11:11:36 AM UTC 24 |
3919451072 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.1557334888 |
|
|
Aug 25 11:08:11 AM UTC 24 |
Aug 25 11:11:38 AM UTC 24 |
54630116103 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.3934649954 |
|
|
Aug 25 11:03:03 AM UTC 24 |
Aug 25 11:11:38 AM UTC 24 |
39780278941 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.983054330 |
|
|
Aug 25 11:11:16 AM UTC 24 |
Aug 25 11:11:39 AM UTC 24 |
970569831 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.1170827924 |
|
|
Aug 25 10:58:00 AM UTC 24 |
Aug 25 11:11:40 AM UTC 24 |
111234036995 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.3582061226 |
|
|
Aug 25 11:06:16 AM UTC 24 |
Aug 25 11:11:43 AM UTC 24 |
90937097896 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.2391328796 |
|
|
Aug 25 11:10:05 AM UTC 24 |
Aug 25 11:11:44 AM UTC 24 |
11377738092 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.1345053453 |
|
|
Aug 25 11:10:09 AM UTC 24 |
Aug 25 11:11:45 AM UTC 24 |
18803177418 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.1213975650 |
|
|
Aug 25 11:05:04 AM UTC 24 |
Aug 25 11:11:49 AM UTC 24 |
272202254085 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.3820223150 |
|
|
Aug 25 11:10:59 AM UTC 24 |
Aug 25 11:11:52 AM UTC 24 |
2976924755 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.811086787 |
|
|
Aug 25 11:11:08 AM UTC 24 |
Aug 25 11:11:55 AM UTC 24 |
7987675695 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.2294325465 |
|
|
Aug 25 11:08:10 AM UTC 24 |
Aug 25 11:11:55 AM UTC 24 |
80454938985 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.4111558010 |
|
|
Aug 25 11:08:50 AM UTC 24 |
Aug 25 11:11:56 AM UTC 24 |
16600660837 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.212929231 |
|
|
Aug 25 11:11:28 AM UTC 24 |
Aug 25 11:12:05 AM UTC 24 |
7303567742 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.3638642967 |
|
|
Aug 25 11:09:58 AM UTC 24 |
Aug 25 11:12:06 AM UTC 24 |
6452053052 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2808004465 |
|
|
Aug 25 11:09:34 AM UTC 24 |
Aug 25 11:12:11 AM UTC 24 |
29233443401 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.2027793006 |
|
|
Aug 25 11:11:30 AM UTC 24 |
Aug 25 11:12:12 AM UTC 24 |
5342398821 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.2762442246 |
|
|
Aug 25 11:09:10 AM UTC 24 |
Aug 25 11:12:13 AM UTC 24 |
52603274720 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3770170286 |
|
|
Aug 25 11:11:22 AM UTC 24 |
Aug 25 11:12:14 AM UTC 24 |
1878952181 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.3801464413 |
|
|
Aug 25 11:00:07 AM UTC 24 |
Aug 25 11:12:19 AM UTC 24 |
103319871233 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.979926542 |
|
|
Aug 25 11:10:39 AM UTC 24 |
Aug 25 11:12:20 AM UTC 24 |
15615247472 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.230468197 |
|
|
Aug 25 11:04:00 AM UTC 24 |
Aug 25 11:12:25 AM UTC 24 |
42573380781 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.380934205 |
|
|
Aug 25 11:05:09 AM UTC 24 |
Aug 25 11:12:26 AM UTC 24 |
61780745789 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.2996444998 |
|
|
Aug 25 11:06:36 AM UTC 24 |
Aug 25 11:12:29 AM UTC 24 |
49038074680 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.353261077 |
|
|
Aug 25 11:03:43 AM UTC 24 |
Aug 25 11:12:30 AM UTC 24 |
51473808631 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.337652274 |
|
|
Aug 25 11:09:57 AM UTC 24 |
Aug 25 11:12:31 AM UTC 24 |
13006811527 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.1606087109 |
|
|
Aug 25 10:59:35 AM UTC 24 |
Aug 25 11:12:34 AM UTC 24 |
74718415199 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.2047149147 |
|
|
Aug 25 11:11:03 AM UTC 24 |
Aug 25 11:12:45 AM UTC 24 |
21108037085 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.1268348239 |
|
|
Aug 25 11:10:41 AM UTC 24 |
Aug 25 11:12:46 AM UTC 24 |
52550458286 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.3545301096 |
|
|
Aug 25 11:03:16 AM UTC 24 |
Aug 25 11:12:47 AM UTC 24 |
44132829206 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.3187028712 |
|
|
Aug 25 11:11:26 AM UTC 24 |
Aug 25 11:12:50 AM UTC 24 |
5193525551 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.1697119415 |
|
|
Aug 25 11:01:06 AM UTC 24 |
Aug 25 11:13:20 AM UTC 24 |
219390821271 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.938743367 |
|
|
Aug 25 11:08:15 AM UTC 24 |
Aug 25 11:13:35 AM UTC 24 |
21651491535 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.1047881098 |
|
|
Aug 25 11:07:21 AM UTC 24 |
Aug 25 11:13:36 AM UTC 24 |
65004179118 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2734380065 |
|
|
Aug 25 11:08:27 AM UTC 24 |
Aug 25 11:13:36 AM UTC 24 |
102547187194 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.235261666 |
|
|
Aug 25 11:03:45 AM UTC 24 |
Aug 25 11:13:37 AM UTC 24 |
40536699628 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.787532699 |
|
|
Aug 25 11:09:25 AM UTC 24 |
Aug 25 11:13:38 AM UTC 24 |
96248510032 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.1619567505 |
|
|
Aug 25 11:11:01 AM UTC 24 |
Aug 25 11:13:50 AM UTC 24 |
11596237786 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.1434801978 |
|
|
Aug 25 11:01:35 AM UTC 24 |
Aug 25 11:14:16 AM UTC 24 |
56897196675 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.533430806 |
|
|
Aug 25 10:58:47 AM UTC 24 |
Aug 25 11:14:24 AM UTC 24 |
62440536804 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.2889667630 |
|
|
Aug 25 11:11:00 AM UTC 24 |
Aug 25 11:14:26 AM UTC 24 |
16215061995 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.3887145603 |
|
|
Aug 25 11:08:00 AM UTC 24 |
Aug 25 11:14:29 AM UTC 24 |
142877396499 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.1500560151 |
|
|
Aug 25 11:08:33 AM UTC 24 |
Aug 25 11:14:31 AM UTC 24 |
15638779880 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.4278736316 |
|
|
Aug 25 11:08:47 AM UTC 24 |
Aug 25 11:14:46 AM UTC 24 |
56784565029 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.3998209173 |
|
|
Aug 25 11:08:51 AM UTC 24 |
Aug 25 11:14:52 AM UTC 24 |
106069763282 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.1779531180 |
|
|
Aug 25 11:09:07 AM UTC 24 |
Aug 25 11:14:53 AM UTC 24 |
30602156245 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.3777994837 |
|
|
Aug 25 11:08:50 AM UTC 24 |
Aug 25 11:15:02 AM UTC 24 |
33144711753 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.217867321 |
|
|
Aug 25 11:06:52 AM UTC 24 |
Aug 25 11:15:13 AM UTC 24 |
161813382701 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.3059534046 |
|
|
Aug 25 11:07:41 AM UTC 24 |
Aug 25 11:15:59 AM UTC 24 |
636240598410 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.1255078576 |
|
|
Aug 25 11:09:38 AM UTC 24 |
Aug 25 11:16:10 AM UTC 24 |
26129703776 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.1427536352 |
|
|
Aug 25 11:10:42 AM UTC 24 |
Aug 25 11:16:11 AM UTC 24 |
18378638989 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.4049569247 |
|
|
Aug 25 11:09:56 AM UTC 24 |
Aug 25 11:16:14 AM UTC 24 |
104251424383 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.1407230807 |
|
|
Aug 25 11:08:01 AM UTC 24 |
Aug 25 11:16:23 AM UTC 24 |
31129166401 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.1145795113 |
|
|
Aug 25 11:09:26 AM UTC 24 |
Aug 25 11:18:12 AM UTC 24 |
94009285858 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.1301332927 |
|
|
Aug 25 11:05:25 AM UTC 24 |
Aug 25 11:18:12 AM UTC 24 |
228965273507 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.2884529319 |
|
|
Aug 25 11:05:59 AM UTC 24 |
Aug 25 11:18:25 AM UTC 24 |
184073817911 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.3199073623 |
|
|
Aug 25 11:10:14 AM UTC 24 |
Aug 25 11:18:49 AM UTC 24 |
69271956477 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.3135863201 |
|
|
Aug 25 11:05:41 AM UTC 24 |
Aug 25 11:19:18 AM UTC 24 |
59507624205 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.3151781342 |
|
|
Aug 25 11:02:30 AM UTC 24 |
Aug 25 11:20:10 AM UTC 24 |
325933404005 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.635095034 |
|
|
Aug 25 11:09:40 AM UTC 24 |
Aug 25 11:20:11 AM UTC 24 |
160670034303 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.1882794894 |
|
|
Aug 25 11:07:37 AM UTC 24 |
Aug 25 11:20:24 AM UTC 24 |
66462357151 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.779112353 |
|
|
Aug 25 11:09:25 AM UTC 24 |
Aug 25 11:21:10 AM UTC 24 |
774916047901 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.222545891 |
|
|
Aug 25 11:03:16 AM UTC 24 |
Aug 25 11:21:49 AM UTC 24 |
353482267114 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.120888421 |
|
|
Aug 25 11:10:14 AM UTC 24 |
Aug 25 11:21:50 AM UTC 24 |
236936696907 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.2136619691 |
|
|
Aug 25 11:09:37 AM UTC 24 |
Aug 25 11:22:52 AM UTC 24 |
609563605478 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.109575810 |
|
|
Aug 25 11:11:03 AM UTC 24 |
Aug 25 11:23:20 AM UTC 24 |
155985022545 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.4223742187 |
|
|
Aug 25 11:08:33 AM UTC 24 |
Aug 25 11:24:10 AM UTC 24 |
135546264687 ps |
| T40 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.539939862 |
|
|
Aug 25 11:03:46 AM UTC 24 |
Aug 25 11:24:19 AM UTC 24 |
76350125747 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.3934665641 |
|
|
Aug 25 11:00:07 AM UTC 24 |
Aug 25 11:25:20 AM UTC 24 |
243654200734 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.143634243 |
|
|
Aug 25 11:03:03 AM UTC 24 |
Aug 25 11:25:46 AM UTC 24 |
101204546994 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.2343722437 |
|
|
Aug 25 11:11:03 AM UTC 24 |
Aug 25 11:26:13 AM UTC 24 |
136503644047 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.1124917761 |
|
|
Aug 25 11:04:06 AM UTC 24 |
Aug 25 11:37:50 AM UTC 24 |
145302011810 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3881608798 |
|
|
Aug 25 10:26:10 AM UTC 24 |
Aug 25 10:26:14 AM UTC 24 |
274358520 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2509465799 |
|
|
Aug 25 10:26:15 AM UTC 24 |
Aug 25 10:26:18 AM UTC 24 |
40081290 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2369997803 |
|
|
Aug 25 10:26:16 AM UTC 24 |
Aug 25 10:26:19 AM UTC 24 |
31474507 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.3828065920 |
|
|
Aug 25 10:26:19 AM UTC 24 |
Aug 25 10:26:22 AM UTC 24 |
173803923 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.312520774 |
|
|
Aug 25 10:26:20 AM UTC 24 |
Aug 25 10:26:22 AM UTC 24 |
32601664 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.153466447 |
|
|
Aug 25 10:26:14 AM UTC 24 |
Aug 25 10:26:25 AM UTC 24 |
201559112 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3398540193 |
|
|
Aug 25 10:26:23 AM UTC 24 |
Aug 25 10:26:28 AM UTC 24 |
112044206 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2950654372 |
|
|
Aug 25 10:26:26 AM UTC 24 |
Aug 25 10:26:30 AM UTC 24 |
103997587 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.4287636390 |
|
|
Aug 25 10:26:26 AM UTC 24 |
Aug 25 10:26:32 AM UTC 24 |
497797825 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3768292515 |
|
|
Aug 25 10:26:33 AM UTC 24 |
Aug 25 10:26:36 AM UTC 24 |
30452955 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.575773155 |
|
|
Aug 25 10:26:35 AM UTC 24 |
Aug 25 10:26:38 AM UTC 24 |
20164021 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2922647740 |
|
|
Aug 25 10:26:29 AM UTC 24 |
Aug 25 10:26:38 AM UTC 24 |
131480307 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1540430717 |
|
|
Aug 25 10:26:36 AM UTC 24 |
Aug 25 10:26:40 AM UTC 24 |
146445121 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.697313809 |
|
|
Aug 25 10:26:38 AM UTC 24 |
Aug 25 10:26:41 AM UTC 24 |
60054210 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.385421723 |
|
|
Aug 25 10:26:38 AM UTC 24 |
Aug 25 10:26:42 AM UTC 24 |
75174599 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.652674986 |
|
|
Aug 25 10:26:44 AM UTC 24 |
Aug 25 10:26:48 AM UTC 24 |
64391594 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.4260906410 |
|
|
Aug 25 10:26:49 AM UTC 24 |
Aug 25 10:26:54 AM UTC 24 |
99347681 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1634626595 |
|
|
Aug 25 10:26:48 AM UTC 24 |
Aug 25 10:26:55 AM UTC 24 |
326236984 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2587524493 |
|
|
Aug 25 10:26:23 AM UTC 24 |
Aug 25 10:26:55 AM UTC 24 |
3031651178 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.1246387888 |
|
|
Aug 25 10:26:30 AM UTC 24 |
Aug 25 10:26:55 AM UTC 24 |
1109817333 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.1400502598 |
|
|
Aug 25 10:26:55 AM UTC 24 |
Aug 25 10:26:57 AM UTC 24 |
42680124 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2943916120 |
|
|
Aug 25 10:26:56 AM UTC 24 |
Aug 25 10:26:58 AM UTC 24 |
26988305 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1962410147 |
|
|
Aug 25 10:26:56 AM UTC 24 |
Aug 25 10:26:59 AM UTC 24 |
27264503 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_08_24/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.3328271384 |
|
|
Aug 25 10:26:56 AM UTC 24 |
Aug 25 10:27:01 AM UTC 24 |
132658988 ps |