| T848 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.3381095979 |
|
|
Aug 27 07:52:57 PM UTC 24 |
Aug 27 07:52:59 PM UTC 24 |
21073572 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.3622269149 |
|
|
Aug 27 07:52:58 PM UTC 24 |
Aug 27 07:53:01 PM UTC 24 |
28200398 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.2081878939 |
|
|
Aug 27 07:52:29 PM UTC 24 |
Aug 27 07:53:01 PM UTC 24 |
27357796146 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.126585896 |
|
|
Aug 27 07:50:33 PM UTC 24 |
Aug 27 07:53:02 PM UTC 24 |
51645535777 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.3747739653 |
|
|
Aug 27 07:52:50 PM UTC 24 |
Aug 27 07:53:02 PM UTC 24 |
477253960 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1786962830 |
|
|
Aug 27 07:52:38 PM UTC 24 |
Aug 27 07:53:03 PM UTC 24 |
2775824095 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.34426491 |
|
|
Aug 27 07:53:00 PM UTC 24 |
Aug 27 07:53:04 PM UTC 24 |
291829016 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.3752807658 |
|
|
Aug 27 07:52:30 PM UTC 24 |
Aug 27 07:53:04 PM UTC 24 |
5433966134 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.2409321597 |
|
|
Aug 27 07:52:52 PM UTC 24 |
Aug 27 07:53:05 PM UTC 24 |
1787266853 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.3137786474 |
|
|
Aug 27 07:53:02 PM UTC 24 |
Aug 27 07:53:05 PM UTC 24 |
123192983 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.368879815 |
|
|
Aug 27 07:52:21 PM UTC 24 |
Aug 27 07:53:06 PM UTC 24 |
10627480527 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.2333498321 |
|
|
Aug 27 07:52:45 PM UTC 24 |
Aug 27 07:53:06 PM UTC 24 |
14131490211 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.3209580054 |
|
|
Aug 27 07:51:30 PM UTC 24 |
Aug 27 07:53:08 PM UTC 24 |
46793478328 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.1841564396 |
|
|
Aug 27 07:53:03 PM UTC 24 |
Aug 27 07:53:08 PM UTC 24 |
596279550 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.3897961258 |
|
|
Aug 27 07:52:41 PM UTC 24 |
Aug 27 07:53:09 PM UTC 24 |
3855589792 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.1154075571 |
|
|
Aug 27 07:52:32 PM UTC 24 |
Aug 27 07:53:09 PM UTC 24 |
2408400051 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.1349754965 |
|
|
Aug 27 07:53:02 PM UTC 24 |
Aug 27 07:53:09 PM UTC 24 |
781719142 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.2214844404 |
|
|
Aug 27 07:51:30 PM UTC 24 |
Aug 27 07:53:11 PM UTC 24 |
35545711263 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.1009488561 |
|
|
Aug 27 07:53:04 PM UTC 24 |
Aug 27 07:53:11 PM UTC 24 |
5040401112 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.338579677 |
|
|
Aug 27 07:49:47 PM UTC 24 |
Aug 27 07:53:11 PM UTC 24 |
20916044139 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.1169078056 |
|
|
Aug 27 07:52:09 PM UTC 24 |
Aug 27 07:53:12 PM UTC 24 |
9400018341 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.1115038729 |
|
|
Aug 27 07:53:07 PM UTC 24 |
Aug 27 07:53:13 PM UTC 24 |
830814966 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.1269592644 |
|
|
Aug 27 07:53:05 PM UTC 24 |
Aug 27 07:53:13 PM UTC 24 |
366778137 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.2821510690 |
|
|
Aug 27 07:53:12 PM UTC 24 |
Aug 27 07:53:14 PM UTC 24 |
14902895 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.2778946852 |
|
|
Aug 27 07:53:12 PM UTC 24 |
Aug 27 07:53:14 PM UTC 24 |
39832329 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.1271356262 |
|
|
Aug 27 07:53:12 PM UTC 24 |
Aug 27 07:53:14 PM UTC 24 |
17476855 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.2917688533 |
|
|
Aug 27 07:52:30 PM UTC 24 |
Aug 27 07:53:14 PM UTC 24 |
47065093698 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.744102171 |
|
|
Aug 27 07:53:05 PM UTC 24 |
Aug 27 07:53:14 PM UTC 24 |
3896592635 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3291039146 |
|
|
Aug 27 07:53:08 PM UTC 24 |
Aug 27 07:53:15 PM UTC 24 |
842533043 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.968661413 |
|
|
Aug 27 07:53:06 PM UTC 24 |
Aug 27 07:53:16 PM UTC 24 |
421647056 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.4027821859 |
|
|
Aug 27 07:53:14 PM UTC 24 |
Aug 27 07:53:16 PM UTC 24 |
93391601 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1667060051 |
|
|
Aug 27 07:52:40 PM UTC 24 |
Aug 27 07:53:17 PM UTC 24 |
7329467186 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.3099581198 |
|
|
Aug 27 07:53:14 PM UTC 24 |
Aug 27 07:53:17 PM UTC 24 |
93425305 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.862983833 |
|
|
Aug 27 07:53:15 PM UTC 24 |
Aug 27 07:53:19 PM UTC 24 |
643917818 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.1673725800 |
|
|
Aug 27 07:53:17 PM UTC 24 |
Aug 27 07:53:20 PM UTC 24 |
60022221 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.2963941537 |
|
|
Aug 27 07:53:14 PM UTC 24 |
Aug 27 07:53:20 PM UTC 24 |
368605273 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.3342850983 |
|
|
Aug 27 07:53:15 PM UTC 24 |
Aug 27 07:53:21 PM UTC 24 |
84955802 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.729422023 |
|
|
Aug 27 07:51:13 PM UTC 24 |
Aug 27 07:53:21 PM UTC 24 |
43049752782 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.3458769009 |
|
|
Aug 27 07:53:14 PM UTC 24 |
Aug 27 07:53:22 PM UTC 24 |
397379911 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.1174582400 |
|
|
Aug 27 07:52:36 PM UTC 24 |
Aug 27 07:53:22 PM UTC 24 |
2032428223 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2362753159 |
|
|
Aug 27 07:53:18 PM UTC 24 |
Aug 27 07:53:23 PM UTC 24 |
133058303 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.919365243 |
|
|
Aug 27 07:53:21 PM UTC 24 |
Aug 27 07:53:23 PM UTC 24 |
13839286 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.1062636554 |
|
|
Aug 27 07:53:21 PM UTC 24 |
Aug 27 07:53:24 PM UTC 24 |
14811127 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.727185565 |
|
|
Aug 27 07:53:13 PM UTC 24 |
Aug 27 07:53:25 PM UTC 24 |
2977858123 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.3211894768 |
|
|
Aug 27 07:53:24 PM UTC 24 |
Aug 27 07:53:26 PM UTC 24 |
97057205 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.3118860117 |
|
|
Aug 27 07:53:24 PM UTC 24 |
Aug 27 07:53:27 PM UTC 24 |
748495284 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.483065892 |
|
|
Aug 27 07:53:25 PM UTC 24 |
Aug 27 07:53:27 PM UTC 24 |
136848477 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.377607479 |
|
|
Aug 27 07:53:06 PM UTC 24 |
Aug 27 07:53:28 PM UTC 24 |
2233839033 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.3682879003 |
|
|
Aug 27 07:53:18 PM UTC 24 |
Aug 27 07:53:29 PM UTC 24 |
656049948 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.753509061 |
|
|
Aug 27 07:53:16 PM UTC 24 |
Aug 27 07:53:30 PM UTC 24 |
1044021832 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1467780883 |
|
|
Aug 27 07:53:30 PM UTC 24 |
Aug 27 07:53:33 PM UTC 24 |
58762456 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.4097504112 |
|
|
Aug 27 07:53:29 PM UTC 24 |
Aug 27 07:53:34 PM UTC 24 |
274356658 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.4290483667 |
|
|
Aug 27 07:53:09 PM UTC 24 |
Aug 27 07:53:35 PM UTC 24 |
2608569188 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.2543421717 |
|
|
Aug 27 07:53:27 PM UTC 24 |
Aug 27 07:53:36 PM UTC 24 |
2076626280 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.515594768 |
|
|
Aug 27 07:50:35 PM UTC 24 |
Aug 27 07:53:40 PM UTC 24 |
13899818462 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.2986840942 |
|
|
Aug 27 07:53:34 PM UTC 24 |
Aug 27 07:53:40 PM UTC 24 |
208648022 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.759463550 |
|
|
Aug 27 07:53:25 PM UTC 24 |
Aug 27 07:53:42 PM UTC 24 |
6289427988 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2545586378 |
|
|
Aug 27 07:53:28 PM UTC 24 |
Aug 27 07:53:42 PM UTC 24 |
4349848557 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.1023318300 |
|
|
Aug 27 07:53:41 PM UTC 24 |
Aug 27 07:53:43 PM UTC 24 |
31689964 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.922113869 |
|
|
Aug 27 07:53:41 PM UTC 24 |
Aug 27 07:53:43 PM UTC 24 |
88761243 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.4145357103 |
|
|
Aug 27 07:53:28 PM UTC 24 |
Aug 27 07:53:44 PM UTC 24 |
2044967166 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.2877799578 |
|
|
Aug 27 07:53:42 PM UTC 24 |
Aug 27 07:53:44 PM UTC 24 |
40701736 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.3137930868 |
|
|
Aug 27 07:53:28 PM UTC 24 |
Aug 27 07:53:45 PM UTC 24 |
3314339390 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.3639376083 |
|
|
Aug 27 07:53:43 PM UTC 24 |
Aug 27 07:53:45 PM UTC 24 |
39171554 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.2504648631 |
|
|
Aug 27 07:53:24 PM UTC 24 |
Aug 27 07:53:45 PM UTC 24 |
9301508628 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.1560911814 |
|
|
Aug 27 07:51:41 PM UTC 24 |
Aug 27 07:53:46 PM UTC 24 |
13529274356 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.3925902789 |
|
|
Aug 27 07:53:44 PM UTC 24 |
Aug 27 07:53:46 PM UTC 24 |
29939274 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.1691356714 |
|
|
Aug 27 07:53:44 PM UTC 24 |
Aug 27 07:53:48 PM UTC 24 |
229616023 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.1708836876 |
|
|
Aug 27 07:53:44 PM UTC 24 |
Aug 27 07:53:52 PM UTC 24 |
677422447 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.3395959443 |
|
|
Aug 27 07:53:46 PM UTC 24 |
Aug 27 07:53:52 PM UTC 24 |
2528535649 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.3485467336 |
|
|
Aug 27 07:53:01 PM UTC 24 |
Aug 27 07:53:55 PM UTC 24 |
6393522031 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.2698818061 |
|
|
Aug 27 07:53:26 PM UTC 24 |
Aug 27 07:53:56 PM UTC 24 |
8170266194 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.2969743254 |
|
|
Aug 27 07:53:46 PM UTC 24 |
Aug 27 07:53:56 PM UTC 24 |
9741920038 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.3530920467 |
|
|
Aug 27 07:50:32 PM UTC 24 |
Aug 27 07:53:57 PM UTC 24 |
108342754534 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.492552175 |
|
|
Aug 27 07:53:47 PM UTC 24 |
Aug 27 07:53:57 PM UTC 24 |
232654105 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.413692018 |
|
|
Aug 27 07:53:55 PM UTC 24 |
Aug 27 07:53:57 PM UTC 24 |
113700509 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.1524657857 |
|
|
Aug 27 07:53:58 PM UTC 24 |
Aug 27 07:54:00 PM UTC 24 |
35870304 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.351025405 |
|
|
Aug 27 07:53:59 PM UTC 24 |
Aug 27 07:54:01 PM UTC 24 |
16814452 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.477805857 |
|
|
Aug 27 07:53:53 PM UTC 24 |
Aug 27 07:54:03 PM UTC 24 |
13886874577 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1722421408 |
|
|
Aug 27 07:52:51 PM UTC 24 |
Aug 27 07:54:03 PM UTC 24 |
10473979449 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.2766113480 |
|
|
Aug 27 07:51:49 PM UTC 24 |
Aug 27 07:54:05 PM UTC 24 |
53855852520 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2183527852 |
|
|
Aug 27 07:54:04 PM UTC 24 |
Aug 27 07:54:06 PM UTC 24 |
97521741 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.4109337142 |
|
|
Aug 27 07:53:46 PM UTC 24 |
Aug 27 07:54:07 PM UTC 24 |
3134952172 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.220648811 |
|
|
Aug 27 07:54:04 PM UTC 24 |
Aug 27 07:54:07 PM UTC 24 |
587302703 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.2391270105 |
|
|
Aug 27 07:50:52 PM UTC 24 |
Aug 27 07:54:08 PM UTC 24 |
43270680651 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.241963484 |
|
|
Aug 27 07:53:18 PM UTC 24 |
Aug 27 07:54:09 PM UTC 24 |
22507204771 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.1110624837 |
|
|
Aug 27 07:45:20 PM UTC 24 |
Aug 27 07:54:10 PM UTC 24 |
83754681722 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.400810 |
|
|
Aug 27 07:53:47 PM UTC 24 |
Aug 27 07:54:11 PM UTC 24 |
1103228542 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.4041239904 |
|
|
Aug 27 07:52:56 PM UTC 24 |
Aug 27 07:54:13 PM UTC 24 |
98948957467 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.2271488837 |
|
|
Aug 27 07:51:15 PM UTC 24 |
Aug 27 07:54:13 PM UTC 24 |
45719245977 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.2673121890 |
|
|
Aug 27 07:54:07 PM UTC 24 |
Aug 27 07:54:15 PM UTC 24 |
3036430200 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.1286486737 |
|
|
Aug 27 07:51:55 PM UTC 24 |
Aug 27 07:54:16 PM UTC 24 |
20923303970 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.3209215929 |
|
|
Aug 27 07:53:48 PM UTC 24 |
Aug 27 07:54:16 PM UTC 24 |
15626774375 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.3688311986 |
|
|
Aug 27 07:53:09 PM UTC 24 |
Aug 27 07:54:17 PM UTC 24 |
19573503927 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.977629128 |
|
|
Aug 27 07:53:47 PM UTC 24 |
Aug 27 07:54:20 PM UTC 24 |
2228869143 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2360902498 |
|
|
Aug 27 07:54:14 PM UTC 24 |
Aug 27 07:54:21 PM UTC 24 |
506653245 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.866758082 |
|
|
Aug 27 07:54:11 PM UTC 24 |
Aug 27 07:54:22 PM UTC 24 |
1794153220 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.3452731157 |
|
|
Aug 27 07:54:20 PM UTC 24 |
Aug 27 07:54:23 PM UTC 24 |
13068941 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.2343763196 |
|
|
Aug 27 07:54:09 PM UTC 24 |
Aug 27 07:54:23 PM UTC 24 |
8800680138 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.370646115 |
|
|
Aug 27 07:54:22 PM UTC 24 |
Aug 27 07:54:24 PM UTC 24 |
17556426 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.728685674 |
|
|
Aug 27 07:54:08 PM UTC 24 |
Aug 27 07:54:25 PM UTC 24 |
986991733 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.3426347770 |
|
|
Aug 27 07:54:23 PM UTC 24 |
Aug 27 07:54:25 PM UTC 24 |
21301149 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.2060170729 |
|
|
Aug 27 07:54:11 PM UTC 24 |
Aug 27 07:54:25 PM UTC 24 |
529098705 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.419496612 |
|
|
Aug 27 07:54:01 PM UTC 24 |
Aug 27 07:54:26 PM UTC 24 |
9973694057 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.4037060115 |
|
|
Aug 27 07:54:02 PM UTC 24 |
Aug 27 07:54:26 PM UTC 24 |
4921448204 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.4026766807 |
|
|
Aug 27 07:54:23 PM UTC 24 |
Aug 27 07:54:27 PM UTC 24 |
267230356 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3725303178 |
|
|
Aug 27 07:54:24 PM UTC 24 |
Aug 27 07:54:29 PM UTC 24 |
69281119 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1759863824 |
|
|
Aug 27 07:54:06 PM UTC 24 |
Aug 27 07:54:29 PM UTC 24 |
7461381324 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.4080269271 |
|
|
Aug 27 07:54:25 PM UTC 24 |
Aug 27 07:54:29 PM UTC 24 |
374957487 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.1435744232 |
|
|
Aug 27 07:54:26 PM UTC 24 |
Aug 27 07:54:31 PM UTC 24 |
146796696 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.2747251421 |
|
|
Aug 27 07:51:56 PM UTC 24 |
Aug 27 07:54:32 PM UTC 24 |
31530140442 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.3200707861 |
|
|
Aug 27 07:54:33 PM UTC 24 |
Aug 27 07:54:36 PM UTC 24 |
41088304 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.219010004 |
|
|
Aug 27 07:54:22 PM UTC 24 |
Aug 27 07:54:38 PM UTC 24 |
5159972518 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.3226365219 |
|
|
Aug 27 07:54:36 PM UTC 24 |
Aug 27 07:54:38 PM UTC 24 |
59260214 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2109471502 |
|
|
Aug 27 07:53:07 PM UTC 24 |
Aug 27 07:54:39 PM UTC 24 |
6799151102 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.3941984461 |
|
|
Aug 27 07:54:28 PM UTC 24 |
Aug 27 07:54:39 PM UTC 24 |
584281568 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.3798371133 |
|
|
Aug 27 07:52:57 PM UTC 24 |
Aug 27 07:54:40 PM UTC 24 |
2975901516 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.204412789 |
|
|
Aug 27 07:49:05 PM UTC 24 |
Aug 27 07:54:41 PM UTC 24 |
122877580853 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.1979828186 |
|
|
Aug 27 07:53:37 PM UTC 24 |
Aug 27 07:54:42 PM UTC 24 |
4942458216 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3658060267 |
|
|
Aug 27 07:54:40 PM UTC 24 |
Aug 27 07:54:42 PM UTC 24 |
68179845 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.3940120312 |
|
|
Aug 27 07:54:40 PM UTC 24 |
Aug 27 07:54:43 PM UTC 24 |
109282943 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.127076491 |
|
|
Aug 27 07:54:27 PM UTC 24 |
Aug 27 07:54:46 PM UTC 24 |
628095278 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.909776540 |
|
|
Aug 27 07:54:43 PM UTC 24 |
Aug 27 07:54:47 PM UTC 24 |
114197142 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.1757687979 |
|
|
Aug 27 07:54:26 PM UTC 24 |
Aug 27 07:54:50 PM UTC 24 |
3745344230 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.659230202 |
|
|
Aug 27 07:53:21 PM UTC 24 |
Aug 27 07:54:52 PM UTC 24 |
14376811295 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.604984205 |
|
|
Aug 27 07:54:43 PM UTC 24 |
Aug 27 07:54:52 PM UTC 24 |
1795460231 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.207237037 |
|
|
Aug 27 07:54:47 PM UTC 24 |
Aug 27 07:54:53 PM UTC 24 |
443799416 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.1144102181 |
|
|
Aug 27 07:54:38 PM UTC 24 |
Aug 27 07:54:53 PM UTC 24 |
2669342150 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.124472852 |
|
|
Aug 27 07:54:47 PM UTC 24 |
Aug 27 07:54:54 PM UTC 24 |
128871071 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.543806126 |
|
|
Aug 27 07:54:44 PM UTC 24 |
Aug 27 07:54:56 PM UTC 24 |
6172730929 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.28211958 |
|
|
Aug 27 07:54:57 PM UTC 24 |
Aug 27 07:54:59 PM UTC 24 |
15447984 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.1514394479 |
|
|
Aug 27 07:54:22 PM UTC 24 |
Aug 27 07:54:59 PM UTC 24 |
13398817906 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.22839017 |
|
|
Aug 27 07:54:41 PM UTC 24 |
Aug 27 07:55:00 PM UTC 24 |
9764418910 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.2198424024 |
|
|
Aug 27 07:55:00 PM UTC 24 |
Aug 27 07:55:02 PM UTC 24 |
15201866 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.2741740912 |
|
|
Aug 27 07:52:38 PM UTC 24 |
Aug 27 07:55:05 PM UTC 24 |
36941640573 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.3947459510 |
|
|
Aug 27 07:54:52 PM UTC 24 |
Aug 27 07:55:05 PM UTC 24 |
3889658174 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.1014890150 |
|
|
Aug 27 07:55:03 PM UTC 24 |
Aug 27 07:55:05 PM UTC 24 |
172270172 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.3537587227 |
|
|
Aug 27 07:49:20 PM UTC 24 |
Aug 27 07:55:07 PM UTC 24 |
166802373410 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.357738615 |
|
|
Aug 27 07:55:05 PM UTC 24 |
Aug 27 07:55:08 PM UTC 24 |
84058929 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.1020991275 |
|
|
Aug 27 07:53:11 PM UTC 24 |
Aug 27 07:55:09 PM UTC 24 |
10312030349 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.1449392588 |
|
|
Aug 27 07:54:39 PM UTC 24 |
Aug 27 07:55:10 PM UTC 24 |
28523757398 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.183484582 |
|
|
Aug 27 07:54:30 PM UTC 24 |
Aug 27 07:55:11 PM UTC 24 |
2194567334 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.3851182121 |
|
|
Aug 27 07:55:07 PM UTC 24 |
Aug 27 07:55:15 PM UTC 24 |
395954743 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.452370784 |
|
|
Aug 27 07:55:00 PM UTC 24 |
Aug 27 07:55:15 PM UTC 24 |
2636956892 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.3350002159 |
|
|
Aug 27 07:55:01 PM UTC 24 |
Aug 27 07:55:15 PM UTC 24 |
2611373343 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.1804096503 |
|
|
Aug 27 07:54:13 PM UTC 24 |
Aug 27 07:55:16 PM UTC 24 |
4818960166 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.2552209543 |
|
|
Aug 27 07:53:35 PM UTC 24 |
Aug 27 07:55:17 PM UTC 24 |
7150829725 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.1238091753 |
|
|
Aug 27 07:55:15 PM UTC 24 |
Aug 27 07:55:17 PM UTC 24 |
23660821 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.820320332 |
|
|
Aug 27 07:54:14 PM UTC 24 |
Aug 27 07:55:19 PM UTC 24 |
37340516308 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.2232145971 |
|
|
Aug 27 07:54:26 PM UTC 24 |
Aug 27 07:55:20 PM UTC 24 |
32647339519 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.1817994292 |
|
|
Aug 27 07:55:09 PM UTC 24 |
Aug 27 07:55:20 PM UTC 24 |
261850206 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.3884089504 |
|
|
Aug 27 07:55:11 PM UTC 24 |
Aug 27 07:55:20 PM UTC 24 |
1479028550 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.875407721 |
|
|
Aug 27 07:55:05 PM UTC 24 |
Aug 27 07:55:20 PM UTC 24 |
1375544957 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.3697673023 |
|
|
Aug 27 07:55:15 PM UTC 24 |
Aug 27 07:55:21 PM UTC 24 |
108822703 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.2350006406 |
|
|
Aug 27 07:55:20 PM UTC 24 |
Aug 27 07:55:22 PM UTC 24 |
13312035 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.710643538 |
|
|
Aug 27 07:55:08 PM UTC 24 |
Aug 27 07:55:22 PM UTC 24 |
1002297284 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.3117854389 |
|
|
Aug 27 07:49:49 PM UTC 24 |
Aug 27 07:55:23 PM UTC 24 |
73785899425 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.383718379 |
|
|
Aug 27 07:55:12 PM UTC 24 |
Aug 27 07:55:23 PM UTC 24 |
971628354 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.204796167 |
|
|
Aug 27 07:55:21 PM UTC 24 |
Aug 27 07:55:23 PM UTC 24 |
58571331 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2985019911 |
|
|
Aug 27 07:55:21 PM UTC 24 |
Aug 27 07:55:23 PM UTC 24 |
146302400 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.1127006325 |
|
|
Aug 27 07:54:30 PM UTC 24 |
Aug 27 07:55:25 PM UTC 24 |
3587083782 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.602631797 |
|
|
Aug 27 07:52:07 PM UTC 24 |
Aug 27 07:55:26 PM UTC 24 |
22556261587 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.3664458084 |
|
|
Aug 27 07:55:22 PM UTC 24 |
Aug 27 07:55:28 PM UTC 24 |
352211614 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.1241951425 |
|
|
Aug 27 07:53:18 PM UTC 24 |
Aug 27 07:55:28 PM UTC 24 |
14712549194 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.3188815252 |
|
|
Aug 27 07:55:23 PM UTC 24 |
Aug 27 07:55:29 PM UTC 24 |
124302695 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.2903350870 |
|
|
Aug 27 07:55:26 PM UTC 24 |
Aug 27 07:55:30 PM UTC 24 |
124044729 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.962995974 |
|
|
Aug 27 07:55:25 PM UTC 24 |
Aug 27 07:55:31 PM UTC 24 |
158032169 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.936292397 |
|
|
Aug 27 07:55:22 PM UTC 24 |
Aug 27 07:55:34 PM UTC 24 |
7546137229 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.2545565053 |
|
|
Aug 27 07:55:33 PM UTC 24 |
Aug 27 07:55:35 PM UTC 24 |
14584571 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.2546006190 |
|
|
Aug 27 07:55:33 PM UTC 24 |
Aug 27 07:55:35 PM UTC 24 |
83122711 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.2734482593 |
|
|
Aug 27 07:55:23 PM UTC 24 |
Aug 27 07:55:37 PM UTC 24 |
3388425213 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.612043727 |
|
|
Aug 27 07:53:58 PM UTC 24 |
Aug 27 07:55:39 PM UTC 24 |
11242918256 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.653281296 |
|
|
Aug 27 07:55:29 PM UTC 24 |
Aug 27 07:55:42 PM UTC 24 |
1395930147 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.642245402 |
|
|
Aug 27 07:55:23 PM UTC 24 |
Aug 27 07:55:43 PM UTC 24 |
3673372476 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.4132017029 |
|
|
Aug 27 07:55:21 PM UTC 24 |
Aug 27 07:55:44 PM UTC 24 |
3242605938 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3574239328 |
|
|
Aug 27 07:54:54 PM UTC 24 |
Aug 27 07:55:45 PM UTC 24 |
23152064818 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.588014170 |
|
|
Aug 27 07:54:15 PM UTC 24 |
Aug 27 07:55:46 PM UTC 24 |
5819477580 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.943462518 |
|
|
Aug 27 07:45:50 PM UTC 24 |
Aug 27 07:55:47 PM UTC 24 |
58372101880 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.2205898170 |
|
|
Aug 27 07:55:23 PM UTC 24 |
Aug 27 07:55:47 PM UTC 24 |
17172094276 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.3202145502 |
|
|
Aug 27 07:52:25 PM UTC 24 |
Aug 27 07:55:48 PM UTC 24 |
19531467168 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.2000162634 |
|
|
Aug 27 07:54:43 PM UTC 24 |
Aug 27 07:55:50 PM UTC 24 |
6628611894 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3229171559 |
|
|
Aug 27 07:54:28 PM UTC 24 |
Aug 27 07:55:50 PM UTC 24 |
6692833993 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.3925433143 |
|
|
Aug 27 07:55:10 PM UTC 24 |
Aug 27 07:55:51 PM UTC 24 |
46676107974 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.4234575352 |
|
|
Aug 27 07:53:36 PM UTC 24 |
Aug 27 07:55:52 PM UTC 24 |
14892039663 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.742181998 |
|
|
Aug 27 07:53:57 PM UTC 24 |
Aug 27 07:55:59 PM UTC 24 |
15578008430 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.2521800647 |
|
|
Aug 27 07:55:21 PM UTC 24 |
Aug 27 07:56:05 PM UTC 24 |
10752564950 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.4051901359 |
|
|
Aug 27 07:52:55 PM UTC 24 |
Aug 27 07:56:06 PM UTC 24 |
17438488631 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.1975601135 |
|
|
Aug 27 07:54:54 PM UTC 24 |
Aug 27 07:56:09 PM UTC 24 |
10715372661 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.2854802757 |
|
|
Aug 27 07:55:30 PM UTC 24 |
Aug 27 07:56:11 PM UTC 24 |
3346794588 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.1465306005 |
|
|
Aug 27 07:54:54 PM UTC 24 |
Aug 27 07:56:18 PM UTC 24 |
18155883952 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.534185539 |
|
|
Aug 27 07:54:16 PM UTC 24 |
Aug 27 07:56:22 PM UTC 24 |
34491991563 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.1076265711 |
|
|
Aug 27 07:50:16 PM UTC 24 |
Aug 27 07:56:35 PM UTC 24 |
57521387639 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.2553759621 |
|
|
Aug 27 07:55:27 PM UTC 24 |
Aug 27 07:56:40 PM UTC 24 |
5461868855 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1156560076 |
|
|
Aug 27 07:55:31 PM UTC 24 |
Aug 27 07:56:52 PM UTC 24 |
7998316363 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.4065999822 |
|
|
Aug 27 07:55:17 PM UTC 24 |
Aug 27 07:56:58 PM UTC 24 |
23730234977 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.4055895346 |
|
|
Aug 27 07:54:17 PM UTC 24 |
Aug 27 07:57:01 PM UTC 24 |
13101299528 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.2732823414 |
|
|
Aug 27 07:52:26 PM UTC 24 |
Aug 27 07:57:01 PM UTC 24 |
30963961737 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.3246274967 |
|
|
Aug 27 07:53:09 PM UTC 24 |
Aug 27 07:57:04 PM UTC 24 |
71760684072 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.653967977 |
|
|
Aug 27 07:54:50 PM UTC 24 |
Aug 27 07:57:05 PM UTC 24 |
9100599647 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.277246769 |
|
|
Aug 27 07:52:05 PM UTC 24 |
Aug 27 07:57:05 PM UTC 24 |
98074961823 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.3055479628 |
|
|
Aug 27 07:53:52 PM UTC 24 |
Aug 27 07:57:15 PM UTC 24 |
69942106557 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.1335190701 |
|
|
Aug 27 07:52:07 PM UTC 24 |
Aug 27 07:57:26 PM UTC 24 |
43690075529 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.3281821225 |
|
|
Aug 27 07:54:55 PM UTC 24 |
Aug 27 07:57:27 PM UTC 24 |
36432242659 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.3442765478 |
|
|
Aug 27 07:55:16 PM UTC 24 |
Aug 27 07:57:30 PM UTC 24 |
26150631645 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.210041554 |
|
|
Aug 27 07:52:10 PM UTC 24 |
Aug 27 07:57:35 PM UTC 24 |
29387379486 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.3465820944 |
|
|
Aug 27 07:51:07 PM UTC 24 |
Aug 27 07:57:38 PM UTC 24 |
58955655853 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.3319702398 |
|
|
Aug 27 07:45:33 PM UTC 24 |
Aug 27 07:57:43 PM UTC 24 |
69299927462 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.676634100 |
|
|
Aug 27 07:53:20 PM UTC 24 |
Aug 27 07:57:49 PM UTC 24 |
27785569041 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.2480762237 |
|
|
Aug 27 07:53:21 PM UTC 24 |
Aug 27 07:57:56 PM UTC 24 |
199490514994 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.3909835238 |
|
|
Aug 27 07:53:57 PM UTC 24 |
Aug 27 07:58:08 PM UTC 24 |
215994058020 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.1859727308 |
|
|
Aug 27 07:49:29 PM UTC 24 |
Aug 27 07:58:13 PM UTC 24 |
181408321355 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.3760353717 |
|
|
Aug 27 07:51:30 PM UTC 24 |
Aug 27 07:58:15 PM UTC 24 |
46428181603 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.3369892533 |
|
|
Aug 27 07:48:25 PM UTC 24 |
Aug 27 07:58:47 PM UTC 24 |
53310847457 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.2292615319 |
|
|
Aug 27 07:52:37 PM UTC 24 |
Aug 27 07:59:44 PM UTC 24 |
45428757224 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.1843887225 |
|
|
Aug 27 07:54:32 PM UTC 24 |
Aug 27 07:59:52 PM UTC 24 |
51116991061 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.1775536664 |
|
|
Aug 27 07:52:55 PM UTC 24 |
Aug 27 08:00:00 PM UTC 24 |
195237461446 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.2743003090 |
|
|
Aug 27 07:54:30 PM UTC 24 |
Aug 27 08:00:03 PM UTC 24 |
28857354534 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.4272462815 |
|
|
Aug 27 07:42:31 PM UTC 24 |
Aug 27 08:00:09 PM UTC 24 |
468989271008 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.1550798068 |
|
|
Aug 27 07:55:19 PM UTC 24 |
Aug 27 08:00:23 PM UTC 24 |
32192126394 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.2348885225 |
|
|
Aug 27 07:44:09 PM UTC 24 |
Aug 27 08:00:33 PM UTC 24 |
97574333012 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.2769339721 |
|
|
Aug 27 07:46:23 PM UTC 24 |
Aug 27 08:00:55 PM UTC 24 |
138476651946 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.3808145920 |
|
|
Aug 27 07:55:29 PM UTC 24 |
Aug 27 08:01:11 PM UTC 24 |
43444342336 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.3489995107 |
|
|
Aug 27 07:51:11 PM UTC 24 |
Aug 27 08:03:06 PM UTC 24 |
279590754854 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.3643805859 |
|
|
Aug 27 07:47:48 PM UTC 24 |
Aug 27 08:05:15 PM UTC 24 |
103504913935 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.1247318128 |
|
|
Aug 27 07:55:19 PM UTC 24 |
Aug 27 08:10:19 PM UTC 24 |
87403279695 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2172152146 |
|
|
Aug 27 07:55:36 PM UTC 24 |
Aug 27 07:55:38 PM UTC 24 |
31736863 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.1638746567 |
|
|
Aug 27 07:55:35 PM UTC 24 |
Aug 27 07:55:39 PM UTC 24 |
376935910 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2011209482 |
|
|
Aug 27 07:55:38 PM UTC 24 |
Aug 27 07:55:40 PM UTC 24 |
12065297 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1060604258 |
|
|
Aug 27 07:55:39 PM UTC 24 |
Aug 27 07:55:42 PM UTC 24 |
133526368 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.4029676874 |
|
|
Aug 27 07:55:39 PM UTC 24 |
Aug 27 07:55:42 PM UTC 24 |
19492051 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3685983555 |
|
|
Aug 27 07:55:40 PM UTC 24 |
Aug 27 07:55:43 PM UTC 24 |
128712708 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3591208523 |
|
|
Aug 27 07:55:36 PM UTC 24 |
Aug 27 07:55:45 PM UTC 24 |
394543211 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.745736669 |
|
|
Aug 27 07:55:44 PM UTC 24 |
Aug 27 07:55:46 PM UTC 24 |
13774494 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2343792051 |
|
|
Aug 27 07:55:43 PM UTC 24 |
Aug 27 07:55:47 PM UTC 24 |
82989605 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2295227013 |
|
|
Aug 27 07:55:45 PM UTC 24 |
Aug 27 07:55:47 PM UTC 24 |
25552792 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1457526333 |
|
|
Aug 27 07:55:46 PM UTC 24 |
Aug 27 07:55:49 PM UTC 24 |
82652598 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.2709067506 |
|
|
Aug 27 07:55:43 PM UTC 24 |
Aug 27 07:55:49 PM UTC 24 |
502987289 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.626588526 |
|
|
Aug 27 07:55:43 PM UTC 24 |
Aug 27 07:55:50 PM UTC 24 |
430707678 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.523272910 |
|
|
Aug 27 07:55:46 PM UTC 24 |
Aug 27 07:55:51 PM UTC 24 |
360176672 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.1838806425 |
|
|
Aug 27 07:55:48 PM UTC 24 |
Aug 27 07:55:51 PM UTC 24 |
62480125 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.2323670987 |
|
|
Aug 27 07:55:48 PM UTC 24 |
Aug 27 07:55:51 PM UTC 24 |
25980079 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2597285218 |
|
|
Aug 27 07:55:48 PM UTC 24 |
Aug 27 07:55:52 PM UTC 24 |
293033969 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.4143038226 |
|
|
Aug 27 07:55:48 PM UTC 24 |
Aug 27 07:55:52 PM UTC 24 |
120535630 ps |
| T1038 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.1460371165 |
|
|
Aug 27 07:55:50 PM UTC 24 |
Aug 27 07:55:52 PM UTC 24 |
12432843 ps |
| T1039 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.675341457 |
|
|
Aug 27 07:55:50 PM UTC 24 |
Aug 27 07:55:52 PM UTC 24 |
135416321 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.4170955631 |
|
|
Aug 27 07:55:50 PM UTC 24 |
Aug 27 07:55:54 PM UTC 24 |
168706306 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.774267092 |
|
|
Aug 27 07:55:52 PM UTC 24 |
Aug 27 07:55:54 PM UTC 24 |
27827821 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.3381688521 |
|
|
Aug 27 07:55:52 PM UTC 24 |
Aug 27 07:55:55 PM UTC 24 |
283935025 ps |
| T1040 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.3844186799 |
|
|
Aug 27 07:55:53 PM UTC 24 |
Aug 27 07:55:56 PM UTC 24 |
12569370 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_08_26/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3088137383 |
|
|
Aug 27 07:55:52 PM UTC 24 |
Aug 27 07:55:56 PM UTC 24 |
399727351 ps |