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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.29 95.43 99.26


Total test records in report: 1151
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T621 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.474192680 Aug 29 12:42:44 PM UTC 24 Aug 29 12:42:46 PM UTC 24 146426276 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.2879206233 Aug 29 12:42:44 PM UTC 24 Aug 29 12:42:46 PM UTC 24 561985389 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.544844010 Aug 29 12:41:49 PM UTC 24 Aug 29 12:42:47 PM UTC 24 9893560688 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.1925763675 Aug 29 12:42:42 PM UTC 24 Aug 29 12:42:48 PM UTC 24 6307627623 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.2392671463 Aug 29 12:42:36 PM UTC 24 Aug 29 12:42:52 PM UTC 24 2278708103 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.3187427307 Aug 29 12:42:49 PM UTC 24 Aug 29 12:42:55 PM UTC 24 1445426420 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.1299955585 Aug 29 12:42:23 PM UTC 24 Aug 29 12:42:55 PM UTC 24 2540905947 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.3700081527 Aug 29 12:42:47 PM UTC 24 Aug 29 12:42:58 PM UTC 24 1201234021 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.2173754731 Aug 29 12:42:53 PM UTC 24 Aug 29 12:43:00 PM UTC 24 435242078 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2594688863 Aug 29 12:34:32 PM UTC 24 Aug 29 12:43:01 PM UTC 24 678179724121 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.2540551672 Aug 29 12:42:44 PM UTC 24 Aug 29 12:43:04 PM UTC 24 2882575284 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.1153766538 Aug 29 12:42:56 PM UTC 24 Aug 29 12:43:05 PM UTC 24 449506277 ps
T293 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.624726091 Aug 29 12:42:45 PM UTC 24 Aug 29 12:43:05 PM UTC 24 4911251243 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.2160099532 Aug 29 12:42:29 PM UTC 24 Aug 29 12:43:07 PM UTC 24 5969074029 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.1502522578 Aug 29 12:43:05 PM UTC 24 Aug 29 12:43:07 PM UTC 24 12619202 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.994974701 Aug 29 12:43:05 PM UTC 24 Aug 29 12:43:08 PM UTC 24 41053086 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.3649650099 Aug 29 12:42:32 PM UTC 24 Aug 29 12:43:08 PM UTC 24 7390072709 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.303469138 Aug 29 12:43:09 PM UTC 24 Aug 29 12:43:11 PM UTC 24 71120662 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.2177608509 Aug 29 12:42:44 PM UTC 24 Aug 29 12:43:11 PM UTC 24 25111533621 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.3767878550 Aug 29 12:43:05 PM UTC 24 Aug 29 12:43:14 PM UTC 24 1478994563 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.1151497538 Aug 29 12:38:03 PM UTC 24 Aug 29 12:43:15 PM UTC 24 29164765752 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.2099412275 Aug 29 12:42:43 PM UTC 24 Aug 29 12:43:15 PM UTC 24 3630711924 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.1338927950 Aug 29 12:43:12 PM UTC 24 Aug 29 12:43:16 PM UTC 24 445317776 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.3040675811 Aug 29 12:43:15 PM UTC 24 Aug 29 12:43:19 PM UTC 24 117756440 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.2412187075 Aug 29 12:42:12 PM UTC 24 Aug 29 12:43:20 PM UTC 24 2319394036 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.1275150928 Aug 29 12:43:16 PM UTC 24 Aug 29 12:43:21 PM UTC 24 211527456 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.486345358 Aug 29 12:43:09 PM UTC 24 Aug 29 12:43:22 PM UTC 24 2453842231 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.396535098 Aug 29 12:42:14 PM UTC 24 Aug 29 12:43:24 PM UTC 24 7351182568 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.3171815948 Aug 29 12:40:32 PM UTC 24 Aug 29 12:43:24 PM UTC 24 56907764093 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.1933445921 Aug 29 12:43:09 PM UTC 24 Aug 29 12:43:26 PM UTC 24 1190632744 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.3101183897 Aug 29 12:43:25 PM UTC 24 Aug 29 12:43:27 PM UTC 24 26391889 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.3276549739 Aug 29 12:41:52 PM UTC 24 Aug 29 12:43:27 PM UTC 24 15283562036 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.3505025872 Aug 29 12:43:26 PM UTC 24 Aug 29 12:43:28 PM UTC 24 15985871 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.436724684 Aug 29 12:42:49 PM UTC 24 Aug 29 12:43:29 PM UTC 24 3547278647 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.668966911 Aug 29 12:43:16 PM UTC 24 Aug 29 12:43:29 PM UTC 24 1728760679 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.3746971622 Aug 29 12:43:12 PM UTC 24 Aug 29 12:43:30 PM UTC 24 4842031765 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.2835942745 Aug 29 12:43:09 PM UTC 24 Aug 29 12:43:30 PM UTC 24 2783653635 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.2246289835 Aug 29 12:45:00 PM UTC 24 Aug 29 12:45:02 PM UTC 24 181917664 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.3012287067 Aug 29 12:40:52 PM UTC 24 Aug 29 12:43:31 PM UTC 24 9474905267 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.4247594053 Aug 29 12:43:29 PM UTC 24 Aug 29 12:43:32 PM UTC 24 256724157 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.3294252065 Aug 29 12:43:30 PM UTC 24 Aug 29 12:43:33 PM UTC 24 32667501 ps
T277 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.2533358262 Aug 29 12:41:51 PM UTC 24 Aug 29 12:43:35 PM UTC 24 3973821557 ps
T656 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.675733094 Aug 29 12:43:16 PM UTC 24 Aug 29 12:43:35 PM UTC 24 11737863394 ps
T657 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.2585242691 Aug 29 12:43:31 PM UTC 24 Aug 29 12:43:36 PM UTC 24 876102934 ps
T658 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.4273579024 Aug 29 12:43:32 PM UTC 24 Aug 29 12:43:36 PM UTC 24 69737717 ps
T659 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.316336620 Aug 29 12:43:19 PM UTC 24 Aug 29 12:43:37 PM UTC 24 1279480764 ps
T660 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.2580798165 Aug 29 12:43:33 PM UTC 24 Aug 29 12:43:37 PM UTC 24 128672572 ps
T661 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.4182604946 Aug 29 12:43:28 PM UTC 24 Aug 29 12:43:38 PM UTC 24 1891152891 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.157562497 Aug 29 12:41:52 PM UTC 24 Aug 29 12:43:40 PM UTC 24 45871118447 ps
T662 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.288523758 Aug 29 12:43:36 PM UTC 24 Aug 29 12:43:43 PM UTC 24 144379538 ps
T663 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.3545346685 Aug 29 12:43:41 PM UTC 24 Aug 29 12:43:43 PM UTC 24 14829069 ps
T664 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.3467128867 Aug 29 12:43:34 PM UTC 24 Aug 29 12:43:44 PM UTC 24 1393737795 ps
T665 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.772011618 Aug 29 12:43:44 PM UTC 24 Aug 29 12:43:46 PM UTC 24 45854801 ps
T666 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.4033394976 Aug 29 12:43:47 PM UTC 24 Aug 29 12:43:49 PM UTC 24 70882728 ps
T667 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.3854397123 Aug 29 12:43:31 PM UTC 24 Aug 29 12:43:50 PM UTC 24 2624194140 ps
T668 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.269474945 Aug 29 12:43:50 PM UTC 24 Aug 29 12:43:53 PM UTC 24 1064195669 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.3214856221 Aug 29 12:30:28 PM UTC 24 Aug 29 12:43:54 PM UTC 24 162034624495 ps
T669 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.28643590 Aug 29 12:44:49 PM UTC 24 Aug 29 12:45:02 PM UTC 24 3213554825 ps
T294 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.3101525298 Aug 29 12:41:12 PM UTC 24 Aug 29 12:43:56 PM UTC 24 4712057048 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.1679184459 Aug 29 12:43:36 PM UTC 24 Aug 29 12:43:56 PM UTC 24 1042899818 ps
T670 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.1084680755 Aug 29 12:43:54 PM UTC 24 Aug 29 12:43:58 PM UTC 24 55716439 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.119471150 Aug 29 12:41:10 PM UTC 24 Aug 29 12:44:00 PM UTC 24 34259451908 ps
T671 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.2466117017 Aug 29 12:43:58 PM UTC 24 Aug 29 12:44:02 PM UTC 24 104945488 ps
T672 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.1506078906 Aug 29 12:43:28 PM UTC 24 Aug 29 12:44:02 PM UTC 24 3958150615 ps
T673 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.3003148545 Aug 29 12:43:44 PM UTC 24 Aug 29 12:44:03 PM UTC 24 3112171641 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.2162689170 Aug 29 12:40:44 PM UTC 24 Aug 29 12:44:07 PM UTC 24 106431022428 ps
T674 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.8503906 Aug 29 12:43:22 PM UTC 24 Aug 29 12:44:07 PM UTC 24 8990609272 ps
T675 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.132578176 Aug 29 12:43:33 PM UTC 24 Aug 29 12:44:08 PM UTC 24 8077707881 ps
T676 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.4202221670 Aug 29 12:43:59 PM UTC 24 Aug 29 12:44:09 PM UTC 24 331354408 ps
T677 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.3973491047 Aug 29 12:43:54 PM UTC 24 Aug 29 12:44:11 PM UTC 24 11985693160 ps
T678 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.1632466211 Aug 29 12:44:04 PM UTC 24 Aug 29 12:44:11 PM UTC 24 245336734 ps
T278 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3539594380 Aug 29 12:39:17 PM UTC 24 Aug 29 12:44:12 PM UTC 24 19555112112 ps
T679 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.1510556624 Aug 29 12:44:11 PM UTC 24 Aug 29 12:44:13 PM UTC 24 51861040 ps
T680 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.808297299 Aug 29 12:44:12 PM UTC 24 Aug 29 12:44:14 PM UTC 24 49909435 ps
T681 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.340911911 Aug 29 12:44:01 PM UTC 24 Aug 29 12:44:14 PM UTC 24 1384315444 ps
T682 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.2237606802 Aug 29 12:43:58 PM UTC 24 Aug 29 12:44:15 PM UTC 24 2000723909 ps
T683 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.2704389527 Aug 29 12:44:14 PM UTC 24 Aug 29 12:44:17 PM UTC 24 173103046 ps
T684 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.3867768146 Aug 29 12:43:50 PM UTC 24 Aug 29 12:44:17 PM UTC 24 15441454112 ps
T685 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.1651745322 Aug 29 12:44:12 PM UTC 24 Aug 29 12:44:17 PM UTC 24 444110799 ps
T686 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.474263683 Aug 29 12:43:45 PM UTC 24 Aug 29 12:44:19 PM UTC 24 7796165295 ps
T687 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.1705294783 Aug 29 12:44:16 PM UTC 24 Aug 29 12:44:22 PM UTC 24 231732323 ps
T688 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.1407084533 Aug 29 12:44:18 PM UTC 24 Aug 29 12:44:24 PM UTC 24 830575419 ps
T689 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.491908568 Aug 29 12:42:37 PM UTC 24 Aug 29 12:44:24 PM UTC 24 20875393061 ps
T690 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.2473305978 Aug 29 12:44:18 PM UTC 24 Aug 29 12:44:27 PM UTC 24 131107300 ps
T691 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.1701348903 Aug 29 12:41:12 PM UTC 24 Aug 29 12:44:28 PM UTC 24 19375344203 ps
T692 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.2740539652 Aug 29 12:44:23 PM UTC 24 Aug 29 12:44:29 PM UTC 24 670566323 ps
T693 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.2983048814 Aug 29 12:44:20 PM UTC 24 Aug 29 12:44:29 PM UTC 24 4738967322 ps
T694 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.1165931912 Aug 29 12:44:17 PM UTC 24 Aug 29 12:44:30 PM UTC 24 4596528660 ps
T695 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.2594905545 Aug 29 12:42:47 PM UTC 24 Aug 29 12:44:30 PM UTC 24 39641075787 ps
T696 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.1929996715 Aug 29 12:43:17 PM UTC 24 Aug 29 12:44:30 PM UTC 24 28365337322 ps
T697 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.396393200 Aug 29 12:44:31 PM UTC 24 Aug 29 12:44:33 PM UTC 24 24620440 ps
T698 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.3068491852 Aug 29 12:44:31 PM UTC 24 Aug 29 12:44:34 PM UTC 24 29329168 ps
T699 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.1694059203 Aug 29 12:43:02 PM UTC 24 Aug 29 12:44:35 PM UTC 24 4492538360 ps
T700 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.1686624489 Aug 29 12:44:13 PM UTC 24 Aug 29 12:44:35 PM UTC 24 4465704665 ps
T701 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.686509405 Aug 29 12:44:31 PM UTC 24 Aug 29 12:44:36 PM UTC 24 569307607 ps
T702 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.2950932762 Aug 29 12:44:35 PM UTC 24 Aug 29 12:44:37 PM UTC 24 227207766 ps
T703 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.2666986709 Aug 29 12:44:16 PM UTC 24 Aug 29 12:44:39 PM UTC 24 15254036881 ps
T704 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.136564236 Aug 29 12:44:36 PM UTC 24 Aug 29 12:44:40 PM UTC 24 221282354 ps
T705 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.910154914 Aug 29 12:44:38 PM UTC 24 Aug 29 12:44:43 PM UTC 24 506014553 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.3481606887 Aug 29 12:43:39 PM UTC 24 Aug 29 12:44:44 PM UTC 24 7841375256 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.496195930 Aug 29 12:37:41 PM UTC 24 Aug 29 12:44:46 PM UTC 24 135452998589 ps
T706 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.924244524 Aug 29 12:44:25 PM UTC 24 Aug 29 12:44:48 PM UTC 24 7120671552 ps
T707 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.2522938006 Aug 29 12:44:36 PM UTC 24 Aug 29 12:44:48 PM UTC 24 2739699365 ps
T708 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.1118149237 Aug 29 12:44:38 PM UTC 24 Aug 29 12:44:49 PM UTC 24 859058295 ps
T709 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.1751705326 Aug 29 12:44:41 PM UTC 24 Aug 29 12:44:53 PM UTC 24 4462609265 ps
T710 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.4176260324 Aug 29 12:44:44 PM UTC 24 Aug 29 12:44:56 PM UTC 24 554896320 ps
T711 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.3920970169 Aug 29 12:44:45 PM UTC 24 Aug 29 12:44:56 PM UTC 24 396046298 ps
T712 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.3392991162 Aug 29 12:43:23 PM UTC 24 Aug 29 12:44:57 PM UTC 24 40905280243 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.1319674358 Aug 29 12:43:23 PM UTC 24 Aug 29 12:44:58 PM UTC 24 18561486678 ps
T713 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.1514385677 Aug 29 12:44:57 PM UTC 24 Aug 29 12:44:59 PM UTC 24 34187863 ps
T714 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.1125370945 Aug 29 12:44:58 PM UTC 24 Aug 29 12:45:00 PM UTC 24 49258476 ps
T233 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.1546849312 Aug 29 12:44:40 PM UTC 24 Aug 29 12:45:00 PM UTC 24 11752193956 ps
T715 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.391897517 Aug 29 12:44:35 PM UTC 24 Aug 29 12:45:01 PM UTC 24 20515758235 ps
T716 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.1333668108 Aug 29 12:43:37 PM UTC 24 Aug 29 12:45:01 PM UTC 24 3567834807 ps
T717 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.1970631355 Aug 29 12:44:18 PM UTC 24 Aug 29 12:45:05 PM UTC 24 25628467571 ps
T718 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.1641775970 Aug 29 12:45:01 PM UTC 24 Aug 29 12:45:05 PM UTC 24 137562118 ps
T719 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.3249495960 Aug 29 12:45:02 PM UTC 24 Aug 29 12:45:07 PM UTC 24 31499750 ps
T720 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.433267214 Aug 29 12:45:04 PM UTC 24 Aug 29 12:45:09 PM UTC 24 107890722 ps
T721 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.3788931338 Aug 29 12:45:02 PM UTC 24 Aug 29 12:45:12 PM UTC 24 454150475 ps
T722 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.625146017 Aug 29 12:44:58 PM UTC 24 Aug 29 12:45:13 PM UTC 24 1362772704 ps
T723 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.219059910 Aug 29 12:45:06 PM UTC 24 Aug 29 12:45:13 PM UTC 24 536332237 ps
T724 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.422720770 Aug 29 12:45:02 PM UTC 24 Aug 29 12:45:15 PM UTC 24 1039950905 ps
T230 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.1540428630 Aug 29 12:43:38 PM UTC 24 Aug 29 12:45:19 PM UTC 24 73484886265 ps
T725 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.4233814980 Aug 29 12:45:09 PM UTC 24 Aug 29 12:45:21 PM UTC 24 1163849372 ps
T726 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.498670221 Aug 29 12:45:20 PM UTC 24 Aug 29 12:45:22 PM UTC 24 14705470 ps
T727 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.1168907371 Aug 29 12:45:22 PM UTC 24 Aug 29 12:45:25 PM UTC 24 56298023 ps
T728 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.3984106094 Aug 29 12:45:02 PM UTC 24 Aug 29 12:45:26 PM UTC 24 3647297847 ps
T729 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.1229204115 Aug 29 12:43:36 PM UTC 24 Aug 29 12:45:28 PM UTC 24 8217187242 ps
T262 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.354497797 Aug 29 12:44:49 PM UTC 24 Aug 29 12:45:28 PM UTC 24 1911864147 ps
T730 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.2468257468 Aug 29 12:45:27 PM UTC 24 Aug 29 12:45:29 PM UTC 24 59001719 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.1407163065 Aug 29 12:45:06 PM UTC 24 Aug 29 12:45:30 PM UTC 24 1440362947 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.360929367 Aug 29 12:35:04 PM UTC 24 Aug 29 12:45:33 PM UTC 24 152321411982 ps
T731 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.2065514479 Aug 29 12:45:29 PM UTC 24 Aug 29 12:45:34 PM UTC 24 311815300 ps
T732 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.3767090005 Aug 29 12:45:29 PM UTC 24 Aug 29 12:45:36 PM UTC 24 69902641 ps
T733 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.914432401 Aug 29 12:45:31 PM UTC 24 Aug 29 12:45:36 PM UTC 24 1180896149 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.781160951 Aug 29 12:45:00 PM UTC 24 Aug 29 12:45:37 PM UTC 24 20226299415 ps
T734 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.2416391991 Aug 29 12:44:48 PM UTC 24 Aug 29 12:45:39 PM UTC 24 1505404029 ps
T735 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.3025251369 Aug 29 12:44:30 PM UTC 24 Aug 29 12:45:39 PM UTC 24 5266772332 ps
T736 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.3115105403 Aug 29 12:45:35 PM UTC 24 Aug 29 12:45:40 PM UTC 24 593737920 ps
T737 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.3964939426 Aug 29 12:45:39 PM UTC 24 Aug 29 12:45:46 PM UTC 24 531068001 ps
T738 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.3325523720 Aug 29 12:45:34 PM UTC 24 Aug 29 12:45:47 PM UTC 24 5757117653 ps
T739 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.3424290405 Aug 29 12:45:26 PM UTC 24 Aug 29 12:45:48 PM UTC 24 2015903583 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.3443568583 Aug 29 12:40:27 PM UTC 24 Aug 29 12:45:48 PM UTC 24 32621747880 ps
T740 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.693897090 Aug 29 12:45:48 PM UTC 24 Aug 29 12:45:50 PM UTC 24 14165497 ps
T741 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.641930355 Aug 29 12:45:31 PM UTC 24 Aug 29 12:45:50 PM UTC 24 1467541356 ps
T742 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.498446707 Aug 29 12:45:49 PM UTC 24 Aug 29 12:45:51 PM UTC 24 16572924 ps
T743 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.3890550342 Aug 29 12:45:52 PM UTC 24 Aug 29 12:45:54 PM UTC 24 35895681 ps
T744 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.114662022 Aug 29 12:45:52 PM UTC 24 Aug 29 12:45:54 PM UTC 24 210686085 ps
T745 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.3919450497 Aug 29 12:45:24 PM UTC 24 Aug 29 12:45:59 PM UTC 24 5331734823 ps
T213 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.4154661902 Aug 29 12:36:49 PM UTC 24 Aug 29 12:46:00 PM UTC 24 856813048988 ps
T746 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.3507737759 Aug 29 12:45:55 PM UTC 24 Aug 29 12:46:01 PM UTC 24 113706163 ps
T747 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.2669999217 Aug 29 12:45:31 PM UTC 24 Aug 29 12:46:01 PM UTC 24 12376826882 ps
T42 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.3598169346 Aug 29 12:43:01 PM UTC 24 Aug 29 12:46:01 PM UTC 24 61604840143 ps
T748 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.2592472988 Aug 29 12:45:51 PM UTC 24 Aug 29 12:46:02 PM UTC 24 1556767591 ps
T749 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.697839119 Aug 29 12:45:49 PM UTC 24 Aug 29 12:46:03 PM UTC 24 1648344074 ps
T750 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.1044949035 Aug 29 12:46:02 PM UTC 24 Aug 29 12:46:08 PM UTC 24 526492640 ps
T751 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.336878523 Aug 29 12:45:36 PM UTC 24 Aug 29 12:46:09 PM UTC 24 13992553247 ps
T752 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.317197015 Aug 29 12:46:01 PM UTC 24 Aug 29 12:46:11 PM UTC 24 1112989774 ps
T753 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.2886630825 Aug 29 12:46:04 PM UTC 24 Aug 29 12:46:11 PM UTC 24 162442523 ps
T754 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.3453125822 Aug 29 12:46:03 PM UTC 24 Aug 29 12:46:13 PM UTC 24 453886940 ps
T259 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.728571130 Aug 29 12:45:55 PM UTC 24 Aug 29 12:46:14 PM UTC 24 12773730678 ps
T331 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.1557356339 Aug 29 12:36:00 PM UTC 24 Aug 29 12:46:14 PM UTC 24 47209749672 ps
T755 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.1089071009 Aug 29 12:46:12 PM UTC 24 Aug 29 12:46:14 PM UTC 24 35867819 ps
T756 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.1880959979 Aug 29 12:46:14 PM UTC 24 Aug 29 12:46:16 PM UTC 24 22079423 ps
T757 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.2638817901 Aug 29 12:40:49 PM UTC 24 Aug 29 12:46:16 PM UTC 24 30552689873 ps
T758 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.4027735608 Aug 29 12:46:16 PM UTC 24 Aug 29 12:46:18 PM UTC 24 54805574 ps
T759 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.3982126243 Aug 29 12:46:00 PM UTC 24 Aug 29 12:46:19 PM UTC 24 1027908304 ps
T760 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.3148675226 Aug 29 12:46:17 PM UTC 24 Aug 29 12:46:20 PM UTC 24 84414374 ps
T761 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.792447645 Aug 29 12:46:17 PM UTC 24 Aug 29 12:46:21 PM UTC 24 70519102 ps
T762 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.1762148019 Aug 29 12:46:18 PM UTC 24 Aug 29 12:46:22 PM UTC 24 337457629 ps
T763 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.2051053708 Aug 29 12:46:21 PM UTC 24 Aug 29 12:46:25 PM UTC 24 307668119 ps
T764 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.3288395167 Aug 29 12:46:21 PM UTC 24 Aug 29 12:46:26 PM UTC 24 127273913 ps
T765 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.3675686962 Aug 29 12:46:23 PM UTC 24 Aug 29 12:46:28 PM UTC 24 2716721924 ps
T307 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.2934339128 Aug 29 12:44:07 PM UTC 24 Aug 29 12:46:30 PM UTC 24 14543455507 ps
T766 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.199473798 Aug 29 12:44:50 PM UTC 24 Aug 29 12:46:32 PM UTC 24 17781941874 ps
T767 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.3912276731 Aug 29 12:46:26 PM UTC 24 Aug 29 12:46:34 PM UTC 24 300701737 ps
T768 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.995590662 Aug 29 12:46:04 PM UTC 24 Aug 29 12:46:37 PM UTC 24 3746873002 ps
T769 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.2502836712 Aug 29 12:46:02 PM UTC 24 Aug 29 12:46:38 PM UTC 24 2371301763 ps
T770 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.2496347185 Aug 29 12:46:16 PM UTC 24 Aug 29 12:46:38 PM UTC 24 4359086979 ps
T214 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.1502439749 Aug 29 12:44:07 PM UTC 24 Aug 29 12:46:39 PM UTC 24 13311765423 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.672144313 Aug 29 12:39:55 PM UTC 24 Aug 29 12:46:40 PM UTC 24 579077916990 ps
T43 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.2449810425 Aug 29 12:44:09 PM UTC 24 Aug 29 12:46:42 PM UTC 24 9587865264 ps
T771 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.1773079234 Aug 29 12:46:40 PM UTC 24 Aug 29 12:46:42 PM UTC 24 15400029 ps
T772 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.11858546 Aug 29 12:46:39 PM UTC 24 Aug 29 12:46:42 PM UTC 24 37066981 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.2432258905 Aug 29 12:45:07 PM UTC 24 Aug 29 12:46:43 PM UTC 24 4710548048 ps
T773 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.717998069 Aug 29 12:46:41 PM UTC 24 Aug 29 12:46:44 PM UTC 24 16420964 ps
T774 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.686363832 Aug 29 12:46:30 PM UTC 24 Aug 29 12:46:44 PM UTC 24 1173937166 ps
T775 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.1330697373 Aug 29 12:46:42 PM UTC 24 Aug 29 12:46:45 PM UTC 24 93942101 ps
T776 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.1666915303 Aug 29 12:46:44 PM UTC 24 Aug 29 12:46:48 PM UTC 24 96689031 ps
T777 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.3595636288 Aug 29 12:46:44 PM UTC 24 Aug 29 12:46:49 PM UTC 24 219148818 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.1216092946 Aug 29 12:46:27 PM UTC 24 Aug 29 12:46:50 PM UTC 24 6617324252 ps
T44 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.1555848860 Aug 29 12:37:12 PM UTC 24 Aug 29 12:46:51 PM UTC 24 45659137330 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.3894506822 Aug 29 12:46:50 PM UTC 24 Aug 29 12:46:54 PM UTC 24 311428727 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.3159067362 Aug 29 12:46:16 PM UTC 24 Aug 29 12:46:55 PM UTC 24 4362390214 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.2314926967 Aug 29 12:46:49 PM UTC 24 Aug 29 12:46:55 PM UTC 24 400727359 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.315283230 Aug 29 12:46:46 PM UTC 24 Aug 29 12:46:56 PM UTC 24 765196784 ps
T332 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.931308879 Aug 29 12:45:40 PM UTC 24 Aug 29 12:46:58 PM UTC 24 3596832303 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.2132970438 Aug 29 12:46:51 PM UTC 24 Aug 29 12:46:59 PM UTC 24 377158273 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.3178991752 Aug 29 12:47:00 PM UTC 24 Aug 29 12:47:02 PM UTC 24 78577425 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.65785669 Aug 29 12:46:46 PM UTC 24 Aug 29 12:47:03 PM UTC 24 3495268194 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.12929419 Aug 29 12:46:44 PM UTC 24 Aug 29 12:47:04 PM UTC 24 2021934817 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.3260263040 Aug 29 12:46:55 PM UTC 24 Aug 29 12:47:05 PM UTC 24 745863675 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.1643239497 Aug 29 12:47:03 PM UTC 24 Aug 29 12:47:06 PM UTC 24 55256709 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.1493693824 Aug 29 12:47:05 PM UTC 24 Aug 29 12:47:07 PM UTC 24 14487156 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.2049891070 Aug 29 12:47:06 PM UTC 24 Aug 29 12:47:08 PM UTC 24 77620004 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.3979806255 Aug 29 12:46:41 PM UTC 24 Aug 29 12:47:10 PM UTC 24 5833676497 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.2740552342 Aug 29 12:47:07 PM UTC 24 Aug 29 12:47:12 PM UTC 24 144087607 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.2437351425 Aug 29 12:47:05 PM UTC 24 Aug 29 12:47:13 PM UTC 24 1617012620 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.3954405133 Aug 29 12:46:22 PM UTC 24 Aug 29 12:47:14 PM UTC 24 15290518725 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.2426674795 Aug 29 12:47:08 PM UTC 24 Aug 29 12:47:15 PM UTC 24 639741224 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.1611631088 Aug 29 12:47:11 PM UTC 24 Aug 29 12:47:17 PM UTC 24 338167481 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.2565417218 Aug 29 12:42:11 PM UTC 24 Aug 29 12:47:17 PM UTC 24 36683571605 ps
T281 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.4076301562 Aug 29 12:43:25 PM UTC 24 Aug 29 12:47:18 PM UTC 24 14647989444 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.3159514567 Aug 29 12:46:56 PM UTC 24 Aug 29 12:47:19 PM UTC 24 4857850487 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.698939786 Aug 29 12:47:10 PM UTC 24 Aug 29 12:47:19 PM UTC 24 2043963876 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.349944737 Aug 29 12:47:15 PM UTC 24 Aug 29 12:47:19 PM UTC 24 1338561427 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.761546655 Aug 29 12:47:16 PM UTC 24 Aug 29 12:47:20 PM UTC 24 115977495 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.1580709445 Aug 29 12:47:15 PM UTC 24 Aug 29 12:47:22 PM UTC 24 346828979 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.3922329952 Aug 29 12:47:20 PM UTC 24 Aug 29 12:47:22 PM UTC 24 50690701 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.3064663904 Aug 29 12:47:22 PM UTC 24 Aug 29 12:47:24 PM UTC 24 32081771 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.3447861261 Aug 29 12:42:56 PM UTC 24 Aug 29 12:47:26 PM UTC 24 31462710751 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.372087121 Aug 29 12:47:24 PM UTC 24 Aug 29 12:47:26 PM UTC 24 19168872 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.1181645563 Aug 29 12:46:34 PM UTC 24 Aug 29 12:47:28 PM UTC 24 35626448712 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.2986260687 Aug 29 12:45:47 PM UTC 24 Aug 29 12:47:28 PM UTC 24 3260440236 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.3251948102 Aug 29 12:47:18 PM UTC 24 Aug 29 12:47:29 PM UTC 24 4096528443 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.2765061347 Aug 29 12:47:28 PM UTC 24 Aug 29 12:47:31 PM UTC 24 27361250 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.4167116344 Aug 29 12:47:28 PM UTC 24 Aug 29 12:47:32 PM UTC 24 231551242 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.674714243 Aug 29 12:47:29 PM UTC 24 Aug 29 12:47:34 PM UTC 24 215498268 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.2104300236 Aug 29 12:47:30 PM UTC 24 Aug 29 12:47:38 PM UTC 24 738613606 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.2492426939 Aug 29 12:44:55 PM UTC 24 Aug 29 12:47:38 PM UTC 24 19698674270 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.1084866458 Aug 29 12:47:23 PM UTC 24 Aug 29 12:47:42 PM UTC 24 1820115623 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.2756061222 Aug 29 12:47:13 PM UTC 24 Aug 29 12:47:42 PM UTC 24 2574518740 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.2994408315 Aug 29 12:42:59 PM UTC 24 Aug 29 12:47:45 PM UTC 24 84802228521 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.3299727222 Aug 29 12:47:32 PM UTC 24 Aug 29 12:47:46 PM UTC 24 2781318843 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.3491998824 Aug 29 12:47:33 PM UTC 24 Aug 29 12:47:46 PM UTC 24 3890939960 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.1936623472 Aug 29 12:47:40 PM UTC 24 Aug 29 12:47:47 PM UTC 24 1340002840 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.536159613 Aug 29 12:46:42 PM UTC 24 Aug 29 12:47:48 PM UTC 24 96335665155 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.107304365 Aug 29 12:47:47 PM UTC 24 Aug 29 12:47:49 PM UTC 24 12301769 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.2575937813 Aug 29 12:47:48 PM UTC 24 Aug 29 12:47:50 PM UTC 24 47681811 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.2399617376 Aug 29 12:44:51 PM UTC 24 Aug 29 12:47:50 PM UTC 24 13311514701 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.124174135 Aug 29 12:47:23 PM UTC 24 Aug 29 12:47:53 PM UTC 24 5198014446 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.407202105 Aug 29 12:47:51 PM UTC 24 Aug 29 12:47:53 PM UTC 24 64114631 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.1144516370 Aug 29 12:47:51 PM UTC 24 Aug 29 12:47:55 PM UTC 24 121288011 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.384512193 Aug 29 12:47:50 PM UTC 24 Aug 29 12:47:55 PM UTC 24 361919804 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2997245136 Aug 29 12:42:38 PM UTC 24 Aug 29 12:47:57 PM UTC 24 59896433861 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.815171156 Aug 29 12:44:25 PM UTC 24 Aug 29 12:47:57 PM UTC 24 9953541145 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2718160151 Aug 29 12:46:10 PM UTC 24 Aug 29 12:47:58 PM UTC 24 5710735373 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.1213331275 Aug 29 12:47:30 PM UTC 24 Aug 29 12:48:00 PM UTC 24 2582296370 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2860340856 Aug 29 12:47:53 PM UTC 24 Aug 29 12:48:02 PM UTC 24 709634636 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.3932491974 Aug 29 12:47:59 PM UTC 24 Aug 29 12:48:03 PM UTC 24 1941633451 ps
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