| T831 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.2025311711 |
|
|
Aug 29 12:47:55 PM UTC 24 |
Aug 29 12:48:03 PM UTC 24 |
1793224667 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.622863594 |
|
|
Aug 29 12:47:59 PM UTC 24 |
Aug 29 12:48:06 PM UTC 24 |
217481921 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.2683839147 |
|
|
Aug 29 12:36:48 PM UTC 24 |
Aug 29 12:48:06 PM UTC 24 |
66145926395 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.877834294 |
|
|
Aug 29 12:47:56 PM UTC 24 |
Aug 29 12:48:08 PM UTC 24 |
1169586308 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.3394170990 |
|
|
Aug 29 12:47:20 PM UTC 24 |
Aug 29 12:48:09 PM UTC 24 |
10101973763 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.1905785253 |
|
|
Aug 29 12:48:07 PM UTC 24 |
Aug 29 12:48:10 PM UTC 24 |
46579633 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.3085825713 |
|
|
Aug 29 12:48:08 PM UTC 24 |
Aug 29 12:48:10 PM UTC 24 |
25191709 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1429724867 |
|
|
Aug 29 12:47:45 PM UTC 24 |
Aug 29 12:48:13 PM UTC 24 |
1625677159 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.3744865037 |
|
|
Aug 29 12:48:11 PM UTC 24 |
Aug 29 12:48:13 PM UTC 24 |
17155163 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.3321390838 |
|
|
Aug 29 12:48:02 PM UTC 24 |
Aug 29 12:48:14 PM UTC 24 |
665177922 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.136968970 |
|
|
Aug 29 12:47:59 PM UTC 24 |
Aug 29 12:48:14 PM UTC 24 |
2298427990 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.104535298 |
|
|
Aug 29 12:48:14 PM UTC 24 |
Aug 29 12:48:17 PM UTC 24 |
25026030 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.1768319117 |
|
|
Aug 29 12:48:15 PM UTC 24 |
Aug 29 12:48:17 PM UTC 24 |
155482209 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.1333823562 |
|
|
Aug 29 12:48:03 PM UTC 24 |
Aug 29 12:48:19 PM UTC 24 |
2057149556 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.143650735 |
|
|
Aug 29 12:44:30 PM UTC 24 |
Aug 29 12:48:20 PM UTC 24 |
26607348998 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.3331603080 |
|
|
Aug 29 12:48:16 PM UTC 24 |
Aug 29 12:48:22 PM UTC 24 |
3374310277 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.2200003331 |
|
|
Aug 29 12:47:20 PM UTC 24 |
Aug 29 12:48:22 PM UTC 24 |
3118986343 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.31781096 |
|
|
Aug 29 12:48:11 PM UTC 24 |
Aug 29 12:48:22 PM UTC 24 |
5433779064 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.3714195148 |
|
|
Aug 29 12:48:18 PM UTC 24 |
Aug 29 12:48:23 PM UTC 24 |
665404933 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2975388675 |
|
|
Aug 29 12:48:24 PM UTC 24 |
Aug 29 12:48:26 PM UTC 24 |
38786016 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.1028542317 |
|
|
Aug 29 12:47:35 PM UTC 24 |
Aug 29 12:48:26 PM UTC 24 |
12075420741 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.2891045425 |
|
|
Aug 29 12:48:21 PM UTC 24 |
Aug 29 12:48:28 PM UTC 24 |
5673165585 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.1730762858 |
|
|
Aug 29 12:48:22 PM UTC 24 |
Aug 29 12:48:28 PM UTC 24 |
335369575 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.3109016544 |
|
|
Aug 29 12:48:16 PM UTC 24 |
Aug 29 12:48:29 PM UTC 24 |
9071260386 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.3926720959 |
|
|
Aug 29 12:47:50 PM UTC 24 |
Aug 29 12:48:29 PM UTC 24 |
5928781515 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.1685206793 |
|
|
Aug 29 12:48:29 PM UTC 24 |
Aug 29 12:48:31 PM UTC 24 |
42517339 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.2142023815 |
|
|
Aug 29 12:46:09 PM UTC 24 |
Aug 29 12:48:31 PM UTC 24 |
6963409037 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.3027897893 |
|
|
Aug 29 12:48:30 PM UTC 24 |
Aug 29 12:48:32 PM UTC 24 |
43979168 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.2955021468 |
|
|
Aug 29 12:48:24 PM UTC 24 |
Aug 29 12:48:35 PM UTC 24 |
1143935553 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.1269162019 |
|
|
Aug 29 12:48:33 PM UTC 24 |
Aug 29 12:48:35 PM UTC 24 |
35578369 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.1185308604 |
|
|
Aug 29 12:48:33 PM UTC 24 |
Aug 29 12:48:35 PM UTC 24 |
13343656 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.78521493 |
|
|
Aug 29 12:48:32 PM UTC 24 |
Aug 29 12:48:37 PM UTC 24 |
2532632067 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2592606036 |
|
|
Aug 29 12:48:01 PM UTC 24 |
Aug 29 12:48:38 PM UTC 24 |
1155157318 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.3077710140 |
|
|
Aug 29 12:48:37 PM UTC 24 |
Aug 29 12:48:41 PM UTC 24 |
115000922 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.840511071 |
|
|
Aug 29 12:48:37 PM UTC 24 |
Aug 29 12:48:44 PM UTC 24 |
161272950 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.1871606397 |
|
|
Aug 29 12:48:24 PM UTC 24 |
Aug 29 12:48:44 PM UTC 24 |
974761004 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.95901454 |
|
|
Aug 29 12:48:39 PM UTC 24 |
Aug 29 12:48:45 PM UTC 24 |
213118928 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.1182978305 |
|
|
Aug 29 12:48:18 PM UTC 24 |
Aug 29 12:48:47 PM UTC 24 |
6165099126 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.4102419226 |
|
|
Aug 29 12:36:52 PM UTC 24 |
Aug 29 12:48:50 PM UTC 24 |
125720513887 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.3536230615 |
|
|
Aug 29 12:46:56 PM UTC 24 |
Aug 29 12:48:53 PM UTC 24 |
36236572043 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2471807522 |
|
|
Aug 29 12:48:45 PM UTC 24 |
Aug 29 12:48:54 PM UTC 24 |
318928403 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.3758616837 |
|
|
Aug 29 12:48:35 PM UTC 24 |
Aug 29 12:48:55 PM UTC 24 |
1304334829 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.3319019305 |
|
|
Aug 29 12:48:54 PM UTC 24 |
Aug 29 12:48:57 PM UTC 24 |
101279449 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.669157759 |
|
|
Aug 29 12:48:55 PM UTC 24 |
Aug 29 12:48:57 PM UTC 24 |
36639915 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.2752886576 |
|
|
Aug 29 12:48:57 PM UTC 24 |
Aug 29 12:48:59 PM UTC 24 |
20864660 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.594962601 |
|
|
Aug 29 12:47:18 PM UTC 24 |
Aug 29 12:48:59 PM UTC 24 |
23749776808 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.3457021854 |
|
|
Aug 29 12:48:58 PM UTC 24 |
Aug 29 12:49:00 PM UTC 24 |
11344331 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.2822301190 |
|
|
Aug 29 12:48:59 PM UTC 24 |
Aug 29 12:49:01 PM UTC 24 |
160552004 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.2926656119 |
|
|
Aug 29 12:48:30 PM UTC 24 |
Aug 29 12:49:02 PM UTC 24 |
22870513005 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.923851364 |
|
|
Aug 29 12:44:28 PM UTC 24 |
Aug 29 12:49:03 PM UTC 24 |
125385240962 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.1191031923 |
|
|
Aug 29 12:49:01 PM UTC 24 |
Aug 29 12:49:03 PM UTC 24 |
42462037 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.2806621016 |
|
|
Aug 29 12:48:49 PM UTC 24 |
Aug 29 12:49:07 PM UTC 24 |
4353310734 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.3294870302 |
|
|
Aug 29 12:45:15 PM UTC 24 |
Aug 29 12:49:08 PM UTC 24 |
50398032873 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.2815358875 |
|
|
Aug 29 12:46:35 PM UTC 24 |
Aug 29 12:49:08 PM UTC 24 |
127534570371 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.3862540542 |
|
|
Aug 29 12:49:04 PM UTC 24 |
Aug 29 12:49:10 PM UTC 24 |
601434467 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.631064139 |
|
|
Aug 29 12:49:02 PM UTC 24 |
Aug 29 12:49:12 PM UTC 24 |
902363406 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.2307843658 |
|
|
Aug 29 12:48:39 PM UTC 24 |
Aug 29 12:49:12 PM UTC 24 |
27183315471 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.2172712725 |
|
|
Aug 29 12:48:11 PM UTC 24 |
Aug 29 12:49:14 PM UTC 24 |
141407258573 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.2085673236 |
|
|
Aug 29 12:47:47 PM UTC 24 |
Aug 29 12:49:17 PM UTC 24 |
9999329088 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.991099340 |
|
|
Aug 29 12:49:11 PM UTC 24 |
Aug 29 12:49:18 PM UTC 24 |
237468952 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.2052947254 |
|
|
Aug 29 12:48:43 PM UTC 24 |
Aug 29 12:49:19 PM UTC 24 |
5705274191 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.3506492125 |
|
|
Aug 29 12:48:58 PM UTC 24 |
Aug 29 12:49:20 PM UTC 24 |
711824194 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.2463935019 |
|
|
Aug 29 12:49:19 PM UTC 24 |
Aug 29 12:49:21 PM UTC 24 |
17047176 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.1058465130 |
|
|
Aug 29 12:49:10 PM UTC 24 |
Aug 29 12:49:21 PM UTC 24 |
641676536 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.2811594183 |
|
|
Aug 29 12:49:21 PM UTC 24 |
Aug 29 12:49:22 PM UTC 24 |
61396386 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.1425522041 |
|
|
Aug 29 12:49:01 PM UTC 24 |
Aug 29 12:49:24 PM UTC 24 |
5603005449 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.2927526454 |
|
|
Aug 29 12:49:10 PM UTC 24 |
Aug 29 12:49:25 PM UTC 24 |
615609831 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.2549893811 |
|
|
Aug 29 12:49:23 PM UTC 24 |
Aug 29 12:49:26 PM UTC 24 |
135006390 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.3254693279 |
|
|
Aug 29 12:49:23 PM UTC 24 |
Aug 29 12:49:26 PM UTC 24 |
62218308 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.766488618 |
|
|
Aug 29 12:41:51 PM UTC 24 |
Aug 29 12:49:28 PM UTC 24 |
160972936319 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.3375363645 |
|
|
Aug 29 12:49:08 PM UTC 24 |
Aug 29 12:49:29 PM UTC 24 |
3578795750 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.3916542546 |
|
|
Aug 29 12:49:27 PM UTC 24 |
Aug 29 12:49:31 PM UTC 24 |
57265806 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.3036088164 |
|
|
Aug 29 12:48:51 PM UTC 24 |
Aug 29 12:49:32 PM UTC 24 |
4590923046 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.1387305676 |
|
|
Aug 29 12:47:43 PM UTC 24 |
Aug 29 12:49:33 PM UTC 24 |
14304175892 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.1991872667 |
|
|
Aug 29 12:49:29 PM UTC 24 |
Aug 29 12:49:33 PM UTC 24 |
186401378 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.1866337179 |
|
|
Aug 29 12:49:04 PM UTC 24 |
Aug 29 12:49:36 PM UTC 24 |
45980481820 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.1789992422 |
|
|
Aug 29 12:49:22 PM UTC 24 |
Aug 29 12:49:38 PM UTC 24 |
1904970724 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.85900330 |
|
|
Aug 29 12:48:38 PM UTC 24 |
Aug 29 12:49:39 PM UTC 24 |
12652959625 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.4015647790 |
|
|
Aug 29 12:49:27 PM UTC 24 |
Aug 29 12:49:39 PM UTC 24 |
3887351787 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.1843228148 |
|
|
Aug 29 12:46:53 PM UTC 24 |
Aug 29 12:49:39 PM UTC 24 |
85266951040 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1043312469 |
|
|
Aug 29 12:49:25 PM UTC 24 |
Aug 29 12:49:41 PM UTC 24 |
2561904160 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.3984148152 |
|
|
Aug 29 12:49:40 PM UTC 24 |
Aug 29 12:49:42 PM UTC 24 |
39763434 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.208548931 |
|
|
Aug 29 12:49:41 PM UTC 24 |
Aug 29 12:49:43 PM UTC 24 |
33155878 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.478814146 |
|
|
Aug 29 12:44:02 PM UTC 24 |
Aug 29 12:49:44 PM UTC 24 |
131890897398 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.2974801060 |
|
|
Aug 29 12:49:21 PM UTC 24 |
Aug 29 12:49:44 PM UTC 24 |
4355528029 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3277854810 |
|
|
Aug 29 12:49:43 PM UTC 24 |
Aug 29 12:49:45 PM UTC 24 |
419990461 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.3070168075 |
|
|
Aug 29 12:49:32 PM UTC 24 |
Aug 29 12:49:48 PM UTC 24 |
2206124915 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.610956040 |
|
|
Aug 29 12:49:41 PM UTC 24 |
Aug 29 12:49:48 PM UTC 24 |
1476621715 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.452497327 |
|
|
Aug 29 12:45:15 PM UTC 24 |
Aug 29 12:49:48 PM UTC 24 |
21035084296 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.193311192 |
|
|
Aug 29 12:49:44 PM UTC 24 |
Aug 29 12:49:50 PM UTC 24 |
330392692 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.940725244 |
|
|
Aug 29 12:49:30 PM UTC 24 |
Aug 29 12:49:50 PM UTC 24 |
2188504124 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.740486349 |
|
|
Aug 29 12:49:46 PM UTC 24 |
Aug 29 12:49:50 PM UTC 24 |
168264134 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.712952887 |
|
|
Aug 29 12:49:46 PM UTC 24 |
Aug 29 12:49:52 PM UTC 24 |
252874293 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.2311353171 |
|
|
Aug 29 12:45:41 PM UTC 24 |
Aug 29 12:49:53 PM UTC 24 |
20848010397 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.614662205 |
|
|
Aug 29 12:46:59 PM UTC 24 |
Aug 29 12:49:54 PM UTC 24 |
29492091807 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.2210059303 |
|
|
Aug 29 12:49:50 PM UTC 24 |
Aug 29 12:49:55 PM UTC 24 |
615029366 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2122285748 |
|
|
Aug 29 12:49:26 PM UTC 24 |
Aug 29 12:49:56 PM UTC 24 |
8655319115 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.2332755584 |
|
|
Aug 29 12:49:50 PM UTC 24 |
Aug 29 12:49:56 PM UTC 24 |
926424628 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.4153018485 |
|
|
Aug 29 12:46:58 PM UTC 24 |
Aug 29 12:49:58 PM UTC 24 |
43785962226 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.4074957445 |
|
|
Aug 29 12:49:56 PM UTC 24 |
Aug 29 12:49:59 PM UTC 24 |
38434938 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.4103081125 |
|
|
Aug 29 12:37:11 PM UTC 24 |
Aug 29 12:49:59 PM UTC 24 |
286424832524 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.981556787 |
|
|
Aug 29 12:49:51 PM UTC 24 |
Aug 29 12:50:00 PM UTC 24 |
756631604 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.3058688071 |
|
|
Aug 29 12:49:58 PM UTC 24 |
Aug 29 12:50:00 PM UTC 24 |
56198702 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.680521782 |
|
|
Aug 29 12:48:45 PM UTC 24 |
Aug 29 12:50:01 PM UTC 24 |
20342225994 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.1881685828 |
|
|
Aug 29 12:50:01 PM UTC 24 |
Aug 29 12:50:03 PM UTC 24 |
30276474 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.69026269 |
|
|
Aug 29 12:49:27 PM UTC 24 |
Aug 29 12:50:05 PM UTC 24 |
3272170845 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1049174658 |
|
|
Aug 29 12:49:59 PM UTC 24 |
Aug 29 12:50:05 PM UTC 24 |
285924407 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.4128612757 |
|
|
Aug 29 12:50:02 PM UTC 24 |
Aug 29 12:50:07 PM UTC 24 |
70529972 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.1874971347 |
|
|
Aug 29 12:49:43 PM UTC 24 |
Aug 29 12:50:07 PM UTC 24 |
3085865284 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.1319827393 |
|
|
Aug 29 12:50:01 PM UTC 24 |
Aug 29 12:50:07 PM UTC 24 |
932848202 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.1997727837 |
|
|
Aug 29 12:49:51 PM UTC 24 |
Aug 29 12:50:07 PM UTC 24 |
15255285717 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.1045258451 |
|
|
Aug 29 12:50:27 PM UTC 24 |
Aug 29 12:51:08 PM UTC 24 |
11927078028 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.2436227748 |
|
|
Aug 29 12:50:06 PM UTC 24 |
Aug 29 12:50:11 PM UTC 24 |
141066884 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.286552535 |
|
|
Aug 29 12:50:06 PM UTC 24 |
Aug 29 12:50:12 PM UTC 24 |
121248621 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.2659732318 |
|
|
Aug 29 12:49:13 PM UTC 24 |
Aug 29 12:50:13 PM UTC 24 |
32678447220 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.3034457732 |
|
|
Aug 29 12:49:59 PM UTC 24 |
Aug 29 12:50:13 PM UTC 24 |
5476973636 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.105547714 |
|
|
Aug 29 12:50:05 PM UTC 24 |
Aug 29 12:50:15 PM UTC 24 |
297212387 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.558867209 |
|
|
Aug 29 12:49:37 PM UTC 24 |
Aug 29 12:50:15 PM UTC 24 |
6875244375 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.1628120697 |
|
|
Aug 29 12:50:09 PM UTC 24 |
Aug 29 12:50:16 PM UTC 24 |
238408675 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.3941756100 |
|
|
Aug 29 12:50:08 PM UTC 24 |
Aug 29 12:50:17 PM UTC 24 |
849752615 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.3772851364 |
|
|
Aug 29 12:50:16 PM UTC 24 |
Aug 29 12:50:18 PM UTC 24 |
20346390 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.1096559819 |
|
|
Aug 29 12:49:32 PM UTC 24 |
Aug 29 12:50:18 PM UTC 24 |
19539681181 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.2541235548 |
|
|
Aug 29 12:50:01 PM UTC 24 |
Aug 29 12:50:19 PM UTC 24 |
13464127460 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.2313302579 |
|
|
Aug 29 12:50:17 PM UTC 24 |
Aug 29 12:50:20 PM UTC 24 |
65105209 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.715351682 |
|
|
Aug 29 12:50:17 PM UTC 24 |
Aug 29 12:50:20 PM UTC 24 |
330218310 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3065337696 |
|
|
Aug 29 12:50:19 PM UTC 24 |
Aug 29 12:50:21 PM UTC 24 |
27374836 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.4190102318 |
|
|
Aug 29 12:48:46 PM UTC 24 |
Aug 29 12:50:21 PM UTC 24 |
4342602609 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.2828587058 |
|
|
Aug 29 12:49:55 PM UTC 24 |
Aug 29 12:51:13 PM UTC 24 |
8886484482 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2126874898 |
|
|
Aug 29 12:49:51 PM UTC 24 |
Aug 29 12:50:23 PM UTC 24 |
2906447114 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.2047504718 |
|
|
Aug 29 12:50:20 PM UTC 24 |
Aug 29 12:50:23 PM UTC 24 |
54448154 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.1453752329 |
|
|
Aug 29 12:50:08 PM UTC 24 |
Aug 29 12:50:25 PM UTC 24 |
567705950 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.3759046752 |
|
|
Aug 29 12:47:43 PM UTC 24 |
Aug 29 12:50:25 PM UTC 24 |
10020014282 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.1401340772 |
|
|
Aug 29 12:50:21 PM UTC 24 |
Aug 29 12:50:27 PM UTC 24 |
4160076268 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.1397859950 |
|
|
Aug 29 12:49:55 PM UTC 24 |
Aug 29 12:50:28 PM UTC 24 |
5010503130 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.1916539222 |
|
|
Aug 29 12:49:04 PM UTC 24 |
Aug 29 12:50:30 PM UTC 24 |
7908004767 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.4073068671 |
|
|
Aug 29 12:50:27 PM UTC 24 |
Aug 29 12:50:33 PM UTC 24 |
130127699 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.4091640836 |
|
|
Aug 29 12:45:38 PM UTC 24 |
Aug 29 12:51:12 PM UTC 24 |
39724418994 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.4274843775 |
|
|
Aug 29 12:48:29 PM UTC 24 |
Aug 29 12:50:33 PM UTC 24 |
88164466994 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.4054771486 |
|
|
Aug 29 12:50:09 PM UTC 24 |
Aug 29 12:50:34 PM UTC 24 |
1780254578 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2788513895 |
|
|
Aug 29 12:50:21 PM UTC 24 |
Aug 29 12:50:36 PM UTC 24 |
10584960464 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.4278046573 |
|
|
Aug 29 12:50:24 PM UTC 24 |
Aug 29 12:50:36 PM UTC 24 |
3169626022 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.2300565598 |
|
|
Aug 29 12:50:34 PM UTC 24 |
Aug 29 12:50:36 PM UTC 24 |
53556656 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.433949980 |
|
|
Aug 29 12:50:24 PM UTC 24 |
Aug 29 12:50:37 PM UTC 24 |
4427273364 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.4027689523 |
|
|
Aug 29 12:50:36 PM UTC 24 |
Aug 29 12:50:38 PM UTC 24 |
40885701 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.3552629925 |
|
|
Aug 29 12:50:36 PM UTC 24 |
Aug 29 12:50:38 PM UTC 24 |
21585835 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.2347478557 |
|
|
Aug 29 12:50:37 PM UTC 24 |
Aug 29 12:50:39 PM UTC 24 |
89053550 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.1995136699 |
|
|
Aug 29 12:50:39 PM UTC 24 |
Aug 29 12:50:41 PM UTC 24 |
26429121 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.2599532464 |
|
|
Aug 29 12:46:12 PM UTC 24 |
Aug 29 12:50:43 PM UTC 24 |
183128911938 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.1662535697 |
|
|
Aug 29 12:50:39 PM UTC 24 |
Aug 29 12:50:43 PM UTC 24 |
136961744 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.3930083119 |
|
|
Aug 29 12:49:46 PM UTC 24 |
Aug 29 12:50:43 PM UTC 24 |
24546630481 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.555345716 |
|
|
Aug 29 12:49:48 PM UTC 24 |
Aug 29 12:50:43 PM UTC 24 |
31839085932 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.899137876 |
|
|
Aug 29 12:50:39 PM UTC 24 |
Aug 29 12:50:44 PM UTC 24 |
224445818 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.2267244265 |
|
|
Aug 29 12:50:24 PM UTC 24 |
Aug 29 12:50:48 PM UTC 24 |
1179188196 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.760242818 |
|
|
Aug 29 12:50:45 PM UTC 24 |
Aug 29 12:50:51 PM UTC 24 |
1840928242 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.364346238 |
|
|
Aug 29 12:50:40 PM UTC 24 |
Aug 29 12:50:52 PM UTC 24 |
3690956294 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.2320497800 |
|
|
Aug 29 12:50:46 PM UTC 24 |
Aug 29 12:50:54 PM UTC 24 |
213080069 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.2314767374 |
|
|
Aug 29 12:50:45 PM UTC 24 |
Aug 29 12:50:54 PM UTC 24 |
240678300 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.3194516726 |
|
|
Aug 29 12:50:37 PM UTC 24 |
Aug 29 12:50:55 PM UTC 24 |
25170569060 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.728565294 |
|
|
Aug 29 12:50:55 PM UTC 24 |
Aug 29 12:50:57 PM UTC 24 |
75170237 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.1822090292 |
|
|
Aug 29 12:50:19 PM UTC 24 |
Aug 29 12:50:58 PM UTC 24 |
1563893785 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.3751546885 |
|
|
Aug 29 12:50:45 PM UTC 24 |
Aug 29 12:50:59 PM UTC 24 |
2336758408 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.215821357 |
|
|
Aug 29 12:48:27 PM UTC 24 |
Aug 29 12:50:59 PM UTC 24 |
6934333216 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.2634904563 |
|
|
Aug 29 12:50:57 PM UTC 24 |
Aug 29 12:50:59 PM UTC 24 |
15346652 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.1578355695 |
|
|
Aug 29 12:50:22 PM UTC 24 |
Aug 29 12:50:59 PM UTC 24 |
2387603827 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.3347003363 |
|
|
Aug 29 12:51:00 PM UTC 24 |
Aug 29 12:51:02 PM UTC 24 |
62437877 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3723468431 |
|
|
Aug 29 12:51:01 PM UTC 24 |
Aug 29 12:51:05 PM UTC 24 |
115034801 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.1708744335 |
|
|
Aug 29 12:50:13 PM UTC 24 |
Aug 29 12:51:06 PM UTC 24 |
2929790240 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.383263106 |
|
|
Aug 29 12:43:37 PM UTC 24 |
Aug 29 12:51:08 PM UTC 24 |
218956986471 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.1749238653 |
|
|
Aug 29 12:51:00 PM UTC 24 |
Aug 29 12:51:08 PM UTC 24 |
177164584 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.3009889913 |
|
|
Aug 29 12:50:29 PM UTC 24 |
Aug 29 12:51:13 PM UTC 24 |
20710071017 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.1794069820 |
|
|
Aug 29 12:51:08 PM UTC 24 |
Aug 29 12:51:13 PM UTC 24 |
605109922 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.616968368 |
|
|
Aug 29 12:51:09 PM UTC 24 |
Aug 29 12:51:15 PM UTC 24 |
188637296 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.3117437507 |
|
|
Aug 29 12:51:03 PM UTC 24 |
Aug 29 12:51:16 PM UTC 24 |
3274297320 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.841045653 |
|
|
Aug 29 12:51:15 PM UTC 24 |
Aug 29 12:51:18 PM UTC 24 |
206568006 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.1253915661 |
|
|
Aug 29 12:51:17 PM UTC 24 |
Aug 29 12:51:19 PM UTC 24 |
12465801 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.903063390 |
|
|
Aug 29 12:47:56 PM UTC 24 |
Aug 29 12:51:19 PM UTC 24 |
19550698939 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.4251599856 |
|
|
Aug 29 12:51:14 PM UTC 24 |
Aug 29 12:51:21 PM UTC 24 |
570057848 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.2440980542 |
|
|
Aug 29 12:51:09 PM UTC 24 |
Aug 29 12:51:22 PM UTC 24 |
1206604334 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.1195467845 |
|
|
Aug 29 12:49:34 PM UTC 24 |
Aug 29 12:51:26 PM UTC 24 |
47682779344 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.711400480 |
|
|
Aug 29 12:47:40 PM UTC 24 |
Aug 29 12:51:26 PM UTC 24 |
48546199012 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.2786844117 |
|
|
Aug 29 12:50:58 PM UTC 24 |
Aug 29 12:51:26 PM UTC 24 |
32776216314 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.2348195721 |
|
|
Aug 29 12:51:02 PM UTC 24 |
Aug 29 12:51:27 PM UTC 24 |
5424342759 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.1946822840 |
|
|
Aug 29 12:50:43 PM UTC 24 |
Aug 29 12:51:29 PM UTC 24 |
2788871084 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.2986467890 |
|
|
Aug 29 12:50:28 PM UTC 24 |
Aug 29 12:51:29 PM UTC 24 |
2382957942 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.204153096 |
|
|
Aug 29 12:50:37 PM UTC 24 |
Aug 29 12:51:31 PM UTC 24 |
43487342417 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3118232514 |
|
|
Aug 29 12:49:16 PM UTC 24 |
Aug 29 12:51:32 PM UTC 24 |
17363063831 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.3100314958 |
|
|
Aug 29 12:48:24 PM UTC 24 |
Aug 29 12:51:38 PM UTC 24 |
36639489180 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.3650813635 |
|
|
Aug 29 12:41:37 PM UTC 24 |
Aug 29 12:51:45 PM UTC 24 |
51310792343 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.814914637 |
|
|
Aug 29 12:49:53 PM UTC 24 |
Aug 29 12:51:46 PM UTC 24 |
16500301375 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.3818149077 |
|
|
Aug 29 12:51:00 PM UTC 24 |
Aug 29 12:51:50 PM UTC 24 |
8899380119 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.3963187098 |
|
|
Aug 29 12:49:56 PM UTC 24 |
Aug 29 12:51:53 PM UTC 24 |
12731576022 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.2025546803 |
|
|
Aug 29 12:50:14 PM UTC 24 |
Aug 29 12:51:58 PM UTC 24 |
19487876557 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.148406457 |
|
|
Aug 29 12:45:16 PM UTC 24 |
Aug 29 12:52:05 PM UTC 24 |
156389514167 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.4202514989 |
|
|
Aug 29 12:50:22 PM UTC 24 |
Aug 29 12:52:06 PM UTC 24 |
5544932536 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.3358453109 |
|
|
Aug 29 12:48:27 PM UTC 24 |
Aug 29 12:52:10 PM UTC 24 |
12429271409 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.1923829322 |
|
|
Aug 29 12:50:55 PM UTC 24 |
Aug 29 12:52:14 PM UTC 24 |
3214343014 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.61148607 |
|
|
Aug 29 12:44:30 PM UTC 24 |
Aug 29 12:52:16 PM UTC 24 |
98267194197 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.3507062958 |
|
|
Aug 29 12:38:45 PM UTC 24 |
Aug 29 12:52:21 PM UTC 24 |
367786120385 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.961387311 |
|
|
Aug 29 12:51:14 PM UTC 24 |
Aug 29 12:52:29 PM UTC 24 |
3495469694 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3348413561 |
|
|
Aug 29 12:46:38 PM UTC 24 |
Aug 29 12:52:32 PM UTC 24 |
146650478083 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.481174403 |
|
|
Aug 29 12:46:29 PM UTC 24 |
Aug 29 12:52:37 PM UTC 24 |
70116094609 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.2101101201 |
|
|
Aug 29 12:51:06 PM UTC 24 |
Aug 29 12:52:47 PM UTC 24 |
23738488251 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3452949202 |
|
|
Aug 29 12:50:31 PM UTC 24 |
Aug 29 12:52:51 PM UTC 24 |
4907390654 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.613495517 |
|
|
Aug 29 12:48:05 PM UTC 24 |
Aug 29 12:52:52 PM UTC 24 |
38312163619 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.3151390233 |
|
|
Aug 29 12:44:04 PM UTC 24 |
Aug 29 12:53:11 PM UTC 24 |
105379935599 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.2858516023 |
|
|
Aug 29 12:48:07 PM UTC 24 |
Aug 29 12:53:23 PM UTC 24 |
30779407613 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.771716411 |
|
|
Aug 29 12:42:17 PM UTC 24 |
Aug 29 12:53:41 PM UTC 24 |
577667331091 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.1244906699 |
|
|
Aug 29 12:50:54 PM UTC 24 |
Aug 29 12:53:45 PM UTC 24 |
11144180456 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.2885131494 |
|
|
Aug 29 12:49:34 PM UTC 24 |
Aug 29 12:53:49 PM UTC 24 |
25554250849 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.4023827328 |
|
|
Aug 29 12:50:53 PM UTC 24 |
Aug 29 12:54:23 PM UTC 24 |
83927974111 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.1794298059 |
|
|
Aug 29 12:45:14 PM UTC 24 |
Aug 29 12:54:48 PM UTC 24 |
70583906265 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.233245155 |
|
|
Aug 29 12:45:40 PM UTC 24 |
Aug 29 12:54:58 PM UTC 24 |
44848899595 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.1297652711 |
|
|
Aug 29 12:51:09 PM UTC 24 |
Aug 29 12:55:06 PM UTC 24 |
82331270452 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.1232235669 |
|
|
Aug 29 12:50:49 PM UTC 24 |
Aug 29 12:55:09 PM UTC 24 |
24318427783 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.1980406742 |
|
|
Aug 29 12:47:18 PM UTC 24 |
Aug 29 12:55:14 PM UTC 24 |
101542478267 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.3697774033 |
|
|
Aug 29 12:40:53 PM UTC 24 |
Aug 29 12:55:32 PM UTC 24 |
79483117002 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.1021437184 |
|
|
Aug 29 12:51:14 PM UTC 24 |
Aug 29 12:55:42 PM UTC 24 |
45450709122 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.3187337309 |
|
|
Aug 29 12:50:13 PM UTC 24 |
Aug 29 12:55:51 PM UTC 24 |
171101922084 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.1190902799 |
|
|
Aug 29 12:49:18 PM UTC 24 |
Aug 29 12:55:52 PM UTC 24 |
88206609371 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.3912319947 |
|
|
Aug 29 12:42:39 PM UTC 24 |
Aug 29 12:55:57 PM UTC 24 |
518340949381 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.3421583479 |
|
|
Aug 29 12:50:14 PM UTC 24 |
Aug 29 12:57:13 PM UTC 24 |
41323597129 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.467637158 |
|
|
Aug 29 12:50:45 PM UTC 24 |
Aug 29 12:58:07 PM UTC 24 |
500470589445 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.1030731116 |
|
|
Aug 29 12:49:40 PM UTC 24 |
Aug 29 12:58:18 PM UTC 24 |
1053922645939 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.3430470583 |
|
|
Aug 29 12:51:14 PM UTC 24 |
Aug 29 12:58:21 PM UTC 24 |
32058938548 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2777510033 |
|
|
Aug 29 12:49:13 PM UTC 24 |
Aug 29 12:58:27 PM UTC 24 |
440873656076 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3144957449 |
|
|
Aug 29 12:47:20 PM UTC 24 |
Aug 29 01:00:32 PM UTC 24 |
72835982320 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.3533654761 |
|
|
Aug 29 12:27:32 PM UTC 24 |
Aug 29 12:27:38 PM UTC 24 |
59192815 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.2570735239 |
|
|
Aug 29 12:27:36 PM UTC 24 |
Aug 29 12:27:38 PM UTC 24 |
24798219 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.2614544393 |
|
|
Aug 29 12:27:39 PM UTC 24 |
Aug 29 12:27:41 PM UTC 24 |
10659643 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.4282869860 |
|
|
Aug 29 12:27:39 PM UTC 24 |
Aug 29 12:27:42 PM UTC 24 |
281030337 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3623046647 |
|
|
Aug 29 12:27:35 PM UTC 24 |
Aug 29 12:27:44 PM UTC 24 |
382138260 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3111231038 |
|
|
Aug 29 12:27:42 PM UTC 24 |
Aug 29 12:27:45 PM UTC 24 |
57157093 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.3827140447 |
|
|
Aug 29 12:27:43 PM UTC 24 |
Aug 29 12:27:47 PM UTC 24 |
123770524 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.3214520161 |
|
|
Aug 29 12:27:49 PM UTC 24 |
Aug 29 12:27:53 PM UTC 24 |
43034155 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3782761343 |
|
|
Aug 29 12:27:55 PM UTC 24 |
Aug 29 12:27:59 PM UTC 24 |
87325867 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3736898891 |
|
|
Aug 29 12:28:02 PM UTC 24 |
Aug 29 12:28:04 PM UTC 24 |
21156847 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.788220385 |
|
|
Aug 29 12:27:59 PM UTC 24 |
Aug 29 12:28:07 PM UTC 24 |
395541296 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.2220044275 |
|
|
Aug 29 12:28:05 PM UTC 24 |
Aug 29 12:28:07 PM UTC 24 |
33912149 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.384650578 |
|
|
Aug 29 12:28:07 PM UTC 24 |
Aug 29 12:28:11 PM UTC 24 |
63027142 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.638905998 |
|
|
Aug 29 12:28:08 PM UTC 24 |
Aug 29 12:28:11 PM UTC 24 |
23874696 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.2306438168 |
|
|
Aug 29 12:27:45 PM UTC 24 |
Aug 29 12:28:12 PM UTC 24 |
2580214360 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.352424255 |
|
|
Aug 29 12:28:12 PM UTC 24 |
Aug 29 12:28:15 PM UTC 24 |
45392904 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.2409350156 |
|
|
Aug 29 12:28:00 PM UTC 24 |
Aug 29 12:28:17 PM UTC 24 |
203968261 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3857753397 |
|
|
Aug 29 12:28:15 PM UTC 24 |
Aug 29 12:28:19 PM UTC 24 |
68930975 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3948336515 |
|
|
Aug 29 12:28:15 PM UTC 24 |
Aug 29 12:28:22 PM UTC 24 |
154833192 ps |
| T1036 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.1089398382 |
|
|
Aug 29 12:28:22 PM UTC 24 |
Aug 29 12:28:24 PM UTC 24 |
27877054 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.129869262 |
|
|
Aug 29 12:28:18 PM UTC 24 |
Aug 29 12:28:24 PM UTC 24 |
1141501926 ps |
| T1037 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2140137421 |
|
|
Aug 29 12:28:24 PM UTC 24 |
Aug 29 12:28:26 PM UTC 24 |
10429502 ps |
| T103 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1161012804 |
|
|
Aug 29 12:28:25 PM UTC 24 |
Aug 29 12:28:28 PM UTC 24 |
22395963 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_28/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.2281535975 |
|
|
Aug 29 12:28:25 PM UTC 24 |
Aug 29 12:28:28 PM UTC 24 |
82738710 ps |