| T834 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.2508090687 |
|
|
Sep 01 08:44:07 PM UTC 24 |
Sep 01 08:44:09 PM UTC 24 |
78277386 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.1015332787 |
|
|
Sep 01 08:44:08 PM UTC 24 |
Sep 01 08:44:11 PM UTC 24 |
87139821 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.4257759110 |
|
|
Sep 01 08:40:24 PM UTC 24 |
Sep 01 08:44:13 PM UTC 24 |
39629569536 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.1727042140 |
|
|
Sep 01 08:44:09 PM UTC 24 |
Sep 01 08:44:13 PM UTC 24 |
114725773 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.1432724211 |
|
|
Sep 01 08:43:58 PM UTC 24 |
Sep 01 08:44:15 PM UTC 24 |
10028116135 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.2567916438 |
|
|
Sep 01 08:42:27 PM UTC 24 |
Sep 01 08:44:15 PM UTC 24 |
57456714331 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.984911197 |
|
|
Sep 01 08:44:11 PM UTC 24 |
Sep 01 08:44:17 PM UTC 24 |
180351473 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.2994244350 |
|
|
Sep 01 08:43:27 PM UTC 24 |
Sep 01 08:44:18 PM UTC 24 |
28017386650 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.922404529 |
|
|
Sep 01 08:42:53 PM UTC 24 |
Sep 01 08:44:19 PM UTC 24 |
30835247825 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.2776928771 |
|
|
Sep 01 08:44:13 PM UTC 24 |
Sep 01 08:44:21 PM UTC 24 |
932191179 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3400757976 |
|
|
Sep 01 08:44:16 PM UTC 24 |
Sep 01 08:44:24 PM UTC 24 |
398405886 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.3166123355 |
|
|
Sep 01 08:43:40 PM UTC 24 |
Sep 01 08:44:25 PM UTC 24 |
3091922270 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.3317394868 |
|
|
Sep 01 08:44:01 PM UTC 24 |
Sep 01 08:44:25 PM UTC 24 |
6842858863 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.1615874855 |
|
|
Sep 01 08:40:53 PM UTC 24 |
Sep 01 08:44:26 PM UTC 24 |
83558097211 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.3553659615 |
|
|
Sep 01 08:44:25 PM UTC 24 |
Sep 01 08:44:27 PM UTC 24 |
32409691 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.2329240057 |
|
|
Sep 01 08:44:07 PM UTC 24 |
Sep 01 08:44:27 PM UTC 24 |
8408252814 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.170445463 |
|
|
Sep 01 08:44:08 PM UTC 24 |
Sep 01 08:44:28 PM UTC 24 |
10229644895 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.2639087368 |
|
|
Sep 01 08:44:26 PM UTC 24 |
Sep 01 08:44:28 PM UTC 24 |
26716783 ps |
| T91 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.4272054519 |
|
|
Sep 01 08:42:18 PM UTC 24 |
Sep 01 08:44:28 PM UTC 24 |
37827428815 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.3085481266 |
|
|
Sep 01 08:43:12 PM UTC 24 |
Sep 01 08:44:29 PM UTC 24 |
9990952829 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.1080971084 |
|
|
Sep 01 08:41:53 PM UTC 24 |
Sep 01 08:44:29 PM UTC 24 |
43057826200 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.283950278 |
|
|
Sep 01 08:44:28 PM UTC 24 |
Sep 01 08:44:30 PM UTC 24 |
29391524 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.3050036654 |
|
|
Sep 01 08:44:28 PM UTC 24 |
Sep 01 08:44:30 PM UTC 24 |
13334696 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.955038780 |
|
|
Sep 01 08:44:26 PM UTC 24 |
Sep 01 08:44:31 PM UTC 24 |
2214274039 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.4168498300 |
|
|
Sep 01 08:43:11 PM UTC 24 |
Sep 01 08:44:35 PM UTC 24 |
17587994089 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.1660541402 |
|
|
Sep 01 08:44:00 PM UTC 24 |
Sep 01 08:44:35 PM UTC 24 |
4597316751 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1237721436 |
|
|
Sep 01 08:44:29 PM UTC 24 |
Sep 01 08:44:35 PM UTC 24 |
183042103 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.4243569691 |
|
|
Sep 01 08:44:09 PM UTC 24 |
Sep 01 08:44:35 PM UTC 24 |
13233145814 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.3379722812 |
|
|
Sep 01 08:44:29 PM UTC 24 |
Sep 01 08:44:37 PM UTC 24 |
152737687 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.2383510829 |
|
|
Sep 01 08:44:29 PM UTC 24 |
Sep 01 08:44:37 PM UTC 24 |
693535236 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.1954765497 |
|
|
Sep 01 08:44:32 PM UTC 24 |
Sep 01 08:44:39 PM UTC 24 |
2133347411 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.2818678852 |
|
|
Sep 01 08:44:37 PM UTC 24 |
Sep 01 08:44:39 PM UTC 24 |
22796795 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.2391754317 |
|
|
Sep 01 08:42:18 PM UTC 24 |
Sep 01 08:44:40 PM UTC 24 |
24595341495 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.3853531710 |
|
|
Sep 01 08:44:31 PM UTC 24 |
Sep 01 08:44:40 PM UTC 24 |
1315127515 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3869597108 |
|
|
Sep 01 08:44:31 PM UTC 24 |
Sep 01 08:44:41 PM UTC 24 |
774189133 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.3490153641 |
|
|
Sep 01 08:44:39 PM UTC 24 |
Sep 01 08:44:42 PM UTC 24 |
24916968 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.3811397899 |
|
|
Sep 01 08:44:42 PM UTC 24 |
Sep 01 08:44:44 PM UTC 24 |
134752730 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.3422645835 |
|
|
Sep 01 08:44:42 PM UTC 24 |
Sep 01 08:44:44 PM UTC 24 |
31159283 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.3769206190 |
|
|
Sep 01 08:40:50 PM UTC 24 |
Sep 01 08:44:46 PM UTC 24 |
34945829073 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1171071685 |
|
|
Sep 01 08:44:01 PM UTC 24 |
Sep 01 08:44:46 PM UTC 24 |
15270184508 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.2460635272 |
|
|
Sep 01 08:42:34 PM UTC 24 |
Sep 01 08:44:49 PM UTC 24 |
21002637602 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.848118226 |
|
|
Sep 01 08:44:35 PM UTC 24 |
Sep 01 08:44:50 PM UTC 24 |
1127471320 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.136611554 |
|
|
Sep 01 08:44:45 PM UTC 24 |
Sep 01 08:44:52 PM UTC 24 |
144914165 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.3469901081 |
|
|
Sep 01 08:44:47 PM UTC 24 |
Sep 01 08:44:58 PM UTC 24 |
1926813310 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.3618505335 |
|
|
Sep 01 08:44:31 PM UTC 24 |
Sep 01 08:45:00 PM UTC 24 |
4364720916 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2729912071 |
|
|
Sep 01 08:40:27 PM UTC 24 |
Sep 01 08:45:03 PM UTC 24 |
73933337764 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.3227200701 |
|
|
Sep 01 08:44:50 PM UTC 24 |
Sep 01 08:45:03 PM UTC 24 |
3109889938 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.1082856526 |
|
|
Sep 01 08:44:14 PM UTC 24 |
Sep 01 08:45:06 PM UTC 24 |
3584640907 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.3159632750 |
|
|
Sep 01 08:44:41 PM UTC 24 |
Sep 01 08:45:06 PM UTC 24 |
2211398703 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.4146796972 |
|
|
Sep 01 08:44:58 PM UTC 24 |
Sep 01 08:45:06 PM UTC 24 |
200465191 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.3490009019 |
|
|
Sep 01 08:44:27 PM UTC 24 |
Sep 01 08:45:08 PM UTC 24 |
4471711074 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.1138908350 |
|
|
Sep 01 08:44:51 PM UTC 24 |
Sep 01 08:45:08 PM UTC 24 |
4422659795 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.2097104075 |
|
|
Sep 01 08:45:07 PM UTC 24 |
Sep 01 08:45:09 PM UTC 24 |
12163161 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.2060436579 |
|
|
Sep 01 08:44:40 PM UTC 24 |
Sep 01 08:45:10 PM UTC 24 |
4980861282 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.3737174450 |
|
|
Sep 01 08:45:08 PM UTC 24 |
Sep 01 08:45:10 PM UTC 24 |
21230207 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.361225633 |
|
|
Sep 01 08:45:08 PM UTC 24 |
Sep 01 08:45:10 PM UTC 24 |
24534210 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.2517285047 |
|
|
Sep 01 08:44:45 PM UTC 24 |
Sep 01 08:45:11 PM UTC 24 |
148835551276 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.818575440 |
|
|
Sep 01 08:35:41 PM UTC 24 |
Sep 01 08:45:12 PM UTC 24 |
210119421339 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1229633711 |
|
|
Sep 01 08:45:10 PM UTC 24 |
Sep 01 08:45:12 PM UTC 24 |
56607933 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3872746104 |
|
|
Sep 01 08:43:46 PM UTC 24 |
Sep 01 08:45:13 PM UTC 24 |
33863175596 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.449902052 |
|
|
Sep 01 08:43:16 PM UTC 24 |
Sep 01 08:45:14 PM UTC 24 |
25226933764 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.2464239 |
|
|
Sep 01 08:39:38 PM UTC 24 |
Sep 01 08:45:14 PM UTC 24 |
70055851196 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.912677544 |
|
|
Sep 01 08:45:09 PM UTC 24 |
Sep 01 08:45:15 PM UTC 24 |
347080184 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2012792894 |
|
|
Sep 01 08:45:11 PM UTC 24 |
Sep 01 08:45:17 PM UTC 24 |
174796294 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.195232823 |
|
|
Sep 01 08:45:12 PM UTC 24 |
Sep 01 08:45:18 PM UTC 24 |
889686079 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.479288781 |
|
|
Sep 01 08:43:32 PM UTC 24 |
Sep 01 08:45:20 PM UTC 24 |
8470880127 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.2400683699 |
|
|
Sep 01 08:45:11 PM UTC 24 |
Sep 01 08:45:20 PM UTC 24 |
412454128 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.4158376888 |
|
|
Sep 01 08:45:12 PM UTC 24 |
Sep 01 08:45:22 PM UTC 24 |
322093902 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.4239108149 |
|
|
Sep 01 08:45:15 PM UTC 24 |
Sep 01 08:45:25 PM UTC 24 |
355162018 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.1251032152 |
|
|
Sep 01 08:45:23 PM UTC 24 |
Sep 01 08:45:26 PM UTC 24 |
20594666 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.3681852625 |
|
|
Sep 01 08:42:30 PM UTC 24 |
Sep 01 08:45:26 PM UTC 24 |
19145769859 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.2558821944 |
|
|
Sep 01 08:45:16 PM UTC 24 |
Sep 01 08:45:27 PM UTC 24 |
915030551 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1061242888 |
|
|
Sep 01 08:43:48 PM UTC 24 |
Sep 01 08:45:27 PM UTC 24 |
17216383207 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.1845697132 |
|
|
Sep 01 08:45:25 PM UTC 24 |
Sep 01 08:45:28 PM UTC 24 |
18030038 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1931581833 |
|
|
Sep 01 08:44:52 PM UTC 24 |
Sep 01 08:45:28 PM UTC 24 |
14392325439 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.3393191818 |
|
|
Sep 01 08:44:43 PM UTC 24 |
Sep 01 08:45:28 PM UTC 24 |
36319360541 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.3519985753 |
|
|
Sep 01 08:41:35 PM UTC 24 |
Sep 01 08:45:30 PM UTC 24 |
19885521383 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2834131392 |
|
|
Sep 01 08:45:28 PM UTC 24 |
Sep 01 08:45:30 PM UTC 24 |
31561654 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.158271251 |
|
|
Sep 01 08:45:26 PM UTC 24 |
Sep 01 08:45:32 PM UTC 24 |
818265940 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.597228958 |
|
|
Sep 01 08:45:29 PM UTC 24 |
Sep 01 08:45:34 PM UTC 24 |
181314389 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2654113913 |
|
|
Sep 01 08:44:16 PM UTC 24 |
Sep 01 08:45:37 PM UTC 24 |
53408151453 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.1099773861 |
|
|
Sep 01 08:45:35 PM UTC 24 |
Sep 01 08:45:39 PM UTC 24 |
142592950 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.641803765 |
|
|
Sep 01 08:45:31 PM UTC 24 |
Sep 01 08:45:40 PM UTC 24 |
832702554 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.2565637824 |
|
|
Sep 01 08:45:11 PM UTC 24 |
Sep 01 08:45:41 PM UTC 24 |
29583531780 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1773076027 |
|
|
Sep 01 08:45:29 PM UTC 24 |
Sep 01 08:45:42 PM UTC 24 |
1571411156 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.944091440 |
|
|
Sep 01 08:44:10 PM UTC 24 |
Sep 01 08:45:44 PM UTC 24 |
9947279057 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.141614996 |
|
|
Sep 01 08:41:23 PM UTC 24 |
Sep 01 08:45:45 PM UTC 24 |
14758757817 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.871995028 |
|
|
Sep 01 08:45:14 PM UTC 24 |
Sep 01 08:45:46 PM UTC 24 |
18035288810 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.3844571566 |
|
|
Sep 01 08:45:39 PM UTC 24 |
Sep 01 08:45:46 PM UTC 24 |
2468913944 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.477093279 |
|
|
Sep 01 08:45:14 PM UTC 24 |
Sep 01 08:45:48 PM UTC 24 |
5159973392 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.210045956 |
|
|
Sep 01 08:45:46 PM UTC 24 |
Sep 01 08:45:48 PM UTC 24 |
29000256 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.665589379 |
|
|
Sep 01 08:45:47 PM UTC 24 |
Sep 01 08:45:49 PM UTC 24 |
24901258 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.21260715 |
|
|
Sep 01 08:45:33 PM UTC 24 |
Sep 01 08:45:50 PM UTC 24 |
1117562107 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.4259693576 |
|
|
Sep 01 08:45:29 PM UTC 24 |
Sep 01 08:45:51 PM UTC 24 |
3304402356 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2880379256 |
|
|
Sep 01 08:45:49 PM UTC 24 |
Sep 01 08:45:51 PM UTC 24 |
51104911 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.331486256 |
|
|
Sep 01 08:45:00 PM UTC 24 |
Sep 01 08:45:52 PM UTC 24 |
18741999890 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.116851829 |
|
|
Sep 01 08:45:47 PM UTC 24 |
Sep 01 08:45:53 PM UTC 24 |
776034374 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.1898595946 |
|
|
Sep 01 08:45:29 PM UTC 24 |
Sep 01 08:45:54 PM UTC 24 |
4180787423 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.212854551 |
|
|
Sep 01 08:45:50 PM UTC 24 |
Sep 01 08:45:54 PM UTC 24 |
526620887 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3602870849 |
|
|
Sep 01 08:42:57 PM UTC 24 |
Sep 01 08:45:56 PM UTC 24 |
16387431674 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.1152393338 |
|
|
Sep 01 08:45:28 PM UTC 24 |
Sep 01 08:45:59 PM UTC 24 |
1794059191 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.663225748 |
|
|
Sep 01 08:45:55 PM UTC 24 |
Sep 01 08:45:59 PM UTC 24 |
82340057 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3827657078 |
|
|
Sep 01 08:43:32 PM UTC 24 |
Sep 01 08:46:00 PM UTC 24 |
39530541231 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.143896330 |
|
|
Sep 01 08:38:33 PM UTC 24 |
Sep 01 08:46:00 PM UTC 24 |
40433748507 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.2588744448 |
|
|
Sep 01 08:45:18 PM UTC 24 |
Sep 01 08:46:00 PM UTC 24 |
47681656524 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.2400558569 |
|
|
Sep 01 08:45:51 PM UTC 24 |
Sep 01 08:46:03 PM UTC 24 |
8365160716 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.1538798838 |
|
|
Sep 01 08:46:03 PM UTC 24 |
Sep 01 08:46:06 PM UTC 24 |
14626562 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.185466921 |
|
|
Sep 01 08:43:58 PM UTC 24 |
Sep 01 08:46:07 PM UTC 24 |
55044111148 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.3376770056 |
|
|
Sep 01 08:46:07 PM UTC 24 |
Sep 01 08:46:09 PM UTC 24 |
44575670 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.4139261710 |
|
|
Sep 01 08:45:31 PM UTC 24 |
Sep 01 08:46:10 PM UTC 24 |
12614062664 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.284763006 |
|
|
Sep 01 08:45:59 PM UTC 24 |
Sep 01 08:46:12 PM UTC 24 |
2680402422 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3232847468 |
|
|
Sep 01 08:46:11 PM UTC 24 |
Sep 01 08:46:13 PM UTC 24 |
180348148 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.1527260911 |
|
|
Sep 01 08:44:36 PM UTC 24 |
Sep 01 08:46:14 PM UTC 24 |
9788230067 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.3383746511 |
|
|
Sep 01 08:45:49 PM UTC 24 |
Sep 01 08:46:15 PM UTC 24 |
5729710354 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.3346565467 |
|
|
Sep 01 08:46:13 PM UTC 24 |
Sep 01 08:46:15 PM UTC 24 |
16173162 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.2190317732 |
|
|
Sep 01 08:46:10 PM UTC 24 |
Sep 01 08:46:16 PM UTC 24 |
228625403 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3334334010 |
|
|
Sep 01 08:45:57 PM UTC 24 |
Sep 01 08:46:19 PM UTC 24 |
2937536503 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.2353592349 |
|
|
Sep 01 08:45:53 PM UTC 24 |
Sep 01 08:46:20 PM UTC 24 |
2587637832 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.3577138324 |
|
|
Sep 01 08:45:55 PM UTC 24 |
Sep 01 08:46:22 PM UTC 24 |
1831851658 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.1491028681 |
|
|
Sep 01 08:46:14 PM UTC 24 |
Sep 01 08:46:22 PM UTC 24 |
913557334 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.1568018047 |
|
|
Sep 01 08:45:54 PM UTC 24 |
Sep 01 08:46:24 PM UTC 24 |
13359655477 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.898519693 |
|
|
Sep 01 08:40:51 PM UTC 24 |
Sep 01 08:46:25 PM UTC 24 |
123223047170 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.1195542410 |
|
|
Sep 01 08:46:20 PM UTC 24 |
Sep 01 08:46:25 PM UTC 24 |
243700144 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.2302898754 |
|
|
Sep 01 08:46:21 PM UTC 24 |
Sep 01 08:46:26 PM UTC 24 |
436251168 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.815886158 |
|
|
Sep 01 08:46:17 PM UTC 24 |
Sep 01 08:46:27 PM UTC 24 |
3935587073 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.304601648 |
|
|
Sep 01 08:44:36 PM UTC 24 |
Sep 01 08:46:28 PM UTC 24 |
31416689736 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.3709136483 |
|
|
Sep 01 08:35:26 PM UTC 24 |
Sep 01 08:46:30 PM UTC 24 |
143638140349 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.4177072753 |
|
|
Sep 01 08:46:28 PM UTC 24 |
Sep 01 08:46:30 PM UTC 24 |
34167526 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.3063225411 |
|
|
Sep 01 08:46:29 PM UTC 24 |
Sep 01 08:46:32 PM UTC 24 |
37615316 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.880482539 |
|
|
Sep 01 08:45:51 PM UTC 24 |
Sep 01 08:46:32 PM UTC 24 |
7529013448 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.208484643 |
|
|
Sep 01 08:46:23 PM UTC 24 |
Sep 01 08:46:32 PM UTC 24 |
834081268 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.1356739151 |
|
|
Sep 01 08:46:25 PM UTC 24 |
Sep 01 08:46:33 PM UTC 24 |
499266357 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.4176863756 |
|
|
Sep 01 08:46:31 PM UTC 24 |
Sep 01 08:46:34 PM UTC 24 |
29853949 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1525448548 |
|
|
Sep 01 08:43:43 PM UTC 24 |
Sep 01 08:46:34 PM UTC 24 |
11973742333 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.2065206700 |
|
|
Sep 01 08:46:32 PM UTC 24 |
Sep 01 08:46:35 PM UTC 24 |
30536586 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2721125590 |
|
|
Sep 01 08:46:09 PM UTC 24 |
Sep 01 08:46:35 PM UTC 24 |
14652261424 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.3139294917 |
|
|
Sep 01 08:46:16 PM UTC 24 |
Sep 01 08:46:35 PM UTC 24 |
1820610418 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2646443847 |
|
|
Sep 01 08:46:15 PM UTC 24 |
Sep 01 08:46:36 PM UTC 24 |
4431666160 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.3389523954 |
|
|
Sep 01 08:45:41 PM UTC 24 |
Sep 01 08:46:36 PM UTC 24 |
48252710789 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.363916535 |
|
|
Sep 01 08:46:16 PM UTC 24 |
Sep 01 08:46:37 PM UTC 24 |
3071808538 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.2809939446 |
|
|
Sep 01 08:46:32 PM UTC 24 |
Sep 01 08:46:38 PM UTC 24 |
77751745 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.108978261 |
|
|
Sep 01 08:46:34 PM UTC 24 |
Sep 01 08:46:38 PM UTC 24 |
57479273 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2082172297 |
|
|
Sep 01 08:46:34 PM UTC 24 |
Sep 01 08:46:39 PM UTC 24 |
240595032 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.2485341098 |
|
|
Sep 01 08:46:35 PM UTC 24 |
Sep 01 08:46:40 PM UTC 24 |
214033969 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.227671094 |
|
|
Sep 01 08:46:31 PM UTC 24 |
Sep 01 08:46:41 PM UTC 24 |
5686180079 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.290909264 |
|
|
Sep 01 08:46:41 PM UTC 24 |
Sep 01 08:46:43 PM UTC 24 |
40484107 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.851178711 |
|
|
Sep 01 08:44:20 PM UTC 24 |
Sep 01 08:46:43 PM UTC 24 |
190377973060 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.2211217226 |
|
|
Sep 01 08:46:36 PM UTC 24 |
Sep 01 08:46:43 PM UTC 24 |
384168908 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.3064925095 |
|
|
Sep 01 08:46:42 PM UTC 24 |
Sep 01 08:46:44 PM UTC 24 |
47211090 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2338143940 |
|
|
Sep 01 08:46:44 PM UTC 24 |
Sep 01 08:46:46 PM UTC 24 |
427567290 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.51742139 |
|
|
Sep 01 08:46:44 PM UTC 24 |
Sep 01 08:46:48 PM UTC 24 |
390412109 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.344315185 |
|
|
Sep 01 08:46:45 PM UTC 24 |
Sep 01 08:46:48 PM UTC 24 |
94942700 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.343505979 |
|
|
Sep 01 08:38:12 PM UTC 24 |
Sep 01 08:46:49 PM UTC 24 |
588194160374 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2976779805 |
|
|
Sep 01 08:46:36 PM UTC 24 |
Sep 01 08:46:51 PM UTC 24 |
1038748359 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.3109349213 |
|
|
Sep 01 08:44:02 PM UTC 24 |
Sep 01 08:46:52 PM UTC 24 |
336110827954 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.4125982826 |
|
|
Sep 01 08:46:44 PM UTC 24 |
Sep 01 08:46:52 PM UTC 24 |
591213112 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.1643231239 |
|
|
Sep 01 08:41:06 PM UTC 24 |
Sep 01 08:46:53 PM UTC 24 |
134699693448 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.3350573577 |
|
|
Sep 01 08:43:18 PM UTC 24 |
Sep 01 08:46:55 PM UTC 24 |
68551573332 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.3503798075 |
|
|
Sep 01 08:44:19 PM UTC 24 |
Sep 01 08:46:56 PM UTC 24 |
13265660722 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.4042955636 |
|
|
Sep 01 08:46:37 PM UTC 24 |
Sep 01 08:47:00 PM UTC 24 |
2469279090 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.152618926 |
|
|
Sep 01 08:46:47 PM UTC 24 |
Sep 01 08:47:00 PM UTC 24 |
3032799131 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.321794712 |
|
|
Sep 01 08:46:48 PM UTC 24 |
Sep 01 08:47:01 PM UTC 24 |
7982843200 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.2069024354 |
|
|
Sep 01 08:46:53 PM UTC 24 |
Sep 01 08:47:01 PM UTC 24 |
1603359815 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.2647070466 |
|
|
Sep 01 08:46:56 PM UTC 24 |
Sep 01 08:47:03 PM UTC 24 |
637215575 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.3690148485 |
|
|
Sep 01 08:47:02 PM UTC 24 |
Sep 01 08:47:04 PM UTC 24 |
40531150 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2292889076 |
|
|
Sep 01 08:45:15 PM UTC 24 |
Sep 01 08:47:05 PM UTC 24 |
9449449044 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.613378345 |
|
|
Sep 01 08:46:27 PM UTC 24 |
Sep 01 08:47:05 PM UTC 24 |
5445818805 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.3972090714 |
|
|
Sep 01 08:45:43 PM UTC 24 |
Sep 01 08:47:06 PM UTC 24 |
21227797760 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.942473030 |
|
|
Sep 01 08:46:00 PM UTC 24 |
Sep 01 08:47:06 PM UTC 24 |
6720467465 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.3689213790 |
|
|
Sep 01 08:46:36 PM UTC 24 |
Sep 01 08:47:09 PM UTC 24 |
11393930130 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.3636403908 |
|
|
Sep 01 08:46:49 PM UTC 24 |
Sep 01 08:47:13 PM UTC 24 |
6577512301 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.3615439019 |
|
|
Sep 01 08:41:37 PM UTC 24 |
Sep 01 08:47:14 PM UTC 24 |
407968225832 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.640444435 |
|
|
Sep 01 08:46:52 PM UTC 24 |
Sep 01 08:47:15 PM UTC 24 |
8854584840 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.687852871 |
|
|
Sep 01 08:44:47 PM UTC 24 |
Sep 01 08:47:15 PM UTC 24 |
88179044832 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.199538032 |
|
|
Sep 01 08:41:52 PM UTC 24 |
Sep 01 08:47:15 PM UTC 24 |
29523851097 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.2633622804 |
|
|
Sep 01 08:36:20 PM UTC 24 |
Sep 01 08:47:20 PM UTC 24 |
67875356729 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.3789449643 |
|
|
Sep 01 08:46:57 PM UTC 24 |
Sep 01 08:47:22 PM UTC 24 |
1157070513 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.1049070701 |
|
|
Sep 01 08:46:53 PM UTC 24 |
Sep 01 08:47:28 PM UTC 24 |
1922565787 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.2373810156 |
|
|
Sep 01 08:45:54 PM UTC 24 |
Sep 01 08:47:28 PM UTC 24 |
13264754080 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.3536898853 |
|
|
Sep 01 08:46:35 PM UTC 24 |
Sep 01 08:47:31 PM UTC 24 |
4077395721 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.12625423 |
|
|
Sep 01 08:43:29 PM UTC 24 |
Sep 01 08:47:43 PM UTC 24 |
24334385058 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.80029364 |
|
|
Sep 01 08:46:26 PM UTC 24 |
Sep 01 08:47:45 PM UTC 24 |
2578743386 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.368503142 |
|
|
Sep 01 08:45:38 PM UTC 24 |
Sep 01 08:47:46 PM UTC 24 |
30265601302 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.4145696191 |
|
|
Sep 01 08:45:04 PM UTC 24 |
Sep 01 08:47:54 PM UTC 24 |
103387700900 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.2716131922 |
|
|
Sep 01 08:46:38 PM UTC 24 |
Sep 01 08:47:57 PM UTC 24 |
8236513754 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.1447291637 |
|
|
Sep 01 08:42:06 PM UTC 24 |
Sep 01 08:47:59 PM UTC 24 |
145380908234 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.816917401 |
|
|
Sep 01 08:44:19 PM UTC 24 |
Sep 01 08:48:00 PM UTC 24 |
21957936890 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.3686364485 |
|
|
Sep 01 08:46:50 PM UTC 24 |
Sep 01 08:48:01 PM UTC 24 |
53031226187 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2132615208 |
|
|
Sep 01 08:45:04 PM UTC 24 |
Sep 01 08:48:01 PM UTC 24 |
30997454439 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.2304584247 |
|
|
Sep 01 08:45:20 PM UTC 24 |
Sep 01 08:48:11 PM UTC 24 |
9780807278 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.2904927868 |
|
|
Sep 01 08:44:36 PM UTC 24 |
Sep 01 08:48:12 PM UTC 24 |
109151147541 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.409313187 |
|
|
Sep 01 08:45:20 PM UTC 24 |
Sep 01 08:48:24 PM UTC 24 |
16770363070 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.2969660530 |
|
|
Sep 01 08:44:22 PM UTC 24 |
Sep 01 08:48:31 PM UTC 24 |
62111209738 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.4126753529 |
|
|
Sep 01 08:43:49 PM UTC 24 |
Sep 01 08:48:32 PM UTC 24 |
96716210261 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.1197221127 |
|
|
Sep 01 08:47:01 PM UTC 24 |
Sep 01 08:48:33 PM UTC 24 |
11352626044 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.3899326272 |
|
|
Sep 01 08:46:37 PM UTC 24 |
Sep 01 08:48:38 PM UTC 24 |
10582736442 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.4175808918 |
|
|
Sep 01 08:47:01 PM UTC 24 |
Sep 01 08:48:46 PM UTC 24 |
4185637119 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.2463640914 |
|
|
Sep 01 08:40:13 PM UTC 24 |
Sep 01 08:48:53 PM UTC 24 |
424236710004 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.1595832364 |
|
|
Sep 01 08:46:23 PM UTC 24 |
Sep 01 08:48:55 PM UTC 24 |
18632882872 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.2848405102 |
|
|
Sep 01 08:46:40 PM UTC 24 |
Sep 01 08:49:06 PM UTC 24 |
37205166455 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.1909519682 |
|
|
Sep 01 08:42:56 PM UTC 24 |
Sep 01 08:49:12 PM UTC 24 |
34278204020 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.3475802215 |
|
|
Sep 01 08:39:04 PM UTC 24 |
Sep 01 08:49:20 PM UTC 24 |
381314653705 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.676534572 |
|
|
Sep 01 08:44:02 PM UTC 24 |
Sep 01 08:49:26 PM UTC 24 |
25596370134 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.3957515345 |
|
|
Sep 01 08:45:45 PM UTC 24 |
Sep 01 08:49:29 PM UTC 24 |
11804630632 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.3995350872 |
|
|
Sep 01 08:44:03 PM UTC 24 |
Sep 01 08:49:31 PM UTC 24 |
147662533890 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.355703186 |
|
|
Sep 01 08:42:46 PM UTC 24 |
Sep 01 08:49:36 PM UTC 24 |
69271034798 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.812878309 |
|
|
Sep 01 08:43:18 PM UTC 24 |
Sep 01 08:49:53 PM UTC 24 |
71406856366 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.472212389 |
|
|
Sep 01 08:42:32 PM UTC 24 |
Sep 01 08:49:57 PM UTC 24 |
220134416772 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.1125988673 |
|
|
Sep 01 08:36:08 PM UTC 24 |
Sep 01 08:51:13 PM UTC 24 |
396598400431 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3943460967 |
|
|
Sep 01 08:46:38 PM UTC 24 |
Sep 01 08:51:30 PM UTC 24 |
27497310548 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3624178718 |
|
|
Sep 01 08:46:54 PM UTC 24 |
Sep 01 08:51:39 PM UTC 24 |
125506857298 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.809596385 |
|
|
Sep 01 08:42:18 PM UTC 24 |
Sep 01 08:51:45 PM UTC 24 |
37982215815 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.1022527722 |
|
|
Sep 01 08:44:03 PM UTC 24 |
Sep 01 08:51:52 PM UTC 24 |
31599753048 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3647051532 |
|
|
Sep 01 08:46:26 PM UTC 24 |
Sep 01 08:52:43 PM UTC 24 |
128703012046 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.2815041383 |
|
|
Sep 01 08:46:00 PM UTC 24 |
Sep 01 08:53:06 PM UTC 24 |
31731709212 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.2512254858 |
|
|
Sep 01 08:34:55 PM UTC 24 |
Sep 01 08:53:24 PM UTC 24 |
1335242654956 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.1437532109 |
|
|
Sep 01 08:44:37 PM UTC 24 |
Sep 01 08:53:41 PM UTC 24 |
116931767874 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.3210514756 |
|
|
Sep 01 08:46:00 PM UTC 24 |
Sep 01 08:53:52 PM UTC 24 |
39499900045 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.121978712 |
|
|
Sep 01 08:47:01 PM UTC 24 |
Sep 01 08:54:05 PM UTC 24 |
68953532686 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.3088765139 |
|
|
Sep 01 08:46:37 PM UTC 24 |
Sep 01 08:54:07 PM UTC 24 |
80809636009 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.2471116777 |
|
|
Sep 01 08:44:32 PM UTC 24 |
Sep 01 08:56:41 PM UTC 24 |
281077205376 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.858174552 |
|
|
Sep 01 08:43:31 PM UTC 24 |
Sep 01 08:56:54 PM UTC 24 |
56076266336 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.2913202575 |
|
|
Sep 01 08:46:01 PM UTC 24 |
Sep 01 08:57:03 PM UTC 24 |
55167563747 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.4141303108 |
|
|
Sep 01 08:45:07 PM UTC 24 |
Sep 01 08:57:41 PM UTC 24 |
63572832592 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.4035445170 |
|
|
Sep 01 08:45:43 PM UTC 24 |
Sep 01 08:57:46 PM UTC 24 |
95306775410 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.890752848 |
|
|
Sep 01 08:45:19 PM UTC 24 |
Sep 01 08:57:49 PM UTC 24 |
301139601770 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.1677870683 |
|
|
Sep 01 08:47:05 PM UTC 24 |
Sep 01 08:47:08 PM UTC 24 |
18718695 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3123823058 |
|
|
Sep 01 08:47:07 PM UTC 24 |
Sep 01 08:47:09 PM UTC 24 |
37046263 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3127453666 |
|
|
Sep 01 08:47:07 PM UTC 24 |
Sep 01 08:47:09 PM UTC 24 |
69046569 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1891401773 |
|
|
Sep 01 08:47:07 PM UTC 24 |
Sep 01 08:47:11 PM UTC 24 |
238344134 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.307244269 |
|
|
Sep 01 08:47:04 PM UTC 24 |
Sep 01 08:47:11 PM UTC 24 |
473643077 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2096274874 |
|
|
Sep 01 08:47:09 PM UTC 24 |
Sep 01 08:47:13 PM UTC 24 |
81805887 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3884419691 |
|
|
Sep 01 08:47:11 PM UTC 24 |
Sep 01 08:47:16 PM UTC 24 |
419032123 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.457115487 |
|
|
Sep 01 08:47:10 PM UTC 24 |
Sep 01 08:47:17 PM UTC 24 |
119784290 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.686687551 |
|
|
Sep 01 08:47:14 PM UTC 24 |
Sep 01 08:47:17 PM UTC 24 |
40878545 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.3300080357 |
|
|
Sep 01 08:47:15 PM UTC 24 |
Sep 01 08:47:18 PM UTC 24 |
37007405 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3948980514 |
|
|
Sep 01 08:47:12 PM UTC 24 |
Sep 01 08:47:18 PM UTC 24 |
197878564 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2073647006 |
|
|
Sep 01 08:47:16 PM UTC 24 |
Sep 01 08:47:18 PM UTC 24 |
15076245 ps |
| T159 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.435765671 |
|
|
Sep 01 08:47:16 PM UTC 24 |
Sep 01 08:47:19 PM UTC 24 |
32662841 ps |
| T160 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2550477375 |
|
|
Sep 01 08:47:16 PM UTC 24 |
Sep 01 08:47:19 PM UTC 24 |
92860031 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2269144896 |
|
|
Sep 01 08:47:19 PM UTC 24 |
Sep 01 08:47:21 PM UTC 24 |
11433816 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3552012209 |
|
|
Sep 01 08:47:18 PM UTC 24 |
Sep 01 08:47:22 PM UTC 24 |
164553345 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2773044948 |
|
|
Sep 01 08:47:20 PM UTC 24 |
Sep 01 08:47:22 PM UTC 24 |
10473600 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3839319073 |
|
|
Sep 01 08:47:19 PM UTC 24 |
Sep 01 08:47:23 PM UTC 24 |
33011028 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.364357950 |
|
|
Sep 01 08:47:21 PM UTC 24 |
Sep 01 08:47:24 PM UTC 24 |
64053417 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3837068060 |
|
|
Sep 01 08:47:22 PM UTC 24 |
Sep 01 08:47:25 PM UTC 24 |
54500262 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1772059965 |
|
|
Sep 01 08:47:19 PM UTC 24 |
Sep 01 08:47:25 PM UTC 24 |
578234128 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.3564676265 |
|
|
Sep 01 08:47:23 PM UTC 24 |
Sep 01 08:47:26 PM UTC 24 |
115005209 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1300496763 |
|
|
Sep 01 08:47:24 PM UTC 24 |
Sep 01 08:47:29 PM UTC 24 |
428745755 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.575754419 |
|
|
Sep 01 08:47:27 PM UTC 24 |
Sep 01 08:47:29 PM UTC 24 |
14865770 ps |