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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.07 98.44 94.08 98.62 89.36 97.28 95.43 99.26


Total test records in report: 1151
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T156 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2168944008 Sep 01 08:47:25 PM UTC 24 Sep 01 08:47:29 PM UTC 24 364876100 ps
T142 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1890657212 Sep 01 08:47:19 PM UTC 24 Sep 01 08:47:30 PM UTC 24 1412853458 ps
T1031 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1652592413 Sep 01 08:47:29 PM UTC 24 Sep 01 08:47:31 PM UTC 24 14920189 ps
T143 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3161698099 Sep 01 08:47:05 PM UTC 24 Sep 01 08:47:31 PM UTC 24 787861875 ps
T162 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.3639746091 Sep 01 08:47:10 PM UTC 24 Sep 01 08:47:32 PM UTC 24 798141056 ps
T163 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2371713198 Sep 01 08:47:29 PM UTC 24 Sep 01 08:47:32 PM UTC 24 52656262 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.1154487701 Sep 01 08:47:26 PM UTC 24 Sep 01 08:47:33 PM UTC 24 331922895 ps
T121 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1682077424 Sep 01 08:47:30 PM UTC 24 Sep 01 08:47:33 PM UTC 24 62530541 ps
T164 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.3290202604 Sep 01 08:47:30 PM UTC 24 Sep 01 08:47:35 PM UTC 24 37476320 ps
T1032 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.2618463293 Sep 01 08:47:33 PM UTC 24 Sep 01 08:47:35 PM UTC 24 28501912 ps
T1033 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.3558339428 Sep 01 08:47:34 PM UTC 24 Sep 01 08:47:36 PM UTC 24 29607497 ps
T155 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1205726039 Sep 01 08:47:33 PM UTC 24 Sep 01 08:47:38 PM UTC 24 107889863 ps
T1034 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1797072759 Sep 01 08:47:34 PM UTC 24 Sep 01 08:47:38 PM UTC 24 338444644 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.3570549126 Sep 01 08:47:33 PM UTC 24 Sep 01 08:47:38 PM UTC 24 199441436 ps
T1035 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2650358233 Sep 01 08:47:32 PM UTC 24 Sep 01 08:47:38 PM UTC 24 152271044 ps
T122 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2493081919 Sep 01 08:47:35 PM UTC 24 Sep 01 08:47:39 PM UTC 24 187706950 ps
T1036 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1826254141 Sep 01 08:47:35 PM UTC 24 Sep 01 08:47:39 PM UTC 24 88820343 ps
T165 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3332526914 Sep 01 08:47:18 PM UTC 24 Sep 01 08:47:41 PM UTC 24 2072964731 ps
T1037 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.120296052 Sep 01 08:47:40 PM UTC 24 Sep 01 08:47:42 PM UTC 24 15055112 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3972334828 Sep 01 08:47:13 PM UTC 24 Sep 01 08:47:43 PM UTC 24 1031222326 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.3766644355 Sep 01 08:47:32 PM UTC 24 Sep 01 08:47:43 PM UTC 24 1231482415 ps
T1038 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4228936758 Sep 01 08:47:39 PM UTC 24 Sep 01 08:47:43 PM UTC 24 74923864 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.100984365 Sep 01 08:47:39 PM UTC 24 Sep 01 08:47:43 PM UTC 24 291317793 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2807313725 Sep 01 08:47:26 PM UTC 24 Sep 01 08:47:44 PM UTC 24 402061176 ps
T1039 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.2795254148 Sep 01 08:47:42 PM UTC 24 Sep 01 08:47:45 PM UTC 24 69328804 ps
T1040 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1199731008 Sep 01 08:47:44 PM UTC 24 Sep 01 08:47:47 PM UTC 24 15289057 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3957720716 Sep 01 08:47:39 PM UTC 24 Sep 01 08:47:47 PM UTC 24 196274199 ps
T1041 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3213312159 Sep 01 08:47:43 PM UTC 24 Sep 01 08:47:48 PM UTC 24 140568853 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.252044390 Sep 01 08:47:39 PM UTC 24 Sep 01 08:47:49 PM UTC 24 110639863 ps
T1042 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3646434743 Sep 01 08:47:10 PM UTC 24 Sep 01 08:47:49 PM UTC 24 1853244399 ps
T1043 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2036267664 Sep 01 08:47:46 PM UTC 24 Sep 01 08:47:49 PM UTC 24 432600467 ps
T1044 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.2102583546 Sep 01 08:47:44 PM UTC 24 Sep 01 08:47:49 PM UTC 24 93917056 ps
T1045 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1384057723 Sep 01 08:47:30 PM UTC 24 Sep 01 08:47:50 PM UTC 24 4116933876 ps
T1046 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.438716285 Sep 01 08:47:24 PM UTC 24 Sep 01 08:47:54 PM UTC 24 1231079959 ps
T1047 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.554548270 Sep 01 08:47:44 PM UTC 24 Sep 01 08:47:50 PM UTC 24 168386435 ps
T1048 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.491038889 Sep 01 08:47:48 PM UTC 24 Sep 01 08:47:50 PM UTC 24 25271414 ps
T1049 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.2601005464 Sep 01 08:47:33 PM UTC 24 Sep 01 08:47:51 PM UTC 24 785640181 ps
T1050 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3513653425 Sep 01 08:47:44 PM UTC 24 Sep 01 08:47:51 PM UTC 24 651065066 ps
T1051 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.2423174783 Sep 01 08:47:48 PM UTC 24 Sep 01 08:47:51 PM UTC 24 75222576 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1187230934 Sep 01 08:47:46 PM UTC 24 Sep 01 08:47:51 PM UTC 24 529775175 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.330257561 Sep 01 08:47:47 PM UTC 24 Sep 01 08:47:52 PM UTC 24 443606715 ps
T1052 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2968420829 Sep 01 08:47:51 PM UTC 24 Sep 01 08:47:53 PM UTC 24 17600562 ps
T1053 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.1521427014 Sep 01 08:47:51 PM UTC 24 Sep 01 08:47:54 PM UTC 24 23170765 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.177725584 Sep 01 08:47:55 PM UTC 24 Sep 01 08:47:59 PM UTC 24 183456879 ps
T1054 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.776215439 Sep 01 08:47:50 PM UTC 24 Sep 01 08:47:54 PM UTC 24 50267760 ps
T1055 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.4023400128 Sep 01 08:47:52 PM UTC 24 Sep 01 08:47:54 PM UTC 24 37004887 ps
T1056 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.875012630 Sep 01 08:47:49 PM UTC 24 Sep 01 08:47:54 PM UTC 24 416708029 ps
T1057 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2461140187 Sep 01 08:47:50 PM UTC 24 Sep 01 08:47:55 PM UTC 24 541389571 ps
T1058 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3499232240 Sep 01 08:47:52 PM UTC 24 Sep 01 08:47:56 PM UTC 24 526090048 ps
T1059 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3878850695 Sep 01 08:47:55 PM UTC 24 Sep 01 08:47:56 PM UTC 24 25536383 ps
T1060 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3399144344 Sep 01 08:47:52 PM UTC 24 Sep 01 08:47:57 PM UTC 24 145750760 ps
T1061 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2078751675 Sep 01 08:47:51 PM UTC 24 Sep 01 08:47:57 PM UTC 24 403107266 ps
T1062 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.795130042 Sep 01 08:47:24 PM UTC 24 Sep 01 08:47:57 PM UTC 24 5397265762 ps
T1063 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2970209444 Sep 01 08:47:55 PM UTC 24 Sep 01 08:47:58 PM UTC 24 76210914 ps
T1064 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2767870652 Sep 01 08:47:53 PM UTC 24 Sep 01 08:47:58 PM UTC 24 156472381 ps
T1065 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3101030612 Sep 01 08:47:53 PM UTC 24 Sep 01 08:47:58 PM UTC 24 64077824 ps
T1066 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.3325029426 Sep 01 08:47:57 PM UTC 24 Sep 01 08:47:59 PM UTC 24 108734289 ps
T1067 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.295305813 Sep 01 08:47:52 PM UTC 24 Sep 01 08:47:59 PM UTC 24 180337015 ps
T1068 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3928331166 Sep 01 08:47:56 PM UTC 24 Sep 01 08:48:00 PM UTC 24 346547639 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3511444862 Sep 01 08:47:40 PM UTC 24 Sep 01 08:48:00 PM UTC 24 307183452 ps
T1069 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2727079777 Sep 01 08:47:56 PM UTC 24 Sep 01 08:48:01 PM UTC 24 149165267 ps
T1070 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2802145677 Sep 01 08:47:58 PM UTC 24 Sep 01 08:48:01 PM UTC 24 91194938 ps
T1071 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2414540872 Sep 01 08:47:55 PM UTC 24 Sep 01 08:48:02 PM UTC 24 261157388 ps
T1072 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3105536611 Sep 01 08:48:00 PM UTC 24 Sep 01 08:48:02 PM UTC 24 52089690 ps
T1073 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1563311659 Sep 01 08:47:58 PM UTC 24 Sep 01 08:48:02 PM UTC 24 33304094 ps
T1074 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.847799254 Sep 01 08:47:58 PM UTC 24 Sep 01 08:48:02 PM UTC 24 30870728 ps
T1075 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.2143048608 Sep 01 08:48:00 PM UTC 24 Sep 01 08:48:03 PM UTC 24 21415915 ps
T1076 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.553044827 Sep 01 08:47:58 PM UTC 24 Sep 01 08:48:03 PM UTC 24 39009469 ps
T1077 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2803355085 Sep 01 08:48:01 PM UTC 24 Sep 01 08:48:03 PM UTC 24 15301238 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.1527449119 Sep 01 08:47:44 PM UTC 24 Sep 01 08:48:04 PM UTC 24 295399645 ps
T1078 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.1724693157 Sep 01 08:48:00 PM UTC 24 Sep 01 08:48:04 PM UTC 24 58531845 ps
T222 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.2107056727 Sep 01 08:47:55 PM UTC 24 Sep 01 08:48:04 PM UTC 24 111930767 ps
T1079 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.2620261611 Sep 01 08:48:03 PM UTC 24 Sep 01 08:48:05 PM UTC 24 28437518 ps
T1080 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.3625220122 Sep 01 08:48:01 PM UTC 24 Sep 01 08:48:05 PM UTC 24 52309921 ps
T1081 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2721716595 Sep 01 08:48:00 PM UTC 24 Sep 01 08:48:05 PM UTC 24 502616842 ps
T1082 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.778608811 Sep 01 08:48:00 PM UTC 24 Sep 01 08:48:06 PM UTC 24 111839690 ps
T1083 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.748009386 Sep 01 08:48:04 PM UTC 24 Sep 01 08:48:06 PM UTC 24 12951499 ps
T1084 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4245156059 Sep 01 08:48:03 PM UTC 24 Sep 01 08:48:07 PM UTC 24 106162638 ps
T1085 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.2188757965 Sep 01 08:48:03 PM UTC 24 Sep 01 08:48:07 PM UTC 24 277681740 ps
T1086 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.311488781 Sep 01 08:48:03 PM UTC 24 Sep 01 08:48:07 PM UTC 24 178719329 ps
T218 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.646554966 Sep 01 08:47:57 PM UTC 24 Sep 01 08:48:07 PM UTC 24 111722165 ps
T1087 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.4190082147 Sep 01 08:48:04 PM UTC 24 Sep 01 08:48:07 PM UTC 24 74453489 ps
T1088 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1549675384 Sep 01 08:47:17 PM UTC 24 Sep 01 08:48:07 PM UTC 24 10817386453 ps
T1089 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2421441426 Sep 01 08:48:03 PM UTC 24 Sep 01 08:48:07 PM UTC 24 725850823 ps
T1090 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.435414178 Sep 01 08:48:01 PM UTC 24 Sep 01 08:48:08 PM UTC 24 222447064 ps
T1091 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.3866142311 Sep 01 08:48:06 PM UTC 24 Sep 01 08:48:08 PM UTC 24 19013349 ps
T1092 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.3874134480 Sep 01 08:48:04 PM UTC 24 Sep 01 08:48:08 PM UTC 24 76060165 ps
T1093 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.2845799292 Sep 01 08:47:50 PM UTC 24 Sep 01 08:48:08 PM UTC 24 214717237 ps
T1094 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.604963535 Sep 01 08:48:06 PM UTC 24 Sep 01 08:48:09 PM UTC 24 84678982 ps
T219 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2862867158 Sep 01 08:47:52 PM UTC 24 Sep 01 08:48:09 PM UTC 24 1072453170 ps
T1095 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.4172377083 Sep 01 08:48:03 PM UTC 24 Sep 01 08:48:09 PM UTC 24 280736920 ps
T1096 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2170699735 Sep 01 08:48:01 PM UTC 24 Sep 01 08:48:10 PM UTC 24 414301453 ps
T1097 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2305293810 Sep 01 08:48:06 PM UTC 24 Sep 01 08:48:10 PM UTC 24 85548191 ps
T215 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.3407069362 Sep 01 08:47:47 PM UTC 24 Sep 01 08:48:10 PM UTC 24 1122787497 ps
T1098 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3381387788 Sep 01 08:48:07 PM UTC 24 Sep 01 08:48:10 PM UTC 24 134740709 ps
T1099 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.1872633114 Sep 01 08:48:09 PM UTC 24 Sep 01 08:48:11 PM UTC 24 36624580 ps
T1100 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.327947047 Sep 01 08:48:09 PM UTC 24 Sep 01 08:48:11 PM UTC 24 15771901 ps
T1101 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2360313745 Sep 01 08:48:07 PM UTC 24 Sep 01 08:48:12 PM UTC 24 344523490 ps
T1102 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3874570863 Sep 01 08:48:07 PM UTC 24 Sep 01 08:48:12 PM UTC 24 58525424 ps
T1103 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3599265503 Sep 01 08:48:05 PM UTC 24 Sep 01 08:48:12 PM UTC 24 961882728 ps
T1104 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2678708733 Sep 01 08:48:09 PM UTC 24 Sep 01 08:48:12 PM UTC 24 34003330 ps
T1105 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1943240930 Sep 01 08:47:37 PM UTC 24 Sep 01 08:48:12 PM UTC 24 3756207200 ps
T1106 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.828386560 Sep 01 08:48:09 PM UTC 24 Sep 01 08:48:12 PM UTC 24 141109322 ps
T1107 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3269071703 Sep 01 08:48:09 PM UTC 24 Sep 01 08:48:13 PM UTC 24 72419689 ps
T1108 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.2676828606 Sep 01 08:48:09 PM UTC 24 Sep 01 08:48:13 PM UTC 24 504125115 ps
T1109 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1261858477 Sep 01 08:48:11 PM UTC 24 Sep 01 08:48:13 PM UTC 24 11832618 ps
T1110 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2392541190 Sep 01 08:48:09 PM UTC 24 Sep 01 08:48:13 PM UTC 24 417124504 ps
T1111 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.292454914 Sep 01 08:48:04 PM UTC 24 Sep 01 08:48:14 PM UTC 24 1166335133 ps
T1112 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.318302576 Sep 01 08:48:11 PM UTC 24 Sep 01 08:48:14 PM UTC 24 59794027 ps
T1113 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.2761713573 Sep 01 08:48:11 PM UTC 24 Sep 01 08:48:14 PM UTC 24 50396858 ps
T1114 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3428114281 Sep 01 08:48:11 PM UTC 24 Sep 01 08:48:15 PM UTC 24 670997839 ps
T1115 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.3142418183 Sep 01 08:48:13 PM UTC 24 Sep 01 08:48:15 PM UTC 24 46037513 ps
T1116 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.2126440231 Sep 01 08:48:13 PM UTC 24 Sep 01 08:48:15 PM UTC 24 17154545 ps
T1117 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3443027044 Sep 01 08:48:11 PM UTC 24 Sep 01 08:48:15 PM UTC 24 42051955 ps
T1118 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.674807141 Sep 01 08:48:13 PM UTC 24 Sep 01 08:48:15 PM UTC 24 27899568 ps
T1119 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.2413219741 Sep 01 08:48:13 PM UTC 24 Sep 01 08:48:15 PM UTC 24 26103853 ps
T1120 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2772591714 Sep 01 08:48:13 PM UTC 24 Sep 01 08:48:15 PM UTC 24 15688218 ps
T1121 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.1664827935 Sep 01 08:48:13 PM UTC 24 Sep 01 08:48:15 PM UTC 24 47836954 ps
T1122 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.235170678 Sep 01 08:48:13 PM UTC 24 Sep 01 08:48:15 PM UTC 24 34429581 ps
T1123 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4012121510 Sep 01 08:48:09 PM UTC 24 Sep 01 08:48:16 PM UTC 24 149864994 ps
T1124 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3616896835 Sep 01 08:48:11 PM UTC 24 Sep 01 08:48:16 PM UTC 24 104122109 ps
T1125 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3950781796 Sep 01 08:48:11 PM UTC 24 Sep 01 08:48:16 PM UTC 24 141406623 ps
T1126 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.3908956546 Sep 01 08:48:15 PM UTC 24 Sep 01 08:48:17 PM UTC 24 31929349 ps
T1127 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.1403520755 Sep 01 08:48:15 PM UTC 24 Sep 01 08:48:17 PM UTC 24 12325363 ps
T1128 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.2139632945 Sep 01 08:48:15 PM UTC 24 Sep 01 08:48:17 PM UTC 24 20320304 ps
T1129 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.361447612 Sep 01 08:48:03 PM UTC 24 Sep 01 08:48:17 PM UTC 24 584065823 ps
T1130 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.351273814 Sep 01 08:48:15 PM UTC 24 Sep 01 08:48:17 PM UTC 24 33007293 ps
T1131 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.1593160655 Sep 01 08:48:15 PM UTC 24 Sep 01 08:48:17 PM UTC 24 57209369 ps
T1132 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3726910726 Sep 01 08:48:15 PM UTC 24 Sep 01 08:48:17 PM UTC 24 26461787 ps
T1133 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.2097289862 Sep 01 08:48:15 PM UTC 24 Sep 01 08:48:17 PM UTC 24 12255322 ps
T1134 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3663610455 Sep 01 08:48:15 PM UTC 24 Sep 01 08:48:17 PM UTC 24 24184518 ps
T1135 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.3463667658 Sep 01 08:48:15 PM UTC 24 Sep 01 08:48:18 PM UTC 24 24566363 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.3532180144 Sep 01 08:48:09 PM UTC 24 Sep 01 08:48:18 PM UTC 24 686299540 ps
T216 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.4050815453 Sep 01 08:48:00 PM UTC 24 Sep 01 08:48:18 PM UTC 24 7422943635 ps
T1136 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.2031754614 Sep 01 08:48:17 PM UTC 24 Sep 01 08:48:20 PM UTC 24 89127177 ps
T1137 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.1129975522 Sep 01 08:48:11 PM UTC 24 Sep 01 08:48:20 PM UTC 24 206093010 ps
T1138 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.2677540320 Sep 01 08:48:17 PM UTC 24 Sep 01 08:48:20 PM UTC 24 23455002 ps
T1139 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.3434343434 Sep 01 08:48:17 PM UTC 24 Sep 01 08:48:20 PM UTC 24 150406924 ps
T1140 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.1185050528 Sep 01 08:48:17 PM UTC 24 Sep 01 08:48:20 PM UTC 24 26198900 ps
T1141 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.1928906070 Sep 01 08:48:18 PM UTC 24 Sep 01 08:48:20 PM UTC 24 17868783 ps
T1142 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.2212282414 Sep 01 08:48:17 PM UTC 24 Sep 01 08:48:20 PM UTC 24 82244894 ps
T1143 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1410490874 Sep 01 08:48:18 PM UTC 24 Sep 01 08:48:20 PM UTC 24 15450893 ps
T1144 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.2958077578 Sep 01 08:48:18 PM UTC 24 Sep 01 08:48:20 PM UTC 24 54827208 ps
T1145 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2995232723 Sep 01 08:48:18 PM UTC 24 Sep 01 08:48:20 PM UTC 24 13754014 ps
T1146 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.4124500682 Sep 01 08:48:18 PM UTC 24 Sep 01 08:48:20 PM UTC 24 172449210 ps
T1147 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.2531532576 Sep 01 08:48:18 PM UTC 24 Sep 01 08:48:20 PM UTC 24 35640047 ps
T1148 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1991406527 Sep 01 08:48:18 PM UTC 24 Sep 01 08:48:20 PM UTC 24 16419363 ps
T1149 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.2082426175 Sep 01 08:48:18 PM UTC 24 Sep 01 08:48:20 PM UTC 24 12521454 ps
T1150 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.983755205 Sep 01 08:48:18 PM UTC 24 Sep 01 08:48:20 PM UTC 24 15415241 ps
T1151 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1543758060 Sep 01 08:48:09 PM UTC 24 Sep 01 08:48:24 PM UTC 24 10773924051 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3144226864 Sep 01 08:48:06 PM UTC 24 Sep 01 08:48:30 PM UTC 24 313344823 ps


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_rw.2409507238
Short name T10
Test name
Test status
Simulation time 278624421 ps
CPU time 1.82 seconds
Started Sep 01 08:33:58 PM UTC 24
Finished Sep 01 08:34:01 PM UTC 24
Peak memory 226924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409507238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.2409507238
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mailbox.1902703648
Short name T19
Test name
Test status
Simulation time 535817758 ps
CPU time 15.83 seconds
Started Sep 01 08:34:24 PM UTC 24
Finished Sep 01 08:34:41 PM UTC 24
Peak memory 245604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902703648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1902703648
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm.3556671025
Short name T67
Test name
Test status
Simulation time 24735213796 ps
CPU time 37.77 seconds
Started Sep 01 08:34:16 PM UTC 24
Finished Sep 01 08:34:55 PM UTC 24
Peak memory 262148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556671025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3556671025
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.1793905217
Short name T48
Test name
Test status
Simulation time 15031300319 ps
CPU time 77.9 seconds
Started Sep 01 08:33:59 PM UTC 24
Finished Sep 01 08:35:19 PM UTC 24
Peak memory 266424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793905217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.1793905217
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.1477490758
Short name T35
Test name
Test status
Simulation time 8248260470 ps
CPU time 131.55 seconds
Started Sep 01 08:34:17 PM UTC 24
Finished Sep 01 08:36:31 PM UTC 24
Peak memory 278528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1477490758 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress_all.1477490758
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_all.780437422
Short name T43
Test name
Test status
Simulation time 1810150044 ps
CPU time 15.7 seconds
Started Sep 01 08:34:02 PM UTC 24
Finished Sep 01 08:34:19 PM UTC 24
Peak memory 227764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=780437422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.780437422
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.1772059965
Short name T141
Test name
Test status
Simulation time 578234128 ps
CPU time 5.27 seconds
Started Sep 01 08:47:19 PM UTC 24
Finished Sep 01 08:47:25 PM UTC 24
Peak memory 226176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1772059965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
1.spi_device_csr_mem_rw_with_rand_reset.1772059965
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.3932848928
Short name T49
Test name
Test status
Simulation time 4195296551 ps
CPU time 98.15 seconds
Started Sep 01 08:34:16 PM UTC 24
Finished Sep 01 08:35:56 PM UTC 24
Peak memory 268360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932848928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3932848928
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_ram_cfg.2175770667
Short name T3
Test name
Test status
Simulation time 25661328 ps
CPU time 0.79 seconds
Started Sep 01 08:33:56 PM UTC 24
Finished Sep 01 08:33:58 PM UTC 24
Peak memory 225668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175770667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.2175770667
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_ram_cfg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.3131572528
Short name T36
Test name
Test status
Simulation time 39092056557 ps
CPU time 166.72 seconds
Started Sep 01 08:34:08 PM UTC 24
Finished Sep 01 08:36:58 PM UTC 24
Peak memory 266316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131572528 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress_all.3131572528
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_upload.551952287
Short name T57
Test name
Test status
Simulation time 5656645156 ps
CPU time 15.75 seconds
Started Sep 01 08:33:56 PM UTC 24
Finished Sep 01 08:34:13 PM UTC 24
Peak memory 264104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551952287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.551952287
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_sec_cm.4006961312
Short name T7
Test name
Test status
Simulation time 86064837 ps
CPU time 1.23 seconds
Started Sep 01 08:33:57 PM UTC 24
Finished Sep 01 08:34:00 PM UTC 24
Peak memory 257736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006961312 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.4006961312
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_sec_cm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_all.2163705094
Short name T50
Test name
Test status
Simulation time 9541140832 ps
CPU time 170.39 seconds
Started Sep 01 08:33:59 PM UTC 24
Finished Sep 01 08:36:53 PM UTC 24
Peak memory 268200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163705094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2163705094
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.1511785423
Short name T197
Test name
Test status
Simulation time 8319482715 ps
CPU time 117.86 seconds
Started Sep 01 08:35:28 PM UTC 24
Finished Sep 01 08:37:28 PM UTC 24
Peak memory 278648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511785423 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stress_all.1511785423
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2902414241
Short name T52
Test name
Test status
Simulation time 16513521090 ps
CPU time 46.4 seconds
Started Sep 01 08:33:59 PM UTC 24
Finished Sep 01 08:34:47 PM UTC 24
Peak memory 251856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902414241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.2902414241
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_all.287319607
Short name T256
Test name
Test status
Simulation time 3034456676 ps
CPU time 98.86 seconds
Started Sep 01 08:39:41 PM UTC 24
Finished Sep 01 08:41:22 PM UTC 24
Peak memory 268228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=287319607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.287319607
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode.395643767
Short name T22
Test name
Test status
Simulation time 423170741 ps
CPU time 7.12 seconds
Started Sep 01 08:33:59 PM UTC 24
Finished Sep 01 08:34:08 PM UTC 24
Peak memory 244252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395643767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.395643767
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_stress_all.4101393059
Short name T34
Test name
Test status
Simulation time 8677112559 ps
CPU time 42.7 seconds
Started Sep 01 08:34:58 PM UTC 24
Finished Sep 01 08:35:42 PM UTC 24
Peak memory 262136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101393059 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress_all.4101393059
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mem_parity.331517450
Short name T2
Test name
Test status
Simulation time 51404215 ps
CPU time 1.03 seconds
Started Sep 01 08:33:55 PM UTC 24
Finished Sep 01 08:33:57 PM UTC 24
Peak memory 229200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331517450 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_parity.331517450
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm.2542548308
Short name T306
Test name
Test status
Simulation time 40730341655 ps
CPU time 182.48 seconds
Started Sep 01 08:40:25 PM UTC 24
Finished Sep 01 08:43:31 PM UTC 24
Peak memory 264200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2542548308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.2542548308
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_stress_all.2453961380
Short name T274
Test name
Test status
Simulation time 16537576080 ps
CPU time 225.15 seconds
Started Sep 01 08:34:29 PM UTC 24
Finished Sep 01 08:38:18 PM UTC 24
Peak memory 266124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453961380 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress_all.2453961380
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_intg_err.3972334828
Short name T144
Test name
Test status
Simulation time 1031222326 ps
CPU time 28.12 seconds
Started Sep 01 08:47:13 PM UTC 24
Finished Sep 01 08:47:43 PM UTC 24
Peak memory 226444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972334828 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_intg_err.3972334828
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.1289049130
Short name T233
Test name
Test status
Simulation time 9002053830 ps
CPU time 143.25 seconds
Started Sep 01 08:37:35 PM UTC 24
Finished Sep 01 08:40:01 PM UTC 24
Peak memory 278528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1289049130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.1289049130
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm.2785409380
Short name T249
Test name
Test status
Simulation time 19818676676 ps
CPU time 157.34 seconds
Started Sep 01 08:34:27 PM UTC 24
Finished Sep 01 08:37:07 PM UTC 24
Peak memory 276520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785409380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2785409380
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_all.960781669
Short name T44
Test name
Test status
Simulation time 49779135107 ps
CPU time 23.96 seconds
Started Sep 01 08:33:56 PM UTC 24
Finished Sep 01 08:34:21 PM UTC 24
Peak memory 227892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960781669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.960781669
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.3127453666
Short name T118
Test name
Test status
Simulation time 69046569 ps
CPU time 1.76 seconds
Started Sep 01 08:47:07 PM UTC 24
Finished Sep 01 08:47:09 PM UTC 24
Peak memory 212844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127453666 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_hw_reset.3127453666
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_csr_hw_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.1069005007
Short name T305
Test name
Test status
Simulation time 41703287720 ps
CPU time 182.13 seconds
Started Sep 01 08:39:06 PM UTC 24
Finished Sep 01 08:42:12 PM UTC 24
Peak memory 268300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069005007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.1069005007
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_errors.3957720716
Short name T148
Test name
Test status
Simulation time 196274199 ps
CPU time 7.13 seconds
Started Sep 01 08:47:39 PM UTC 24
Finished Sep 01 08:47:47 PM UTC 24
Peak memory 226332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957720716 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3957720716
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_stress_all.2529083623
Short name T88
Test name
Test status
Simulation time 33173755267 ps
CPU time 165.19 seconds
Started Sep 01 08:35:13 PM UTC 24
Finished Sep 01 08:38:01 PM UTC 24
Peak memory 268296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529083623 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress_all.2529083623
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode_ignore_cmds.3130320421
Short name T227
Test name
Test status
Simulation time 19769077596 ps
CPU time 217.31 seconds
Started Sep 01 08:35:52 PM UTC 24
Finished Sep 01 08:39:33 PM UTC 24
Peak memory 268356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3130320421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds.3130320421
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.889486623
Short name T236
Test name
Test status
Simulation time 222451573623 ps
CPU time 485.99 seconds
Started Sep 01 08:35:54 PM UTC 24
Finished Sep 01 08:44:07 PM UTC 24
Peak memory 268288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889486623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle.889486623
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.1067039203
Short name T115
Test name
Test status
Simulation time 3048530418 ps
CPU time 89.7 seconds
Started Sep 01 08:34:08 PM UTC 24
Finished Sep 01 08:35:40 PM UTC 24
Peak memory 262412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067039203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.1067039203
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_intercept.2672414455
Short name T24
Test name
Test status
Simulation time 895434706 ps
CPU time 9.48 seconds
Started Sep 01 08:33:58 PM UTC 24
Finished Sep 01 08:34:09 PM UTC 24
Peak memory 235240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672414455 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.2672414455
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3647051532
Short name T1014
Test name
Test status
Simulation time 128703012046 ps
CPU time 371.65 seconds
Started Sep 01 08:46:26 PM UTC 24
Finished Sep 01 08:52:43 PM UTC 24
Peak memory 278528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647051532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idle.3647051532
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.141614996
Short name T373
Test name
Test status
Simulation time 14758757817 ps
CPU time 258.79 seconds
Started Sep 01 08:41:23 PM UTC 24
Finished Sep 01 08:45:45 PM UTC 24
Peak memory 295104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141614996 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stress_all.141614996
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_read_hw_reg.1719540368
Short name T15
Test name
Test status
Simulation time 8471260802 ps
CPU time 4.31 seconds
Started Sep 01 08:33:57 PM UTC 24
Finished Sep 01 08:34:03 PM UTC 24
Peak memory 229856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719540368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1719540368
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_alert_test.1737711189
Short name T5
Test name
Test status
Simulation time 39459569 ps
CPU time 1.01 seconds
Started Sep 01 08:33:57 PM UTC 24
Finished Sep 01 08:33:59 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737711189 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1737711189
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.1207897665
Short name T41
Test name
Test status
Simulation time 49086622786 ps
CPU time 75.17 seconds
Started Sep 01 08:42:09 PM UTC 24
Finished Sep 01 08:43:26 PM UTC 24
Peak memory 268292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207897665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idle.1207897665
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.1125988673
Short name T376
Test name
Test status
Simulation time 396598400431 ps
CPU time 894.52 seconds
Started Sep 01 08:36:08 PM UTC 24
Finished Sep 01 08:51:13 PM UTC 24
Peak memory 284872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125988673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle.1125988673
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.4175808918
Short name T370
Test name
Test status
Simulation time 4185637119 ps
CPU time 102.72 seconds
Started Sep 01 08:47:01 PM UTC 24
Finished Sep 01 08:48:46 PM UTC 24
Peak memory 262152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175808918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle.4175808918
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_cfg_cmd.76329922
Short name T23
Test name
Test status
Simulation time 1108861079 ps
CPU time 8.03 seconds
Started Sep 01 08:33:59 PM UTC 24
Finished Sep 01 08:34:08 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76329922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.76329922
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_intg_err.3144226864
Short name T217
Test name
Test status
Simulation time 313344823 ps
CPU time 22.69 seconds
Started Sep 01 08:48:06 PM UTC 24
Finished Sep 01 08:48:30 PM UTC 24
Peak memory 224340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144226864 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_intg_err.3144226864
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_all.11183588
Short name T45
Test name
Test status
Simulation time 2883888637 ps
CPU time 24.25 seconds
Started Sep 01 08:33:57 PM UTC 24
Finished Sep 01 08:34:23 PM UTC 24
Peak memory 232052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11183588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.11183588
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.676534572
Short name T392
Test name
Test status
Simulation time 25596370134 ps
CPU time 318.92 seconds
Started Sep 01 08:44:02 PM UTC 24
Finished Sep 01 08:49:26 PM UTC 24
Peak memory 276496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676534572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.676534572
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode.4187398630
Short name T145
Test name
Test status
Simulation time 730976356 ps
CPU time 19.32 seconds
Started Sep 01 08:33:57 PM UTC 24
Finished Sep 01 08:34:18 PM UTC 24
Peak memory 245572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4187398630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.4187398630
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_errors.4172377083
Short name T1095
Test name
Test status
Simulation time 280736920 ps
CPU time 5.74 seconds
Started Sep 01 08:48:03 PM UTC 24
Finished Sep 01 08:48:09 PM UTC 24
Peak memory 226324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172377083 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.4172377083
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.2028884454
Short name T273
Test name
Test status
Simulation time 17800373916 ps
CPU time 71.52 seconds
Started Sep 01 08:36:21 PM UTC 24
Finished Sep 01 08:37:34 PM UTC 24
Peak memory 268260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028884454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2028884454
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm.349618318
Short name T254
Test name
Test status
Simulation time 4831763049 ps
CPU time 87.77 seconds
Started Sep 01 08:39:42 PM UTC 24
Finished Sep 01 08:41:12 PM UTC 24
Peak memory 266252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349618318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.349618318
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.1768419796
Short name T235
Test name
Test status
Simulation time 3405265806 ps
CPU time 84.78 seconds
Started Sep 01 08:39:56 PM UTC 24
Finished Sep 01 08:41:23 PM UTC 24
Peak memory 266376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768419796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.1768419796
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.1081546533
Short name T333
Test name
Test status
Simulation time 5438904866 ps
CPU time 118.89 seconds
Started Sep 01 08:39:55 PM UTC 24
Finished Sep 01 08:41:57 PM UTC 24
Peak memory 278496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081546533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.1081546533
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.858174552
Short name T1017
Test name
Test status
Simulation time 56076266336 ps
CPU time 792.17 seconds
Started Sep 01 08:43:31 PM UTC 24
Finished Sep 01 08:56:54 PM UTC 24
Peak memory 276520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858174552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.858174552
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode.440981292
Short name T169
Test name
Test status
Simulation time 1342538108 ps
CPU time 13.36 seconds
Started Sep 01 08:35:06 PM UTC 24
Finished Sep 01 08:35:20 PM UTC 24
Peak memory 245772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440981292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.440981292
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.307244269
Short name T138
Test name
Test status
Simulation time 473643077 ps
CPU time 5.81 seconds
Started Sep 01 08:47:04 PM UTC 24
Finished Sep 01 08:47:11 PM UTC 24
Peak memory 224260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307244269 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.307244269
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_intg_err.3532180144
Short name T223
Test name
Test status
Simulation time 686299540 ps
CPU time 8.09 seconds
Started Sep 01 08:48:09 PM UTC 24
Finished Sep 01 08:48:18 PM UTC 24
Peak memory 224356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3532180144 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_intg_err.3532180144
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.749428425
Short name T629
Test name
Test status
Simulation time 47490520950 ps
CPU time 240.11 seconds
Started Sep 01 08:36:48 PM UTC 24
Finished Sep 01 08:40:52 PM UTC 24
Peak memory 268320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749428425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idle.749428425
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.1471744250
Short name T100
Test name
Test status
Simulation time 39604475526 ps
CPU time 64.96 seconds
Started Sep 01 08:37:01 PM UTC 24
Finished Sep 01 08:38:07 PM UTC 24
Peak memory 247776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471744250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1471744250
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.4272054519
Short name T91
Test name
Test status
Simulation time 37827428815 ps
CPU time 126.09 seconds
Started Sep 01 08:42:18 PM UTC 24
Finished Sep 01 08:44:28 PM UTC 24
Peak memory 268328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4272054519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.4272054519
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_all.2569317059
Short name T228
Test name
Test status
Simulation time 3538191417 ps
CPU time 51 seconds
Started Sep 01 08:42:44 PM UTC 24
Finished Sep 01 08:43:37 PM UTC 24
Peak memory 262116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569317059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.2569317059
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_csb_read.3273746361
Short name T1
Test name
Test status
Simulation time 16894205 ps
CPU time 0.87 seconds
Started Sep 01 08:33:55 PM UTC 24
Finished Sep 01 08:33:57 PM UTC 24
Peak memory 215604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273746361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3273746361
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_cfg_cmd.4078772006
Short name T133
Test name
Test status
Simulation time 560926521 ps
CPU time 8.34 seconds
Started Sep 01 08:36:35 PM UTC 24
Finished Sep 01 08:36:45 PM UTC 24
Peak memory 235332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4078772006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.4078772006
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.2073647006
Short name T119
Test name
Test status
Simulation time 15076245 ps
CPU time 1.42 seconds
Started Sep 01 08:47:16 PM UTC 24
Finished Sep 01 08:47:18 PM UTC 24
Peak memory 213296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2073647006 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_hw_reset.2073647006
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_csr_hw_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_aliasing.3639746091
Short name T162
Test name
Test status
Simulation time 798141056 ps
CPU time 20.32 seconds
Started Sep 01 08:47:10 PM UTC 24
Finished Sep 01 08:47:32 PM UTC 24
Peak memory 213856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639746091 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_aliasing.3639746091
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_csr_aliasing/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.3646434743
Short name T1042
Test name
Test status
Simulation time 1853244399 ps
CPU time 37.52 seconds
Started Sep 01 08:47:10 PM UTC 24
Finished Sep 01 08:47:49 PM UTC 24
Peak memory 214160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646434743 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_bit_bash.3646434743
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_csr_bit_bash/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3884419691
Short name T139
Test name
Test status
Simulation time 419032123 ps
CPU time 3.57 seconds
Started Sep 01 08:47:11 PM UTC 24
Finished Sep 01 08:47:16 PM UTC 24
Peak memory 228552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3884419691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
0.spi_device_csr_mem_rw_with_rand_reset.3884419691
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.2096274874
Short name T158
Test name
Test status
Simulation time 81805887 ps
CPU time 2.99 seconds
Started Sep 01 08:47:09 PM UTC 24
Finished Sep 01 08:47:13 PM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096274874 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.2096274874
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.1677870683
Short name T1022
Test name
Test status
Simulation time 18718695 ps
CPU time 1.17 seconds
Started Sep 01 08:47:05 PM UTC 24
Finished Sep 01 08:47:08 PM UTC 24
Peak memory 211788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677870683 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1677870683
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.1891401773
Short name T157
Test name
Test status
Simulation time 238344134 ps
CPU time 2.97 seconds
Started Sep 01 08:47:07 PM UTC 24
Finished Sep 01 08:47:11 PM UTC 24
Peak memory 224136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891401773 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_partial_access.1891401773
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_mem_partial_access/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.3123823058
Short name T1023
Test name
Test status
Simulation time 37046263 ps
CPU time 1.03 seconds
Started Sep 01 08:47:07 PM UTC 24
Finished Sep 01 08:47:09 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123823058 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem_walk.3123823058
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_mem_walk/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.457115487
Short name T177
Test name
Test status
Simulation time 119784290 ps
CPU time 5.22 seconds
Started Sep 01 08:47:10 PM UTC 24
Finished Sep 01 08:47:17 PM UTC 24
Peak memory 224144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457115487 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_same_csr_outstanding.457115487
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_intg_err.3161698099
Short name T143
Test name
Test status
Simulation time 787861875 ps
CPU time 24.4 seconds
Started Sep 01 08:47:05 PM UTC 24
Finished Sep 01 08:47:31 PM UTC 24
Peak memory 226192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161698099 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_intg_err.3161698099
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_aliasing.3332526914
Short name T165
Test name
Test status
Simulation time 2072964731 ps
CPU time 21.73 seconds
Started Sep 01 08:47:18 PM UTC 24
Finished Sep 01 08:47:41 PM UTC 24
Peak memory 224396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332526914 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_aliasing.3332526914
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_csr_aliasing/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_bit_bash.1549675384
Short name T1088
Test name
Test status
Simulation time 10817386453 ps
CPU time 49.01 seconds
Started Sep 01 08:47:17 PM UTC 24
Finished Sep 01 08:48:07 PM UTC 24
Peak memory 213900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549675384 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_bit_bash.1549675384
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_csr_bit_bash/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2550477375
Short name T160
Test name
Test status
Simulation time 92860031 ps
CPU time 2.11 seconds
Started Sep 01 08:47:16 PM UTC 24
Finished Sep 01 08:47:19 PM UTC 24
Peak memory 214156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550477375 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.2550477375
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.686687551
Short name T1024
Test name
Test status
Simulation time 40878545 ps
CPU time 1.11 seconds
Started Sep 01 08:47:14 PM UTC 24
Finished Sep 01 08:47:17 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686687551 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.686687551
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.435765671
Short name T159
Test name
Test status
Simulation time 32662841 ps
CPU time 1.83 seconds
Started Sep 01 08:47:16 PM UTC 24
Finished Sep 01 08:47:19 PM UTC 24
Peak memory 222884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435765671 -assert nopostpr
oc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_partial_access.435765671
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_mem_partial_access/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.3300080357
Short name T1025
Test name
Test status
Simulation time 37007405 ps
CPU time 1.03 seconds
Started Sep 01 08:47:15 PM UTC 24
Finished Sep 01 08:47:18 PM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300080357 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_walk.3300080357
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_mem_walk/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3552012209
Short name T178
Test name
Test status
Simulation time 164553345 ps
CPU time 2.96 seconds
Started Sep 01 08:47:18 PM UTC 24
Finished Sep 01 08:47:22 PM UTC 24
Peak memory 224308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552012209 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_same_csr_outstanding.3552012209
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.3948980514
Short name T140
Test name
Test status
Simulation time 197878564 ps
CPU time 4.6 seconds
Started Sep 01 08:47:12 PM UTC 24
Finished Sep 01 08:47:18 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948980514 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3948980514
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.2727079777
Short name T1069
Test name
Test status
Simulation time 149165267 ps
CPU time 4.1 seconds
Started Sep 01 08:47:56 PM UTC 24
Finished Sep 01 08:48:01 PM UTC 24
Peak memory 228300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2727079777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
10.spi_device_csr_mem_rw_with_rand_reset.2727079777
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_csr_rw.2970209444
Short name T1063
Test name
Test status
Simulation time 76210914 ps
CPU time 2.75 seconds
Started Sep 01 08:47:55 PM UTC 24
Finished Sep 01 08:47:58 PM UTC 24
Peak memory 224060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970209444 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.2970209444
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_intr_test.3878850695
Short name T1059
Test name
Test status
Simulation time 25536383 ps
CPU time 0.88 seconds
Started Sep 01 08:47:55 PM UTC 24
Finished Sep 01 08:47:56 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878850695 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.3878850695
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.2414540872
Short name T1071
Test name
Test status
Simulation time 261157388 ps
CPU time 5.9 seconds
Started Sep 01 08:47:55 PM UTC 24
Finished Sep 01 08:48:02 PM UTC 24
Peak memory 224136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414540872 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_same_csr_outstanding.2414540872
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_errors.177725584
Short name T149
Test name
Test status
Simulation time 183456879 ps
CPU time 3.47 seconds
Started Sep 01 08:47:55 PM UTC 24
Finished Sep 01 08:47:59 PM UTC 24
Peak memory 226588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177725584 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.177725584
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/10.spi_device_tl_intg_err.2107056727
Short name T222
Test name
Test status
Simulation time 111930767 ps
CPU time 8.58 seconds
Started Sep 01 08:47:55 PM UTC 24
Finished Sep 01 08:48:04 PM UTC 24
Peak memory 224212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107056727 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_intg_err.2107056727
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.553044827
Short name T1076
Test name
Test status
Simulation time 39009469 ps
CPU time 3.44 seconds
Started Sep 01 08:47:58 PM UTC 24
Finished Sep 01 08:48:03 PM UTC 24
Peak memory 226244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=553044827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
11.spi_device_csr_mem_rw_with_rand_reset.553044827
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_csr_rw.1563311659
Short name T1073
Test name
Test status
Simulation time 33304094 ps
CPU time 2.85 seconds
Started Sep 01 08:47:58 PM UTC 24
Finished Sep 01 08:48:02 PM UTC 24
Peak memory 224328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563311659 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.1563311659
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_intr_test.3325029426
Short name T1066
Test name
Test status
Simulation time 108734289 ps
CPU time 1.09 seconds
Started Sep 01 08:47:57 PM UTC 24
Finished Sep 01 08:47:59 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325029426 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.3325029426
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2802145677
Short name T1070
Test name
Test status
Simulation time 91194938 ps
CPU time 1.94 seconds
Started Sep 01 08:47:58 PM UTC 24
Finished Sep 01 08:48:01 PM UTC 24
Peak memory 223184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802145677 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_same_csr_outstanding.2802145677
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_errors.3928331166
Short name T1068
Test name
Test status
Simulation time 346547639 ps
CPU time 3.13 seconds
Started Sep 01 08:47:56 PM UTC 24
Finished Sep 01 08:48:00 PM UTC 24
Peak memory 224296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928331166 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.3928331166
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/11.spi_device_tl_intg_err.646554966
Short name T218
Test name
Test status
Simulation time 111722165 ps
CPU time 8.86 seconds
Started Sep 01 08:47:57 PM UTC 24
Finished Sep 01 08:48:07 PM UTC 24
Peak memory 230448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646554966 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_intg_err.646554966
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.778608811
Short name T1082
Test name
Test status
Simulation time 111839690 ps
CPU time 5.07 seconds
Started Sep 01 08:48:00 PM UTC 24
Finished Sep 01 08:48:06 PM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=778608811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
12.spi_device_csr_mem_rw_with_rand_reset.778608811
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_csr_rw.2143048608
Short name T1075
Test name
Test status
Simulation time 21415915 ps
CPU time 1.8 seconds
Started Sep 01 08:48:00 PM UTC 24
Finished Sep 01 08:48:03 PM UTC 24
Peak memory 214688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143048608 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.2143048608
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_intr_test.3105536611
Short name T1072
Test name
Test status
Simulation time 52089690 ps
CPU time 1.14 seconds
Started Sep 01 08:48:00 PM UTC 24
Finished Sep 01 08:48:02 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105536611 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.3105536611
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.2721716595
Short name T1081
Test name
Test status
Simulation time 502616842 ps
CPU time 4.25 seconds
Started Sep 01 08:48:00 PM UTC 24
Finished Sep 01 08:48:05 PM UTC 24
Peak memory 224136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721716595 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_same_csr_outstanding.2721716595
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_errors.847799254
Short name T1074
Test name
Test status
Simulation time 30870728 ps
CPU time 2.99 seconds
Started Sep 01 08:47:58 PM UTC 24
Finished Sep 01 08:48:02 PM UTC 24
Peak memory 224268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847799254 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.847799254
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/12.spi_device_tl_intg_err.4050815453
Short name T216
Test name
Test status
Simulation time 7422943635 ps
CPU time 17.61 seconds
Started Sep 01 08:48:00 PM UTC 24
Finished Sep 01 08:48:18 PM UTC 24
Peak memory 224228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050815453 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_intg_err.4050815453
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.311488781
Short name T1086
Test name
Test status
Simulation time 178719329 ps
CPU time 3.25 seconds
Started Sep 01 08:48:03 PM UTC 24
Finished Sep 01 08:48:07 PM UTC 24
Peak memory 226224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=311488781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
13.spi_device_csr_mem_rw_with_rand_reset.311488781
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_csr_rw.3625220122
Short name T1080
Test name
Test status
Simulation time 52309921 ps
CPU time 2.46 seconds
Started Sep 01 08:48:01 PM UTC 24
Finished Sep 01 08:48:05 PM UTC 24
Peak memory 224132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625220122 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.3625220122
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_intr_test.2803355085
Short name T1077
Test name
Test status
Simulation time 15301238 ps
CPU time 1.12 seconds
Started Sep 01 08:48:01 PM UTC 24
Finished Sep 01 08:48:03 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803355085 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.2803355085
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.435414178
Short name T1090
Test name
Test status
Simulation time 222447064 ps
CPU time 5.18 seconds
Started Sep 01 08:48:01 PM UTC 24
Finished Sep 01 08:48:08 PM UTC 24
Peak memory 224260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435414178 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_same_csr_outstanding.435414178
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_errors.1724693157
Short name T1078
Test name
Test status
Simulation time 58531845 ps
CPU time 3.01 seconds
Started Sep 01 08:48:00 PM UTC 24
Finished Sep 01 08:48:04 PM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724693157 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.1724693157
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/13.spi_device_tl_intg_err.2170699735
Short name T1096
Test name
Test status
Simulation time 414301453 ps
CPU time 7.42 seconds
Started Sep 01 08:48:01 PM UTC 24
Finished Sep 01 08:48:10 PM UTC 24
Peak memory 226404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2170699735 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_intg_err.2170699735
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2421441426
Short name T1089
Test name
Test status
Simulation time 725850823 ps
CPU time 3.46 seconds
Started Sep 01 08:48:03 PM UTC 24
Finished Sep 01 08:48:07 PM UTC 24
Peak memory 228228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2421441426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
14.spi_device_csr_mem_rw_with_rand_reset.2421441426
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_csr_rw.2188757965
Short name T1085
Test name
Test status
Simulation time 277681740 ps
CPU time 2.93 seconds
Started Sep 01 08:48:03 PM UTC 24
Finished Sep 01 08:48:07 PM UTC 24
Peak memory 224328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2188757965 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.2188757965
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_intr_test.2620261611
Short name T1079
Test name
Test status
Simulation time 28437518 ps
CPU time 0.93 seconds
Started Sep 01 08:48:03 PM UTC 24
Finished Sep 01 08:48:05 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620261611 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.2620261611
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.4245156059
Short name T1084
Test name
Test status
Simulation time 106162638 ps
CPU time 2.69 seconds
Started Sep 01 08:48:03 PM UTC 24
Finished Sep 01 08:48:07 PM UTC 24
Peak memory 224304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245156059 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_same_csr_outstanding.4245156059
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/14.spi_device_tl_intg_err.361447612
Short name T1129
Test name
Test status
Simulation time 584065823 ps
CPU time 13.38 seconds
Started Sep 01 08:48:03 PM UTC 24
Finished Sep 01 08:48:17 PM UTC 24
Peak memory 226196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361447612 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_intg_err.361447612
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.2305293810
Short name T1097
Test name
Test status
Simulation time 85548191 ps
CPU time 3.18 seconds
Started Sep 01 08:48:06 PM UTC 24
Finished Sep 01 08:48:10 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2305293810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
15.spi_device_csr_mem_rw_with_rand_reset.2305293810
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_csr_rw.4190082147
Short name T1087
Test name
Test status
Simulation time 74453489 ps
CPU time 1.81 seconds
Started Sep 01 08:48:04 PM UTC 24
Finished Sep 01 08:48:07 PM UTC 24
Peak memory 222864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190082147 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.4190082147
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_intr_test.748009386
Short name T1083
Test name
Test status
Simulation time 12951499 ps
CPU time 0.99 seconds
Started Sep 01 08:48:04 PM UTC 24
Finished Sep 01 08:48:06 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748009386 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.748009386
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3599265503
Short name T1103
Test name
Test status
Simulation time 961882728 ps
CPU time 5.61 seconds
Started Sep 01 08:48:05 PM UTC 24
Finished Sep 01 08:48:12 PM UTC 24
Peak memory 224136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599265503 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_same_csr_outstanding.3599265503
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_errors.3874134480
Short name T1092
Test name
Test status
Simulation time 76060165 ps
CPU time 2.85 seconds
Started Sep 01 08:48:04 PM UTC 24
Finished Sep 01 08:48:08 PM UTC 24
Peak memory 224272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874134480 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.3874134480
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/15.spi_device_tl_intg_err.292454914
Short name T1111
Test name
Test status
Simulation time 1166335133 ps
CPU time 8.68 seconds
Started Sep 01 08:48:04 PM UTC 24
Finished Sep 01 08:48:14 PM UTC 24
Peak memory 226196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292454914 -assert nopostproc +UVM
_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_intg_err.292454914
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2360313745
Short name T1101
Test name
Test status
Simulation time 344523490 ps
CPU time 3.56 seconds
Started Sep 01 08:48:07 PM UTC 24
Finished Sep 01 08:48:12 PM UTC 24
Peak memory 226264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2360313745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
16.spi_device_csr_mem_rw_with_rand_reset.2360313745
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_csr_rw.3381387788
Short name T1098
Test name
Test status
Simulation time 134740709 ps
CPU time 2.14 seconds
Started Sep 01 08:48:07 PM UTC 24
Finished Sep 01 08:48:10 PM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381387788 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.3381387788
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_intr_test.3866142311
Short name T1091
Test name
Test status
Simulation time 19013349 ps
CPU time 1.07 seconds
Started Sep 01 08:48:06 PM UTC 24
Finished Sep 01 08:48:08 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866142311 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.3866142311
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.3874570863
Short name T1102
Test name
Test status
Simulation time 58525424 ps
CPU time 3.91 seconds
Started Sep 01 08:48:07 PM UTC 24
Finished Sep 01 08:48:12 PM UTC 24
Peak memory 224128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874570863 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_same_csr_outstanding.3874570863
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/16.spi_device_tl_errors.604963535
Short name T1094
Test name
Test status
Simulation time 84678982 ps
CPU time 2.09 seconds
Started Sep 01 08:48:06 PM UTC 24
Finished Sep 01 08:48:09 PM UTC 24
Peak memory 226352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=604963535 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.604963535
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.4012121510
Short name T1123
Test name
Test status
Simulation time 149864994 ps
CPU time 5.41 seconds
Started Sep 01 08:48:09 PM UTC 24
Finished Sep 01 08:48:16 PM UTC 24
Peak memory 228312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=4012121510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
17.spi_device_csr_mem_rw_with_rand_reset.4012121510
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_csr_rw.828386560
Short name T1106
Test name
Test status
Simulation time 141109322 ps
CPU time 2.44 seconds
Started Sep 01 08:48:09 PM UTC 24
Finished Sep 01 08:48:12 PM UTC 24
Peak memory 224248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828386560 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.828386560
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_intr_test.1872633114
Short name T1099
Test name
Test status
Simulation time 36624580 ps
CPU time 1.04 seconds
Started Sep 01 08:48:09 PM UTC 24
Finished Sep 01 08:48:11 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872633114 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.1872633114
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.2392541190
Short name T1110
Test name
Test status
Simulation time 417124504 ps
CPU time 3.1 seconds
Started Sep 01 08:48:09 PM UTC 24
Finished Sep 01 08:48:13 PM UTC 24
Peak memory 226368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392541190 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_same_csr_outstanding.2392541190
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_errors.2676828606
Short name T1108
Test name
Test status
Simulation time 504125115 ps
CPU time 2.91 seconds
Started Sep 01 08:48:09 PM UTC 24
Finished Sep 01 08:48:13 PM UTC 24
Peak memory 226452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676828606 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.2676828606
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/17.spi_device_tl_intg_err.1543758060
Short name T1151
Test name
Test status
Simulation time 10773924051 ps
CPU time 13.88 seconds
Started Sep 01 08:48:09 PM UTC 24
Finished Sep 01 08:48:24 PM UTC 24
Peak memory 224204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543758060 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_intg_err.1543758060
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.318302576
Short name T1112
Test name
Test status
Simulation time 59794027 ps
CPU time 2.12 seconds
Started Sep 01 08:48:11 PM UTC 24
Finished Sep 01 08:48:14 PM UTC 24
Peak memory 223884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=318302576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
18.spi_device_csr_mem_rw_with_rand_reset.318302576
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_csr_rw.2678708733
Short name T1104
Test name
Test status
Simulation time 34003330 ps
CPU time 1.84 seconds
Started Sep 01 08:48:09 PM UTC 24
Finished Sep 01 08:48:12 PM UTC 24
Peak memory 222864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678708733 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.2678708733
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_intr_test.327947047
Short name T1100
Test name
Test status
Simulation time 15771901 ps
CPU time 1.09 seconds
Started Sep 01 08:48:09 PM UTC 24
Finished Sep 01 08:48:11 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327947047 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.327947047
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3428114281
Short name T1114
Test name
Test status
Simulation time 670997839 ps
CPU time 2.8 seconds
Started Sep 01 08:48:11 PM UTC 24
Finished Sep 01 08:48:15 PM UTC 24
Peak memory 224032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428114281 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_same_csr_outstanding.3428114281
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/18.spi_device_tl_errors.3269071703
Short name T1107
Test name
Test status
Simulation time 72419689 ps
CPU time 2.5 seconds
Started Sep 01 08:48:09 PM UTC 24
Finished Sep 01 08:48:13 PM UTC 24
Peak memory 224280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269071703 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.3269071703
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.3616896835
Short name T1124
Test name
Test status
Simulation time 104122109 ps
CPU time 3.45 seconds
Started Sep 01 08:48:11 PM UTC 24
Finished Sep 01 08:48:16 PM UTC 24
Peak memory 226228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3616896835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
19.spi_device_csr_mem_rw_with_rand_reset.3616896835
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_csr_rw.2761713573
Short name T1113
Test name
Test status
Simulation time 50396858 ps
CPU time 2.05 seconds
Started Sep 01 08:48:11 PM UTC 24
Finished Sep 01 08:48:14 PM UTC 24
Peak memory 224388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761713573 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.2761713573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_intr_test.1261858477
Short name T1109
Test name
Test status
Simulation time 11832618 ps
CPU time 1.08 seconds
Started Sep 01 08:48:11 PM UTC 24
Finished Sep 01 08:48:13 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261858477 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.1261858477
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3950781796
Short name T1125
Test name
Test status
Simulation time 141406623 ps
CPU time 4.03 seconds
Started Sep 01 08:48:11 PM UTC 24
Finished Sep 01 08:48:16 PM UTC 24
Peak memory 224316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950781796 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_same_csr_outstanding.3950781796
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_errors.3443027044
Short name T1117
Test name
Test status
Simulation time 42051955 ps
CPU time 3.07 seconds
Started Sep 01 08:48:11 PM UTC 24
Finished Sep 01 08:48:15 PM UTC 24
Peak memory 226252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443027044 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.3443027044
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/19.spi_device_tl_intg_err.1129975522
Short name T1137
Test name
Test status
Simulation time 206093010 ps
CPU time 7.57 seconds
Started Sep 01 08:48:11 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 226192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129975522 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_intg_err.1129975522
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_aliasing.795130042
Short name T1062
Test name
Test status
Simulation time 5397265762 ps
CPU time 32.33 seconds
Started Sep 01 08:47:24 PM UTC 24
Finished Sep 01 08:47:57 PM UTC 24
Peak memory 224180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=795130042 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_aliasing.795130042
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_csr_aliasing/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_bit_bash.438716285
Short name T1046
Test name
Test status
Simulation time 1231079959 ps
CPU time 28.63 seconds
Started Sep 01 08:47:24 PM UTC 24
Finished Sep 01 08:47:54 PM UTC 24
Peak memory 213868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=438716285 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_bit_bash.438716285
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_csr_bit_bash/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3837068060
Short name T120
Test name
Test status
Simulation time 54500262 ps
CPU time 1.69 seconds
Started Sep 01 08:47:22 PM UTC 24
Finished Sep 01 08:47:25 PM UTC 24
Peak memory 213744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837068060 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_hw_reset.3837068060
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_csr_hw_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2168944008
Short name T156
Test name
Test status
Simulation time 364876100 ps
CPU time 3.58 seconds
Started Sep 01 08:47:25 PM UTC 24
Finished Sep 01 08:47:29 PM UTC 24
Peak memory 226268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2168944008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
2.spi_device_csr_mem_rw_with_rand_reset.2168944008
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.3564676265
Short name T1028
Test name
Test status
Simulation time 115005209 ps
CPU time 2.62 seconds
Started Sep 01 08:47:23 PM UTC 24
Finished Sep 01 08:47:26 PM UTC 24
Peak memory 224072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3564676265 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3564676265
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2269144896
Short name T1026
Test name
Test status
Simulation time 11433816 ps
CPU time 1.16 seconds
Started Sep 01 08:47:19 PM UTC 24
Finished Sep 01 08:47:21 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2269144896 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2269144896
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.364357950
Short name T161
Test name
Test status
Simulation time 64053417 ps
CPU time 2 seconds
Started Sep 01 08:47:21 PM UTC 24
Finished Sep 01 08:47:24 PM UTC 24
Peak memory 222928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364357950 -assert nopostpr
oc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_partial_access.364357950
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_mem_partial_access/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.2773044948
Short name T1027
Test name
Test status
Simulation time 10473600 ps
CPU time 1.04 seconds
Started Sep 01 08:47:20 PM UTC 24
Finished Sep 01 08:47:22 PM UTC 24
Peak memory 211452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773044948 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_walk.2773044948
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_mem_walk/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1300496763
Short name T1029
Test name
Test status
Simulation time 428745755 ps
CPU time 4.31 seconds
Started Sep 01 08:47:24 PM UTC 24
Finished Sep 01 08:47:29 PM UTC 24
Peak memory 224056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300496763 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_same_csr_outstanding.1300496763
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.3839319073
Short name T150
Test name
Test status
Simulation time 33011028 ps
CPU time 2.84 seconds
Started Sep 01 08:47:19 PM UTC 24
Finished Sep 01 08:47:23 PM UTC 24
Peak memory 224276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839319073 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.3839319073
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_intg_err.1890657212
Short name T142
Test name
Test status
Simulation time 1412853458 ps
CPU time 9.95 seconds
Started Sep 01 08:47:19 PM UTC 24
Finished Sep 01 08:47:30 PM UTC 24
Peak memory 226256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890657212 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_intg_err.1890657212
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/20.spi_device_intr_test.3142418183
Short name T1115
Test name
Test status
Simulation time 46037513 ps
CPU time 1.1 seconds
Started Sep 01 08:48:13 PM UTC 24
Finished Sep 01 08:48:15 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142418183 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.3142418183
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/21.spi_device_intr_test.2126440231
Short name T1116
Test name
Test status
Simulation time 17154545 ps
CPU time 1.17 seconds
Started Sep 01 08:48:13 PM UTC 24
Finished Sep 01 08:48:15 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126440231 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.2126440231
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/22.spi_device_intr_test.674807141
Short name T1118
Test name
Test status
Simulation time 27899568 ps
CPU time 1.13 seconds
Started Sep 01 08:48:13 PM UTC 24
Finished Sep 01 08:48:15 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674807141 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.674807141
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/23.spi_device_intr_test.2413219741
Short name T1119
Test name
Test status
Simulation time 26103853 ps
CPU time 1.14 seconds
Started Sep 01 08:48:13 PM UTC 24
Finished Sep 01 08:48:15 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413219741 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.2413219741
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/24.spi_device_intr_test.2772591714
Short name T1120
Test name
Test status
Simulation time 15688218 ps
CPU time 1.11 seconds
Started Sep 01 08:48:13 PM UTC 24
Finished Sep 01 08:48:15 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772591714 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.2772591714
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/25.spi_device_intr_test.1664827935
Short name T1121
Test name
Test status
Simulation time 47836954 ps
CPU time 1.07 seconds
Started Sep 01 08:48:13 PM UTC 24
Finished Sep 01 08:48:15 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1664827935 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.1664827935
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/26.spi_device_intr_test.235170678
Short name T1122
Test name
Test status
Simulation time 34429581 ps
CPU time 1.16 seconds
Started Sep 01 08:48:13 PM UTC 24
Finished Sep 01 08:48:15 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=235170678 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.235170678
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/27.spi_device_intr_test.2139632945
Short name T1128
Test name
Test status
Simulation time 20320304 ps
CPU time 1.14 seconds
Started Sep 01 08:48:15 PM UTC 24
Finished Sep 01 08:48:17 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139632945 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.2139632945
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/28.spi_device_intr_test.3908956546
Short name T1126
Test name
Test status
Simulation time 31929349 ps
CPU time 0.96 seconds
Started Sep 01 08:48:15 PM UTC 24
Finished Sep 01 08:48:17 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908956546 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.3908956546
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/29.spi_device_intr_test.1593160655
Short name T1131
Test name
Test status
Simulation time 57209369 ps
CPU time 1.12 seconds
Started Sep 01 08:48:15 PM UTC 24
Finished Sep 01 08:48:17 PM UTC 24
Peak memory 211392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1593160655 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.1593160655
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_aliasing.3766644355
Short name T166
Test name
Test status
Simulation time 1231482415 ps
CPU time 10.22 seconds
Started Sep 01 08:47:32 PM UTC 24
Finished Sep 01 08:47:43 PM UTC 24
Peak memory 213828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766644355 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_aliasing.3766644355
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_csr_aliasing/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1384057723
Short name T1045
Test name
Test status
Simulation time 4116933876 ps
CPU time 17.92 seconds
Started Sep 01 08:47:30 PM UTC 24
Finished Sep 01 08:47:50 PM UTC 24
Peak memory 214096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384057723 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_bit_bash.1384057723
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_csr_bit_bash/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_hw_reset.1682077424
Short name T121
Test name
Test status
Simulation time 62530541 ps
CPU time 1.75 seconds
Started Sep 01 08:47:30 PM UTC 24
Finished Sep 01 08:47:33 PM UTC 24
Peak memory 212960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682077424 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_hw_reset.1682077424
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_csr_hw_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.1205726039
Short name T155
Test name
Test status
Simulation time 107889863 ps
CPU time 3.87 seconds
Started Sep 01 08:47:33 PM UTC 24
Finished Sep 01 08:47:38 PM UTC 24
Peak memory 226076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1205726039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
3.spi_device_csr_mem_rw_with_rand_reset.1205726039
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_csr_rw.3290202604
Short name T164
Test name
Test status
Simulation time 37476320 ps
CPU time 3.19 seconds
Started Sep 01 08:47:30 PM UTC 24
Finished Sep 01 08:47:35 PM UTC 24
Peak memory 224128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290202604 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3290202604
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_intr_test.575754419
Short name T1030
Test name
Test status
Simulation time 14865770 ps
CPU time 1.11 seconds
Started Sep 01 08:47:27 PM UTC 24
Finished Sep 01 08:47:29 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575754419 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.575754419
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_partial_access.2371713198
Short name T163
Test name
Test status
Simulation time 52656262 ps
CPU time 1.8 seconds
Started Sep 01 08:47:29 PM UTC 24
Finished Sep 01 08:47:32 PM UTC 24
Peak memory 222928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2371713198 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_partial_access.2371713198
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_mem_partial_access/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_mem_walk.1652592413
Short name T1031
Test name
Test status
Simulation time 14920189 ps
CPU time 1.03 seconds
Started Sep 01 08:47:29 PM UTC 24
Finished Sep 01 08:47:31 PM UTC 24
Peak memory 211452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652592413 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_walk.1652592413
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_mem_walk/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.2650358233
Short name T1035
Test name
Test status
Simulation time 152271044 ps
CPU time 5.39 seconds
Started Sep 01 08:47:32 PM UTC 24
Finished Sep 01 08:47:38 PM UTC 24
Peak memory 224128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650358233 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_same_csr_outstanding.2650358233
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_errors.1154487701
Short name T146
Test name
Test status
Simulation time 331922895 ps
CPU time 5.48 seconds
Started Sep 01 08:47:26 PM UTC 24
Finished Sep 01 08:47:33 PM UTC 24
Peak memory 224264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154487701 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.1154487701
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/3.spi_device_tl_intg_err.2807313725
Short name T154
Test name
Test status
Simulation time 402061176 ps
CPU time 16.76 seconds
Started Sep 01 08:47:26 PM UTC 24
Finished Sep 01 08:47:44 PM UTC 24
Peak memory 224352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2807313725 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_intg_err.2807313725
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/30.spi_device_intr_test.2097289862
Short name T1133
Test name
Test status
Simulation time 12255322 ps
CPU time 1.07 seconds
Started Sep 01 08:48:15 PM UTC 24
Finished Sep 01 08:48:17 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097289862 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.2097289862
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/31.spi_device_intr_test.3726910726
Short name T1132
Test name
Test status
Simulation time 26461787 ps
CPU time 1.13 seconds
Started Sep 01 08:48:15 PM UTC 24
Finished Sep 01 08:48:17 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3726910726 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.3726910726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/32.spi_device_intr_test.3663610455
Short name T1134
Test name
Test status
Simulation time 24184518 ps
CPU time 1.09 seconds
Started Sep 01 08:48:15 PM UTC 24
Finished Sep 01 08:48:17 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3663610455 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.3663610455
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/33.spi_device_intr_test.351273814
Short name T1130
Test name
Test status
Simulation time 33007293 ps
CPU time 1.12 seconds
Started Sep 01 08:48:15 PM UTC 24
Finished Sep 01 08:48:17 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351273814 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.351273814
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/34.spi_device_intr_test.3463667658
Short name T1135
Test name
Test status
Simulation time 24566363 ps
CPU time 1.17 seconds
Started Sep 01 08:48:15 PM UTC 24
Finished Sep 01 08:48:18 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463667658 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.3463667658
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/35.spi_device_intr_test.1403520755
Short name T1127
Test name
Test status
Simulation time 12325363 ps
CPU time 1.02 seconds
Started Sep 01 08:48:15 PM UTC 24
Finished Sep 01 08:48:17 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403520755 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.1403520755
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/36.spi_device_intr_test.2031754614
Short name T1136
Test name
Test status
Simulation time 89127177 ps
CPU time 0.89 seconds
Started Sep 01 08:48:17 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031754614 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.2031754614
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/37.spi_device_intr_test.1185050528
Short name T1140
Test name
Test status
Simulation time 26198900 ps
CPU time 1.12 seconds
Started Sep 01 08:48:17 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185050528 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.1185050528
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/38.spi_device_intr_test.2212282414
Short name T1142
Test name
Test status
Simulation time 82244894 ps
CPU time 1.09 seconds
Started Sep 01 08:48:17 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212282414 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.2212282414
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/39.spi_device_intr_test.3434343434
Short name T1139
Test name
Test status
Simulation time 150406924 ps
CPU time 0.94 seconds
Started Sep 01 08:48:17 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434343434 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.3434343434
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_aliasing.252044390
Short name T167
Test name
Test status
Simulation time 110639863 ps
CPU time 9.22 seconds
Started Sep 01 08:47:39 PM UTC 24
Finished Sep 01 08:47:49 PM UTC 24
Peak memory 213872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252044390 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_aliasing.252044390
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_csr_aliasing/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1943240930
Short name T1105
Test name
Test status
Simulation time 3756207200 ps
CPU time 33.59 seconds
Started Sep 01 08:47:37 PM UTC 24
Finished Sep 01 08:48:12 PM UTC 24
Peak memory 214088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943240930 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_bit_bash.1943240930
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_csr_bit_bash/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2493081919
Short name T122
Test name
Test status
Simulation time 187706950 ps
CPU time 2.17 seconds
Started Sep 01 08:47:35 PM UTC 24
Finished Sep 01 08:47:39 PM UTC 24
Peak memory 226312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493081919 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_hw_reset.2493081919
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_csr_hw_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.100984365
Short name T153
Test name
Test status
Simulation time 291317793 ps
CPU time 3.73 seconds
Started Sep 01 08:47:39 PM UTC 24
Finished Sep 01 08:47:43 PM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=100984365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
4.spi_device_csr_mem_rw_with_rand_reset.100984365
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_csr_rw.1826254141
Short name T1036
Test name
Test status
Simulation time 88820343 ps
CPU time 2.48 seconds
Started Sep 01 08:47:35 PM UTC 24
Finished Sep 01 08:47:39 PM UTC 24
Peak memory 213900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826254141 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.1826254141
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_intr_test.2618463293
Short name T1032
Test name
Test status
Simulation time 28501912 ps
CPU time 0.95 seconds
Started Sep 01 08:47:33 PM UTC 24
Finished Sep 01 08:47:35 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618463293 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2618463293
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_partial_access.1797072759
Short name T1034
Test name
Test status
Simulation time 338444644 ps
CPU time 2.67 seconds
Started Sep 01 08:47:34 PM UTC 24
Finished Sep 01 08:47:38 PM UTC 24
Peak memory 224160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797072759 -assert nopostp
roc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_partial_access.1797072759
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_mem_partial_access/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_mem_walk.3558339428
Short name T1033
Test name
Test status
Simulation time 29607497 ps
CPU time 1.02 seconds
Started Sep 01 08:47:34 PM UTC 24
Finished Sep 01 08:47:36 PM UTC 24
Peak memory 211452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558339428 -assert nopostproc +UVM_T
ESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_walk.3558339428
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_mem_walk/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.4228936758
Short name T1038
Test name
Test status
Simulation time 74923864 ps
CPU time 3.49 seconds
Started Sep 01 08:47:39 PM UTC 24
Finished Sep 01 08:47:43 PM UTC 24
Peak memory 224312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228936758 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_same_csr_outstanding.4228936758
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_errors.3570549126
Short name T147
Test name
Test status
Simulation time 199441436 ps
CPU time 4.17 seconds
Started Sep 01 08:47:33 PM UTC 24
Finished Sep 01 08:47:38 PM UTC 24
Peak memory 224276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570549126 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3570549126
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/4.spi_device_tl_intg_err.2601005464
Short name T1049
Test name
Test status
Simulation time 785640181 ps
CPU time 16.54 seconds
Started Sep 01 08:47:33 PM UTC 24
Finished Sep 01 08:47:51 PM UTC 24
Peak memory 226188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2601005464 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_intg_err.2601005464
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/40.spi_device_intr_test.2677540320
Short name T1138
Test name
Test status
Simulation time 23455002 ps
CPU time 0.88 seconds
Started Sep 01 08:48:17 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677540320 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.2677540320
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/41.spi_device_intr_test.1928906070
Short name T1141
Test name
Test status
Simulation time 17868783 ps
CPU time 1.06 seconds
Started Sep 01 08:48:18 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928906070 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.1928906070
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/42.spi_device_intr_test.2531532576
Short name T1147
Test name
Test status
Simulation time 35640047 ps
CPU time 1.05 seconds
Started Sep 01 08:48:18 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531532576 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.2531532576
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/43.spi_device_intr_test.1991406527
Short name T1148
Test name
Test status
Simulation time 16419363 ps
CPU time 1.18 seconds
Started Sep 01 08:48:18 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991406527 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.1991406527
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/44.spi_device_intr_test.1410490874
Short name T1143
Test name
Test status
Simulation time 15450893 ps
CPU time 1.07 seconds
Started Sep 01 08:48:18 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410490874 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.1410490874
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/45.spi_device_intr_test.2958077578
Short name T1144
Test name
Test status
Simulation time 54827208 ps
CPU time 1 seconds
Started Sep 01 08:48:18 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958077578 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.2958077578
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/46.spi_device_intr_test.4124500682
Short name T1146
Test name
Test status
Simulation time 172449210 ps
CPU time 0.93 seconds
Started Sep 01 08:48:18 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4124500682 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.4124500682
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/47.spi_device_intr_test.2082426175
Short name T1149
Test name
Test status
Simulation time 12521454 ps
CPU time 0.96 seconds
Started Sep 01 08:48:18 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082426175 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.2082426175
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/48.spi_device_intr_test.983755205
Short name T1150
Test name
Test status
Simulation time 15415241 ps
CPU time 1.17 seconds
Started Sep 01 08:48:18 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 211380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=983755205 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.983755205
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/49.spi_device_intr_test.2995232723
Short name T1145
Test name
Test status
Simulation time 13754014 ps
CPU time 0.93 seconds
Started Sep 01 08:48:18 PM UTC 24
Finished Sep 01 08:48:20 PM UTC 24
Peak memory 211452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995232723 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.2995232723
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.3513653425
Short name T1050
Test name
Test status
Simulation time 651065066 ps
CPU time 5.46 seconds
Started Sep 01 08:47:44 PM UTC 24
Finished Sep 01 08:47:51 PM UTC 24
Peak memory 228240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3513653425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
5.spi_device_csr_mem_rw_with_rand_reset.3513653425
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_csr_rw.2795254148
Short name T1039
Test name
Test status
Simulation time 69328804 ps
CPU time 1.89 seconds
Started Sep 01 08:47:42 PM UTC 24
Finished Sep 01 08:47:45 PM UTC 24
Peak memory 222884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795254148 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.2795254148
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_intr_test.120296052
Short name T1037
Test name
Test status
Simulation time 15055112 ps
CPU time 1.08 seconds
Started Sep 01 08:47:40 PM UTC 24
Finished Sep 01 08:47:42 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=120296052 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.120296052
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3213312159
Short name T1041
Test name
Test status
Simulation time 140568853 ps
CPU time 4.3 seconds
Started Sep 01 08:47:43 PM UTC 24
Finished Sep 01 08:47:48 PM UTC 24
Peak memory 224040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213312159 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_same_csr_outstanding.3213312159
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/5.spi_device_tl_intg_err.3511444862
Short name T220
Test name
Test status
Simulation time 307183452 ps
CPU time 19.13 seconds
Started Sep 01 08:47:40 PM UTC 24
Finished Sep 01 08:48:00 PM UTC 24
Peak memory 224152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511444862 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_intg_err.3511444862
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1187230934
Short name T151
Test name
Test status
Simulation time 529775175 ps
CPU time 4.75 seconds
Started Sep 01 08:47:46 PM UTC 24
Finished Sep 01 08:47:51 PM UTC 24
Peak memory 226272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=1187230934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
6.spi_device_csr_mem_rw_with_rand_reset.1187230934
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_csr_rw.2102583546
Short name T1044
Test name
Test status
Simulation time 93917056 ps
CPU time 3.84 seconds
Started Sep 01 08:47:44 PM UTC 24
Finished Sep 01 08:47:49 PM UTC 24
Peak memory 224148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102583546 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2102583546
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_intr_test.1199731008
Short name T1040
Test name
Test status
Simulation time 15289057 ps
CPU time 1.14 seconds
Started Sep 01 08:47:44 PM UTC 24
Finished Sep 01 08:47:47 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199731008 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1199731008
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2036267664
Short name T1043
Test name
Test status
Simulation time 432600467 ps
CPU time 2.61 seconds
Started Sep 01 08:47:46 PM UTC 24
Finished Sep 01 08:47:49 PM UTC 24
Peak memory 224108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036267664 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_same_csr_outstanding.2036267664
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_errors.554548270
Short name T1047
Test name
Test status
Simulation time 168386435 ps
CPU time 4.35 seconds
Started Sep 01 08:47:44 PM UTC 24
Finished Sep 01 08:47:50 PM UTC 24
Peak memory 226508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554548270 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.554548270
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/6.spi_device_tl_intg_err.1527449119
Short name T221
Test name
Test status
Simulation time 295399645 ps
CPU time 18.09 seconds
Started Sep 01 08:47:44 PM UTC 24
Finished Sep 01 08:48:04 PM UTC 24
Peak memory 224132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527449119 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_intg_err.1527449119
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2461140187
Short name T1057
Test name
Test status
Simulation time 541389571 ps
CPU time 3.75 seconds
Started Sep 01 08:47:50 PM UTC 24
Finished Sep 01 08:47:55 PM UTC 24
Peak memory 226260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2461140187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
7.spi_device_csr_mem_rw_with_rand_reset.2461140187
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_csr_rw.2423174783
Short name T1051
Test name
Test status
Simulation time 75222576 ps
CPU time 1.97 seconds
Started Sep 01 08:47:48 PM UTC 24
Finished Sep 01 08:47:51 PM UTC 24
Peak memory 222884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423174783 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.2423174783
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_intr_test.491038889
Short name T1048
Test name
Test status
Simulation time 25271414 ps
CPU time 1.12 seconds
Started Sep 01 08:47:48 PM UTC 24
Finished Sep 01 08:47:50 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491038889 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.491038889
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.875012630
Short name T1056
Test name
Test status
Simulation time 416708029 ps
CPU time 4.11 seconds
Started Sep 01 08:47:49 PM UTC 24
Finished Sep 01 08:47:54 PM UTC 24
Peak memory 224328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875012630 -assert nopost
proc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_same_csr_outstanding.875012630
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_errors.330257561
Short name T152
Test name
Test status
Simulation time 443606715 ps
CPU time 4.02 seconds
Started Sep 01 08:47:47 PM UTC 24
Finished Sep 01 08:47:52 PM UTC 24
Peak memory 226324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330257561 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.330257561
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/7.spi_device_tl_intg_err.3407069362
Short name T215
Test name
Test status
Simulation time 1122787497 ps
CPU time 21.78 seconds
Started Sep 01 08:47:47 PM UTC 24
Finished Sep 01 08:48:10 PM UTC 24
Peak memory 226200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407069362 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_intg_err.3407069362
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.3499232240
Short name T1058
Test name
Test status
Simulation time 526090048 ps
CPU time 3.35 seconds
Started Sep 01 08:47:52 PM UTC 24
Finished Sep 01 08:47:56 PM UTC 24
Peak memory 226184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=3499232240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
8.spi_device_csr_mem_rw_with_rand_reset.3499232240
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_csr_rw.1521427014
Short name T1053
Test name
Test status
Simulation time 23170765 ps
CPU time 1.93 seconds
Started Sep 01 08:47:51 PM UTC 24
Finished Sep 01 08:47:54 PM UTC 24
Peak memory 222884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521427014 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1521427014
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_intr_test.2968420829
Short name T1052
Test name
Test status
Simulation time 17600562 ps
CPU time 1.18 seconds
Started Sep 01 08:47:51 PM UTC 24
Finished Sep 01 08:47:53 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2968420829 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.2968420829
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.2078751675
Short name T1061
Test name
Test status
Simulation time 403107266 ps
CPU time 5.52 seconds
Started Sep 01 08:47:51 PM UTC 24
Finished Sep 01 08:47:57 PM UTC 24
Peak memory 224140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078751675 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_same_csr_outstanding.2078751675
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_errors.776215439
Short name T1054
Test name
Test status
Simulation time 50267760 ps
CPU time 2.32 seconds
Started Sep 01 08:47:50 PM UTC 24
Finished Sep 01 08:47:54 PM UTC 24
Peak memory 224460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776215439 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.776215439
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/8.spi_device_tl_intg_err.2845799292
Short name T1093
Test name
Test status
Simulation time 214717237 ps
CPU time 16.51 seconds
Started Sep 01 08:47:50 PM UTC 24
Finished Sep 01 08:48:08 PM UTC 24
Peak memory 224136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845799292 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_intg_err.2845799292
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.2767870652
Short name T1064
Test name
Test status
Simulation time 156472381 ps
CPU time 3.71 seconds
Started Sep 01 08:47:53 PM UTC 24
Finished Sep 01 08:47:58 PM UTC 24
Peak memory 226248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=1000000000
0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_r
andom_seed=2767870652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name
9.spi_device_csr_mem_rw_with_rand_reset.2767870652
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_csr_mem_rw_with_rand_reset/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_csr_rw.3399144344
Short name T1060
Test name
Test status
Simulation time 145750760 ps
CPU time 3.57 seconds
Started Sep 01 08:47:52 PM UTC 24
Finished Sep 01 08:47:57 PM UTC 24
Peak memory 224064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399144344 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3399144344
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_csr_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_intr_test.4023400128
Short name T1055
Test name
Test status
Simulation time 37004887 ps
CPU time 1.1 seconds
Started Sep 01 08:47:52 PM UTC 24
Finished Sep 01 08:47:54 PM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023400128 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.4023400128
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_intr_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3101030612
Short name T1065
Test name
Test status
Simulation time 64077824 ps
CPU time 3.87 seconds
Started Sep 01 08:47:53 PM UTC 24
Finished Sep 01 08:47:58 PM UTC 24
Peak memory 224020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_en
abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101030612 -assert nopos
tproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_same_csr_outstanding.3101030612
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_same_csr_outstanding/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_errors.295305813
Short name T1067
Test name
Test status
Simulation time 180337015 ps
CPU time 6.26 seconds
Started Sep 01 08:47:52 PM UTC 24
Finished Sep 01 08:47:59 PM UTC 24
Peak memory 224284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295305813 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.295305813
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_tl_errors/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top/9.spi_device_tl_intg_err.2862867158
Short name T219
Test name
Test status
Simulation time 1072453170 ps
CPU time 16.23 seconds
Started Sep 01 08:47:52 PM UTC 24
Finished Sep 01 08:48:09 PM UTC 24
Peak memory 226320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +
UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862867158 -assert nopostproc +UV
M_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_intg_err.2862867158
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_tl_intg_err/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_cfg_cmd.2322202922
Short name T25
Test name
Test status
Simulation time 6264234008 ps
CPU time 12.35 seconds
Started Sep 01 08:33:56 PM UTC 24
Finished Sep 01 08:34:10 PM UTC 24
Peak memory 235592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322202922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2322202922
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_all.1692074961
Short name T267
Test name
Test status
Simulation time 119361790524 ps
CPU time 465.95 seconds
Started Sep 01 08:33:57 PM UTC 24
Finished Sep 01 08:41:49 PM UTC 24
Peak memory 282568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1692074961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1692074961
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm.1409358024
Short name T252
Test name
Test status
Simulation time 12460122831 ps
CPU time 130.15 seconds
Started Sep 01 08:33:57 PM UTC 24
Finished Sep 01 08:36:10 PM UTC 24
Peak memory 262180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409358024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.1409358024
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_and_tpm_min_idle.1784495524
Short name T109
Test name
Test status
Simulation time 10711318093 ps
CPU time 98.78 seconds
Started Sep 01 08:33:57 PM UTC 24
Finished Sep 01 08:35:38 PM UTC 24
Peak memory 266252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784495524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle.1784495524
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_flash_mode_ignore_cmds.4161733121
Short name T243
Test name
Test status
Simulation time 17216604488 ps
CPU time 138.83 seconds
Started Sep 01 08:33:57 PM UTC 24
Finished Sep 01 08:36:19 PM UTC 24
Peak memory 249808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161733121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.4161733121
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_intercept.3788948192
Short name T13
Test name
Test status
Simulation time 385350157 ps
CPU time 5.1 seconds
Started Sep 01 08:33:56 PM UTC 24
Finished Sep 01 08:34:02 PM UTC 24
Peak memory 245796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788948192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3788948192
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.3588195597
Short name T210
Test name
Test status
Simulation time 6616619600 ps
CPU time 64.06 seconds
Started Sep 01 08:33:56 PM UTC 24
Finished Sep 01 08:35:02 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588195597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3588195597
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_addr_payload_swap.3783544221
Short name T16
Test name
Test status
Simulation time 2520928316 ps
CPU time 6.45 seconds
Started Sep 01 08:33:56 PM UTC 24
Finished Sep 01 08:34:03 PM UTC 24
Peak memory 251860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3783544221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.3783544221
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_pass_cmd_filtering.3816279945
Short name T20
Test name
Test status
Simulation time 1340502898 ps
CPU time 8.85 seconds
Started Sep 01 08:33:56 PM UTC 24
Finished Sep 01 08:34:06 PM UTC 24
Peak memory 245232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816279945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3816279945
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_read_buffer_direct.1226020705
Short name T18
Test name
Test status
Simulation time 621858013 ps
CPU time 6.19 seconds
Started Sep 01 08:33:57 PM UTC 24
Finished Sep 01 08:34:04 PM UTC 24
Peak memory 231856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226020705 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_direct.1226020705
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_stress_all.1746776077
Short name T116
Test name
Test status
Simulation time 77412130426 ps
CPU time 228.8 seconds
Started Sep 01 08:33:57 PM UTC 24
Finished Sep 01 08:37:50 PM UTC 24
Peak memory 268292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746776077 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress_all.1746776077
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_read_hw_reg.1764058045
Short name T29
Test name
Test status
Simulation time 13857337851 ps
CPU time 19.14 seconds
Started Sep 01 08:33:56 PM UTC 24
Finished Sep 01 08:34:16 PM UTC 24
Peak memory 227884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764058045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1764058045
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_rw.263174020
Short name T11
Test name
Test status
Simulation time 269755623 ps
CPU time 3.86 seconds
Started Sep 01 08:33:56 PM UTC 24
Finished Sep 01 08:34:01 PM UTC 24
Peak memory 227760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263174020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.263174020
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/0.spi_device_tpm_sts_read.2273200517
Short name T4
Test name
Test status
Simulation time 88423905 ps
CPU time 0.96 seconds
Started Sep 01 08:33:56 PM UTC 24
Finished Sep 01 08:33:58 PM UTC 24
Peak memory 214740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273200517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.2273200517
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/0.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_alert_test.3126372693
Short name T38
Test name
Test status
Simulation time 21909604 ps
CPU time 1.12 seconds
Started Sep 01 08:34:00 PM UTC 24
Finished Sep 01 08:34:03 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3126372693 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3126372693
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_csb_read.167377810
Short name T6
Test name
Test status
Simulation time 19678838 ps
CPU time 0.96 seconds
Started Sep 01 08:33:57 PM UTC 24
Finished Sep 01 08:34:00 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167377810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.167377810
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.1902138231
Short name T85
Test name
Test status
Simulation time 4923231771 ps
CPU time 34.15 seconds
Started Sep 01 08:33:59 PM UTC 24
Finished Sep 01 08:34:35 PM UTC 24
Peak memory 232116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902138231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1902138231
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mailbox.2216586708
Short name T64
Test name
Test status
Simulation time 749381844 ps
CPU time 10.81 seconds
Started Sep 01 08:33:58 PM UTC 24
Finished Sep 01 08:34:10 PM UTC 24
Peak memory 235528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216586708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.2216586708
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_mem_parity.3745315303
Short name T9
Test name
Test status
Simulation time 25501927 ps
CPU time 1.55 seconds
Started Sep 01 08:33:57 PM UTC 24
Finished Sep 01 08:34:00 PM UTC 24
Peak memory 229264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3745315303 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mem_parity.3745315303
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_addr_payload_swap.261734638
Short name T73
Test name
Test status
Simulation time 31800182978 ps
CPU time 87.48 seconds
Started Sep 01 08:33:58 PM UTC 24
Finished Sep 01 08:35:27 PM UTC 24
Peak memory 245808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261734638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.261734638
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_pass_cmd_filtering.1968088814
Short name T60
Test name
Test status
Simulation time 5533970935 ps
CPU time 20.38 seconds
Started Sep 01 08:33:58 PM UTC 24
Finished Sep 01 08:34:19 PM UTC 24
Peak memory 245748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968088814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1968088814
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_read_buffer_direct.1080178713
Short name T21
Test name
Test status
Simulation time 1282364034 ps
CPU time 6.86 seconds
Started Sep 01 08:33:59 PM UTC 24
Finished Sep 01 08:34:07 PM UTC 24
Peak memory 231664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080178713 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direct.1080178713
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_sec_cm.2137981140
Short name T30
Test name
Test status
Simulation time 80468084 ps
CPU time 1.3 seconds
Started Sep 01 08:34:00 PM UTC 24
Finished Sep 01 08:34:03 PM UTC 24
Peak memory 257736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137981140 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2137981140
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_sec_cm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_stress_all.3385835958
Short name T12
Test name
Test status
Simulation time 97696462 ps
CPU time 1.37 seconds
Started Sep 01 08:33:59 PM UTC 24
Finished Sep 01 08:34:02 PM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385835958 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress_all.3385835958
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_tpm_sts_read.1741181417
Short name T8
Test name
Test status
Simulation time 225289540 ps
CPU time 1.2 seconds
Started Sep 01 08:33:58 PM UTC 24
Finished Sep 01 08:34:00 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741181417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1741181417
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/1.spi_device_upload.2011731464
Short name T59
Test name
Test status
Simulation time 3788843226 ps
CPU time 13.85 seconds
Started Sep 01 08:33:59 PM UTC 24
Finished Sep 01 08:34:14 PM UTC 24
Peak memory 245692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011731464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2011731464
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/1.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_alert_test.2845996326
Short name T455
Test name
Test status
Simulation time 17462835 ps
CPU time 1.11 seconds
Started Sep 01 08:35:56 PM UTC 24
Finished Sep 01 08:35:59 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845996326 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.2845996326
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_cfg_cmd.1694871649
Short name T317
Test name
Test status
Simulation time 244643727 ps
CPU time 4.58 seconds
Started Sep 01 08:35:51 PM UTC 24
Finished Sep 01 08:35:57 PM UTC 24
Peak memory 235360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694871649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1694871649
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_csb_read.2990600879
Short name T191
Test name
Test status
Simulation time 77655106 ps
CPU time 1.09 seconds
Started Sep 01 08:35:43 PM UTC 24
Finished Sep 01 08:35:45 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990600879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2990600879
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_all.2669844036
Short name T208
Test name
Test status
Simulation time 3559776297 ps
CPU time 31.85 seconds
Started Sep 01 08:35:53 PM UTC 24
Finished Sep 01 08:36:26 PM UTC 24
Peak memory 249828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669844036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2669844036
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm.1613877206
Short name T419
Test name
Test status
Simulation time 793085959 ps
CPU time 13.5 seconds
Started Sep 01 08:35:53 PM UTC 24
Finished Sep 01 08:36:08 PM UTC 24
Peak memory 230008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613877206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.1613877206
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_mode.735609341
Short name T214
Test name
Test status
Simulation time 252569623 ps
CPU time 8.73 seconds
Started Sep 01 08:35:51 PM UTC 24
Finished Sep 01 08:36:01 PM UTC 24
Peak memory 235336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735609341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.735609341
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_intercept.1273516738
Short name T135
Test name
Test status
Simulation time 321372902 ps
CPU time 4.29 seconds
Started Sep 01 08:35:48 PM UTC 24
Finished Sep 01 08:35:53 PM UTC 24
Peak memory 235220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273516738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.1273516738
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mailbox.93847274
Short name T459
Test name
Test status
Simulation time 645852640 ps
CPU time 11.2 seconds
Started Sep 01 08:35:49 PM UTC 24
Finished Sep 01 08:36:01 PM UTC 24
Peak memory 251936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93847274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.93847274
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_mem_parity.3275837477
Short name T193
Test name
Test status
Simulation time 57312267 ps
CPU time 1.55 seconds
Started Sep 01 08:35:44 PM UTC 24
Finished Sep 01 08:35:47 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275837477 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mem_parity.3275837477
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_addr_payload_swap.2562831866
Short name T344
Test name
Test status
Simulation time 69729837 ps
CPU time 2.97 seconds
Started Sep 01 08:35:48 PM UTC 24
Finished Sep 01 08:35:52 PM UTC 24
Peak memory 245512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562831866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swap.2562831866
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_pass_cmd_filtering.1348950556
Short name T451
Test name
Test status
Simulation time 53168269 ps
CPU time 2.91 seconds
Started Sep 01 08:35:47 PM UTC 24
Finished Sep 01 08:35:50 PM UTC 24
Peak memory 234688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348950556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1348950556
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_read_buffer_direct.518480817
Short name T462
Test name
Test status
Simulation time 958053122 ps
CPU time 10.89 seconds
Started Sep 01 08:35:53 PM UTC 24
Finished Sep 01 08:36:05 PM UTC 24
Peak memory 231596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518480817 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_direct.518480817
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.434585186
Short name T37
Test name
Test status
Simulation time 4511270457 ps
CPU time 62.04 seconds
Started Sep 01 08:35:56 PM UTC 24
Finished Sep 01 08:37:00 PM UTC 24
Peak memory 268288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=434585186 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stress_all.434585186
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_all.1830525628
Short name T409
Test name
Test status
Simulation time 2382267737 ps
CPU time 12.24 seconds
Started Sep 01 08:35:44 PM UTC 24
Finished Sep 01 08:35:58 PM UTC 24
Peak memory 232048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830525628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1830525628
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_read_hw_reg.3057785282
Short name T454
Test name
Test status
Simulation time 3586420219 ps
CPU time 11.52 seconds
Started Sep 01 08:35:44 PM UTC 24
Finished Sep 01 08:35:57 PM UTC 24
Peak memory 228052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057785282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3057785282
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_rw.4021585082
Short name T450
Test name
Test status
Simulation time 56664295 ps
CPU time 2.23 seconds
Started Sep 01 08:35:46 PM UTC 24
Finished Sep 01 08:35:50 PM UTC 24
Peak memory 227700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021585082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.4021585082
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_tpm_sts_read.631887316
Short name T192
Test name
Test status
Simulation time 337409743 ps
CPU time 1.32 seconds
Started Sep 01 08:35:44 PM UTC 24
Finished Sep 01 08:35:47 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631887316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.631887316
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/10.spi_device_upload.3117702618
Short name T275
Test name
Test status
Simulation time 3070858767 ps
CPU time 18.38 seconds
Started Sep 01 08:35:50 PM UTC 24
Finished Sep 01 08:36:10 PM UTC 24
Peak memory 245664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117702618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.3117702618
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/10.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_alert_test.4090955757
Short name T464
Test name
Test status
Simulation time 24593661 ps
CPU time 1.13 seconds
Started Sep 01 08:36:09 PM UTC 24
Finished Sep 01 08:36:11 PM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090955757 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.4090955757
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_cfg_cmd.3910375331
Short name T463
Test name
Test status
Simulation time 276938252 ps
CPU time 3.05 seconds
Started Sep 01 08:36:03 PM UTC 24
Finished Sep 01 08:36:07 PM UTC 24
Peak memory 234600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910375331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3910375331
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_csb_read.2040618941
Short name T456
Test name
Test status
Simulation time 23414387 ps
CPU time 1.18 seconds
Started Sep 01 08:35:57 PM UTC 24
Finished Sep 01 08:36:00 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040618941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.2040618941
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_all.2943051140
Short name T239
Test name
Test status
Simulation time 32387895050 ps
CPU time 53.16 seconds
Started Sep 01 08:36:07 PM UTC 24
Finished Sep 01 08:37:02 PM UTC 24
Peak memory 262280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2943051140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.2943051140
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.2746658196
Short name T654
Test name
Test status
Simulation time 25886913380 ps
CPU time 309.42 seconds
Started Sep 01 08:36:08 PM UTC 24
Finished Sep 01 08:41:22 PM UTC 24
Peak memory 268324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746658196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2746658196
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode.1442014226
Short name T472
Test name
Test status
Simulation time 4091350004 ps
CPU time 17.29 seconds
Started Sep 01 08:36:06 PM UTC 24
Finished Sep 01 08:36:25 PM UTC 24
Peak memory 235592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442014226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.1442014226
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_mode_ignore_cmds.2082125069
Short name T339
Test name
Test status
Simulation time 30048573998 ps
CPU time 247.79 seconds
Started Sep 01 08:36:06 PM UTC 24
Finished Sep 01 08:40:18 PM UTC 24
Peak memory 262088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082125069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmds.2082125069
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_intercept.3438267954
Short name T326
Test name
Test status
Simulation time 6280901275 ps
CPU time 17.18 seconds
Started Sep 01 08:36:02 PM UTC 24
Finished Sep 01 08:36:20 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438267954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3438267954
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.761586565
Short name T241
Test name
Test status
Simulation time 10812980965 ps
CPU time 34.29 seconds
Started Sep 01 08:36:02 PM UTC 24
Finished Sep 01 08:36:38 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761586565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.761586565
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mem_parity.3445002690
Short name T457
Test name
Test status
Simulation time 77116342 ps
CPU time 1.52 seconds
Started Sep 01 08:35:58 PM UTC 24
Finished Sep 01 08:36:00 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445002690 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mem_parity.3445002690
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_addr_payload_swap.3038733590
Short name T460
Test name
Test status
Simulation time 34910768 ps
CPU time 2.94 seconds
Started Sep 01 08:36:01 PM UTC 24
Finished Sep 01 08:36:05 PM UTC 24
Peak memory 245324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038733590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap.3038733590
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_pass_cmd_filtering.2682368830
Short name T264
Test name
Test status
Simulation time 5007316596 ps
CPU time 11.69 seconds
Started Sep 01 08:36:01 PM UTC 24
Finished Sep 01 08:36:14 PM UTC 24
Peak memory 250028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682368830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2682368830
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_read_buffer_direct.946189784
Short name T469
Test name
Test status
Simulation time 450374554 ps
CPU time 6.94 seconds
Started Sep 01 08:36:06 PM UTC 24
Finished Sep 01 08:36:15 PM UTC 24
Peak memory 231856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946189784 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_direct.946189784
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.1547267488
Short name T184
Test name
Test status
Simulation time 28164889096 ps
CPU time 317.98 seconds
Started Sep 01 08:36:09 PM UTC 24
Finished Sep 01 08:41:32 PM UTC 24
Peak memory 295104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547267488 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stress_all.1547267488
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_all.448462532
Short name T414
Test name
Test status
Simulation time 1713849914 ps
CPU time 19.3 seconds
Started Sep 01 08:35:59 PM UTC 24
Finished Sep 01 08:36:19 PM UTC 24
Peak memory 229744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448462532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.448462532
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_read_hw_reg.1570837089
Short name T461
Test name
Test status
Simulation time 1238952432 ps
CPU time 6.36 seconds
Started Sep 01 08:35:58 PM UTC 24
Finished Sep 01 08:36:05 PM UTC 24
Peak memory 227888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570837089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1570837089
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_rw.1574214650
Short name T466
Test name
Test status
Simulation time 709738420 ps
CPU time 10.26 seconds
Started Sep 01 08:36:00 PM UTC 24
Finished Sep 01 08:36:11 PM UTC 24
Peak memory 227764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574214650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.1574214650
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_tpm_sts_read.317989616
Short name T458
Test name
Test status
Simulation time 128241165 ps
CPU time 1.11 seconds
Started Sep 01 08:35:59 PM UTC 24
Finished Sep 01 08:36:01 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317989616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.317989616
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/11.spi_device_upload.4128577629
Short name T312
Test name
Test status
Simulation time 117096049 ps
CPU time 3.13 seconds
Started Sep 01 08:36:02 PM UTC 24
Finished Sep 01 08:36:06 PM UTC 24
Peak memory 235268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128577629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.4128577629
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/11.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_alert_test.426102299
Short name T473
Test name
Test status
Simulation time 18862440 ps
CPU time 1 seconds
Started Sep 01 08:36:25 PM UTC 24
Finished Sep 01 08:36:27 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426102299 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.426102299
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_cfg_cmd.535025047
Short name T316
Test name
Test status
Simulation time 1361131891 ps
CPU time 6.88 seconds
Started Sep 01 08:36:18 PM UTC 24
Finished Sep 01 08:36:25 PM UTC 24
Peak memory 245736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=535025047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.535025047
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_csb_read.2016467498
Short name T465
Test name
Test status
Simulation time 23962305 ps
CPU time 1.16 seconds
Started Sep 01 08:36:09 PM UTC 24
Finished Sep 01 08:36:11 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2016467498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2016467498
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.3791151255
Short name T258
Test name
Test status
Simulation time 3866118169 ps
CPU time 25.08 seconds
Started Sep 01 08:36:21 PM UTC 24
Finished Sep 01 08:36:47 PM UTC 24
Peak memory 235468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3791151255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3791151255
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.1553916818
Short name T40
Test name
Test status
Simulation time 10356553755 ps
CPU time 101.36 seconds
Started Sep 01 08:36:21 PM UTC 24
Finished Sep 01 08:38:04 PM UTC 24
Peak memory 262144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553916818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle.1553916818
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode.339891773
Short name T494
Test name
Test status
Simulation time 10591532550 ps
CPU time 55.18 seconds
Started Sep 01 08:36:18 PM UTC 24
Finished Sep 01 08:37:14 PM UTC 24
Peak memory 262120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339891773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.339891773
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_mode_ignore_cmds.2633622804
Short name T377
Test name
Test status
Simulation time 67875356729 ps
CPU time 651.73 seconds
Started Sep 01 08:36:20 PM UTC 24
Finished Sep 01 08:47:20 PM UTC 24
Peak memory 278472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633622804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds.2633622804
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_intercept.1307952360
Short name T272
Test name
Test status
Simulation time 1818139372 ps
CPU time 17.35 seconds
Started Sep 01 08:36:14 PM UTC 24
Finished Sep 01 08:36:33 PM UTC 24
Peak memory 229824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307952360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1307952360
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mailbox.2145074015
Short name T471
Test name
Test status
Simulation time 107507027 ps
CPU time 3.23 seconds
Started Sep 01 08:36:15 PM UTC 24
Finished Sep 01 08:36:20 PM UTC 24
Peak memory 245252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145074015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.2145074015
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_mem_parity.2339277467
Short name T467
Test name
Test status
Simulation time 16040201 ps
CPU time 1.29 seconds
Started Sep 01 08:36:11 PM UTC 24
Finished Sep 01 08:36:13 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2339277467 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mem_parity.2339277467
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_addr_payload_swap.1508895277
Short name T75
Test name
Test status
Simulation time 297633630 ps
CPU time 9.02 seconds
Started Sep 01 08:36:14 PM UTC 24
Finished Sep 01 08:36:24 PM UTC 24
Peak memory 251752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508895277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap.1508895277
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_pass_cmd_filtering.1416024170
Short name T470
Test name
Test status
Simulation time 812993584 ps
CPU time 2.97 seconds
Started Sep 01 08:36:13 PM UTC 24
Finished Sep 01 08:36:17 PM UTC 24
Peak memory 234084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416024170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1416024170
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_read_buffer_direct.4211089679
Short name T478
Test name
Test status
Simulation time 2110008363 ps
CPU time 12.59 seconds
Started Sep 01 08:36:20 PM UTC 24
Finished Sep 01 08:36:33 PM UTC 24
Peak memory 231604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211089679 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_direct.4211089679
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_stress_all.2347601694
Short name T181
Test name
Test status
Simulation time 3516142007 ps
CPU time 75.74 seconds
Started Sep 01 08:36:25 PM UTC 24
Finished Sep 01 08:37:43 PM UTC 24
Peak memory 264360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347601694 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stress_all.2347601694
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.3248492815
Short name T408
Test name
Test status
Simulation time 9483523058 ps
CPU time 42.05 seconds
Started Sep 01 08:36:12 PM UTC 24
Finished Sep 01 08:36:56 PM UTC 24
Peak memory 228172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248492815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3248492815
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_read_hw_reg.524480806
Short name T486
Test name
Test status
Simulation time 28417538024 ps
CPU time 47.44 seconds
Started Sep 01 08:36:11 PM UTC 24
Finished Sep 01 08:37:00 PM UTC 24
Peak memory 227860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=524480806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.524480806
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_rw.926005
Short name T421
Test name
Test status
Simulation time 733495250 ps
CPU time 3.49 seconds
Started Sep 01 08:36:12 PM UTC 24
Finished Sep 01 08:36:17 PM UTC 24
Peak memory 227936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_
TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_device
_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.926005
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_sts_read.117416625
Short name T468
Test name
Test status
Simulation time 120954044 ps
CPU time 1.33 seconds
Started Sep 01 08:36:12 PM UTC 24
Finished Sep 01 08:36:14 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117416625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.117416625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/12.spi_device_upload.698978051
Short name T320
Test name
Test status
Simulation time 47280700 ps
CPU time 3.51 seconds
Started Sep 01 08:36:15 PM UTC 24
Finished Sep 01 08:36:20 PM UTC 24
Peak memory 251908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698978051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.698978051
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/12.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_alert_test.833292427
Short name T480
Test name
Test status
Simulation time 22627612 ps
CPU time 1.1 seconds
Started Sep 01 08:36:51 PM UTC 24
Finished Sep 01 08:36:53 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833292427 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.833292427
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_csb_read.3544468962
Short name T474
Test name
Test status
Simulation time 18994720 ps
CPU time 1.21 seconds
Started Sep 01 08:36:26 PM UTC 24
Finished Sep 01 08:36:28 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544468962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.3544468962
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.773880087
Short name T551
Test name
Test status
Simulation time 246834804288 ps
CPU time 132 seconds
Started Sep 01 08:36:46 PM UTC 24
Finished Sep 01 08:39:02 PM UTC 24
Peak memory 250056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773880087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.773880087
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.2714772770
Short name T202
Test name
Test status
Simulation time 6927419670 ps
CPU time 113.31 seconds
Started Sep 01 08:36:47 PM UTC 24
Finished Sep 01 08:38:43 PM UTC 24
Peak memory 268288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714772770 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2714772770
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode.1292062367
Short name T285
Test name
Test status
Simulation time 1259307905 ps
CPU time 6.3 seconds
Started Sep 01 08:36:39 PM UTC 24
Finished Sep 01 08:36:47 PM UTC 24
Peak memory 235464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292062367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1292062367
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.1210348657
Short name T224
Test name
Test status
Simulation time 1525713974 ps
CPU time 9.81 seconds
Started Sep 01 08:36:41 PM UTC 24
Finished Sep 01 08:36:53 PM UTC 24
Peak memory 251716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210348657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmds.1210348657
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_intercept.2597142424
Short name T237
Test name
Test status
Simulation time 9887440681 ps
CPU time 19.45 seconds
Started Sep 01 08:36:34 PM UTC 24
Finished Sep 01 08:36:54 PM UTC 24
Peak memory 245816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597142424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2597142424
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.605198168
Short name T255
Test name
Test status
Simulation time 3433943251 ps
CPU time 29 seconds
Started Sep 01 08:36:34 PM UTC 24
Finished Sep 01 08:37:04 PM UTC 24
Peak memory 247748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605198168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.605198168
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mem_parity.2337314975
Short name T475
Test name
Test status
Simulation time 32202811 ps
CPU time 1.55 seconds
Started Sep 01 08:36:26 PM UTC 24
Finished Sep 01 08:36:29 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337314975 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mem_parity.2337314975
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_addr_payload_swap.279258520
Short name T277
Test name
Test status
Simulation time 3615051611 ps
CPU time 6.22 seconds
Started Sep 01 08:36:33 PM UTC 24
Finished Sep 01 08:36:40 PM UTC 24
Peak memory 235400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=279258520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap.279258520
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_pass_cmd_filtering.3387993915
Short name T251
Test name
Test status
Simulation time 1822944722 ps
CPU time 13.09 seconds
Started Sep 01 08:36:32 PM UTC 24
Finished Sep 01 08:36:46 PM UTC 24
Peak memory 235344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387993915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3387993915
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_read_buffer_direct.3961844725
Short name T485
Test name
Test status
Simulation time 4548008728 ps
CPU time 14.04 seconds
Started Sep 01 08:36:44 PM UTC 24
Finished Sep 01 08:37:00 PM UTC 24
Peak memory 233872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961844725 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_direct.3961844725
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.654100749
Short name T298
Test name
Test status
Simulation time 13495858116 ps
CPU time 66 seconds
Started Sep 01 08:36:49 PM UTC 24
Finished Sep 01 08:37:56 PM UTC 24
Peak memory 264216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654100749 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stress_all.654100749
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_all.60108825
Short name T411
Test name
Test status
Simulation time 3439134983 ps
CPU time 46.31 seconds
Started Sep 01 08:36:28 PM UTC 24
Finished Sep 01 08:37:16 PM UTC 24
Peak memory 227928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=60108825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.60108825
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_read_hw_reg.440831359
Short name T477
Test name
Test status
Simulation time 433117508 ps
CPU time 4.57 seconds
Started Sep 01 08:36:27 PM UTC 24
Finished Sep 01 08:36:33 PM UTC 24
Peak memory 227696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440831359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.440831359
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_rw.2420052766
Short name T479
Test name
Test status
Simulation time 133395031 ps
CPU time 2.89 seconds
Started Sep 01 08:36:30 PM UTC 24
Finished Sep 01 08:36:34 PM UTC 24
Peak memory 227816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420052766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2420052766
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_tpm_sts_read.3067848552
Short name T476
Test name
Test status
Simulation time 124622723 ps
CPU time 1.38 seconds
Started Sep 01 08:36:29 PM UTC 24
Finished Sep 01 08:36:32 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067848552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.3067848552
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.585916956
Short name T242
Test name
Test status
Simulation time 1459321946 ps
CPU time 13.07 seconds
Started Sep 01 08:36:35 PM UTC 24
Finished Sep 01 08:36:50 PM UTC 24
Peak memory 245512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585916956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.585916956
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/13.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.2623314147
Short name T488
Test name
Test status
Simulation time 30635484 ps
CPU time 1.07 seconds
Started Sep 01 08:37:03 PM UTC 24
Finished Sep 01 08:37:05 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623314147 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.2623314147
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.1153155802
Short name T487
Test name
Test status
Simulation time 29981892 ps
CPU time 2.18 seconds
Started Sep 01 08:37:00 PM UTC 24
Finished Sep 01 08:37:04 PM UTC 24
Peak memory 234960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1153155802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1153155802
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_csb_read.1901856909
Short name T481
Test name
Test status
Simulation time 25712557 ps
CPU time 1.19 seconds
Started Sep 01 08:36:54 PM UTC 24
Finished Sep 01 08:36:56 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901856909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.1901856909
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.2801380909
Short name T117
Test name
Test status
Simulation time 19054342891 ps
CPU time 85.98 seconds
Started Sep 01 08:37:01 PM UTC 24
Finished Sep 01 08:38:29 PM UTC 24
Peak memory 266376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801380909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2801380909
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm.1500184684
Short name T332
Test name
Test status
Simulation time 132358043745 ps
CPU time 239.55 seconds
Started Sep 01 08:37:02 PM UTC 24
Finished Sep 01 08:41:05 PM UTC 24
Peak memory 262348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500184684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1500184684
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.4234750358
Short name T589
Test name
Test status
Simulation time 12670194314 ps
CPU time 170.82 seconds
Started Sep 01 08:37:03 PM UTC 24
Finished Sep 01 08:39:57 PM UTC 24
Peak memory 268320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234750358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.4234750358
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.3934610873
Short name T348
Test name
Test status
Simulation time 1435848447 ps
CPU time 23.29 seconds
Started Sep 01 08:37:01 PM UTC 24
Finished Sep 01 08:37:25 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3934610873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds.3934610873
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_intercept.4087398897
Short name T257
Test name
Test status
Simulation time 2622118346 ps
CPU time 9.15 seconds
Started Sep 01 08:36:58 PM UTC 24
Finished Sep 01 08:37:09 PM UTC 24
Peak memory 245736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087398897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.4087398897
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.864128660
Short name T563
Test name
Test status
Simulation time 70074377509 ps
CPU time 142.37 seconds
Started Sep 01 08:36:59 PM UTC 24
Finished Sep 01 08:39:24 PM UTC 24
Peak memory 245832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864128660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.864128660
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mem_parity.1160318673
Short name T482
Test name
Test status
Simulation time 32377410 ps
CPU time 1.62 seconds
Started Sep 01 08:36:54 PM UTC 24
Finished Sep 01 08:36:56 PM UTC 24
Peak memory 229264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160318673 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mem_parity.1160318673
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.3098349806
Short name T338
Test name
Test status
Simulation time 342734118 ps
CPU time 3.48 seconds
Started Sep 01 08:36:57 PM UTC 24
Finished Sep 01 08:37:02 PM UTC 24
Peak memory 234908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098349806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap.3098349806
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.1642511692
Short name T358
Test name
Test status
Simulation time 902683057 ps
CPU time 3.3 seconds
Started Sep 01 08:36:57 PM UTC 24
Finished Sep 01 08:37:01 PM UTC 24
Peak memory 245336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642511692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1642511692
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.3794465541
Short name T493
Test name
Test status
Simulation time 6530742856 ps
CPU time 11.06 seconds
Started Sep 01 08:37:01 PM UTC 24
Finished Sep 01 08:37:13 PM UTC 24
Peak memory 231724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794465541 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_direct.3794465541
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.2107763207
Short name T196
Test name
Test status
Simulation time 63939216 ps
CPU time 1.69 seconds
Started Sep 01 08:37:03 PM UTC 24
Finished Sep 01 08:37:06 PM UTC 24
Peak memory 215880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107763207 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stress_all.2107763207
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.3563197725
Short name T418
Test name
Test status
Simulation time 3337613731 ps
CPU time 24.57 seconds
Started Sep 01 08:36:55 PM UTC 24
Finished Sep 01 08:37:21 PM UTC 24
Peak memory 227952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563197725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.3563197725
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_read_hw_reg.3321046501
Short name T483
Test name
Test status
Simulation time 562523451 ps
CPU time 2.85 seconds
Started Sep 01 08:36:54 PM UTC 24
Finished Sep 01 08:36:58 PM UTC 24
Peak memory 217248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321046501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3321046501
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_rw.3283762691
Short name T416
Test name
Test status
Simulation time 155500001 ps
CPU time 2 seconds
Started Sep 01 08:36:56 PM UTC 24
Finished Sep 01 08:36:59 PM UTC 24
Peak memory 228076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3283762691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.3283762691
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_sts_read.574760723
Short name T484
Test name
Test status
Simulation time 55041951 ps
CPU time 1.07 seconds
Started Sep 01 08:36:56 PM UTC 24
Finished Sep 01 08:36:58 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574760723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.574760723
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.836914105
Short name T352
Test name
Test status
Simulation time 1496962904 ps
CPU time 8.14 seconds
Started Sep 01 08:36:59 PM UTC 24
Finished Sep 01 08:37:08 PM UTC 24
Peak memory 245792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836914105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.836914105
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/14.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.2406815144
Short name T498
Test name
Test status
Simulation time 13522006 ps
CPU time 1.1 seconds
Started Sep 01 08:37:22 PM UTC 24
Finished Sep 01 08:37:24 PM UTC 24
Peak memory 215024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406815144 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.2406815144
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.2661911398
Short name T324
Test name
Test status
Simulation time 7432965813 ps
CPU time 17.03 seconds
Started Sep 01 08:37:12 PM UTC 24
Finished Sep 01 08:37:30 PM UTC 24
Peak memory 235404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661911398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2661911398
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.4234389941
Short name T489
Test name
Test status
Simulation time 17765070 ps
CPU time 1.17 seconds
Started Sep 01 08:37:04 PM UTC 24
Finished Sep 01 08:37:06 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234389941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.4234389941
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_all.3916724967
Short name T530
Test name
Test status
Simulation time 17165157440 ps
CPU time 74.53 seconds
Started Sep 01 08:37:17 PM UTC 24
Finished Sep 01 08:38:34 PM UTC 24
Peak memory 262116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3916724967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3916724967
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.767826332
Short name T620
Test name
Test status
Simulation time 73826867412 ps
CPU time 195.82 seconds
Started Sep 01 08:37:17 PM UTC 24
Finished Sep 01 08:40:36 PM UTC 24
Peak memory 262156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767826332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.767826332
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.319291513
Short name T175
Test name
Test status
Simulation time 69500126807 ps
CPU time 176.92 seconds
Started Sep 01 08:37:18 PM UTC 24
Finished Sep 01 08:40:18 PM UTC 24
Peak memory 252096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319291513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle.319291513
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.72886289
Short name T403
Test name
Test status
Simulation time 2557405536 ps
CPU time 10.9 seconds
Started Sep 01 08:37:13 PM UTC 24
Finished Sep 01 08:37:25 PM UTC 24
Peak memory 245740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72886289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.72886289
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode_ignore_cmds.1112254737
Short name T226
Test name
Test status
Simulation time 15330629875 ps
CPU time 118.44 seconds
Started Sep 01 08:37:14 PM UTC 24
Finished Sep 01 08:39:15 PM UTC 24
Peak memory 262052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112254737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmds.1112254737
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.1200954285
Short name T318
Test name
Test status
Simulation time 338837872 ps
CPU time 8.25 seconds
Started Sep 01 08:37:10 PM UTC 24
Finished Sep 01 08:37:19 PM UTC 24
Peak memory 235332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200954285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1200954285
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.3280555073
Short name T495
Test name
Test status
Simulation time 267833386 ps
CPU time 5.27 seconds
Started Sep 01 08:37:11 PM UTC 24
Finished Sep 01 08:37:17 PM UTC 24
Peak memory 245576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280555073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3280555073
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.2929965106
Short name T490
Test name
Test status
Simulation time 137606531 ps
CPU time 1.51 seconds
Started Sep 01 08:37:05 PM UTC 24
Finished Sep 01 08:37:08 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929965106 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mem_parity.2929965106
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.890010269
Short name T350
Test name
Test status
Simulation time 13943127028 ps
CPU time 17.89 seconds
Started Sep 01 08:37:10 PM UTC 24
Finished Sep 01 08:37:29 PM UTC 24
Peak memory 235404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890010269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.890010269
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.3943482592
Short name T313
Test name
Test status
Simulation time 2604518492 ps
CPU time 12.17 seconds
Started Sep 01 08:37:09 PM UTC 24
Finished Sep 01 08:37:22 PM UTC 24
Peak memory 235604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943482592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3943482592
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.2401554420
Short name T497
Test name
Test status
Simulation time 193081743 ps
CPU time 6.52 seconds
Started Sep 01 08:37:15 PM UTC 24
Finished Sep 01 08:37:23 PM UTC 24
Peak memory 231604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401554420 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_direct.2401554420
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.680382156
Short name T89
Test name
Test status
Simulation time 88207765111 ps
CPU time 168.8 seconds
Started Sep 01 08:37:19 PM UTC 24
Finished Sep 01 08:40:11 PM UTC 24
Peak memory 268292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680382156 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stress_all.680382156
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.2746978990
Short name T417
Test name
Test status
Simulation time 7434882136 ps
CPU time 28.04 seconds
Started Sep 01 08:37:06 PM UTC 24
Finished Sep 01 08:37:36 PM UTC 24
Peak memory 227980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746978990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2746978990
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.3047456400
Short name T496
Test name
Test status
Simulation time 5695339574 ps
CPU time 12.84 seconds
Started Sep 01 08:37:06 PM UTC 24
Finished Sep 01 08:37:20 PM UTC 24
Peak memory 228120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047456400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3047456400
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.2163320615
Short name T492
Test name
Test status
Simulation time 200159365 ps
CPU time 2.66 seconds
Started Sep 01 08:37:08 PM UTC 24
Finished Sep 01 08:37:12 PM UTC 24
Peak memory 227952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163320615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2163320615
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.946710294
Short name T491
Test name
Test status
Simulation time 69962015 ps
CPU time 1.15 seconds
Started Sep 01 08:37:07 PM UTC 24
Finished Sep 01 08:37:10 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=946710294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.946710294
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.190921725
Short name T323
Test name
Test status
Simulation time 445880708 ps
CPU time 4.33 seconds
Started Sep 01 08:37:11 PM UTC 24
Finished Sep 01 08:37:16 PM UTC 24
Peak memory 245704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190921725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.190921725
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/15.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.2924395317
Short name T505
Test name
Test status
Simulation time 20088900 ps
CPU time 1.11 seconds
Started Sep 01 08:37:37 PM UTC 24
Finished Sep 01 08:37:40 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2924395317 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.2924395317
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.520678959
Short name T322
Test name
Test status
Simulation time 98182562 ps
CPU time 3.18 seconds
Started Sep 01 08:37:31 PM UTC 24
Finished Sep 01 08:37:36 PM UTC 24
Peak memory 235336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520678959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.520678959
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.868106993
Short name T499
Test name
Test status
Simulation time 40581379 ps
CPU time 1.23 seconds
Started Sep 01 08:37:22 PM UTC 24
Finished Sep 01 08:37:24 PM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868106993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.868106993
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.3320871082
Short name T632
Test name
Test status
Simulation time 23397259914 ps
CPU time 196.96 seconds
Started Sep 01 08:37:35 PM UTC 24
Finished Sep 01 08:40:55 PM UTC 24
Peak memory 262344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320871082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3320871082
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.1277444440
Short name T582
Test name
Test status
Simulation time 9254655515 ps
CPU time 131 seconds
Started Sep 01 08:37:35 PM UTC 24
Finished Sep 01 08:39:48 PM UTC 24
Peak memory 268232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277444440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.1277444440
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.2677041457
Short name T399
Test name
Test status
Simulation time 255384271 ps
CPU time 7.45 seconds
Started Sep 01 08:37:31 PM UTC 24
Finished Sep 01 08:37:41 PM UTC 24
Peak memory 251740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2677041457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.2677041457
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode_ignore_cmds.2638282929
Short name T550
Test name
Test status
Simulation time 7953057635 ps
CPU time 86.02 seconds
Started Sep 01 08:37:33 PM UTC 24
Finished Sep 01 08:39:01 PM UTC 24
Peak memory 249768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638282929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmds.2638282929
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.209709017
Short name T240
Test name
Test status
Simulation time 1753985575 ps
CPU time 10.68 seconds
Started Sep 01 08:37:28 PM UTC 24
Finished Sep 01 08:37:40 PM UTC 24
Peak memory 245836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=209709017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.209709017
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.1451772945
Short name T508
Test name
Test status
Simulation time 627951511 ps
CPU time 13.01 seconds
Started Sep 01 08:37:28 PM UTC 24
Finished Sep 01 08:37:43 PM UTC 24
Peak memory 251780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451772945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.1451772945
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.2949766079
Short name T500
Test name
Test status
Simulation time 34942277 ps
CPU time 1.65 seconds
Started Sep 01 08:37:23 PM UTC 24
Finished Sep 01 08:37:25 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949766079 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mem_parity.2949766079
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.1362485615
Short name T290
Test name
Test status
Simulation time 251464494 ps
CPU time 5.51 seconds
Started Sep 01 08:37:26 PM UTC 24
Finished Sep 01 08:37:33 PM UTC 24
Peak memory 235532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362485615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap.1362485615
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.3484487726
Short name T286
Test name
Test status
Simulation time 151801994 ps
CPU time 4.12 seconds
Started Sep 01 08:37:26 PM UTC 24
Finished Sep 01 08:37:31 PM UTC 24
Peak memory 235412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484487726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3484487726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.1111494594
Short name T506
Test name
Test status
Simulation time 195962767 ps
CPU time 4.94 seconds
Started Sep 01 08:37:34 PM UTC 24
Finished Sep 01 08:37:40 PM UTC 24
Peak memory 233832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111494594 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_direct.1111494594
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.2519294086
Short name T101
Test name
Test status
Simulation time 2032698503 ps
CPU time 31.1 seconds
Started Sep 01 08:37:36 PM UTC 24
Finished Sep 01 08:38:09 PM UTC 24
Peak memory 235400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519294086 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stress_all.2519294086
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.461913651
Short name T406
Test name
Test status
Simulation time 1042722504 ps
CPU time 20.94 seconds
Started Sep 01 08:37:25 PM UTC 24
Finished Sep 01 08:37:47 PM UTC 24
Peak memory 228044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=461913651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.461913651
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.837427409
Short name T503
Test name
Test status
Simulation time 1289214204 ps
CPU time 8.75 seconds
Started Sep 01 08:37:24 PM UTC 24
Finished Sep 01 08:37:34 PM UTC 24
Peak memory 227776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837427409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.837427409
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.1916883018
Short name T502
Test name
Test status
Simulation time 270240669 ps
CPU time 2.96 seconds
Started Sep 01 08:37:26 PM UTC 24
Finished Sep 01 08:37:30 PM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916883018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1916883018
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.1757520130
Short name T501
Test name
Test status
Simulation time 83737615 ps
CPU time 1.35 seconds
Started Sep 01 08:37:25 PM UTC 24
Finished Sep 01 08:37:27 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757520130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.1757520130
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.4115983800
Short name T504
Test name
Test status
Simulation time 226797965 ps
CPU time 3.63 seconds
Started Sep 01 08:37:29 PM UTC 24
Finished Sep 01 08:37:34 PM UTC 24
Peak memory 245664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115983800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.4115983800
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/16.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.155821153
Short name T94
Test name
Test status
Simulation time 46109986 ps
CPU time 1.08 seconds
Started Sep 01 08:38:00 PM UTC 24
Finished Sep 01 08:38:02 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=155821153 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.155821153
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.2443538774
Short name T308
Test name
Test status
Simulation time 1502268959 ps
CPU time 7.93 seconds
Started Sep 01 08:37:50 PM UTC 24
Finished Sep 01 08:37:59 PM UTC 24
Peak memory 245540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443538774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2443538774
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.3223472064
Short name T507
Test name
Test status
Simulation time 69575318 ps
CPU time 0.97 seconds
Started Sep 01 08:37:40 PM UTC 24
Finished Sep 01 08:37:42 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3223472064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3223472064
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_all.2229756098
Short name T755
Test name
Test status
Simulation time 26533946933 ps
CPU time 292.63 seconds
Started Sep 01 08:37:55 PM UTC 24
Finished Sep 01 08:42:52 PM UTC 24
Peak memory 262084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229756098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2229756098
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.4093187504
Short name T829
Test name
Test status
Simulation time 695676768680 ps
CPU time 364.21 seconds
Started Sep 01 08:37:55 PM UTC 24
Finished Sep 01 08:44:05 PM UTC 24
Peak memory 264232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093187504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.4093187504
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.4131286116
Short name T541
Test name
Test status
Simulation time 37329559913 ps
CPU time 50.9 seconds
Started Sep 01 08:37:57 PM UTC 24
Finished Sep 01 08:38:50 PM UTC 24
Peak memory 262368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131286116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle.4131286116
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.1739379741
Short name T515
Test name
Test status
Simulation time 496663671 ps
CPU time 5.9 seconds
Started Sep 01 08:37:51 PM UTC 24
Finished Sep 01 08:37:58 PM UTC 24
Peak memory 235524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739379741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1739379741
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.4023395713
Short name T514
Test name
Test status
Simulation time 27501482 ps
CPU time 1.15 seconds
Started Sep 01 08:37:52 PM UTC 24
Finished Sep 01 08:37:55 PM UTC 24
Peak memory 215788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023395713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds.4023395713
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.4176047881
Short name T283
Test name
Test status
Simulation time 48203219 ps
CPU time 3.36 seconds
Started Sep 01 08:37:47 PM UTC 24
Finished Sep 01 08:37:51 PM UTC 24
Peak memory 245572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176047881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.4176047881
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.1658354722
Short name T513
Test name
Test status
Simulation time 520143732 ps
CPU time 3.37 seconds
Started Sep 01 08:37:48 PM UTC 24
Finished Sep 01 08:37:52 PM UTC 24
Peak memory 235128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658354722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1658354722
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.165821239
Short name T509
Test name
Test status
Simulation time 77267897 ps
CPU time 1.43 seconds
Started Sep 01 08:37:40 PM UTC 24
Finished Sep 01 08:37:43 PM UTC 24
Peak memory 229200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165821239 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mem_parity.165821239
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.2311596983
Short name T334
Test name
Test status
Simulation time 1370191380 ps
CPU time 12.55 seconds
Started Sep 01 08:37:44 PM UTC 24
Finished Sep 01 08:37:57 PM UTC 24
Peak memory 235460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311596983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swap.2311596983
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.4291643320
Short name T303
Test name
Test status
Simulation time 1167071000 ps
CPU time 9.46 seconds
Started Sep 01 08:37:44 PM UTC 24
Finished Sep 01 08:37:54 PM UTC 24
Peak memory 235368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291643320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.4291643320
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.1894739921
Short name T96
Test name
Test status
Simulation time 1146023732 ps
CPU time 8.36 seconds
Started Sep 01 08:37:53 PM UTC 24
Finished Sep 01 08:38:03 PM UTC 24
Peak memory 233708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1894739921 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_direct.1894739921
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.3435574214
Short name T90
Test name
Test status
Simulation time 28462554627 ps
CPU time 211.77 seconds
Started Sep 01 08:37:59 PM UTC 24
Finished Sep 01 08:41:34 PM UTC 24
Peak memory 266440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3435574214 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stress_all.3435574214
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.220393115
Short name T407
Test name
Test status
Simulation time 2136194244 ps
CPU time 17.68 seconds
Started Sep 01 08:37:41 PM UTC 24
Finished Sep 01 08:38:00 PM UTC 24
Peak memory 227824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220393115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.220393115
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.3583271446
Short name T512
Test name
Test status
Simulation time 962234221 ps
CPU time 6.29 seconds
Started Sep 01 08:37:41 PM UTC 24
Finished Sep 01 08:37:49 PM UTC 24
Peak memory 217212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583271446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.3583271446
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.1572499551
Short name T511
Test name
Test status
Simulation time 62631258 ps
CPU time 1.99 seconds
Started Sep 01 08:37:43 PM UTC 24
Finished Sep 01 08:37:46 PM UTC 24
Peak memory 228040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1572499551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.1572499551
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.216219966
Short name T510
Test name
Test status
Simulation time 270839098 ps
CPU time 1.35 seconds
Started Sep 01 08:37:43 PM UTC 24
Finished Sep 01 08:37:46 PM UTC 24
Peak memory 215916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=216219966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.216219966
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.530581437
Short name T294
Test name
Test status
Simulation time 5720799921 ps
CPU time 41.35 seconds
Started Sep 01 08:37:48 PM UTC 24
Finished Sep 01 08:38:31 PM UTC 24
Peak memory 245704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530581437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.530581437
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/17.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.770131079
Short name T520
Test name
Test status
Simulation time 14485878 ps
CPU time 1.08 seconds
Started Sep 01 08:38:18 PM UTC 24
Finished Sep 01 08:38:20 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770131079 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.770131079
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.811936352
Short name T525
Test name
Test status
Simulation time 2890938949 ps
CPU time 21.66 seconds
Started Sep 01 08:38:06 PM UTC 24
Finished Sep 01 08:38:29 PM UTC 24
Peak memory 235720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811936352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.811936352
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.631592417
Short name T95
Test name
Test status
Simulation time 19119716 ps
CPU time 1.18 seconds
Started Sep 01 08:38:00 PM UTC 24
Finished Sep 01 08:38:02 PM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631592417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.631592417
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_all.1085953977
Short name T533
Test name
Test status
Simulation time 2881148804 ps
CPU time 21.14 seconds
Started Sep 01 08:38:12 PM UTC 24
Finished Sep 01 08:38:34 PM UTC 24
Peak memory 245704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085953977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.1085953977
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.343505979
Short name T262
Test name
Test status
Simulation time 588194160374 ps
CPU time 510.92 seconds
Started Sep 01 08:38:12 PM UTC 24
Finished Sep 01 08:46:49 PM UTC 24
Peak memory 262156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343505979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.343505979
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm_min_idle.2612487860
Short name T343
Test name
Test status
Simulation time 167737420361 ps
CPU time 209.86 seconds
Started Sep 01 08:38:18 PM UTC 24
Finished Sep 01 08:41:51 PM UTC 24
Peak memory 280576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612487860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle.2612487860
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.990240170
Short name T519
Test name
Test status
Simulation time 283157724 ps
CPU time 10.13 seconds
Started Sep 01 08:38:08 PM UTC 24
Finished Sep 01 08:38:19 PM UTC 24
Peak memory 245580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990240170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.990240170
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.3280536033
Short name T278
Test name
Test status
Simulation time 4745934442 ps
CPU time 38.27 seconds
Started Sep 01 08:38:10 PM UTC 24
Finished Sep 01 08:38:49 PM UTC 24
Peak memory 247768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280536033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds.3280536033
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.3909028949
Short name T293
Test name
Test status
Simulation time 1819754415 ps
CPU time 11.43 seconds
Started Sep 01 08:38:04 PM UTC 24
Finished Sep 01 08:38:17 PM UTC 24
Peak memory 244444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909028949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3909028949
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.3754458420
Short name T269
Test name
Test status
Simulation time 1530047118 ps
CPU time 14.95 seconds
Started Sep 01 08:38:05 PM UTC 24
Finished Sep 01 08:38:21 PM UTC 24
Peak memory 242192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754458420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3754458420
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.200243488
Short name T97
Test name
Test status
Simulation time 16076584 ps
CPU time 1.42 seconds
Started Sep 01 08:38:01 PM UTC 24
Finished Sep 01 08:38:03 PM UTC 24
Peak memory 229260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200243488 -assert
nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mem_parity.200243488
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.2098264152
Short name T340
Test name
Test status
Simulation time 6973882109 ps
CPU time 38.38 seconds
Started Sep 01 08:38:04 PM UTC 24
Finished Sep 01 08:38:44 PM UTC 24
Peak memory 245868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098264152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swap.2098264152
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.883315825
Short name T315
Test name
Test status
Simulation time 1924421957 ps
CPU time 13.15 seconds
Started Sep 01 08:38:03 PM UTC 24
Finished Sep 01 08:38:17 PM UTC 24
Peak memory 245584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883315825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.883315825
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.2927883603
Short name T518
Test name
Test status
Simulation time 836047891 ps
CPU time 6.49 seconds
Started Sep 01 08:38:10 PM UTC 24
Finished Sep 01 08:38:17 PM UTC 24
Peak memory 233880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927883603 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_direct.2927883603
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.1895796415
Short name T544
Test name
Test status
Simulation time 1257817176 ps
CPU time 35.41 seconds
Started Sep 01 08:38:18 PM UTC 24
Finished Sep 01 08:38:55 PM UTC 24
Peak memory 264164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895796415 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stress_all.1895796415
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.255430542
Short name T526
Test name
Test status
Simulation time 11065212674 ps
CPU time 26.64 seconds
Started Sep 01 08:38:02 PM UTC 24
Finished Sep 01 08:38:30 PM UTC 24
Peak memory 228084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255430542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.255430542
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.2799791571
Short name T99
Test name
Test status
Simulation time 2716759143 ps
CPU time 3.69 seconds
Started Sep 01 08:38:01 PM UTC 24
Finished Sep 01 08:38:05 PM UTC 24
Peak memory 217336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799791571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2799791571
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.1093568755
Short name T517
Test name
Test status
Simulation time 252994807 ps
CPU time 6.57 seconds
Started Sep 01 08:38:03 PM UTC 24
Finished Sep 01 08:38:11 PM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093568755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.1093568755
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.3215551136
Short name T98
Test name
Test status
Simulation time 18967960 ps
CPU time 1.08 seconds
Started Sep 01 08:38:02 PM UTC 24
Finished Sep 01 08:38:04 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215551136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.3215551136
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.2151265141
Short name T516
Test name
Test status
Simulation time 47491345 ps
CPU time 2.92 seconds
Started Sep 01 08:38:05 PM UTC 24
Finished Sep 01 08:38:09 PM UTC 24
Peak memory 234892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2151265141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2151265141
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/18.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.1738641173
Short name T534
Test name
Test status
Simulation time 79822640 ps
CPU time 1.12 seconds
Started Sep 01 08:38:35 PM UTC 24
Finished Sep 01 08:38:37 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738641173 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.1738641173
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.1306989610
Short name T531
Test name
Test status
Simulation time 67369411 ps
CPU time 2.77 seconds
Started Sep 01 08:38:30 PM UTC 24
Finished Sep 01 08:38:34 PM UTC 24
Peak memory 245220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306989610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1306989610
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.3131976413
Short name T521
Test name
Test status
Simulation time 86778325 ps
CPU time 1.18 seconds
Started Sep 01 08:38:19 PM UTC 24
Finished Sep 01 08:38:21 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131976413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3131976413
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.1749335132
Short name T270
Test name
Test status
Simulation time 9998560932 ps
CPU time 87.21 seconds
Started Sep 01 08:38:33 PM UTC 24
Finished Sep 01 08:40:03 PM UTC 24
Peak memory 266376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749335132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1749335132
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm.143896330
Short name T924
Test name
Test status
Simulation time 40433748507 ps
CPU time 440.45 seconds
Started Sep 01 08:38:33 PM UTC 24
Finished Sep 01 08:46:00 PM UTC 24
Peak memory 268392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143896330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.143896330
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_and_tpm_min_idle.663243824
Short name T565
Test name
Test status
Simulation time 7116012478 ps
CPU time 49.48 seconds
Started Sep 01 08:38:35 PM UTC 24
Finished Sep 01 08:39:26 PM UTC 24
Peak memory 262172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663243824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idle.663243824
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.1893558855
Short name T401
Test name
Test status
Simulation time 373986647 ps
CPU time 12.29 seconds
Started Sep 01 08:38:31 PM UTC 24
Finished Sep 01 08:38:45 PM UTC 24
Peak memory 235524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1893558855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1893558855
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode_ignore_cmds.3089656434
Short name T529
Test name
Test status
Simulation time 34390835 ps
CPU time 1.31 seconds
Started Sep 01 08:38:31 PM UTC 24
Finished Sep 01 08:38:33 PM UTC 24
Peak memory 225732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089656434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmds.3089656434
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.1787637558
Short name T527
Test name
Test status
Simulation time 100956344 ps
CPU time 2.27 seconds
Started Sep 01 08:38:29 PM UTC 24
Finished Sep 01 08:38:32 PM UTC 24
Peak memory 234160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787637558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.1787637558
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.2315048415
Short name T265
Test name
Test status
Simulation time 15013795898 ps
CPU time 46.02 seconds
Started Sep 01 08:38:30 PM UTC 24
Finished Sep 01 08:39:18 PM UTC 24
Peak memory 235456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315048415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.2315048415
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.1898087493
Short name T522
Test name
Test status
Simulation time 450474330 ps
CPU time 1.54 seconds
Started Sep 01 08:38:19 PM UTC 24
Finished Sep 01 08:38:22 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898087493 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mem_parity.1898087493
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.306813205
Short name T346
Test name
Test status
Simulation time 12347737500 ps
CPU time 17.75 seconds
Started Sep 01 08:38:27 PM UTC 24
Finished Sep 01 08:38:46 PM UTC 24
Peak memory 235440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306813205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap.306813205
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1199419216
Short name T253
Test name
Test status
Simulation time 9102383926 ps
CPU time 46.6 seconds
Started Sep 01 08:38:26 PM UTC 24
Finished Sep 01 08:39:14 PM UTC 24
Peak memory 245652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199419216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1199419216
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.414205303
Short name T536
Test name
Test status
Simulation time 731523833 ps
CPU time 4.74 seconds
Started Sep 01 08:38:31 PM UTC 24
Finished Sep 01 08:38:37 PM UTC 24
Peak memory 233968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414205303 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_direct.414205303
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_stress_all.3196462553
Short name T183
Test name
Test status
Simulation time 7415327352 ps
CPU time 78.21 seconds
Started Sep 01 08:38:35 PM UTC 24
Finished Sep 01 08:39:55 PM UTC 24
Peak memory 262156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196462553 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stress_all.3196462553
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.1138735086
Short name T542
Test name
Test status
Simulation time 4993433336 ps
CPU time 29.73 seconds
Started Sep 01 08:38:22 PM UTC 24
Finished Sep 01 08:38:53 PM UTC 24
Peak memory 227952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138735086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1138735086
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.1759102538
Short name T528
Test name
Test status
Simulation time 43498218418 ps
CPU time 10.69 seconds
Started Sep 01 08:38:21 PM UTC 24
Finished Sep 01 08:38:33 PM UTC 24
Peak memory 227872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759102538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1759102538
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.2866800839
Short name T524
Test name
Test status
Simulation time 92447081 ps
CPU time 2.41 seconds
Started Sep 01 08:38:23 PM UTC 24
Finished Sep 01 08:38:26 PM UTC 24
Peak memory 227844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866800839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2866800839
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.3113274682
Short name T523
Test name
Test status
Simulation time 517592760 ps
CPU time 1.44 seconds
Started Sep 01 08:38:22 PM UTC 24
Finished Sep 01 08:38:25 PM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113274682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.3113274682
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.3794014658
Short name T532
Test name
Test status
Simulation time 247261511 ps
CPU time 2.9 seconds
Started Sep 01 08:38:30 PM UTC 24
Finished Sep 01 08:38:34 PM UTC 24
Peak memory 235460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794014658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3794014658
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/19.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_alert_test.119870295
Short name T112
Test name
Test status
Simulation time 36684050 ps
CPU time 1.08 seconds
Started Sep 01 08:34:10 PM UTC 24
Finished Sep 01 08:34:12 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119870295 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.119870295
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_cfg_cmd.2628493896
Short name T61
Test name
Test status
Simulation time 2250841059 ps
CPU time 4.27 seconds
Started Sep 01 08:34:05 PM UTC 24
Finished Sep 01 08:34:10 PM UTC 24
Peak memory 235528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628493896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2628493896
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_csb_read.3129754213
Short name T14
Test name
Test status
Simulation time 65207729 ps
CPU time 0.88 seconds
Started Sep 01 08:34:00 PM UTC 24
Finished Sep 01 08:34:03 PM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129754213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.3129754213
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_all.2779955452
Short name T104
Test name
Test status
Simulation time 26485257240 ps
CPU time 70.98 seconds
Started Sep 01 08:34:06 PM UTC 24
Finished Sep 01 08:35:19 PM UTC 24
Peak memory 249744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2779955452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2779955452
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm.2800140122
Short name T70
Test name
Test status
Simulation time 60419188993 ps
CPU time 154.53 seconds
Started Sep 01 08:34:06 PM UTC 24
Finished Sep 01 08:36:44 PM UTC 24
Peak memory 268272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800140122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2800140122
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode.763385279
Short name T54
Test name
Test status
Simulation time 618490815 ps
CPU time 8.18 seconds
Started Sep 01 08:34:05 PM UTC 24
Finished Sep 01 08:34:15 PM UTC 24
Peak memory 251728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763385279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.763385279
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_mode_ignore_cmds.1330852873
Short name T53
Test name
Test status
Simulation time 5242728683 ps
CPU time 50.47 seconds
Started Sep 01 08:34:05 PM UTC 24
Finished Sep 01 08:34:57 PM UTC 24
Peak memory 251852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330852873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.1330852873
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_intercept.2544723709
Short name T111
Test name
Test status
Simulation time 1878676441 ps
CPU time 9.56 seconds
Started Sep 01 08:34:04 PM UTC 24
Finished Sep 01 08:34:15 PM UTC 24
Peak memory 245604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544723709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.2544723709
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mailbox.1992072270
Short name T423
Test name
Test status
Simulation time 5404133350 ps
CPU time 8.82 seconds
Started Sep 01 08:34:04 PM UTC 24
Finished Sep 01 08:34:14 PM UTC 24
Peak memory 234748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992072270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1992072270
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_mem_parity.1492031573
Short name T39
Test name
Test status
Simulation time 38750198 ps
CPU time 1.45 seconds
Started Sep 01 08:34:01 PM UTC 24
Finished Sep 01 08:34:04 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1492031573 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mem_parity.1492031573
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_addr_payload_swap.2255795961
Short name T66
Test name
Test status
Simulation time 36602827480 ps
CPU time 30.67 seconds
Started Sep 01 08:34:04 PM UTC 24
Finished Sep 01 08:34:36 PM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255795961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.2255795961
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_pass_cmd_filtering.3331246565
Short name T58
Test name
Test status
Simulation time 1890611613 ps
CPU time 9.22 seconds
Started Sep 01 08:34:03 PM UTC 24
Finished Sep 01 08:34:13 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331246565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.3331246565
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_read_buffer_direct.1277451563
Short name T47
Test name
Test status
Simulation time 2348869860 ps
CPU time 7.32 seconds
Started Sep 01 08:34:05 PM UTC 24
Finished Sep 01 08:34:14 PM UTC 24
Peak memory 231988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277451563 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direct.1277451563
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_sec_cm.1943147198
Short name T31
Test name
Test status
Simulation time 79758441 ps
CPU time 1.54 seconds
Started Sep 01 08:34:09 PM UTC 24
Finished Sep 01 08:34:11 PM UTC 24
Peak memory 257736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1943147198 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1943147198
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_sec_cm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_read_hw_reg.285806826
Short name T125
Test name
Test status
Simulation time 16790502048 ps
CPU time 17.41 seconds
Started Sep 01 08:34:02 PM UTC 24
Finished Sep 01 08:34:20 PM UTC 24
Peak memory 228084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285806826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.285806826
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_rw.2349978737
Short name T26
Test name
Test status
Simulation time 93952559 ps
CPU time 1.04 seconds
Started Sep 01 08:34:03 PM UTC 24
Finished Sep 01 08:34:05 PM UTC 24
Peak memory 215984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349978737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2349978737
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_tpm_sts_read.4073436127
Short name T17
Test name
Test status
Simulation time 94606378 ps
CPU time 1.02 seconds
Started Sep 01 08:34:02 PM UTC 24
Finished Sep 01 08:34:04 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073436127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.4073436127
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/2.spi_device_upload.3980538020
Short name T56
Test name
Test status
Simulation time 862524037 ps
CPU time 8.29 seconds
Started Sep 01 08:34:04 PM UTC 24
Finished Sep 01 08:34:14 PM UTC 24
Peak memory 245600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980538020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3980538020
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/2.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.1778936952
Short name T545
Test name
Test status
Simulation time 14053602 ps
CPU time 1.11 seconds
Started Sep 01 08:38:54 PM UTC 24
Finished Sep 01 08:38:56 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778936952 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.1778936952
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.3275591709
Short name T302
Test name
Test status
Simulation time 1007756975 ps
CPU time 6.6 seconds
Started Sep 01 08:38:46 PM UTC 24
Finished Sep 01 08:38:54 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275591709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3275591709
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.2049802901
Short name T535
Test name
Test status
Simulation time 52390419 ps
CPU time 1.14 seconds
Started Sep 01 08:38:35 PM UTC 24
Finished Sep 01 08:38:37 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049802901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2049802901
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.3749777622
Short name T608
Test name
Test status
Simulation time 31351014242 ps
CPU time 87.93 seconds
Started Sep 01 08:38:50 PM UTC 24
Finished Sep 01 08:40:20 PM UTC 24
Peak memory 262280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749777622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3749777622
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.1549348764
Short name T579
Test name
Test status
Simulation time 6165016341 ps
CPU time 54.56 seconds
Started Sep 01 08:38:51 PM UTC 24
Finished Sep 01 08:39:47 PM UTC 24
Peak memory 262156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549348764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1549348764
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.3942456443
Short name T266
Test name
Test status
Simulation time 7327784457 ps
CPU time 128.83 seconds
Started Sep 01 08:38:51 PM UTC 24
Finished Sep 01 08:41:02 PM UTC 24
Peak memory 268324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942456443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.3942456443
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.1798290755
Short name T404
Test name
Test status
Simulation time 1058859002 ps
CPU time 22.69 seconds
Started Sep 01 08:38:47 PM UTC 24
Finished Sep 01 08:39:10 PM UTC 24
Peak memory 245600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798290755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1798290755
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode_ignore_cmds.308277648
Short name T284
Test name
Test status
Simulation time 839452591 ps
CPU time 15.58 seconds
Started Sep 01 08:38:49 PM UTC 24
Finished Sep 01 08:39:05 PM UTC 24
Peak memory 247560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308277648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds.308277648
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.3260571445
Short name T539
Test name
Test status
Simulation time 646008099 ps
CPU time 3.72 seconds
Started Sep 01 08:38:44 PM UTC 24
Finished Sep 01 08:38:49 PM UTC 24
Peak memory 235268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260571445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3260571445
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.15472239
Short name T353
Test name
Test status
Simulation time 3057441278 ps
CPU time 33.18 seconds
Started Sep 01 08:38:45 PM UTC 24
Finished Sep 01 08:39:20 PM UTC 24
Peak memory 262308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15472239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.15472239
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.2650022965
Short name T351
Test name
Test status
Simulation time 2392442498 ps
CPU time 20.29 seconds
Started Sep 01 08:38:41 PM UTC 24
Finished Sep 01 08:39:03 PM UTC 24
Peak memory 252040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2650022965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap.2650022965
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.3737243783
Short name T301
Test name
Test status
Simulation time 2757368012 ps
CPU time 14.44 seconds
Started Sep 01 08:38:38 PM UTC 24
Finished Sep 01 08:38:54 PM UTC 24
Peak memory 245712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737243783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.3737243783
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.3812641124
Short name T546
Test name
Test status
Simulation time 874798518 ps
CPU time 6.55 seconds
Started Sep 01 08:38:50 PM UTC 24
Finished Sep 01 08:38:57 PM UTC 24
Peak memory 233936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812641124 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_direct.3812641124
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.3827483604
Short name T182
Test name
Test status
Simulation time 3001365969 ps
CPU time 47.04 seconds
Started Sep 01 08:38:54 PM UTC 24
Finished Sep 01 08:39:43 PM UTC 24
Peak memory 262188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827483604 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stress_all.3827483604
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.92779619
Short name T543
Test name
Test status
Simulation time 17438282180 ps
CPU time 16.89 seconds
Started Sep 01 08:38:36 PM UTC 24
Finished Sep 01 08:38:54 PM UTC 24
Peak memory 232000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92779619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.92779619
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1342682886
Short name T540
Test name
Test status
Simulation time 4943673615 ps
CPU time 14.14 seconds
Started Sep 01 08:38:35 PM UTC 24
Finished Sep 01 08:38:50 PM UTC 24
Peak memory 227888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342682886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1342682886
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.3544418186
Short name T538
Test name
Test status
Simulation time 368502119 ps
CPU time 6.55 seconds
Started Sep 01 08:38:38 PM UTC 24
Finished Sep 01 08:38:46 PM UTC 24
Peak memory 227980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544418186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.3544418186
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.3881327848
Short name T537
Test name
Test status
Simulation time 450925117 ps
CPU time 1.33 seconds
Started Sep 01 08:38:38 PM UTC 24
Finished Sep 01 08:38:40 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881327848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.3881327848
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.97803620
Short name T331
Test name
Test status
Simulation time 1054700061 ps
CPU time 12.93 seconds
Started Sep 01 08:38:45 PM UTC 24
Finished Sep 01 08:38:59 PM UTC 24
Peak memory 235332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97803620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_devi
ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.97803620
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/20.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.1206053541
Short name T556
Test name
Test status
Simulation time 13117322 ps
CPU time 1 seconds
Started Sep 01 08:39:08 PM UTC 24
Finished Sep 01 08:39:11 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206053541 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.1206053541
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.3678376161
Short name T327
Test name
Test status
Simulation time 212653622 ps
CPU time 4 seconds
Started Sep 01 08:39:03 PM UTC 24
Finished Sep 01 08:39:08 PM UTC 24
Peak memory 245368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678376161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.3678376161
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.2355646091
Short name T547
Test name
Test status
Simulation time 50829864 ps
CPU time 1.13 seconds
Started Sep 01 08:38:55 PM UTC 24
Finished Sep 01 08:38:57 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355646091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2355646091
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_all.1825703139
Short name T600
Test name
Test status
Simulation time 7491436549 ps
CPU time 64.77 seconds
Started Sep 01 08:39:05 PM UTC 24
Finished Sep 01 08:40:12 PM UTC 24
Peak memory 235432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825703139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1825703139
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.1527828444
Short name T583
Test name
Test status
Simulation time 2289592390 ps
CPU time 40.99 seconds
Started Sep 01 08:39:06 PM UTC 24
Finished Sep 01 08:39:49 PM UTC 24
Peak memory 264196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527828444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle.1527828444
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.1996088846
Short name T560
Test name
Test status
Simulation time 3073894993 ps
CPU time 14.14 seconds
Started Sep 01 08:39:03 PM UTC 24
Finished Sep 01 08:39:19 PM UTC 24
Peak memory 252068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996088846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1996088846
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.3475802215
Short name T1007
Test name
Test status
Simulation time 381314653705 ps
CPU time 607.42 seconds
Started Sep 01 08:39:04 PM UTC 24
Finished Sep 01 08:49:20 PM UTC 24
Peak memory 276424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475802215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds.3475802215
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.1243635883
Short name T554
Test name
Test status
Simulation time 45336979 ps
CPU time 3.65 seconds
Started Sep 01 08:39:01 PM UTC 24
Finished Sep 01 08:39:05 PM UTC 24
Peak memory 245800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243635883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1243635883
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.2326634011
Short name T287
Test name
Test status
Simulation time 1047255325 ps
CPU time 18.72 seconds
Started Sep 01 08:39:02 PM UTC 24
Finished Sep 01 08:39:22 PM UTC 24
Peak memory 245572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326634011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2326634011
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.669373906
Short name T349
Test name
Test status
Simulation time 64368243 ps
CPU time 2.75 seconds
Started Sep 01 08:39:01 PM UTC 24
Finished Sep 01 08:39:04 PM UTC 24
Peak memory 245220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669373906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swap.669373906
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.3387743454
Short name T555
Test name
Test status
Simulation time 2262302046 ps
CPU time 6.07 seconds
Started Sep 01 08:38:59 PM UTC 24
Finished Sep 01 08:39:06 PM UTC 24
Peak memory 245652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387743454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.3387743454
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.2033473212
Short name T564
Test name
Test status
Simulation time 1680533619 ps
CPU time 18.39 seconds
Started Sep 01 08:39:04 PM UTC 24
Finished Sep 01 08:39:25 PM UTC 24
Peak memory 231664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033473212 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_direct.2033473212
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.3625588072
Short name T559
Test name
Test status
Simulation time 707280623 ps
CPU time 9.73 seconds
Started Sep 01 08:39:06 PM UTC 24
Finished Sep 01 08:39:18 PM UTC 24
Peak memory 235396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3625588072 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stress_all.3625588072
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.2931578061
Short name T575
Test name
Test status
Simulation time 8045810298 ps
CPU time 41.92 seconds
Started Sep 01 08:38:56 PM UTC 24
Finished Sep 01 08:39:40 PM UTC 24
Peak memory 227952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931578061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2931578061
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.1099836943
Short name T562
Test name
Test status
Simulation time 16047470971 ps
CPU time 24.26 seconds
Started Sep 01 08:38:55 PM UTC 24
Finished Sep 01 08:39:21 PM UTC 24
Peak memory 228088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099836943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.1099836943
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.2496620806
Short name T552
Test name
Test status
Simulation time 897814277 ps
CPU time 2.47 seconds
Started Sep 01 08:38:58 PM UTC 24
Finished Sep 01 08:39:02 PM UTC 24
Peak memory 227760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496620806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2496620806
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.2023520660
Short name T548
Test name
Test status
Simulation time 98389900 ps
CPU time 1.36 seconds
Started Sep 01 08:38:57 PM UTC 24
Finished Sep 01 08:39:00 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023520660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.2023520660
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.3890691940
Short name T319
Test name
Test status
Simulation time 228010050 ps
CPU time 6.18 seconds
Started Sep 01 08:39:02 PM UTC 24
Finished Sep 01 08:39:09 PM UTC 24
Peak memory 235460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890691940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3890691940
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/21.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.3696949036
Short name T566
Test name
Test status
Simulation time 11117517 ps
CPU time 1.1 seconds
Started Sep 01 08:39:26 PM UTC 24
Finished Sep 01 08:39:28 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696949036 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.3696949036
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.3556087023
Short name T230
Test name
Test status
Simulation time 464949820 ps
CPU time 3.4 seconds
Started Sep 01 08:39:20 PM UTC 24
Finished Sep 01 08:39:25 PM UTC 24
Peak memory 235272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556087023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3556087023
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.1327899904
Short name T557
Test name
Test status
Simulation time 19937283 ps
CPU time 1.22 seconds
Started Sep 01 08:39:10 PM UTC 24
Finished Sep 01 08:39:12 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327899904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1327899904
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_all.2454786184
Short name T710
Test name
Test status
Simulation time 23581676682 ps
CPU time 170.76 seconds
Started Sep 01 08:39:23 PM UTC 24
Finished Sep 01 08:42:17 PM UTC 24
Peak memory 268232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454786184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.2454786184
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm.4079689568
Short name T410
Test name
Test status
Simulation time 5205869192 ps
CPU time 40.3 seconds
Started Sep 01 08:39:25 PM UTC 24
Finished Sep 01 08:40:07 PM UTC 24
Peak memory 235496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079689568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.4079689568
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_and_tpm_min_idle.2226120418
Short name T639
Test name
Test status
Simulation time 20939265351 ps
CPU time 95.56 seconds
Started Sep 01 08:39:26 PM UTC 24
Finished Sep 01 08:41:04 PM UTC 24
Peak memory 262372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226120418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idle.2226120418
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.2958814125
Short name T571
Test name
Test status
Simulation time 636880050 ps
CPU time 11.17 seconds
Started Sep 01 08:39:21 PM UTC 24
Finished Sep 01 08:39:34 PM UTC 24
Peak memory 235552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2958814125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.2958814125
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.3170729296
Short name T730
Test name
Test status
Simulation time 38123345525 ps
CPU time 190.35 seconds
Started Sep 01 08:39:21 PM UTC 24
Finished Sep 01 08:42:35 PM UTC 24
Peak memory 268256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170729296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds.3170729296
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.3747339423
Short name T325
Test name
Test status
Simulation time 681359341 ps
CPU time 5.6 seconds
Started Sep 01 08:39:18 PM UTC 24
Finished Sep 01 08:39:25 PM UTC 24
Peak memory 245552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747339423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.3747339423
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.2072150492
Short name T567
Test name
Test status
Simulation time 628343218 ps
CPU time 8.75 seconds
Started Sep 01 08:39:18 PM UTC 24
Finished Sep 01 08:39:28 PM UTC 24
Peak memory 245600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2072150492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2072150492
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.737647659
Short name T347
Test name
Test status
Simulation time 5620164605 ps
CPU time 35.98 seconds
Started Sep 01 08:39:16 PM UTC 24
Finished Sep 01 08:39:54 PM UTC 24
Peak memory 262084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737647659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swap.737647659
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.2396038354
Short name T330
Test name
Test status
Simulation time 1372533802 ps
CPU time 2.77 seconds
Started Sep 01 08:39:16 PM UTC 24
Finished Sep 01 08:39:20 PM UTC 24
Peak memory 245584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396038354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2396038354
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.1767038982
Short name T573
Test name
Test status
Simulation time 6296563419 ps
CPU time 12.16 seconds
Started Sep 01 08:39:21 PM UTC 24
Finished Sep 01 08:39:35 PM UTC 24
Peak memory 234096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767038982 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_direct.1767038982
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.321391780
Short name T185
Test name
Test status
Simulation time 238602820019 ps
CPU time 159.68 seconds
Started Sep 01 08:39:26 PM UTC 24
Finished Sep 01 08:42:09 PM UTC 24
Peak memory 266368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321391780 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stress_all.321391780
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.3682229627
Short name T576
Test name
Test status
Simulation time 2582001621 ps
CPU time 31.01 seconds
Started Sep 01 08:39:12 PM UTC 24
Finished Sep 01 08:39:44 PM UTC 24
Peak memory 228208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682229627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3682229627
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.3543357648
Short name T569
Test name
Test status
Simulation time 5181988690 ps
CPU time 18.76 seconds
Started Sep 01 08:39:12 PM UTC 24
Finished Sep 01 08:39:32 PM UTC 24
Peak memory 227916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543357648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3543357648
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.1460793146
Short name T561
Test name
Test status
Simulation time 279362459 ps
CPU time 3.2 seconds
Started Sep 01 08:39:15 PM UTC 24
Finished Sep 01 08:39:19 PM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460793146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1460793146
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.3688461945
Short name T558
Test name
Test status
Simulation time 308667862 ps
CPU time 1.4 seconds
Started Sep 01 08:39:13 PM UTC 24
Finished Sep 01 08:39:15 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688461945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3688461945
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.4126760911
Short name T314
Test name
Test status
Simulation time 886126816 ps
CPU time 9.36 seconds
Started Sep 01 08:39:19 PM UTC 24
Finished Sep 01 08:39:30 PM UTC 24
Peak memory 235424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126760911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.4126760911
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/22.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.1397589353
Short name T580
Test name
Test status
Simulation time 14343471 ps
CPU time 1.15 seconds
Started Sep 01 08:39:45 PM UTC 24
Finished Sep 01 08:39:48 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397589353 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.1397589353
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.3646255611
Short name T577
Test name
Test status
Simulation time 3380950481 ps
CPU time 7.07 seconds
Started Sep 01 08:39:36 PM UTC 24
Finished Sep 01 08:39:44 PM UTC 24
Peak memory 245668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646255611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3646255611
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.3389591350
Short name T568
Test name
Test status
Simulation time 46033449 ps
CPU time 1.2 seconds
Started Sep 01 08:39:27 PM UTC 24
Finished Sep 01 08:39:29 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389591350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3389591350
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_and_tpm_min_idle.1383807128
Short name T594
Test name
Test status
Simulation time 3693651174 ps
CPU time 21.57 seconds
Started Sep 01 08:39:43 PM UTC 24
Finished Sep 01 08:40:06 PM UTC 24
Peak memory 235528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383807128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle.1383807128
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.62298934
Short name T400
Test name
Test status
Simulation time 2174737711 ps
CPU time 31.02 seconds
Started Sep 01 08:39:36 PM UTC 24
Finished Sep 01 08:40:08 PM UTC 24
Peak memory 245968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62298934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.62298934
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.2464239
Short name T367
Test name
Test status
Simulation time 70055851196 ps
CPU time 331.24 seconds
Started Sep 01 08:39:38 PM UTC 24
Finished Sep 01 08:45:14 PM UTC 24
Peak memory 268292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM
_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds.2464239
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.1559414805
Short name T292
Test name
Test status
Simulation time 1009417732 ps
CPU time 7.73 seconds
Started Sep 01 08:39:35 PM UTC 24
Finished Sep 01 08:39:43 PM UTC 24
Peak memory 235472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559414805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1559414805
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.1960623969
Short name T297
Test name
Test status
Simulation time 437260211 ps
CPU time 4.12 seconds
Started Sep 01 08:39:35 PM UTC 24
Finished Sep 01 08:39:40 PM UTC 24
Peak memory 245572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960623969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.1960623969
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.2067066589
Short name T271
Test name
Test status
Simulation time 5340456899 ps
CPU time 6.8 seconds
Started Sep 01 08:39:33 PM UTC 24
Finished Sep 01 08:39:42 PM UTC 24
Peak memory 235408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067066589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swap.2067066589
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.4109628801
Short name T574
Test name
Test status
Simulation time 51301235 ps
CPU time 3.16 seconds
Started Sep 01 08:39:32 PM UTC 24
Finished Sep 01 08:39:37 PM UTC 24
Peak memory 235536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109628801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.4109628801
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.2098861498
Short name T590
Test name
Test status
Simulation time 17445610138 ps
CPU time 17.72 seconds
Started Sep 01 08:39:41 PM UTC 24
Finished Sep 01 08:40:00 PM UTC 24
Peak memory 233840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098861498 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_direct.2098861498
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_stress_all.1865608624
Short name T805
Test name
Test status
Simulation time 14103540575 ps
CPU time 237 seconds
Started Sep 01 08:39:44 PM UTC 24
Finished Sep 01 08:43:45 PM UTC 24
Peak memory 284672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1865608624 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stress_all.1865608624
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.4126827791
Short name T591
Test name
Test status
Simulation time 8349685506 ps
CPU time 31.22 seconds
Started Sep 01 08:39:29 PM UTC 24
Finished Sep 01 08:40:02 PM UTC 24
Peak memory 227948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126827791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.4126827791
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.1324473659
Short name T578
Test name
Test status
Simulation time 1474738107 ps
CPU time 13.92 seconds
Started Sep 01 08:39:29 PM UTC 24
Finished Sep 01 08:39:44 PM UTC 24
Peak memory 227776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324473659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1324473659
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.583043219
Short name T572
Test name
Test status
Simulation time 220680427 ps
CPU time 1.9 seconds
Started Sep 01 08:39:31 PM UTC 24
Finished Sep 01 08:39:34 PM UTC 24
Peak memory 226380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583043219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.583043219
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.1221207397
Short name T570
Test name
Test status
Simulation time 23960016 ps
CPU time 1.13 seconds
Started Sep 01 08:39:30 PM UTC 24
Finished Sep 01 08:39:32 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221207397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1221207397
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.1175205183
Short name T612
Test name
Test status
Simulation time 8057866111 ps
CPU time 43.69 seconds
Started Sep 01 08:39:36 PM UTC 24
Finished Sep 01 08:40:21 PM UTC 24
Peak memory 235392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175205183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1175205183
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/23.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.3646447395
Short name T592
Test name
Test status
Simulation time 23603642 ps
CPU time 1.1 seconds
Started Sep 01 08:40:02 PM UTC 24
Finished Sep 01 08:40:04 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3646447395 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.3646447395
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.2486541607
Short name T300
Test name
Test status
Simulation time 219103132 ps
CPU time 5.93 seconds
Started Sep 01 08:39:54 PM UTC 24
Finished Sep 01 08:40:01 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486541607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2486541607
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.2666971207
Short name T581
Test name
Test status
Simulation time 59102918 ps
CPU time 1.14 seconds
Started Sep 01 08:39:45 PM UTC 24
Finished Sep 01 08:39:48 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666971207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.2666971207
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm.1429412929
Short name T304
Test name
Test status
Simulation time 7772037963 ps
CPU time 88.34 seconds
Started Sep 01 08:39:58 PM UTC 24
Finished Sep 01 08:41:28 PM UTC 24
Peak memory 264232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1429412929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.1429412929
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_and_tpm_min_idle.722586145
Short name T711
Test name
Test status
Simulation time 29972116311 ps
CPU time 134.98 seconds
Started Sep 01 08:40:00 PM UTC 24
Finished Sep 01 08:42:17 PM UTC 24
Peak memory 280768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722586145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle.722586145
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.340117007
Short name T402
Test name
Test status
Simulation time 477018915 ps
CPU time 6.72 seconds
Started Sep 01 08:39:55 PM UTC 24
Finished Sep 01 08:40:03 PM UTC 24
Peak memory 235532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340117007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.340117007
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.595304361
Short name T281
Test name
Test status
Simulation time 2104270351 ps
CPU time 15.82 seconds
Started Sep 01 08:39:52 PM UTC 24
Finished Sep 01 08:40:09 PM UTC 24
Peak memory 235344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595304361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.595304361
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.1537737507
Short name T311
Test name
Test status
Simulation time 13673308048 ps
CPU time 60.5 seconds
Started Sep 01 08:39:52 PM UTC 24
Finished Sep 01 08:40:54 PM UTC 24
Peak memory 262304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537737507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1537737507
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.3100894919
Short name T585
Test name
Test status
Simulation time 89650362 ps
CPU time 2.47 seconds
Started Sep 01 08:39:50 PM UTC 24
Finished Sep 01 08:39:53 PM UTC 24
Peak memory 235500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100894919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swap.3100894919
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.2357878360
Short name T586
Test name
Test status
Simulation time 77296911 ps
CPU time 3.01 seconds
Started Sep 01 08:39:50 PM UTC 24
Finished Sep 01 08:39:54 PM UTC 24
Peak memory 234880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357878360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2357878360
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.3050268958
Short name T597
Test name
Test status
Simulation time 4081773584 ps
CPU time 14.09 seconds
Started Sep 01 08:39:55 PM UTC 24
Finished Sep 01 08:40:11 PM UTC 24
Peak memory 231792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050268958 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_direct.3050268958
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_stress_all.76907296
Short name T806
Test name
Test status
Simulation time 91973510692 ps
CPU time 220.95 seconds
Started Sep 01 08:40:01 PM UTC 24
Finished Sep 01 08:43:45 PM UTC 24
Peak memory 274628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76907296 -assert nopostproc +UVM_TEST
NAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stress_all.76907296
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.608789614
Short name T605
Test name
Test status
Simulation time 1083857060 ps
CPU time 28.96 seconds
Started Sep 01 08:39:48 PM UTC 24
Finished Sep 01 08:40:18 PM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608789614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.608789614
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.1936169594
Short name T588
Test name
Test status
Simulation time 2987506928 ps
CPU time 9.01 seconds
Started Sep 01 08:39:45 PM UTC 24
Finished Sep 01 08:39:56 PM UTC 24
Peak memory 227896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936169594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1936169594
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.1788656239
Short name T587
Test name
Test status
Simulation time 942143031 ps
CPU time 4.23 seconds
Started Sep 01 08:39:49 PM UTC 24
Finished Sep 01 08:39:54 PM UTC 24
Peak memory 228012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788656239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.1788656239
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.1002333372
Short name T584
Test name
Test status
Simulation time 141326335 ps
CPU time 1.64 seconds
Started Sep 01 08:39:49 PM UTC 24
Finished Sep 01 08:39:51 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002333372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.1002333372
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.4028906864
Short name T356
Test name
Test status
Simulation time 129717134 ps
CPU time 3.78 seconds
Started Sep 01 08:39:54 PM UTC 24
Finished Sep 01 08:39:59 PM UTC 24
Peak memory 245668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028906864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.4028906864
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/24.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.1929721686
Short name T606
Test name
Test status
Simulation time 22327957 ps
CPU time 0.98 seconds
Started Sep 01 08:40:16 PM UTC 24
Finished Sep 01 08:40:18 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929721686 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.1929721686
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.3487199880
Short name T601
Test name
Test status
Simulation time 478114448 ps
CPU time 3.19 seconds
Started Sep 01 08:40:10 PM UTC 24
Finished Sep 01 08:40:14 PM UTC 24
Peak memory 234384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487199880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3487199880
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.2806630722
Short name T593
Test name
Test status
Simulation time 15630829 ps
CPU time 1.14 seconds
Started Sep 01 08:40:02 PM UTC 24
Finished Sep 01 08:40:04 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806630722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.2806630722
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.3311772448
Short name T336
Test name
Test status
Simulation time 12375008921 ps
CPU time 84.99 seconds
Started Sep 01 08:40:12 PM UTC 24
Finished Sep 01 08:41:39 PM UTC 24
Peak memory 266356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3311772448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.3311772448
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.296922718
Short name T662
Test name
Test status
Simulation time 147377373088 ps
CPU time 78.26 seconds
Started Sep 01 08:40:13 PM UTC 24
Finished Sep 01 08:41:33 PM UTC 24
Peak memory 262184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296922718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.296922718
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm_min_idle.2463640914
Short name T1003
Test name
Test status
Simulation time 424236710004 ps
CPU time 512.79 seconds
Started Sep 01 08:40:13 PM UTC 24
Finished Sep 01 08:48:53 PM UTC 24
Peak memory 268292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463640914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle.2463640914
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.1231376792
Short name T602
Test name
Test status
Simulation time 110374424 ps
CPU time 4.79 seconds
Started Sep 01 08:40:10 PM UTC 24
Finished Sep 01 08:40:16 PM UTC 24
Peak memory 245796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231376792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1231376792
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode_ignore_cmds.3463313706
Short name T682
Test name
Test status
Simulation time 171035739859 ps
CPU time 101.76 seconds
Started Sep 01 08:40:12 PM UTC 24
Finished Sep 01 08:41:56 PM UTC 24
Peak memory 251848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463313706 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmds.3463313706
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.2330605629
Short name T599
Test name
Test status
Simulation time 126931397 ps
CPU time 3.23 seconds
Started Sep 01 08:40:07 PM UTC 24
Finished Sep 01 08:40:12 PM UTC 24
Peak memory 239832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330605629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.2330605629
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.2171975625
Short name T630
Test name
Test status
Simulation time 10706540359 ps
CPU time 44.64 seconds
Started Sep 01 08:40:07 PM UTC 24
Finished Sep 01 08:40:54 PM UTC 24
Peak memory 250080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171975625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.2171975625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.3642417370
Short name T341
Test name
Test status
Simulation time 982678452 ps
CPU time 6.72 seconds
Started Sep 01 08:40:07 PM UTC 24
Finished Sep 01 08:40:15 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642417370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap.3642417370
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.2691093822
Short name T603
Test name
Test status
Simulation time 2240878164 ps
CPU time 9.89 seconds
Started Sep 01 08:40:05 PM UTC 24
Finished Sep 01 08:40:16 PM UTC 24
Peak memory 235264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2691093822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.2691093822
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.545921817
Short name T615
Test name
Test status
Simulation time 4537492964 ps
CPU time 15.68 seconds
Started Sep 01 08:40:12 PM UTC 24
Finished Sep 01 08:40:29 PM UTC 24
Peak memory 231748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545921817 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_direct.545921817
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_stress_all.2306106342
Short name T604
Test name
Test status
Simulation time 250430174 ps
CPU time 1.44 seconds
Started Sep 01 08:40:15 PM UTC 24
Finished Sep 01 08:40:18 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306106342 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stress_all.2306106342
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.2994124425
Short name T619
Test name
Test status
Simulation time 13753480727 ps
CPU time 31.56 seconds
Started Sep 01 08:40:03 PM UTC 24
Finished Sep 01 08:40:36 PM UTC 24
Peak memory 228084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994124425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2994124425
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.4192678341
Short name T598
Test name
Test status
Simulation time 664677159 ps
CPU time 6.85 seconds
Started Sep 01 08:40:03 PM UTC 24
Finished Sep 01 08:40:11 PM UTC 24
Peak memory 227700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192678341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.4192678341
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.2256755466
Short name T596
Test name
Test status
Simulation time 20109859 ps
CPU time 1.44 seconds
Started Sep 01 08:40:05 PM UTC 24
Finished Sep 01 08:40:08 PM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256755466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.2256755466
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.1255594630
Short name T595
Test name
Test status
Simulation time 252485800 ps
CPU time 1.47 seconds
Started Sep 01 08:40:04 PM UTC 24
Finished Sep 01 08:40:07 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255594630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.1255594630
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.1342579944
Short name T360
Test name
Test status
Simulation time 264620816 ps
CPU time 6.77 seconds
Started Sep 01 08:40:08 PM UTC 24
Finished Sep 01 08:40:16 PM UTC 24
Peak memory 235356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342579944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1342579944
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/25.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.3801978772
Short name T617
Test name
Test status
Simulation time 27678902 ps
CPU time 1.14 seconds
Started Sep 01 08:40:31 PM UTC 24
Finished Sep 01 08:40:33 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801978772 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.3801978772
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.3432830941
Short name T614
Test name
Test status
Simulation time 33483839 ps
CPU time 3.3 seconds
Started Sep 01 08:40:22 PM UTC 24
Finished Sep 01 08:40:26 PM UTC 24
Peak memory 245196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432830941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3432830941
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.3133658726
Short name T607
Test name
Test status
Simulation time 27923259 ps
CPU time 1.15 seconds
Started Sep 01 08:40:16 PM UTC 24
Finished Sep 01 08:40:18 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133658726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3133658726
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_all.4257759110
Short name T836
Test name
Test status
Simulation time 39629569536 ps
CPU time 224.75 seconds
Started Sep 01 08:40:24 PM UTC 24
Finished Sep 01 08:44:13 PM UTC 24
Peak memory 268324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257759110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.4257759110
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_and_tpm_min_idle.2729912071
Short name T872
Test name
Test status
Simulation time 73933337764 ps
CPU time 271.19 seconds
Started Sep 01 08:40:27 PM UTC 24
Finished Sep 01 08:45:03 PM UTC 24
Peak memory 268320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729912071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idle.2729912071
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.2496847427
Short name T627
Test name
Test status
Simulation time 1922459823 ps
CPU time 21.67 seconds
Started Sep 01 08:40:22 PM UTC 24
Finished Sep 01 08:40:45 PM UTC 24
Peak memory 261940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2496847427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2496847427
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.347686231
Short name T613
Test name
Test status
Simulation time 57569973 ps
CPU time 1.29 seconds
Started Sep 01 08:40:22 PM UTC 24
Finished Sep 01 08:40:24 PM UTC 24
Peak memory 225732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=347686231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds.347686231
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.937281802
Short name T616
Test name
Test status
Simulation time 368126217 ps
CPU time 9.06 seconds
Started Sep 01 08:40:20 PM UTC 24
Finished Sep 01 08:40:30 PM UTC 24
Peak memory 245740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937281802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.937281802
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_mailbox.2515598387
Short name T636
Test name
Test status
Simulation time 3898606730 ps
CPU time 37 seconds
Started Sep 01 08:40:20 PM UTC 24
Finished Sep 01 08:40:58 PM UTC 24
Peak memory 235488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2515598387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.2515598387
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_addr_payload_swap.1667130492
Short name T361
Test name
Test status
Simulation time 163986038 ps
CPU time 3.23 seconds
Started Sep 01 08:40:20 PM UTC 24
Finished Sep 01 08:40:24 PM UTC 24
Peak memory 235260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667130492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap.1667130492
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.3887151126
Short name T310
Test name
Test status
Simulation time 3534961728 ps
CPU time 14.05 seconds
Started Sep 01 08:40:19 PM UTC 24
Finished Sep 01 08:40:34 PM UTC 24
Peak memory 245776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887151126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3887151126
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.3786369733
Short name T618
Test name
Test status
Simulation time 778135214 ps
CPU time 11.7 seconds
Started Sep 01 08:40:22 PM UTC 24
Finished Sep 01 08:40:35 PM UTC 24
Peak memory 233712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786369733 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_direct.3786369733
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.1672424713
Short name T647
Test name
Test status
Simulation time 6927736340 ps
CPU time 38.59 seconds
Started Sep 01 08:40:30 PM UTC 24
Finished Sep 01 08:41:10 PM UTC 24
Peak memory 251908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672424713 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stress_all.1672424713
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.3264808477
Short name T625
Test name
Test status
Simulation time 6141071636 ps
CPU time 22.63 seconds
Started Sep 01 08:40:17 PM UTC 24
Finished Sep 01 08:40:41 PM UTC 24
Peak memory 228020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264808477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.3264808477
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1912153106
Short name T610
Test name
Test status
Simulation time 244090438 ps
CPU time 2.58 seconds
Started Sep 01 08:40:17 PM UTC 24
Finished Sep 01 08:40:21 PM UTC 24
Peak memory 217308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1912153106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1912153106
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.4121958359
Short name T611
Test name
Test status
Simulation time 75881952 ps
CPU time 1.64 seconds
Started Sep 01 08:40:19 PM UTC 24
Finished Sep 01 08:40:21 PM UTC 24
Peak memory 215980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121958359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.4121958359
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.854581763
Short name T609
Test name
Test status
Simulation time 118777615 ps
CPU time 1.31 seconds
Started Sep 01 08:40:19 PM UTC 24
Finished Sep 01 08:40:21 PM UTC 24
Peak memory 215920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854581763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.854581763
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.3868759112
Short name T626
Test name
Test status
Simulation time 3282032013 ps
CPU time 22.52 seconds
Started Sep 01 08:40:21 PM UTC 24
Finished Sep 01 08:40:45 PM UTC 24
Peak memory 251812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868759112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3868759112
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/26.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_alert_test.4243182283
Short name T633
Test name
Test status
Simulation time 13464259 ps
CPU time 1.11 seconds
Started Sep 01 08:40:53 PM UTC 24
Finished Sep 01 08:40:56 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243182283 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.4243182283
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.2717843309
Short name T354
Test name
Test status
Simulation time 1212669454 ps
CPU time 8.29 seconds
Started Sep 01 08:40:42 PM UTC 24
Finished Sep 01 08:40:52 PM UTC 24
Peak memory 245544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717843309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2717843309
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.437980654
Short name T621
Test name
Test status
Simulation time 16226839 ps
CPU time 1.18 seconds
Started Sep 01 08:40:34 PM UTC 24
Finished Sep 01 08:40:37 PM UTC 24
Peak memory 215732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437980654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.437980654
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_all.3769206190
Short name T866
Test name
Test status
Simulation time 34945829073 ps
CPU time 232.52 seconds
Started Sep 01 08:40:50 PM UTC 24
Finished Sep 01 08:44:46 PM UTC 24
Peak memory 262084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769206190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3769206190
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm.898519693
Short name T386
Test name
Test status
Simulation time 123223047170 ps
CPU time 328.88 seconds
Started Sep 01 08:40:51 PM UTC 24
Finished Sep 01 08:46:25 PM UTC 24
Peak memory 268520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=898519693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.898519693
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_and_tpm_min_idle.901116788
Short name T761
Test name
Test status
Simulation time 10812745777 ps
CPU time 124.12 seconds
Started Sep 01 08:40:52 PM UTC 24
Finished Sep 01 08:42:59 PM UTC 24
Peak memory 247800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901116788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle.901116788
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode.2211042447
Short name T628
Test name
Test status
Simulation time 192083287 ps
CPU time 4.23 seconds
Started Sep 01 08:40:46 PM UTC 24
Finished Sep 01 08:40:51 PM UTC 24
Peak memory 245516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211042447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2211042447
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_flash_mode_ignore_cmds.3306892006
Short name T134
Test name
Test status
Simulation time 13048331789 ps
CPU time 26.67 seconds
Started Sep 01 08:40:46 PM UTC 24
Finished Sep 01 08:41:14 PM UTC 24
Peak memory 268256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306892006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.3306892006
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_intercept.3515568087
Short name T234
Test name
Test status
Simulation time 221295802 ps
CPU time 7.2 seconds
Started Sep 01 08:40:40 PM UTC 24
Finished Sep 01 08:40:49 PM UTC 24
Peak memory 230012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515568087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.3515568087
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_mailbox.1550196986
Short name T268
Test name
Test status
Simulation time 312509030 ps
CPU time 5.03 seconds
Started Sep 01 08:40:40 PM UTC 24
Finished Sep 01 08:40:47 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1550196986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.1550196986
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.1066703243
Short name T393
Test name
Test status
Simulation time 6221217217 ps
CPU time 12.64 seconds
Started Sep 01 08:40:39 PM UTC 24
Finished Sep 01 08:40:54 PM UTC 24
Peak memory 245708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066703243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap.1066703243
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.526554537
Short name T355
Test name
Test status
Simulation time 33583633708 ps
CPU time 29.63 seconds
Started Sep 01 08:40:38 PM UTC 24
Finished Sep 01 08:41:09 PM UTC 24
Peak memory 245712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526554537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.526554537
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_read_buffer_direct.1016430728
Short name T631
Test name
Test status
Simulation time 807598433 ps
CPU time 5.38 seconds
Started Sep 01 08:40:48 PM UTC 24
Finished Sep 01 08:40:54 PM UTC 24
Peak memory 233900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016430728 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_direct.1016430728
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_stress_all.1615874855
Short name T845
Test name
Test status
Simulation time 83558097211 ps
CPU time 208.87 seconds
Started Sep 01 08:40:53 PM UTC 24
Finished Sep 01 08:44:26 PM UTC 24
Peak memory 266532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615874855 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stress_all.1615874855
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_all.2461393100
Short name T642
Test name
Test status
Simulation time 1422108217 ps
CPU time 28.34 seconds
Started Sep 01 08:40:36 PM UTC 24
Finished Sep 01 08:41:06 PM UTC 24
Peak memory 227852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461393100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2461393100
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.2110585475
Short name T622
Test name
Test status
Simulation time 69454236 ps
CPU time 2.04 seconds
Started Sep 01 08:40:35 PM UTC 24
Finished Sep 01 08:40:38 PM UTC 24
Peak memory 216780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110585475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.2110585475
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.3343924501
Short name T624
Test name
Test status
Simulation time 40573330 ps
CPU time 1.78 seconds
Started Sep 01 08:40:37 PM UTC 24
Finished Sep 01 08:40:40 PM UTC 24
Peak memory 226572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343924501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.3343924501
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.3882389903
Short name T623
Test name
Test status
Simulation time 36960833 ps
CPU time 1.17 seconds
Started Sep 01 08:40:37 PM UTC 24
Finished Sep 01 08:40:39 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882389903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.3882389903
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/27.spi_device_upload.1156995397
Short name T644
Test name
Test status
Simulation time 23478131507 ps
CPU time 26.5 seconds
Started Sep 01 08:40:41 PM UTC 24
Finished Sep 01 08:41:09 PM UTC 24
Peak memory 247772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156995397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1156995397
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/27.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_alert_test.949424910
Short name T643
Test name
Test status
Simulation time 36867020 ps
CPU time 1.12 seconds
Started Sep 01 08:41:06 PM UTC 24
Finished Sep 01 08:41:09 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949424910 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.949424910
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_cfg_cmd.253962961
Short name T645
Test name
Test status
Simulation time 577024439 ps
CPU time 8.4 seconds
Started Sep 01 08:41:00 PM UTC 24
Finished Sep 01 08:41:10 PM UTC 24
Peak memory 235336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253962961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.253962961
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_csb_read.3151860139
Short name T634
Test name
Test status
Simulation time 50083462 ps
CPU time 1.19 seconds
Started Sep 01 08:40:54 PM UTC 24
Finished Sep 01 08:40:57 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151860139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3151860139
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_all.2620508715
Short name T248
Test name
Test status
Simulation time 1790912925 ps
CPU time 38.53 seconds
Started Sep 01 08:41:05 PM UTC 24
Finished Sep 01 08:41:45 PM UTC 24
Peak memory 262152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620508715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2620508715
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm.1455771362
Short name T390
Test name
Test status
Simulation time 7646021022 ps
CPU time 139.94 seconds
Started Sep 01 08:41:05 PM UTC 24
Finished Sep 01 08:43:28 PM UTC 24
Peak memory 262176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455771362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1455771362
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_and_tpm_min_idle.173378827
Short name T695
Test name
Test status
Simulation time 9637797745 ps
CPU time 60.71 seconds
Started Sep 01 08:41:05 PM UTC 24
Finished Sep 01 08:42:08 PM UTC 24
Peak memory 249860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173378827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.173378827
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode.628932313
Short name T641
Test name
Test status
Simulation time 145249989 ps
CPU time 4.08 seconds
Started Sep 01 08:41:00 PM UTC 24
Finished Sep 01 08:41:05 PM UTC 24
Peak memory 245580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628932313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.628932313
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_flash_mode_ignore_cmds.2992095111
Short name T389
Test name
Test status
Simulation time 1647363337 ps
CPU time 31.89 seconds
Started Sep 01 08:41:03 PM UTC 24
Finished Sep 01 08:41:36 PM UTC 24
Peak memory 261952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992095111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds.2992095111
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_intercept.164599081
Short name T640
Test name
Test status
Simulation time 143674430 ps
CPU time 5.8 seconds
Started Sep 01 08:40:58 PM UTC 24
Finished Sep 01 08:41:05 PM UTC 24
Peak memory 245768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164599081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.164599081
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_mailbox.4191293145
Short name T732
Test name
Test status
Simulation time 42158684758 ps
CPU time 95.04 seconds
Started Sep 01 08:40:59 PM UTC 24
Finished Sep 01 08:42:36 PM UTC 24
Peak memory 251868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191293145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.4191293145
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_addr_payload_swap.3240028126
Short name T368
Test name
Test status
Simulation time 662626573 ps
CPU time 8.13 seconds
Started Sep 01 08:40:58 PM UTC 24
Finished Sep 01 08:41:07 PM UTC 24
Peak memory 245772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240028126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap.3240028126
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_pass_cmd_filtering.4223656991
Short name T263
Test name
Test status
Simulation time 1830785379 ps
CPU time 9.22 seconds
Started Sep 01 08:40:57 PM UTC 24
Finished Sep 01 08:41:07 PM UTC 24
Peak memory 235320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223656991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.4223656991
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_read_buffer_direct.4180573998
Short name T650
Test name
Test status
Simulation time 480159080 ps
CPU time 8.79 seconds
Started Sep 01 08:41:04 PM UTC 24
Finished Sep 01 08:41:14 PM UTC 24
Peak memory 231656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180573998 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_direct.4180573998
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_stress_all.1643231239
Short name T245
Test name
Test status
Simulation time 134699693448 ps
CPU time 341.45 seconds
Started Sep 01 08:41:06 PM UTC 24
Finished Sep 01 08:46:53 PM UTC 24
Peak memory 284748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643231239 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stress_all.1643231239
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_all.2796106335
Short name T648
Test name
Test status
Simulation time 1995529915 ps
CPU time 14.74 seconds
Started Sep 01 08:40:55 PM UTC 24
Finished Sep 01 08:41:12 PM UTC 24
Peak memory 231860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796106335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2796106335
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_read_hw_reg.3974458161
Short name T638
Test name
Test status
Simulation time 222166474 ps
CPU time 3.53 seconds
Started Sep 01 08:40:54 PM UTC 24
Finished Sep 01 08:40:59 PM UTC 24
Peak memory 227648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974458161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3974458161
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_rw.1858488803
Short name T637
Test name
Test status
Simulation time 12904667 ps
CPU time 0.94 seconds
Started Sep 01 08:40:56 PM UTC 24
Finished Sep 01 08:40:59 PM UTC 24
Peak memory 215796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858488803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.1858488803
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_tpm_sts_read.8251947
Short name T635
Test name
Test status
Simulation time 227703730 ps
CPU time 1.44 seconds
Started Sep 01 08:40:55 PM UTC 24
Finished Sep 01 08:40:58 PM UTC 24
Peak memory 215920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8251947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM
_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.8251947
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/28.spi_device_upload.2157294665
Short name T307
Test name
Test status
Simulation time 999891828 ps
CPU time 4.7 seconds
Started Sep 01 08:40:59 PM UTC 24
Finished Sep 01 08:41:05 PM UTC 24
Peak memory 235524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157294665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2157294665
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/28.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_alert_test.3576393187
Short name T655
Test name
Test status
Simulation time 13359873 ps
CPU time 1.13 seconds
Started Sep 01 08:41:23 PM UTC 24
Finished Sep 01 08:41:25 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3576393187 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.3576393187
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_cfg_cmd.3394789174
Short name T656
Test name
Test status
Simulation time 2897603714 ps
CPU time 11.47 seconds
Started Sep 01 08:41:13 PM UTC 24
Finished Sep 01 08:41:26 PM UTC 24
Peak memory 245708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394789174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3394789174
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_csb_read.222042439
Short name T646
Test name
Test status
Simulation time 31947149 ps
CPU time 1.03 seconds
Started Sep 01 08:41:08 PM UTC 24
Finished Sep 01 08:41:10 PM UTC 24
Peak memory 215704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222042439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.222042439
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_all.3021005865
Short name T738
Test name
Test status
Simulation time 3419792179 ps
CPU time 80.67 seconds
Started Sep 01 08:41:18 PM UTC 24
Finished Sep 01 08:42:40 PM UTC 24
Peak memory 262088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021005865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3021005865
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm.2177146931
Short name T822
Test name
Test status
Simulation time 17892628734 ps
CPU time 160.21 seconds
Started Sep 01 08:41:18 PM UTC 24
Finished Sep 01 08:44:00 PM UTC 24
Peak memory 262408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177146931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2177146931
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_and_tpm_min_idle.1087936625
Short name T716
Test name
Test status
Simulation time 17088913891 ps
CPU time 61.26 seconds
Started Sep 01 08:41:20 PM UTC 24
Finished Sep 01 08:42:23 PM UTC 24
Peak memory 235720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087936625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle.1087936625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode.1613529301
Short name T734
Test name
Test status
Simulation time 10695013668 ps
CPU time 81 seconds
Started Sep 01 08:41:14 PM UTC 24
Finished Sep 01 08:42:37 PM UTC 24
Peak memory 251840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613529301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.1613529301
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_flash_mode_ignore_cmds.1428168144
Short name T729
Test name
Test status
Simulation time 28179985452 ps
CPU time 77.11 seconds
Started Sep 01 08:41:14 PM UTC 24
Finished Sep 01 08:42:33 PM UTC 24
Peak memory 268228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428168144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds.1428168144
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_intercept.2643581349
Short name T329
Test name
Test status
Simulation time 3308476892 ps
CPU time 27.08 seconds
Started Sep 01 08:41:11 PM UTC 24
Finished Sep 01 08:41:39 PM UTC 24
Peak memory 235436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643581349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2643581349
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_mailbox.3795845271
Short name T658
Test name
Test status
Simulation time 1040838226 ps
CPU time 13.33 seconds
Started Sep 01 08:41:12 PM UTC 24
Finished Sep 01 08:41:27 PM UTC 24
Peak memory 235276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795845271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.3795845271
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_addr_payload_swap.2558049938
Short name T651
Test name
Test status
Simulation time 384129841 ps
CPU time 3.07 seconds
Started Sep 01 08:41:11 PM UTC 24
Finished Sep 01 08:41:15 PM UTC 24
Peak memory 234848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558049938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap.2558049938
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_pass_cmd_filtering.3314703312
Short name T653
Test name
Test status
Simulation time 948799259 ps
CPU time 4.73 seconds
Started Sep 01 08:41:11 PM UTC 24
Finished Sep 01 08:41:17 PM UTC 24
Peak memory 245584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314703312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.3314703312
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_read_buffer_direct.2134350181
Short name T673
Test name
Test status
Simulation time 11293676816 ps
CPU time 28.41 seconds
Started Sep 01 08:41:15 PM UTC 24
Finished Sep 01 08:41:45 PM UTC 24
Peak memory 231988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134350181 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_direct.2134350181
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_all.4283257224
Short name T667
Test name
Test status
Simulation time 7033386286 ps
CPU time 29.96 seconds
Started Sep 01 08:41:10 PM UTC 24
Finished Sep 01 08:41:41 PM UTC 24
Peak memory 228144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283257224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.4283257224
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_read_hw_reg.2841140283
Short name T661
Test name
Test status
Simulation time 10537662362 ps
CPU time 24.1 seconds
Started Sep 01 08:41:08 PM UTC 24
Finished Sep 01 08:41:33 PM UTC 24
Peak memory 227708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841140283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.2841140283
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_rw.823703360
Short name T652
Test name
Test status
Simulation time 689759663 ps
CPU time 4.77 seconds
Started Sep 01 08:41:11 PM UTC 24
Finished Sep 01 08:41:17 PM UTC 24
Peak memory 227740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823703360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.823703360
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_tpm_sts_read.368987837
Short name T649
Test name
Test status
Simulation time 26423646 ps
CPU time 1.05 seconds
Started Sep 01 08:41:11 PM UTC 24
Finished Sep 01 08:41:13 PM UTC 24
Peak memory 215808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368987837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.368987837
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/29.spi_device_upload.4103660364
Short name T357
Test name
Test status
Simulation time 3667271791 ps
CPU time 21.08 seconds
Started Sep 01 08:41:13 PM UTC 24
Finished Sep 01 08:41:36 PM UTC 24
Peak memory 235396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4103660364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.4103660364
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/29.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_alert_test.2744024403
Short name T424
Test name
Test status
Simulation time 41710001 ps
CPU time 1.11 seconds
Started Sep 01 08:34:20 PM UTC 24
Finished Sep 01 08:34:22 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2744024403 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.2744024403
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_cfg_cmd.3992124655
Short name T107
Test name
Test status
Simulation time 768035476 ps
CPU time 11.71 seconds
Started Sep 01 08:34:15 PM UTC 24
Finished Sep 01 08:34:29 PM UTC 24
Peak memory 235268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992124655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3992124655
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_csb_read.350822634
Short name T422
Test name
Test status
Simulation time 37155632 ps
CPU time 1.12 seconds
Started Sep 01 08:34:10 PM UTC 24
Finished Sep 01 08:34:12 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350822634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.350822634
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_and_tpm_min_idle.1671779824
Short name T103
Test name
Test status
Simulation time 22634725633 ps
CPU time 59.26 seconds
Started Sep 01 08:34:17 PM UTC 24
Finished Sep 01 08:35:18 PM UTC 24
Peak memory 262160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671779824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.1671779824
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode.2169627937
Short name T81
Test name
Test status
Simulation time 4036832704 ps
CPU time 25.5 seconds
Started Sep 01 08:34:15 PM UTC 24
Finished Sep 01 08:34:43 PM UTC 24
Peak memory 245632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169627937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.2169627937
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_mode_ignore_cmds.1270526185
Short name T335
Test name
Test status
Simulation time 195652305349 ps
CPU time 498.38 seconds
Started Sep 01 08:34:15 PM UTC 24
Finished Sep 01 08:42:41 PM UTC 24
Peak memory 266192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270526185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.1270526185
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_intercept.2696282263
Short name T105
Test name
Test status
Simulation time 609155312 ps
CPU time 10.58 seconds
Started Sep 01 08:34:14 PM UTC 24
Finished Sep 01 08:34:26 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696282263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.2696282263
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mailbox.465107884
Short name T288
Test name
Test status
Simulation time 116863680223 ps
CPU time 99.89 seconds
Started Sep 01 08:34:14 PM UTC 24
Finished Sep 01 08:35:56 PM UTC 24
Peak memory 251812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465107884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.465107884
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_mem_parity.2115552108
Short name T46
Test name
Test status
Simulation time 92662485 ps
CPU time 1.45 seconds
Started Sep 01 08:34:11 PM UTC 24
Finished Sep 01 08:34:13 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115552108 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mem_parity.2115552108
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_addr_payload_swap.1530804493
Short name T63
Test name
Test status
Simulation time 6848825328 ps
CPU time 22.38 seconds
Started Sep 01 08:34:14 PM UTC 24
Finished Sep 01 08:34:38 PM UTC 24
Peak memory 235416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530804493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap.1530804493
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_pass_cmd_filtering.4060610098
Short name T131
Test name
Test status
Simulation time 20235830710 ps
CPU time 37.22 seconds
Started Sep 01 08:34:13 PM UTC 24
Finished Sep 01 08:34:52 PM UTC 24
Peak memory 245900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060610098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.4060610098
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_read_buffer_direct.542839027
Short name T87
Test name
Test status
Simulation time 670666639 ps
CPU time 8.32 seconds
Started Sep 01 08:34:16 PM UTC 24
Finished Sep 01 08:34:25 PM UTC 24
Peak memory 233424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=542839027 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_direct.542839027
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_sec_cm.2634523145
Short name T32
Test name
Test status
Simulation time 819777598 ps
CPU time 1.74 seconds
Started Sep 01 08:34:19 PM UTC 24
Finished Sep 01 08:34:22 PM UTC 24
Peak memory 257736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634523145 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2634523145
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_sec_cm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_all.1888039042
Short name T78
Test name
Test status
Simulation time 2578194745 ps
CPU time 27.05 seconds
Started Sep 01 08:34:12 PM UTC 24
Finished Sep 01 08:34:40 PM UTC 24
Peak memory 227980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888039042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1888039042
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_read_hw_reg.430665211
Short name T123
Test name
Test status
Simulation time 1328774660 ps
CPU time 6.87 seconds
Started Sep 01 08:34:11 PM UTC 24
Finished Sep 01 08:34:19 PM UTC 24
Peak memory 227776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430665211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.430665211
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_rw.972596874
Short name T28
Test name
Test status
Simulation time 20304432 ps
CPU time 1.3 seconds
Started Sep 01 08:34:13 PM UTC 24
Finished Sep 01 08:34:15 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972596874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.972596874
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_tpm_sts_read.261850354
Short name T27
Test name
Test status
Simulation time 216764188 ps
CPU time 1.38 seconds
Started Sep 01 08:34:12 PM UTC 24
Finished Sep 01 08:34:15 PM UTC 24
Peak memory 215920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261850354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.261850354
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/3.spi_device_upload.979680916
Short name T65
Test name
Test status
Simulation time 1707117169 ps
CPU time 9.1 seconds
Started Sep 01 08:34:14 PM UTC 24
Finished Sep 01 08:34:25 PM UTC 24
Peak memory 245744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979680916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.979680916
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/3.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_alert_test.3860189752
Short name T668
Test name
Test status
Simulation time 25097926 ps
CPU time 1.13 seconds
Started Sep 01 08:41:39 PM UTC 24
Finished Sep 01 08:41:41 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860189752 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.3860189752
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_cfg_cmd.1259059754
Short name T672
Test name
Test status
Simulation time 1435357736 ps
CPU time 10.08 seconds
Started Sep 01 08:41:34 PM UTC 24
Finished Sep 01 08:41:45 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259059754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1259059754
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_csb_read.3030742822
Short name T657
Test name
Test status
Simulation time 17120316 ps
CPU time 1.17 seconds
Started Sep 01 08:41:24 PM UTC 24
Finished Sep 01 08:41:26 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030742822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3030742822
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_all.964354969
Short name T666
Test name
Test status
Simulation time 107939705 ps
CPU time 1.24 seconds
Started Sep 01 08:41:36 PM UTC 24
Finished Sep 01 08:41:38 PM UTC 24
Peak memory 225728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964354969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.964354969
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.779289123
Short name T675
Test name
Test status
Simulation time 2102604552 ps
CPU time 9 seconds
Started Sep 01 08:41:37 PM UTC 24
Finished Sep 01 08:41:47 PM UTC 24
Peak memory 230104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779289123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.779289123
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm_min_idle.3615439019
Short name T395
Test name
Test status
Simulation time 407968225832 ps
CPU time 332.25 seconds
Started Sep 01 08:41:37 PM UTC 24
Finished Sep 01 08:47:14 PM UTC 24
Peak memory 278560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615439019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle.3615439019
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode.1737269704
Short name T703
Test name
Test status
Simulation time 2012290424 ps
CPU time 38.59 seconds
Started Sep 01 08:41:34 PM UTC 24
Finished Sep 01 08:42:14 PM UTC 24
Peak memory 251720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737269704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1737269704
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.3519985753
Short name T899
Test name
Test status
Simulation time 19885521383 ps
CPU time 231.24 seconds
Started Sep 01 08:41:35 PM UTC 24
Finished Sep 01 08:45:30 PM UTC 24
Peak memory 268224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519985753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds.3519985753
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_intercept.929711750
Short name T664
Test name
Test status
Simulation time 158955064 ps
CPU time 4.4 seconds
Started Sep 01 08:41:30 PM UTC 24
Finished Sep 01 08:41:36 PM UTC 24
Peak memory 235240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929711750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.929711750
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_mailbox.2032576823
Short name T684
Test name
Test status
Simulation time 989502288 ps
CPU time 23.26 seconds
Started Sep 01 08:41:32 PM UTC 24
Finished Sep 01 08:41:56 PM UTC 24
Peak memory 251744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032576823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2032576823
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_addr_payload_swap.662626853
Short name T663
Test name
Test status
Simulation time 126399216 ps
CPU time 5.4 seconds
Started Sep 01 08:41:28 PM UTC 24
Finished Sep 01 08:41:35 PM UTC 24
Peak memory 235464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662626853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swap.662626853
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_pass_cmd_filtering.520685773
Short name T665
Test name
Test status
Simulation time 200843418 ps
CPU time 7.43 seconds
Started Sep 01 08:41:28 PM UTC 24
Finished Sep 01 08:41:37 PM UTC 24
Peak memory 245124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520685773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.520685773
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_read_buffer_direct.1260184516
Short name T687
Test name
Test status
Simulation time 1378077131 ps
CPU time 19.45 seconds
Started Sep 01 08:41:36 PM UTC 24
Finished Sep 01 08:41:57 PM UTC 24
Peak memory 231668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1260184516 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_direct.1260184516
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_stress_all.641380444
Short name T186
Test name
Test status
Simulation time 8106376421 ps
CPU time 65.61 seconds
Started Sep 01 08:41:38 PM UTC 24
Finished Sep 01 08:42:45 PM UTC 24
Peak memory 266264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641380444 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stress_all.641380444
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_all.2478642056
Short name T671
Test name
Test status
Simulation time 2325665843 ps
CPU time 16.14 seconds
Started Sep 01 08:41:27 PM UTC 24
Finished Sep 01 08:41:45 PM UTC 24
Peak memory 227892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478642056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2478642056
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_read_hw_reg.3439759412
Short name T723
Test name
Test status
Simulation time 10470850778 ps
CPU time 58.75 seconds
Started Sep 01 08:41:26 PM UTC 24
Finished Sep 01 08:42:27 PM UTC 24
Peak memory 227864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439759412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.3439759412
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_rw.594213102
Short name T660
Test name
Test status
Simulation time 1399019938 ps
CPU time 2.58 seconds
Started Sep 01 08:41:27 PM UTC 24
Finished Sep 01 08:41:31 PM UTC 24
Peak memory 227756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594213102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.594213102
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_tpm_sts_read.481545170
Short name T659
Test name
Test status
Simulation time 111455182 ps
CPU time 1.14 seconds
Started Sep 01 08:41:27 PM UTC 24
Finished Sep 01 08:41:29 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481545170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.481545170
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/30.spi_device_upload.76885193
Short name T678
Test name
Test status
Simulation time 5668394216 ps
CPU time 18.08 seconds
Started Sep 01 08:41:33 PM UTC 24
Finished Sep 01 08:41:52 PM UTC 24
Peak memory 262116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76885193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_devi
ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.76885193
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/30.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_alert_test.1958804782
Short name T683
Test name
Test status
Simulation time 37982428 ps
CPU time 1 seconds
Started Sep 01 08:41:54 PM UTC 24
Finished Sep 01 08:41:56 PM UTC 24
Peak memory 215796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958804782 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.1958804782
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_cfg_cmd.2126742070
Short name T676
Test name
Test status
Simulation time 258219640 ps
CPU time 3.07 seconds
Started Sep 01 08:41:47 PM UTC 24
Finished Sep 01 08:41:51 PM UTC 24
Peak memory 235236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126742070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2126742070
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_csb_read.1434397954
Short name T669
Test name
Test status
Simulation time 15026784 ps
CPU time 1.18 seconds
Started Sep 01 08:41:39 PM UTC 24
Finished Sep 01 08:41:41 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1434397954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1434397954
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_all.2367000541
Short name T735
Test name
Test status
Simulation time 7651742076 ps
CPU time 44.35 seconds
Started Sep 01 08:41:52 PM UTC 24
Finished Sep 01 08:42:38 PM UTC 24
Peak memory 249932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367000541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2367000541
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm.199538032
Short name T985
Test name
Test status
Simulation time 29523851097 ps
CPU time 317.63 seconds
Started Sep 01 08:41:52 PM UTC 24
Finished Sep 01 08:47:15 PM UTC 24
Peak memory 278564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=199538032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.199538032
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_and_tpm_min_idle.1080971084
Short name T244
Test name
Test status
Simulation time 43057826200 ps
CPU time 154.04 seconds
Started Sep 01 08:41:53 PM UTC 24
Finished Sep 01 08:44:29 PM UTC 24
Peak memory 278728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1080971084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle.1080971084
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode.1866289855
Short name T680
Test name
Test status
Simulation time 121121251 ps
CPU time 3.9 seconds
Started Sep 01 08:41:48 PM UTC 24
Finished Sep 01 08:41:53 PM UTC 24
Peak memory 235272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866289855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1866289855
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_flash_mode_ignore_cmds.929106155
Short name T260
Test name
Test status
Simulation time 1558104360 ps
CPU time 48.27 seconds
Started Sep 01 08:41:50 PM UTC 24
Finished Sep 01 08:42:40 PM UTC 24
Peak memory 251908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929106155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmds.929106155
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_intercept.3733954232
Short name T681
Test name
Test status
Simulation time 856599171 ps
CPU time 7.37 seconds
Started Sep 01 08:41:46 PM UTC 24
Finished Sep 01 08:41:54 PM UTC 24
Peak memory 235236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733954232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3733954232
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_mailbox.3747862636
Short name T693
Test name
Test status
Simulation time 787259689 ps
CPU time 17.87 seconds
Started Sep 01 08:41:46 PM UTC 24
Finished Sep 01 08:42:05 PM UTC 24
Peak memory 245600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747862636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3747862636
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_addr_payload_swap.1083821867
Short name T697
Test name
Test status
Simulation time 3322880436 ps
CPU time 24.02 seconds
Started Sep 01 08:41:46 PM UTC 24
Finished Sep 01 08:42:11 PM UTC 24
Peak memory 251916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083821867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap.1083821867
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_pass_cmd_filtering.119785150
Short name T690
Test name
Test status
Simulation time 3157129710 ps
CPU time 12.86 seconds
Started Sep 01 08:41:46 PM UTC 24
Finished Sep 01 08:42:00 PM UTC 24
Peak memory 245712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119785150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.119785150
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_read_buffer_direct.2035630908
Short name T709
Test name
Test status
Simulation time 1499936937 ps
CPU time 22.98 seconds
Started Sep 01 08:41:52 PM UTC 24
Finished Sep 01 08:42:17 PM UTC 24
Peak memory 233680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035630908 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_direct.2035630908
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_stress_all.4140395155
Short name T685
Test name
Test status
Simulation time 59749132 ps
CPU time 1.71 seconds
Started Sep 01 08:41:54 PM UTC 24
Finished Sep 01 08:41:56 PM UTC 24
Peak memory 215860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140395155 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stress_all.4140395155
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_all.1858055049
Short name T699
Test name
Test status
Simulation time 10511778132 ps
CPU time 28.45 seconds
Started Sep 01 08:41:41 PM UTC 24
Finished Sep 01 08:42:11 PM UTC 24
Peak memory 227956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1858055049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1858055049
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_read_hw_reg.2025278288
Short name T679
Test name
Test status
Simulation time 2574140686 ps
CPU time 11.12 seconds
Started Sep 01 08:41:40 PM UTC 24
Finished Sep 01 08:41:53 PM UTC 24
Peak memory 227832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025278288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.2025278288
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_rw.4275069372
Short name T674
Test name
Test status
Simulation time 40487593 ps
CPU time 2.69 seconds
Started Sep 01 08:41:43 PM UTC 24
Finished Sep 01 08:41:46 PM UTC 24
Peak memory 228016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4275069372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.4275069372
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_tpm_sts_read.2286304620
Short name T670
Test name
Test status
Simulation time 42964228 ps
CPU time 1 seconds
Started Sep 01 08:41:43 PM UTC 24
Finished Sep 01 08:41:45 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286304620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.2286304620
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/31.spi_device_upload.1497862061
Short name T677
Test name
Test status
Simulation time 231070436 ps
CPU time 4.49 seconds
Started Sep 01 08:41:46 PM UTC 24
Finished Sep 01 08:41:52 PM UTC 24
Peak memory 245728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497862061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1497862061
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/31.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_alert_test.2989039896
Short name T698
Test name
Test status
Simulation time 13078758 ps
CPU time 1.13 seconds
Started Sep 01 08:42:09 PM UTC 24
Finished Sep 01 08:42:11 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989039896 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.2989039896
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_cfg_cmd.879353940
Short name T362
Test name
Test status
Simulation time 166072875 ps
CPU time 5.41 seconds
Started Sep 01 08:42:00 PM UTC 24
Finished Sep 01 08:42:07 PM UTC 24
Peak memory 235276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879353940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.879353940
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_csb_read.1130860018
Short name T686
Test name
Test status
Simulation time 71108349 ps
CPU time 1 seconds
Started Sep 01 08:41:55 PM UTC 24
Finished Sep 01 08:41:57 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130860018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1130860018
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.3861654270
Short name T781
Test name
Test status
Simulation time 17932605801 ps
CPU time 73.45 seconds
Started Sep 01 08:42:07 PM UTC 24
Finished Sep 01 08:43:22 PM UTC 24
Peak memory 262372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861654270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.3861654270
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm.977947823
Short name T763
Test name
Test status
Simulation time 4118492058 ps
CPU time 49.84 seconds
Started Sep 01 08:42:08 PM UTC 24
Finished Sep 01 08:42:59 PM UTC 24
Peak memory 252104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977947823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.977947823
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode.1890513473
Short name T397
Test name
Test status
Simulation time 102276124 ps
CPU time 7.93 seconds
Started Sep 01 08:42:06 PM UTC 24
Finished Sep 01 08:42:15 PM UTC 24
Peak memory 245572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890513473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1890513473
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.1447291637
Short name T994
Test name
Test status
Simulation time 145380908234 ps
CPU time 348.23 seconds
Started Sep 01 08:42:06 PM UTC 24
Finished Sep 01 08:47:59 PM UTC 24
Peak memory 268232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447291637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds.1447291637
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_intercept.2394553079
Short name T696
Test name
Test status
Simulation time 3660460173 ps
CPU time 11.55 seconds
Started Sep 01 08:41:58 PM UTC 24
Finished Sep 01 08:42:11 PM UTC 24
Peak memory 245708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394553079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2394553079
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_mailbox.3141638799
Short name T701
Test name
Test status
Simulation time 664778494 ps
CPU time 11.5 seconds
Started Sep 01 08:42:00 PM UTC 24
Finished Sep 01 08:42:13 PM UTC 24
Peak memory 261924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141638799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3141638799
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_addr_payload_swap.3857664014
Short name T691
Test name
Test status
Simulation time 1192763834 ps
CPU time 5.06 seconds
Started Sep 01 08:41:58 PM UTC 24
Finished Sep 01 08:42:04 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857664014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap.3857664014
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_pass_cmd_filtering.318589758
Short name T705
Test name
Test status
Simulation time 1153159796 ps
CPU time 14.9 seconds
Started Sep 01 08:41:58 PM UTC 24
Finished Sep 01 08:42:14 PM UTC 24
Peak memory 251756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318589758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.318589758
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_read_buffer_direct.3103728622
Short name T700
Test name
Test status
Simulation time 1543498782 ps
CPU time 5.6 seconds
Started Sep 01 08:42:06 PM UTC 24
Finished Sep 01 08:42:12 PM UTC 24
Peak memory 231604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103728622 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direct.3103728622
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_stress_all.4284552747
Short name T746
Test name
Test status
Simulation time 16022689126 ps
CPU time 35.53 seconds
Started Sep 01 08:42:09 PM UTC 24
Finished Sep 01 08:42:46 PM UTC 24
Peak memory 232148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284552747 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stress_all.4284552747
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_all.403883648
Short name T702
Test name
Test status
Simulation time 554580901 ps
CPU time 15.1 seconds
Started Sep 01 08:41:57 PM UTC 24
Finished Sep 01 08:42:13 PM UTC 24
Peak memory 227852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403883648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.403883648
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_read_hw_reg.473589052
Short name T694
Test name
Test status
Simulation time 1666614781 ps
CPU time 7.54 seconds
Started Sep 01 08:41:57 PM UTC 24
Finished Sep 01 08:42:05 PM UTC 24
Peak memory 227688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473589052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.473589052
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_rw.3633854723
Short name T689
Test name
Test status
Simulation time 19317041 ps
CPU time 1.7 seconds
Started Sep 01 08:41:57 PM UTC 24
Finished Sep 01 08:42:00 PM UTC 24
Peak memory 226608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633854723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.3633854723
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_tpm_sts_read.1520141103
Short name T688
Test name
Test status
Simulation time 119564978 ps
CPU time 1.27 seconds
Started Sep 01 08:41:57 PM UTC 24
Finished Sep 01 08:41:59 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1520141103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1520141103
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/32.spi_device_upload.1683912314
Short name T692
Test name
Test status
Simulation time 222988456 ps
CPU time 3.03 seconds
Started Sep 01 08:42:00 PM UTC 24
Finished Sep 01 08:42:04 PM UTC 24
Peak memory 235168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683912314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1683912314
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/32.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_alert_test.1079387810
Short name T718
Test name
Test status
Simulation time 12853093 ps
CPU time 1.04 seconds
Started Sep 01 08:42:21 PM UTC 24
Finished Sep 01 08:42:23 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079387810 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.1079387810
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_cfg_cmd.518000652
Short name T715
Test name
Test status
Simulation time 520506185 ps
CPU time 4.05 seconds
Started Sep 01 08:42:16 PM UTC 24
Finished Sep 01 08:42:21 PM UTC 24
Peak memory 235468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518000652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.518000652
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_csb_read.4290097580
Short name T706
Test name
Test status
Simulation time 31170991 ps
CPU time 1.19 seconds
Started Sep 01 08:42:12 PM UTC 24
Finished Sep 01 08:42:15 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290097580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.4290097580
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.2391754317
Short name T860
Test name
Test status
Simulation time 24595341495 ps
CPU time 137.61 seconds
Started Sep 01 08:42:18 PM UTC 24
Finished Sep 01 08:44:40 PM UTC 24
Peak memory 268360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391754317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2391754317
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.809596385
Short name T378
Test name
Test status
Simulation time 37982215815 ps
CPU time 558.19 seconds
Started Sep 01 08:42:18 PM UTC 24
Finished Sep 01 08:51:45 PM UTC 24
Peak memory 294912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809596385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle.809596385
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode.1198336666
Short name T714
Test name
Test status
Simulation time 50563175 ps
CPU time 3.83 seconds
Started Sep 01 08:42:16 PM UTC 24
Finished Sep 01 08:42:21 PM UTC 24
Peak memory 234884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198336666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1198336666
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_mode_ignore_cmds.3837653165
Short name T721
Test name
Test status
Simulation time 1051351084 ps
CPU time 8.18 seconds
Started Sep 01 08:42:16 PM UTC 24
Finished Sep 01 08:42:25 PM UTC 24
Peak memory 235276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837653165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds.3837653165
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_intercept.2796568031
Short name T238
Test name
Test status
Simulation time 254989417 ps
CPU time 8.28 seconds
Started Sep 01 08:42:15 PM UTC 24
Finished Sep 01 08:42:24 PM UTC 24
Peak memory 235408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796568031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2796568031
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_mailbox.2760081320
Short name T719
Test name
Test status
Simulation time 386630547 ps
CPU time 7.55 seconds
Started Sep 01 08:42:15 PM UTC 24
Finished Sep 01 08:42:24 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760081320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.2760081320
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_addr_payload_swap.2097666153
Short name T713
Test name
Test status
Simulation time 126059711 ps
CPU time 4.73 seconds
Started Sep 01 08:42:13 PM UTC 24
Finished Sep 01 08:42:19 PM UTC 24
Peak memory 235272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097666153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.2097666153
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_pass_cmd_filtering.1322722929
Short name T712
Test name
Test status
Simulation time 222111519 ps
CPU time 3.75 seconds
Started Sep 01 08:42:13 PM UTC 24
Finished Sep 01 08:42:18 PM UTC 24
Peak memory 245584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322722929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.1322722929
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_read_buffer_direct.2320297901
Short name T717
Test name
Test status
Simulation time 181088137 ps
CPU time 4.88 seconds
Started Sep 01 08:42:17 PM UTC 24
Finished Sep 01 08:42:23 PM UTC 24
Peak memory 231664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320297901 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_direct.2320297901
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_stress_all.4255944461
Short name T769
Test name
Test status
Simulation time 14982320536 ps
CPU time 44.43 seconds
Started Sep 01 08:42:19 PM UTC 24
Finished Sep 01 08:43:06 PM UTC 24
Peak memory 234316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255944461 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_all.4255944461
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_all.3731677702
Short name T749
Test name
Test status
Simulation time 1597217447 ps
CPU time 35.03 seconds
Started Sep 01 08:42:12 PM UTC 24
Finished Sep 01 08:42:49 PM UTC 24
Peak memory 231768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731677702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3731677702
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_read_hw_reg.2876031403
Short name T727
Test name
Test status
Simulation time 3089217027 ps
CPU time 18.51 seconds
Started Sep 01 08:42:12 PM UTC 24
Finished Sep 01 08:42:32 PM UTC 24
Peak memory 228008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876031403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2876031403
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_rw.830652472
Short name T708
Test name
Test status
Simulation time 41813555 ps
CPU time 1.61 seconds
Started Sep 01 08:42:13 PM UTC 24
Finished Sep 01 08:42:16 PM UTC 24
Peak memory 227012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830652472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.830652472
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_tpm_sts_read.3211416615
Short name T707
Test name
Test status
Simulation time 229828995 ps
CPU time 1.35 seconds
Started Sep 01 08:42:12 PM UTC 24
Finished Sep 01 08:42:15 PM UTC 24
Peak memory 215744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211416615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3211416615
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/33.spi_device_upload.3880196064
Short name T309
Test name
Test status
Simulation time 274611401 ps
CPU time 10.84 seconds
Started Sep 01 08:42:15 PM UTC 24
Finished Sep 01 08:42:26 PM UTC 24
Peak memory 235332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880196064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3880196064
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/33.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_alert_test.2272105989
Short name T731
Test name
Test status
Simulation time 164625682 ps
CPU time 1.11 seconds
Started Sep 01 08:42:34 PM UTC 24
Finished Sep 01 08:42:36 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272105989 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.2272105989
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_cfg_cmd.2897862013
Short name T737
Test name
Test status
Simulation time 756007382 ps
CPU time 9.98 seconds
Started Sep 01 08:42:27 PM UTC 24
Finished Sep 01 08:42:38 PM UTC 24
Peak memory 245600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897862013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.2897862013
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_csb_read.2866574758
Short name T704
Test name
Test status
Simulation time 27349725 ps
CPU time 1.2 seconds
Started Sep 01 08:42:21 PM UTC 24
Finished Sep 01 08:42:24 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866574758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.2866574758
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_all.3681852625
Short name T893
Test name
Test status
Simulation time 19145769859 ps
CPU time 172.82 seconds
Started Sep 01 08:42:30 PM UTC 24
Finished Sep 01 08:45:26 PM UTC 24
Peak memory 264136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681852625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3681852625
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.472212389
Short name T1010
Test name
Test status
Simulation time 220134416772 ps
CPU time 438.07 seconds
Started Sep 01 08:42:32 PM UTC 24
Finished Sep 01 08:49:57 PM UTC 24
Peak memory 276580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472212389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.472212389
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.2220940607
Short name T741
Test name
Test status
Simulation time 852181946 ps
CPU time 7.77 seconds
Started Sep 01 08:42:33 PM UTC 24
Finished Sep 01 08:42:42 PM UTC 24
Peak memory 230196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220940607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle.2220940607
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode.864494428
Short name T733
Test name
Test status
Simulation time 565959111 ps
CPU time 8.4 seconds
Started Sep 01 08:42:27 PM UTC 24
Finished Sep 01 08:42:37 PM UTC 24
Peak memory 245580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=864494428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.864494428
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_mode_ignore_cmds.2567916438
Short name T371
Test name
Test status
Simulation time 57456714331 ps
CPU time 105.73 seconds
Started Sep 01 08:42:27 PM UTC 24
Finished Sep 01 08:44:15 PM UTC 24
Peak memory 262080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567916438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds.2567916438
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_intercept.1177731980
Short name T728
Test name
Test status
Simulation time 1056279583 ps
CPU time 6.77 seconds
Started Sep 01 08:42:25 PM UTC 24
Finished Sep 01 08:42:33 PM UTC 24
Peak memory 245608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177731980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1177731980
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_mailbox.345233033
Short name T744
Test name
Test status
Simulation time 3498919666 ps
CPU time 16.44 seconds
Started Sep 01 08:42:26 PM UTC 24
Finished Sep 01 08:42:44 PM UTC 24
Peak memory 245920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345233033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.345233033
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_addr_payload_swap.3397969249
Short name T337
Test name
Test status
Simulation time 3581557404 ps
CPU time 25.7 seconds
Started Sep 01 08:42:25 PM UTC 24
Finished Sep 01 08:42:52 PM UTC 24
Peak memory 245684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3397969249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap.3397969249
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_pass_cmd_filtering.4259655486
Short name T725
Test name
Test status
Simulation time 98038790 ps
CPU time 2.94 seconds
Started Sep 01 08:42:25 PM UTC 24
Finished Sep 01 08:42:29 PM UTC 24
Peak memory 245264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259655486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.4259655486
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_read_buffer_direct.2240405216
Short name T745
Test name
Test status
Simulation time 3322645070 ps
CPU time 15.89 seconds
Started Sep 01 08:42:28 PM UTC 24
Finished Sep 01 08:42:46 PM UTC 24
Peak memory 233872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240405216 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_direct.2240405216
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_stress_all.2460635272
Short name T363
Test name
Test status
Simulation time 21002637602 ps
CPU time 132.5 seconds
Started Sep 01 08:42:34 PM UTC 24
Finished Sep 01 08:44:49 PM UTC 24
Peak memory 250056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460635272 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stress_all.2460635272
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_all.2146696783
Short name T759
Test name
Test status
Simulation time 1481963471 ps
CPU time 31.61 seconds
Started Sep 01 08:42:24 PM UTC 24
Finished Sep 01 08:42:57 PM UTC 24
Peak memory 228080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146696783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.2146696783
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_read_hw_reg.1837717179
Short name T726
Test name
Test status
Simulation time 911530329 ps
CPU time 7.78 seconds
Started Sep 01 08:42:22 PM UTC 24
Finished Sep 01 08:42:31 PM UTC 24
Peak memory 227672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1837717179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1837717179
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_rw.528699216
Short name T724
Test name
Test status
Simulation time 21893938 ps
CPU time 1.52 seconds
Started Sep 01 08:42:25 PM UTC 24
Finished Sep 01 08:42:28 PM UTC 24
Peak memory 215632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=528699216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.528699216
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_tpm_sts_read.427100624
Short name T722
Test name
Test status
Simulation time 121724261 ps
CPU time 1.14 seconds
Started Sep 01 08:42:24 PM UTC 24
Finished Sep 01 08:42:26 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427100624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.427100624
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/34.spi_device_upload.3165646488
Short name T743
Test name
Test status
Simulation time 1408766462 ps
CPU time 15.53 seconds
Started Sep 01 08:42:27 PM UTC 24
Finished Sep 01 08:42:44 PM UTC 24
Peak memory 245596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165646488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3165646488
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/34.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_alert_test.3582047690
Short name T751
Test name
Test status
Simulation time 18876810 ps
CPU time 1.09 seconds
Started Sep 01 08:42:47 PM UTC 24
Finished Sep 01 08:42:50 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582047690 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.3582047690
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_cfg_cmd.581283952
Short name T750
Test name
Test status
Simulation time 154574085 ps
CPU time 5.89 seconds
Started Sep 01 08:42:42 PM UTC 24
Finished Sep 01 08:42:49 PM UTC 24
Peak memory 245544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581283952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.581283952
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_csb_read.3810059559
Short name T736
Test name
Test status
Simulation time 26148436 ps
CPU time 1.18 seconds
Started Sep 01 08:42:36 PM UTC 24
Finished Sep 01 08:42:38 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810059559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3810059559
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.110030264
Short name T811
Test name
Test status
Simulation time 38512905735 ps
CPU time 66.28 seconds
Started Sep 01 08:42:45 PM UTC 24
Finished Sep 01 08:43:53 PM UTC 24
Peak memory 234236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110030264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.110030264
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.1918892822
Short name T792
Test name
Test status
Simulation time 2170207280 ps
CPU time 46.19 seconds
Started Sep 01 08:42:45 PM UTC 24
Finished Sep 01 08:43:33 PM UTC 24
Peak memory 245764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918892822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle.1918892822
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode.1870242973
Short name T756
Test name
Test status
Simulation time 569972927 ps
CPU time 9.63 seconds
Started Sep 01 08:42:42 PM UTC 24
Finished Sep 01 08:42:53 PM UTC 24
Peak memory 262244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1870242973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1870242973
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_mode_ignore_cmds.39322160
Short name T773
Test name
Test status
Simulation time 1370564851 ps
CPU time 26 seconds
Started Sep 01 08:42:42 PM UTC 24
Finished Sep 01 08:43:09 PM UTC 24
Peak memory 266148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39322160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmds.39322160
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_intercept.2621278872
Short name T758
Test name
Test status
Simulation time 1135999422 ps
CPU time 14.49 seconds
Started Sep 01 08:42:39 PM UTC 24
Finished Sep 01 08:42:55 PM UTC 24
Peak memory 245548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2621278872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2621278872
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_mailbox.4095685086
Short name T747
Test name
Test status
Simulation time 78274025 ps
CPU time 3.14 seconds
Started Sep 01 08:42:41 PM UTC 24
Finished Sep 01 08:42:46 PM UTC 24
Peak memory 235120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095685086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4095685086
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_addr_payload_swap.3627136815
Short name T345
Test name
Test status
Simulation time 1800039566 ps
CPU time 11.65 seconds
Started Sep 01 08:42:39 PM UTC 24
Finished Sep 01 08:42:52 PM UTC 24
Peak memory 235276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627136815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap.3627136815
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_pass_cmd_filtering.2740381240
Short name T777
Test name
Test status
Simulation time 7567365613 ps
CPU time 36.11 seconds
Started Sep 01 08:42:39 PM UTC 24
Finished Sep 01 08:43:17 PM UTC 24
Peak memory 245688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740381240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2740381240
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_read_buffer_direct.1630161032
Short name T753
Test name
Test status
Simulation time 185570594 ps
CPU time 6.61 seconds
Started Sep 01 08:42:43 PM UTC 24
Finished Sep 01 08:42:51 PM UTC 24
Peak memory 234092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630161032 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_direct.1630161032
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_stress_all.355703186
Short name T1009
Test name
Test status
Simulation time 69271034798 ps
CPU time 403.88 seconds
Started Sep 01 08:42:46 PM UTC 24
Finished Sep 01 08:49:36 PM UTC 24
Peak memory 284664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355703186 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stress_all.355703186
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_all.4221954784
Short name T779
Test name
Test status
Simulation time 61639374367 ps
CPU time 40.53 seconds
Started Sep 01 08:42:37 PM UTC 24
Finished Sep 01 08:43:19 PM UTC 24
Peak memory 228016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221954784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4221954784
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_read_hw_reg.1005428883
Short name T742
Test name
Test status
Simulation time 1557538246 ps
CPU time 4.97 seconds
Started Sep 01 08:42:37 PM UTC 24
Finished Sep 01 08:42:43 PM UTC 24
Peak memory 227700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005428883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1005428883
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_rw.686626951
Short name T740
Test name
Test status
Simulation time 54296377 ps
CPU time 1.19 seconds
Started Sep 01 08:42:38 PM UTC 24
Finished Sep 01 08:42:40 PM UTC 24
Peak memory 215984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686626951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.686626951
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_tpm_sts_read.1518467526
Short name T739
Test name
Test status
Simulation time 16941374 ps
CPU time 1.1 seconds
Started Sep 01 08:42:38 PM UTC 24
Finished Sep 01 08:42:40 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518467526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1518467526
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/35.spi_device_upload.2549613595
Short name T748
Test name
Test status
Simulation time 562230590 ps
CPU time 4.54 seconds
Started Sep 01 08:42:42 PM UTC 24
Finished Sep 01 08:42:47 PM UTC 24
Peak memory 235352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549613595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2549613595
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/35.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_alert_test.1093329329
Short name T765
Test name
Test status
Simulation time 39046790 ps
CPU time 1.12 seconds
Started Sep 01 08:43:00 PM UTC 24
Finished Sep 01 08:43:02 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093329329 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.1093329329
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_cfg_cmd.1925243149
Short name T760
Test name
Test status
Simulation time 101480319 ps
CPU time 3.98 seconds
Started Sep 01 08:42:53 PM UTC 24
Finished Sep 01 08:42:58 PM UTC 24
Peak memory 235588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925243149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1925243149
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_csb_read.4048999783
Short name T752
Test name
Test status
Simulation time 65019722 ps
CPU time 1.17 seconds
Started Sep 01 08:42:47 PM UTC 24
Finished Sep 01 08:42:50 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048999783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.4048999783
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_all.3432511749
Short name T819
Test name
Test status
Simulation time 4285486067 ps
CPU time 62.14 seconds
Started Sep 01 08:42:55 PM UTC 24
Finished Sep 01 08:43:59 PM UTC 24
Peak memory 272328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432511749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3432511749
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm.1909519682
Short name T1006
Test name
Test status
Simulation time 34278204020 ps
CPU time 370.35 seconds
Started Sep 01 08:42:56 PM UTC 24
Finished Sep 01 08:49:12 PM UTC 24
Peak memory 280780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909519682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.1909519682
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3602870849
Short name T921
Test name
Test status
Simulation time 16387431674 ps
CPU time 175.39 seconds
Started Sep 01 08:42:57 PM UTC 24
Finished Sep 01 08:45:56 PM UTC 24
Peak memory 251912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602870849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle.3602870849
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode.691656615
Short name T772
Test name
Test status
Simulation time 8906042820 ps
CPU time 14.27 seconds
Started Sep 01 08:42:53 PM UTC 24
Finished Sep 01 08:43:08 PM UTC 24
Peak memory 251876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691656615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.691656615
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.922404529
Short name T841
Test name
Test status
Simulation time 30835247825 ps
CPU time 83.58 seconds
Started Sep 01 08:42:53 PM UTC 24
Finished Sep 01 08:44:19 PM UTC 24
Peak memory 235716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922404529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmds.922404529
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_intercept.621698473
Short name T782
Test name
Test status
Simulation time 13031162576 ps
CPU time 29.91 seconds
Started Sep 01 08:42:52 PM UTC 24
Finished Sep 01 08:43:23 PM UTC 24
Peak memory 245704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621698473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.621698473
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_mailbox.2759331904
Short name T807
Test name
Test status
Simulation time 6163320983 ps
CPU time 53.15 seconds
Started Sep 01 08:42:52 PM UTC 24
Finished Sep 01 08:43:47 PM UTC 24
Peak memory 245640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759331904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2759331904
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_addr_payload_swap.1945117846
Short name T364
Test name
Test status
Simulation time 1771872454 ps
CPU time 11.13 seconds
Started Sep 01 08:42:51 PM UTC 24
Finished Sep 01 08:43:03 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945117846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap.1945117846
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_pass_cmd_filtering.1243863167
Short name T770
Test name
Test status
Simulation time 550558552 ps
CPU time 15.86 seconds
Started Sep 01 08:42:51 PM UTC 24
Finished Sep 01 08:43:08 PM UTC 24
Peak memory 245584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243863167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1243863167
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_read_buffer_direct.636515224
Short name T771
Test name
Test status
Simulation time 1719561725 ps
CPU time 12.55 seconds
Started Sep 01 08:42:54 PM UTC 24
Finished Sep 01 08:43:08 PM UTC 24
Peak memory 231796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636515224 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_direct.636515224
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.306358038
Short name T764
Test name
Test status
Simulation time 207890121 ps
CPU time 1.58 seconds
Started Sep 01 08:42:58 PM UTC 24
Finished Sep 01 08:43:01 PM UTC 24
Peak memory 216664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306358038 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stress_all.306358038
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_all.3723001413
Short name T762
Test name
Test status
Simulation time 478189132 ps
CPU time 8.86 seconds
Started Sep 01 08:42:48 PM UTC 24
Finished Sep 01 08:42:59 PM UTC 24
Peak memory 227764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723001413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.3723001413
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_read_hw_reg.1382841702
Short name T776
Test name
Test status
Simulation time 4254328089 ps
CPU time 25.96 seconds
Started Sep 01 08:42:47 PM UTC 24
Finished Sep 01 08:43:15 PM UTC 24
Peak memory 228180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382841702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.1382841702
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_rw.2931513516
Short name T757
Test name
Test status
Simulation time 187780376 ps
CPU time 4.12 seconds
Started Sep 01 08:42:50 PM UTC 24
Finished Sep 01 08:42:55 PM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931513516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.2931513516
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_tpm_sts_read.652869522
Short name T754
Test name
Test status
Simulation time 25046503 ps
CPU time 1.26 seconds
Started Sep 01 08:42:49 PM UTC 24
Finished Sep 01 08:42:52 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652869522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.652869522
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/36.spi_device_upload.729820536
Short name T803
Test name
Test status
Simulation time 9517640984 ps
CPU time 48.44 seconds
Started Sep 01 08:42:53 PM UTC 24
Finished Sep 01 08:43:43 PM UTC 24
Peak memory 247740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729820536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.729820536
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/36.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_alert_test.3900029122
Short name T780
Test name
Test status
Simulation time 19330875 ps
CPU time 0.92 seconds
Started Sep 01 08:43:20 PM UTC 24
Finished Sep 01 08:43:22 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900029122 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.3900029122
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_cfg_cmd.3408268543
Short name T778
Test name
Test status
Simulation time 512297494 ps
CPU time 7.39 seconds
Started Sep 01 08:43:08 PM UTC 24
Finished Sep 01 08:43:17 PM UTC 24
Peak memory 235268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408268543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3408268543
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_csb_read.1246531295
Short name T766
Test name
Test status
Simulation time 40518916 ps
CPU time 1.17 seconds
Started Sep 01 08:43:00 PM UTC 24
Finished Sep 01 08:43:02 PM UTC 24
Peak memory 215796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246531295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.1246531295
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.3085481266
Short name T850
Test name
Test status
Simulation time 9990952829 ps
CPU time 75.48 seconds
Started Sep 01 08:43:12 PM UTC 24
Finished Sep 01 08:44:29 PM UTC 24
Peak memory 264132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085481266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3085481266
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.449902052
Short name T885
Test name
Test status
Simulation time 25226933764 ps
CPU time 115.58 seconds
Started Sep 01 08:43:16 PM UTC 24
Finished Sep 01 08:45:14 PM UTC 24
Peak memory 268328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449902052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.449902052
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.3350573577
Short name T970
Test name
Test status
Simulation time 68551573332 ps
CPU time 212.58 seconds
Started Sep 01 08:43:18 PM UTC 24
Finished Sep 01 08:46:55 PM UTC 24
Peak memory 262172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350573577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle.3350573577
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode.3033726369
Short name T789
Test name
Test status
Simulation time 3393730011 ps
CPU time 19.93 seconds
Started Sep 01 08:43:09 PM UTC 24
Finished Sep 01 08:43:31 PM UTC 24
Peak memory 252036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033726369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3033726369
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.4168498300
Short name T385
Test name
Test status
Simulation time 17587994089 ps
CPU time 81.94 seconds
Started Sep 01 08:43:11 PM UTC 24
Finished Sep 01 08:44:35 PM UTC 24
Peak memory 249800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168498300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds.4168498300
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_intercept.1626444132
Short name T359
Test name
Test status
Simulation time 1888467588 ps
CPU time 15.1 seconds
Started Sep 01 08:43:06 PM UTC 24
Finished Sep 01 08:43:22 PM UTC 24
Peak memory 235528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626444132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.1626444132
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_mailbox.2752398307
Short name T775
Test name
Test status
Simulation time 29160101 ps
CPU time 2.91 seconds
Started Sep 01 08:43:07 PM UTC 24
Finished Sep 01 08:43:11 PM UTC 24
Peak memory 234584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752398307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.2752398307
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_addr_payload_swap.861744144
Short name T342
Test name
Test status
Simulation time 6655758286 ps
CPU time 15.04 seconds
Started Sep 01 08:43:06 PM UTC 24
Finished Sep 01 08:43:22 PM UTC 24
Peak memory 245864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861744144 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap.861744144
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_pass_cmd_filtering.3480030118
Short name T785
Test name
Test status
Simulation time 8718030143 ps
CPU time 22.52 seconds
Started Sep 01 08:43:04 PM UTC 24
Finished Sep 01 08:43:28 PM UTC 24
Peak memory 252048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480030118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3480030118
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_read_buffer_direct.1915037858
Short name T790
Test name
Test status
Simulation time 3014491771 ps
CPU time 19.04 seconds
Started Sep 01 08:43:11 PM UTC 24
Finished Sep 01 08:43:31 PM UTC 24
Peak memory 233836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915037858 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_direct.1915037858
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.812878309
Short name T176
Test name
Test status
Simulation time 71406856366 ps
CPU time 389.84 seconds
Started Sep 01 08:43:18 PM UTC 24
Finished Sep 01 08:49:53 PM UTC 24
Peak memory 266432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812878309 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stress_all.812878309
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_all.3340393932
Short name T794
Test name
Test status
Simulation time 18968694858 ps
CPU time 30.02 seconds
Started Sep 01 08:43:02 PM UTC 24
Finished Sep 01 08:43:33 PM UTC 24
Peak memory 227952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340393932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3340393932
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_read_hw_reg.3741823011
Short name T774
Test name
Test status
Simulation time 1254642116 ps
CPU time 8.27 seconds
Started Sep 01 08:43:01 PM UTC 24
Finished Sep 01 08:43:10 PM UTC 24
Peak memory 227792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741823011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3741823011
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_rw.869227825
Short name T767
Test name
Test status
Simulation time 19332379 ps
CPU time 1.33 seconds
Started Sep 01 08:43:03 PM UTC 24
Finished Sep 01 08:43:05 PM UTC 24
Peak memory 215632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869227825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.869227825
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_tpm_sts_read.3552703097
Short name T768
Test name
Test status
Simulation time 111059319 ps
CPU time 1.66 seconds
Started Sep 01 08:43:03 PM UTC 24
Finished Sep 01 08:43:06 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552703097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.3552703097
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/37.spi_device_upload.1847872833
Short name T791
Test name
Test status
Simulation time 3279552379 ps
CPU time 21.57 seconds
Started Sep 01 08:43:08 PM UTC 24
Finished Sep 01 08:43:31 PM UTC 24
Peak memory 245692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847872833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1847872833
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/37.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_alert_test.3134749905
Short name T796
Test name
Test status
Simulation time 16437375 ps
CPU time 1.09 seconds
Started Sep 01 08:43:33 PM UTC 24
Finished Sep 01 08:43:35 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134749905 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.3134749905
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_cfg_cmd.1078430852
Short name T802
Test name
Test status
Simulation time 790443547 ps
CPU time 9.39 seconds
Started Sep 01 08:43:29 PM UTC 24
Finished Sep 01 08:43:40 PM UTC 24
Peak memory 245708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078430852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1078430852
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_csb_read.2495988802
Short name T783
Test name
Test status
Simulation time 13143766 ps
CPU time 1.16 seconds
Started Sep 01 08:43:23 PM UTC 24
Finished Sep 01 08:43:25 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495988802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2495988802
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.169006535
Short name T394
Test name
Test status
Simulation time 2414129735 ps
CPU time 20.25 seconds
Started Sep 01 08:43:31 PM UTC 24
Finished Sep 01 08:43:53 PM UTC 24
Peak memory 245488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169006535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.169006535
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.3827657078
Short name T42
Test name
Test status
Simulation time 39530541231 ps
CPU time 144.46 seconds
Started Sep 01 08:43:32 PM UTC 24
Finished Sep 01 08:46:00 PM UTC 24
Peak memory 276488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827657078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.3827657078
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode.2616359693
Short name T816
Test name
Test status
Simulation time 1685947569 ps
CPU time 25.47 seconds
Started Sep 01 08:43:29 PM UTC 24
Finished Sep 01 08:43:56 PM UTC 24
Peak memory 245548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616359693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2616359693
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.12625423
Short name T990
Test name
Test status
Simulation time 24334385058 ps
CPU time 249.9 seconds
Started Sep 01 08:43:29 PM UTC 24
Finished Sep 01 08:47:43 PM UTC 24
Peak memory 280712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12625423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmds.12625423
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_intercept.594420345
Short name T788
Test name
Test status
Simulation time 107930058 ps
CPU time 2.2 seconds
Started Sep 01 08:43:27 PM UTC 24
Finished Sep 01 08:43:30 PM UTC 24
Peak memory 245420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594420345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.594420345
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_mailbox.2994244350
Short name T840
Test name
Test status
Simulation time 28017386650 ps
CPU time 49.19 seconds
Started Sep 01 08:43:27 PM UTC 24
Finished Sep 01 08:44:18 PM UTC 24
Peak memory 245700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994244350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2994244350
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_addr_payload_swap.3512862977
Short name T369
Test name
Test status
Simulation time 6881144135 ps
CPU time 37.25 seconds
Started Sep 01 08:43:27 PM UTC 24
Finished Sep 01 08:44:06 PM UTC 24
Peak memory 245648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512862977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swap.3512862977
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_pass_cmd_filtering.984693436
Short name T786
Test name
Test status
Simulation time 140593221 ps
CPU time 2.54 seconds
Started Sep 01 08:43:25 PM UTC 24
Finished Sep 01 08:43:28 PM UTC 24
Peak memory 235136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984693436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.984693436
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_read_buffer_direct.2780835439
Short name T795
Test name
Test status
Simulation time 260415534 ps
CPU time 4.37 seconds
Started Sep 01 08:43:29 PM UTC 24
Finished Sep 01 08:43:35 PM UTC 24
Peak memory 231604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780835439 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direct.2780835439
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.479288781
Short name T384
Test name
Test status
Simulation time 8470880127 ps
CPU time 104.65 seconds
Started Sep 01 08:43:32 PM UTC 24
Finished Sep 01 08:45:20 PM UTC 24
Peak memory 266432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479288781 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stress_all.479288781
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_all.1449118623
Short name T787
Test name
Test status
Simulation time 1137128741 ps
CPU time 4 seconds
Started Sep 01 08:43:23 PM UTC 24
Finished Sep 01 08:43:28 PM UTC 24
Peak memory 228016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449118623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.1449118623
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_read_hw_reg.1777767358
Short name T793
Test name
Test status
Simulation time 3034555464 ps
CPU time 8.74 seconds
Started Sep 01 08:43:23 PM UTC 24
Finished Sep 01 08:43:33 PM UTC 24
Peak memory 228092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777767358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1777767358
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_rw.1891468910
Short name T720
Test name
Test status
Simulation time 81248196 ps
CPU time 1.25 seconds
Started Sep 01 08:43:24 PM UTC 24
Finished Sep 01 08:43:27 PM UTC 24
Peak memory 215980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891468910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1891468910
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_tpm_sts_read.3436656923
Short name T784
Test name
Test status
Simulation time 78589533 ps
CPU time 1.27 seconds
Started Sep 01 08:43:23 PM UTC 24
Finished Sep 01 08:43:26 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436656923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3436656923
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/38.spi_device_upload.1899947810
Short name T799
Test name
Test status
Simulation time 1282726120 ps
CPU time 8.67 seconds
Started Sep 01 08:43:28 PM UTC 24
Finished Sep 01 08:43:38 PM UTC 24
Peak memory 261972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899947810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.1899947810
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/38.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_alert_test.3787247556
Short name T812
Test name
Test status
Simulation time 13030519 ps
CPU time 1.13 seconds
Started Sep 01 08:43:51 PM UTC 24
Finished Sep 01 08:43:54 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787247556 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.3787247556
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_cfg_cmd.497317693
Short name T815
Test name
Test status
Simulation time 1047138019 ps
CPU time 14.8 seconds
Started Sep 01 08:43:39 PM UTC 24
Finished Sep 01 08:43:55 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497317693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.497317693
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_csb_read.681030986
Short name T798
Test name
Test status
Simulation time 16924905 ps
CPU time 1.25 seconds
Started Sep 01 08:43:34 PM UTC 24
Finished Sep 01 08:43:36 PM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681030986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.681030986
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.2737383409
Short name T826
Test name
Test status
Simulation time 6094044117 ps
CPU time 15.64 seconds
Started Sep 01 08:43:46 PM UTC 24
Finished Sep 01 08:44:02 PM UTC 24
Peak memory 245152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737383409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2737383409
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.3872746104
Short name T884
Test name
Test status
Simulation time 33863175596 ps
CPU time 85.13 seconds
Started Sep 01 08:43:46 PM UTC 24
Finished Sep 01 08:45:13 PM UTC 24
Peak memory 245712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872746104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3872746104
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1061242888
Short name T895
Test name
Test status
Simulation time 17216383207 ps
CPU time 97.49 seconds
Started Sep 01 08:43:48 PM UTC 24
Finished Sep 01 08:45:27 PM UTC 24
Peak memory 268236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061242888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle.1061242888
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.3166123355
Short name T398
Test name
Test status
Simulation time 3091922270 ps
CPU time 43.21 seconds
Started Sep 01 08:43:40 PM UTC 24
Finished Sep 01 08:44:25 PM UTC 24
Peak memory 245892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166123355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3166123355
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode_ignore_cmds.1525448548
Short name T391
Test name
Test status
Simulation time 11973742333 ps
CPU time 167.14 seconds
Started Sep 01 08:43:43 PM UTC 24
Finished Sep 01 08:46:34 PM UTC 24
Peak memory 262080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525448548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds.1525448548
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_intercept.3121789028
Short name T820
Test name
Test status
Simulation time 1307593978 ps
CPU time 20.56 seconds
Started Sep 01 08:43:38 PM UTC 24
Finished Sep 01 08:44:00 PM UTC 24
Peak memory 235364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121789028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3121789028
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.1345003813
Short name T810
Test name
Test status
Simulation time 1589827879 ps
CPU time 13.77 seconds
Started Sep 01 08:43:38 PM UTC 24
Finished Sep 01 08:43:53 PM UTC 24
Peak memory 235360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345003813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1345003813
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_addr_payload_swap.2128151481
Short name T804
Test name
Test status
Simulation time 1666444865 ps
CPU time 5.86 seconds
Started Sep 01 08:43:37 PM UTC 24
Finished Sep 01 08:43:44 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2128151481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swap.2128151481
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_pass_cmd_filtering.3244608339
Short name T808
Test name
Test status
Simulation time 479121321 ps
CPU time 10.01 seconds
Started Sep 01 08:43:37 PM UTC 24
Finished Sep 01 08:43:48 PM UTC 24
Peak memory 245524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244608339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3244608339
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_read_buffer_direct.2118634731
Short name T813
Test name
Test status
Simulation time 914448953 ps
CPU time 8.16 seconds
Started Sep 01 08:43:45 PM UTC 24
Finished Sep 01 08:43:54 PM UTC 24
Peak memory 231600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2118634731 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_direct.2118634731
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.4126753529
Short name T1000
Test name
Test status
Simulation time 96716210261 ps
CPU time 279.45 seconds
Started Sep 01 08:43:49 PM UTC 24
Finished Sep 01 08:48:32 PM UTC 24
Peak memory 266252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4126753529 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stress_all.4126753529
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_all.747908781
Short name T814
Test name
Test status
Simulation time 10023189728 ps
CPU time 19.85 seconds
Started Sep 01 08:43:34 PM UTC 24
Finished Sep 01 08:43:55 PM UTC 24
Peak memory 228136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=747908781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.747908781
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_read_hw_reg.3091196240
Short name T797
Test name
Test status
Simulation time 37134539 ps
CPU time 1.1 seconds
Started Sep 01 08:43:34 PM UTC 24
Finished Sep 01 08:43:36 PM UTC 24
Peak memory 215620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091196240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3091196240
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_rw.686623251
Short name T801
Test name
Test status
Simulation time 115436201 ps
CPU time 1.44 seconds
Started Sep 01 08:43:36 PM UTC 24
Finished Sep 01 08:43:39 PM UTC 24
Peak memory 215984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686623251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.686623251
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_tpm_sts_read.1116256495
Short name T800
Test name
Test status
Simulation time 97417732 ps
CPU time 1.42 seconds
Started Sep 01 08:43:36 PM UTC 24
Finished Sep 01 08:43:39 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116256495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1116256495
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/39.spi_device_upload.1501828785
Short name T809
Test name
Test status
Simulation time 9637484441 ps
CPU time 9.62 seconds
Started Sep 01 08:43:39 PM UTC 24
Finished Sep 01 08:43:50 PM UTC 24
Peak memory 235420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501828785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.1501828785
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/39.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_alert_test.1569529684
Short name T427
Test name
Test status
Simulation time 68892459 ps
CPU time 1.1 seconds
Started Sep 01 08:34:33 PM UTC 24
Finished Sep 01 08:34:36 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569529684 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1569529684
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_cfg_cmd.82775972
Short name T108
Test name
Test status
Simulation time 877986772 ps
CPU time 5.37 seconds
Started Sep 01 08:34:26 PM UTC 24
Finished Sep 01 08:34:32 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82775972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.82775972
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_csb_read.3429568122
Short name T425
Test name
Test status
Simulation time 23753838 ps
CPU time 1.15 seconds
Started Sep 01 08:34:20 PM UTC 24
Finished Sep 01 08:34:22 PM UTC 24
Peak memory 215740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429568122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3429568122
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.1941047228
Short name T51
Test name
Test status
Simulation time 1856065803 ps
CPU time 15.25 seconds
Started Sep 01 08:34:27 PM UTC 24
Finished Sep 01 08:34:44 PM UTC 24
Peak memory 245600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941047228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.1941047228
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.4174208820
Short name T250
Test name
Test status
Simulation time 22530833970 ps
CPU time 237.47 seconds
Started Sep 01 08:34:29 PM UTC 24
Finished Sep 01 08:38:30 PM UTC 24
Peak memory 261948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174208820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.4174208820
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode.322939033
Short name T55
Test name
Test status
Simulation time 70291627 ps
CPU time 5.67 seconds
Started Sep 01 08:34:26 PM UTC 24
Finished Sep 01 08:34:32 PM UTC 24
Peak memory 245616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322939033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.322939033
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_mode_ignore_cmds.3974389058
Short name T102
Test name
Test status
Simulation time 2556556251 ps
CPU time 36.82 seconds
Started Sep 01 08:34:26 PM UTC 24
Finished Sep 01 08:35:04 PM UTC 24
Peak memory 262116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974389058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.3974389058
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_intercept.1712217881
Short name T128
Test name
Test status
Simulation time 2379424730 ps
CPU time 24.38 seconds
Started Sep 01 08:34:23 PM UTC 24
Finished Sep 01 08:34:49 PM UTC 24
Peak memory 235644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712217881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1712217881
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_mem_parity.3249113407
Short name T426
Test name
Test status
Simulation time 156107339 ps
CPU time 1.49 seconds
Started Sep 01 08:34:20 PM UTC 24
Finished Sep 01 08:34:23 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249113407 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mem_parity.3249113407
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_addr_payload_swap.2718323562
Short name T62
Test name
Test status
Simulation time 1816174726 ps
CPU time 8.15 seconds
Started Sep 01 08:34:23 PM UTC 24
Finished Sep 01 08:34:33 PM UTC 24
Peak memory 251808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718323562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.2718323562
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_pass_cmd_filtering.160120520
Short name T113
Test name
Test status
Simulation time 102402813 ps
CPU time 2.72 seconds
Started Sep 01 08:34:22 PM UTC 24
Finished Sep 01 08:34:26 PM UTC 24
Peak memory 234052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160120520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.160120520
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_read_buffer_direct.2087833987
Short name T82
Test name
Test status
Simulation time 7473133170 ps
CPU time 14.43 seconds
Started Sep 01 08:34:27 PM UTC 24
Finished Sep 01 08:34:43 PM UTC 24
Peak memory 231792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087833987 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direct.2087833987
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_sec_cm.1483261745
Short name T33
Test name
Test status
Simulation time 152518336 ps
CPU time 1.35 seconds
Started Sep 01 08:34:33 PM UTC 24
Finished Sep 01 08:34:36 PM UTC 24
Peak memory 257736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_R
ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483261745 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1483261745
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_sec_cm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_all.2894962431
Short name T84
Test name
Test status
Simulation time 2892097848 ps
CPU time 8.76 seconds
Started Sep 01 08:34:22 PM UTC 24
Finished Sep 01 08:34:32 PM UTC 24
Peak memory 232268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894962431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2894962431
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_read_hw_reg.2762634821
Short name T106
Test name
Test status
Simulation time 3277925389 ps
CPU time 4.11 seconds
Started Sep 01 08:34:21 PM UTC 24
Finished Sep 01 08:34:26 PM UTC 24
Peak memory 227920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762634821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2762634821
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_rw.3366228011
Short name T83
Test name
Test status
Simulation time 105646942 ps
CPU time 4.68 seconds
Started Sep 01 08:34:22 PM UTC 24
Finished Sep 01 08:34:28 PM UTC 24
Peak memory 227764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366228011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.3366228011
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_tpm_sts_read.3597823458
Short name T86
Test name
Test status
Simulation time 424077290 ps
CPU time 1.2 seconds
Started Sep 01 08:34:22 PM UTC 24
Finished Sep 01 08:34:25 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597823458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.3597823458
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/4.spi_device_upload.193222941
Short name T79
Test name
Test status
Simulation time 6989695206 ps
CPU time 15.84 seconds
Started Sep 01 08:34:24 PM UTC 24
Finished Sep 01 08:34:41 PM UTC 24
Peak memory 235656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193222941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.193222941
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/4.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.2088543014
Short name T831
Test name
Test status
Simulation time 14266619 ps
CPU time 1.13 seconds
Started Sep 01 08:44:04 PM UTC 24
Finished Sep 01 08:44:07 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088543014 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.2088543014
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_cfg_cmd.1660541402
Short name T229
Test name
Test status
Simulation time 4597316751 ps
CPU time 33.75 seconds
Started Sep 01 08:44:00 PM UTC 24
Finished Sep 01 08:44:35 PM UTC 24
Peak memory 235620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660541402 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1660541402
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_csb_read.284695929
Short name T818
Test name
Test status
Simulation time 47103301 ps
CPU time 1.16 seconds
Started Sep 01 08:43:54 PM UTC 24
Finished Sep 01 08:43:56 PM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284695929 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.284695929
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.3109349213
Short name T968
Test name
Test status
Simulation time 336110827954 ps
CPU time 166.81 seconds
Started Sep 01 08:44:02 PM UTC 24
Finished Sep 01 08:46:52 PM UTC 24
Peak memory 262080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109349213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.3109349213
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.3995350872
Short name T1008
Test name
Test status
Simulation time 147662533890 ps
CPU time 322.91 seconds
Started Sep 01 08:44:03 PM UTC 24
Finished Sep 01 08:49:31 PM UTC 24
Peak memory 262084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995350872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idle.3995350872
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.3552904293
Short name T830
Test name
Test status
Simulation time 148106664 ps
CPU time 3.67 seconds
Started Sep 01 08:44:01 PM UTC 24
Finished Sep 01 08:44:06 PM UTC 24
Peak memory 245576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552904293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3552904293
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.1171071685
Short name T867
Test name
Test status
Simulation time 15270184508 ps
CPU time 43.84 seconds
Started Sep 01 08:44:01 PM UTC 24
Finished Sep 01 08:44:46 PM UTC 24
Peak memory 262108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171071685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.1171071685
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_intercept.3448723734
Short name T828
Test name
Test status
Simulation time 1434768165 ps
CPU time 6.21 seconds
Started Sep 01 08:43:57 PM UTC 24
Finished Sep 01 08:44:04 PM UTC 24
Peak memory 245608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448723734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.3448723734
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.185466921
Short name T928
Test name
Test status
Simulation time 55044111148 ps
CPU time 126.69 seconds
Started Sep 01 08:43:58 PM UTC 24
Finished Sep 01 08:46:07 PM UTC 24
Peak memory 264324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185466921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.185466921
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.4002560472
Short name T824
Test name
Test status
Simulation time 32170675 ps
CPU time 3.2 seconds
Started Sep 01 08:43:57 PM UTC 24
Finished Sep 01 08:44:01 PM UTC 24
Peak memory 245228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002560472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap.4002560472
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2534390879
Short name T827
Test name
Test status
Simulation time 426140950 ps
CPU time 6.26 seconds
Started Sep 01 08:43:55 PM UTC 24
Finished Sep 01 08:44:03 PM UTC 24
Peak memory 245804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534390879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2534390879
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_read_buffer_direct.3317394868
Short name T844
Test name
Test status
Simulation time 6842858863 ps
CPU time 23.03 seconds
Started Sep 01 08:44:01 PM UTC 24
Finished Sep 01 08:44:25 PM UTC 24
Peak memory 231732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317394868 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_direct.3317394868
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.1022527722
Short name T1013
Test name
Test status
Simulation time 31599753048 ps
CPU time 462.3 seconds
Started Sep 01 08:44:03 PM UTC 24
Finished Sep 01 08:51:52 PM UTC 24
Peak memory 296972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022527722 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stress_all.1022527722
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.3724791351
Short name T823
Test name
Test status
Simulation time 530095228 ps
CPU time 5.58 seconds
Started Sep 01 08:43:54 PM UTC 24
Finished Sep 01 08:44:01 PM UTC 24
Peak memory 227980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724791351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3724791351
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.430074688
Short name T825
Test name
Test status
Simulation time 2013576564 ps
CPU time 6.89 seconds
Started Sep 01 08:43:54 PM UTC 24
Finished Sep 01 08:44:02 PM UTC 24
Peak memory 227696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430074688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.430074688
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_rw.152875054
Short name T821
Test name
Test status
Simulation time 176233442 ps
CPU time 3.4 seconds
Started Sep 01 08:43:55 PM UTC 24
Finished Sep 01 08:44:00 PM UTC 24
Peak memory 227976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152875054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.152875054
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_sts_read.1547616414
Short name T817
Test name
Test status
Simulation time 20243718 ps
CPU time 1.09 seconds
Started Sep 01 08:43:54 PM UTC 24
Finished Sep 01 08:43:56 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1547616414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1547616414
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/40.spi_device_upload.1432724211
Short name T838
Test name
Test status
Simulation time 10028116135 ps
CPU time 16.16 seconds
Started Sep 01 08:43:58 PM UTC 24
Finished Sep 01 08:44:15 PM UTC 24
Peak memory 245696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432724211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1432724211
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/40.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.3553659615
Short name T846
Test name
Test status
Simulation time 32409691 ps
CPU time 1.09 seconds
Started Sep 01 08:44:25 PM UTC 24
Finished Sep 01 08:44:27 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553659615 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.3553659615
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.2776928771
Short name T842
Test name
Test status
Simulation time 932191179 ps
CPU time 5.87 seconds
Started Sep 01 08:44:13 PM UTC 24
Finished Sep 01 08:44:21 PM UTC 24
Peak memory 235336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776928771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2776928771
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.2701364884
Short name T833
Test name
Test status
Simulation time 44422867 ps
CPU time 1.18 seconds
Started Sep 01 08:44:05 PM UTC 24
Finished Sep 01 08:44:08 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701364884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2701364884
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.816917401
Short name T381
Test name
Test status
Simulation time 21957936890 ps
CPU time 217.5 seconds
Started Sep 01 08:44:19 PM UTC 24
Finished Sep 01 08:48:00 PM UTC 24
Peak memory 262224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816917401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.816917401
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.3503798075
Short name T92
Test name
Test status
Simulation time 13265660722 ps
CPU time 154.73 seconds
Started Sep 01 08:44:19 PM UTC 24
Finished Sep 01 08:46:56 PM UTC 24
Peak memory 284688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503798075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3503798075
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.851178711
Short name T961
Test name
Test status
Simulation time 190377973060 ps
CPU time 141.33 seconds
Started Sep 01 08:44:20 PM UTC 24
Finished Sep 01 08:46:43 PM UTC 24
Peak memory 268424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=851178711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idle.851178711
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.1082856526
Short name T874
Test name
Test status
Simulation time 3584640907 ps
CPU time 49.82 seconds
Started Sep 01 08:44:14 PM UTC 24
Finished Sep 01 08:45:06 PM UTC 24
Peak memory 262340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082856526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1082856526
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.2654113913
Short name T903
Test name
Test status
Simulation time 53408151453 ps
CPU time 78.97 seconds
Started Sep 01 08:44:16 PM UTC 24
Finished Sep 01 08:45:37 PM UTC 24
Peak memory 264136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654113913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds.2654113913
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.1727042140
Short name T837
Test name
Test status
Simulation time 114725773 ps
CPU time 3.14 seconds
Started Sep 01 08:44:09 PM UTC 24
Finished Sep 01 08:44:13 PM UTC 24
Peak memory 245260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727042140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.1727042140
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.944091440
Short name T908
Test name
Test status
Simulation time 9947279057 ps
CPU time 92.33 seconds
Started Sep 01 08:44:10 PM UTC 24
Finished Sep 01 08:45:44 PM UTC 24
Peak memory 262076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944091440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.944091440
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.4243569691
Short name T855
Test name
Test status
Simulation time 13233145814 ps
CPU time 25.11 seconds
Started Sep 01 08:44:09 PM UTC 24
Finished Sep 01 08:44:35 PM UTC 24
Peak memory 245776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243569691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap.4243569691
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.170445463
Short name T848
Test name
Test status
Simulation time 10229644895 ps
CPU time 18.83 seconds
Started Sep 01 08:44:08 PM UTC 24
Finished Sep 01 08:44:28 PM UTC 24
Peak memory 251856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170445463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.170445463
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.3400757976
Short name T843
Test name
Test status
Simulation time 398405886 ps
CPU time 6.59 seconds
Started Sep 01 08:44:16 PM UTC 24
Finished Sep 01 08:44:24 PM UTC 24
Peak memory 231664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400757976 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_direct.3400757976
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.2969660530
Short name T383
Test name
Test status
Simulation time 62111209738 ps
CPU time 245.4 seconds
Started Sep 01 08:44:22 PM UTC 24
Finished Sep 01 08:48:31 PM UTC 24
Peak memory 284808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969660530 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stress_all.2969660530
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.2329240057
Short name T847
Test name
Test status
Simulation time 8408252814 ps
CPU time 19.07 seconds
Started Sep 01 08:44:07 PM UTC 24
Finished Sep 01 08:44:27 PM UTC 24
Peak memory 227892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329240057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2329240057
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.2970649619
Short name T832
Test name
Test status
Simulation time 10565146 ps
CPU time 1.09 seconds
Started Sep 01 08:44:06 PM UTC 24
Finished Sep 01 08:44:08 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970649619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2970649619
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.1015332787
Short name T835
Test name
Test status
Simulation time 87139821 ps
CPU time 1.79 seconds
Started Sep 01 08:44:08 PM UTC 24
Finished Sep 01 08:44:11 PM UTC 24
Peak memory 228076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015332787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1015332787
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.2508090687
Short name T834
Test name
Test status
Simulation time 78277386 ps
CPU time 1.09 seconds
Started Sep 01 08:44:07 PM UTC 24
Finished Sep 01 08:44:09 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508090687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2508090687
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.984911197
Short name T839
Test name
Test status
Simulation time 180351473 ps
CPU time 4.94 seconds
Started Sep 01 08:44:11 PM UTC 24
Finished Sep 01 08:44:17 PM UTC 24
Peak memory 235324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984911197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.984911197
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/41.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.2818678852
Short name T859
Test name
Test status
Simulation time 22796795 ps
CPU time 1.13 seconds
Started Sep 01 08:44:37 PM UTC 24
Finished Sep 01 08:44:39 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818678852 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.2818678852
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.3869597108
Short name T862
Test name
Test status
Simulation time 774189133 ps
CPU time 9.03 seconds
Started Sep 01 08:44:31 PM UTC 24
Finished Sep 01 08:44:41 PM UTC 24
Peak memory 235528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869597108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.3869597108
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.2639087368
Short name T849
Test name
Test status
Simulation time 26716783 ps
CPU time 1.14 seconds
Started Sep 01 08:44:26 PM UTC 24
Finished Sep 01 08:44:28 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639087368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2639087368
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.1527260911
Short name T261
Test name
Test status
Simulation time 9788230067 ps
CPU time 96.13 seconds
Started Sep 01 08:44:36 PM UTC 24
Finished Sep 01 08:46:14 PM UTC 24
Peak memory 268232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527260911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1527260911
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.304601648
Short name T387
Test name
Test status
Simulation time 31416689736 ps
CPU time 109.92 seconds
Started Sep 01 08:44:36 PM UTC 24
Finished Sep 01 08:46:28 PM UTC 24
Peak memory 266444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304601648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.304601648
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.2904927868
Short name T998
Test name
Test status
Simulation time 109151147541 ps
CPU time 212.07 seconds
Started Sep 01 08:44:36 PM UTC 24
Finished Sep 01 08:48:12 PM UTC 24
Peak memory 262144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904927868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idle.2904927868
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.1954765497
Short name T858
Test name
Test status
Simulation time 2133347411 ps
CPU time 5.86 seconds
Started Sep 01 08:44:32 PM UTC 24
Finished Sep 01 08:44:39 PM UTC 24
Peak memory 251720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1954765497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1954765497
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.2471116777
Short name T379
Test name
Test status
Simulation time 281077205376 ps
CPU time 720.16 seconds
Started Sep 01 08:44:32 PM UTC 24
Finished Sep 01 08:56:41 PM UTC 24
Peak memory 278688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471116777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds.2471116777
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.3379722812
Short name T856
Test name
Test status
Simulation time 152737687 ps
CPU time 6.13 seconds
Started Sep 01 08:44:29 PM UTC 24
Finished Sep 01 08:44:37 PM UTC 24
Peak memory 245860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379722812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.3379722812
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.3853531710
Short name T861
Test name
Test status
Simulation time 1315127515 ps
CPU time 8.78 seconds
Started Sep 01 08:44:31 PM UTC 24
Finished Sep 01 08:44:40 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3853531710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.3853531710
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.1237721436
Short name T854
Test name
Test status
Simulation time 183042103 ps
CPU time 4.88 seconds
Started Sep 01 08:44:29 PM UTC 24
Finished Sep 01 08:44:35 PM UTC 24
Peak memory 242172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237721436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swap.1237721436
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.2383510829
Short name T857
Test name
Test status
Simulation time 693535236 ps
CPU time 6.51 seconds
Started Sep 01 08:44:29 PM UTC 24
Finished Sep 01 08:44:37 PM UTC 24
Peak memory 245584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383510829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2383510829
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.848118226
Short name T868
Test name
Test status
Simulation time 1127471320 ps
CPU time 13.9 seconds
Started Sep 01 08:44:35 PM UTC 24
Finished Sep 01 08:44:50 PM UTC 24
Peak memory 233712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848118226 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_direct.848118226
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.1437532109
Short name T1015
Test name
Test status
Simulation time 116931767874 ps
CPU time 537.07 seconds
Started Sep 01 08:44:37 PM UTC 24
Finished Sep 01 08:53:41 PM UTC 24
Peak memory 284684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437532109 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stress_all.1437532109
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.3490009019
Short name T877
Test name
Test status
Simulation time 4471711074 ps
CPU time 38.98 seconds
Started Sep 01 08:44:27 PM UTC 24
Finished Sep 01 08:45:08 PM UTC 24
Peak memory 227952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490009019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3490009019
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.955038780
Short name T853
Test name
Test status
Simulation time 2214274039 ps
CPU time 3.51 seconds
Started Sep 01 08:44:26 PM UTC 24
Finished Sep 01 08:44:31 PM UTC 24
Peak memory 217352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955038780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.955038780
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.283950278
Short name T851
Test name
Test status
Simulation time 29391524 ps
CPU time 0.83 seconds
Started Sep 01 08:44:28 PM UTC 24
Finished Sep 01 08:44:30 PM UTC 24
Peak memory 215864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283950278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.283950278
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.3050036654
Short name T852
Test name
Test status
Simulation time 13334696 ps
CPU time 1.12 seconds
Started Sep 01 08:44:28 PM UTC 24
Finished Sep 01 08:44:30 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050036654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.3050036654
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.3618505335
Short name T871
Test name
Test status
Simulation time 4364720916 ps
CPU time 27.88 seconds
Started Sep 01 08:44:31 PM UTC 24
Finished Sep 01 08:45:00 PM UTC 24
Peak memory 245980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3618505335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.3618505335
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/42.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.2097104075
Short name T879
Test name
Test status
Simulation time 12163161 ps
CPU time 1.09 seconds
Started Sep 01 08:45:07 PM UTC 24
Finished Sep 01 08:45:09 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097104075 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.2097104075
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.3227200701
Short name T873
Test name
Test status
Simulation time 3109889938 ps
CPU time 11.89 seconds
Started Sep 01 08:44:50 PM UTC 24
Finished Sep 01 08:45:03 PM UTC 24
Peak memory 235596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227200701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.3227200701
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.3490153641
Short name T863
Test name
Test status
Simulation time 24916968 ps
CPU time 1.15 seconds
Started Sep 01 08:44:39 PM UTC 24
Finished Sep 01 08:44:42 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490153641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3490153641
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.331486256
Short name T917
Test name
Test status
Simulation time 18741999890 ps
CPU time 50.39 seconds
Started Sep 01 08:45:00 PM UTC 24
Finished Sep 01 08:45:52 PM UTC 24
Peak memory 251840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331486256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.331486256
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.2132615208
Short name T996
Test name
Test status
Simulation time 30997454439 ps
CPU time 174.54 seconds
Started Sep 01 08:45:04 PM UTC 24
Finished Sep 01 08:48:01 PM UTC 24
Peak memory 268364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132615208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.2132615208
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.4145696191
Short name T992
Test name
Test status
Simulation time 103387700900 ps
CPU time 167.58 seconds
Started Sep 01 08:45:04 PM UTC 24
Finished Sep 01 08:47:54 PM UTC 24
Peak memory 278532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145696191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idle.4145696191
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.1138908350
Short name T878
Test name
Test status
Simulation time 4422659795 ps
CPU time 15.74 seconds
Started Sep 01 08:44:51 PM UTC 24
Finished Sep 01 08:45:08 PM UTC 24
Peak memory 235464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138908350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1138908350
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.1931581833
Short name T897
Test name
Test status
Simulation time 14392325439 ps
CPU time 34.48 seconds
Started Sep 01 08:44:52 PM UTC 24
Finished Sep 01 08:45:28 PM UTC 24
Peak memory 251848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931581833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds.1931581833
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.136611554
Short name T869
Test name
Test status
Simulation time 144914165 ps
CPU time 5.73 seconds
Started Sep 01 08:44:45 PM UTC 24
Finished Sep 01 08:44:52 PM UTC 24
Peak memory 235364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136611554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.136611554
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.687852871
Short name T984
Test name
Test status
Simulation time 88179044832 ps
CPU time 145.21 seconds
Started Sep 01 08:44:47 PM UTC 24
Finished Sep 01 08:47:15 PM UTC 24
Peak memory 245704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687852871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.687852871
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.2517285047
Short name T380
Test name
Test status
Simulation time 148835551276 ps
CPU time 25.37 seconds
Started Sep 01 08:44:45 PM UTC 24
Finished Sep 01 08:45:11 PM UTC 24
Peak memory 245648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517285047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap.2517285047
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.3393191818
Short name T898
Test name
Test status
Simulation time 36319360541 ps
CPU time 43.95 seconds
Started Sep 01 08:44:43 PM UTC 24
Finished Sep 01 08:45:28 PM UTC 24
Peak memory 245932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393191818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.3393191818
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.4146796972
Short name T876
Test name
Test status
Simulation time 200465191 ps
CPU time 6.94 seconds
Started Sep 01 08:44:58 PM UTC 24
Finished Sep 01 08:45:06 PM UTC 24
Peak memory 231600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146796972 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_direct.4146796972
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.4141303108
Short name T1019
Test name
Test status
Simulation time 63572832592 ps
CPU time 745.65 seconds
Started Sep 01 08:45:07 PM UTC 24
Finished Sep 01 08:57:41 PM UTC 24
Peak memory 294924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141303108 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stress_all.4141303108
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.3159632750
Short name T875
Test name
Test status
Simulation time 2211398703 ps
CPU time 24.52 seconds
Started Sep 01 08:44:41 PM UTC 24
Finished Sep 01 08:45:06 PM UTC 24
Peak memory 227980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3159632750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3159632750
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.2060436579
Short name T880
Test name
Test status
Simulation time 4980861282 ps
CPU time 28.04 seconds
Started Sep 01 08:44:40 PM UTC 24
Finished Sep 01 08:45:10 PM UTC 24
Peak memory 228176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060436579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2060436579
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.3811397899
Short name T864
Test name
Test status
Simulation time 134752730 ps
CPU time 1.13 seconds
Started Sep 01 08:44:42 PM UTC 24
Finished Sep 01 08:44:44 PM UTC 24
Peak memory 215980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3811397899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3811397899
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.3422645835
Short name T865
Test name
Test status
Simulation time 31159283 ps
CPU time 1.2 seconds
Started Sep 01 08:44:42 PM UTC 24
Finished Sep 01 08:44:44 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3422645835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3422645835
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.3469901081
Short name T870
Test name
Test status
Simulation time 1926813310 ps
CPU time 9.86 seconds
Started Sep 01 08:44:47 PM UTC 24
Finished Sep 01 08:44:58 PM UTC 24
Peak memory 235324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469901081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3469901081
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/43.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.1251032152
Short name T892
Test name
Test status
Simulation time 20594666 ps
CPU time 1.18 seconds
Started Sep 01 08:45:23 PM UTC 24
Finished Sep 01 08:45:26 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251032152 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.1251032152
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.477093279
Short name T911
Test name
Test status
Simulation time 5159973392 ps
CPU time 33.12 seconds
Started Sep 01 08:45:14 PM UTC 24
Finished Sep 01 08:45:48 PM UTC 24
Peak memory 245924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477093279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.477093279
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.361225633
Short name T882
Test name
Test status
Simulation time 24534210 ps
CPU time 1.19 seconds
Started Sep 01 08:45:08 PM UTC 24
Finished Sep 01 08:45:10 PM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361225633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.361225633
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.2588744448
Short name T925
Test name
Test status
Simulation time 47681656524 ps
CPU time 40.44 seconds
Started Sep 01 08:45:18 PM UTC 24
Finished Sep 01 08:46:00 PM UTC 24
Peak memory 245764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588744448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2588744448
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.890752848
Short name T1021
Test name
Test status
Simulation time 301139601770 ps
CPU time 740.06 seconds
Started Sep 01 08:45:19 PM UTC 24
Finished Sep 01 08:57:49 PM UTC 24
Peak memory 278532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890752848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.890752848
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.409313187
Short name T999
Test name
Test status
Simulation time 16770363070 ps
CPU time 180.81 seconds
Started Sep 01 08:45:20 PM UTC 24
Finished Sep 01 08:48:24 PM UTC 24
Peak memory 264220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=409313187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle.409313187
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.4239108149
Short name T891
Test name
Test status
Simulation time 355162018 ps
CPU time 8.63 seconds
Started Sep 01 08:45:15 PM UTC 24
Finished Sep 01 08:45:25 PM UTC 24
Peak memory 235524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239108149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4239108149
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.2292889076
Short name T977
Test name
Test status
Simulation time 9449449044 ps
CPU time 108.07 seconds
Started Sep 01 08:45:15 PM UTC 24
Finished Sep 01 08:47:05 PM UTC 24
Peak memory 262088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2292889076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmds.2292889076
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.4158376888
Short name T890
Test name
Test status
Simulation time 322093902 ps
CPU time 8.53 seconds
Started Sep 01 08:45:12 PM UTC 24
Finished Sep 01 08:45:22 PM UTC 24
Peak memory 235620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158376888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4158376888
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.195232823
Short name T888
Test name
Test status
Simulation time 889686079 ps
CPU time 4.45 seconds
Started Sep 01 08:45:12 PM UTC 24
Finished Sep 01 08:45:18 PM UTC 24
Peak memory 235260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195232823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.195232823
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.2012792894
Short name T887
Test name
Test status
Simulation time 174796294 ps
CPU time 4.86 seconds
Started Sep 01 08:45:11 PM UTC 24
Finished Sep 01 08:45:17 PM UTC 24
Peak memory 245548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012792894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.2012792894
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.2565637824
Short name T906
Test name
Test status
Simulation time 29583531780 ps
CPU time 28.84 seconds
Started Sep 01 08:45:11 PM UTC 24
Finished Sep 01 08:45:41 PM UTC 24
Peak memory 249776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565637824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.2565637824
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.2558821944
Short name T894
Test name
Test status
Simulation time 915030551 ps
CPU time 9.76 seconds
Started Sep 01 08:45:16 PM UTC 24
Finished Sep 01 08:45:27 PM UTC 24
Peak memory 233712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558821944 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_direct.2558821944
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.2304584247
Short name T997
Test name
Test status
Simulation time 9780807278 ps
CPU time 167.47 seconds
Started Sep 01 08:45:20 PM UTC 24
Finished Sep 01 08:48:11 PM UTC 24
Peak memory 276684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304584247 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stress_all.2304584247
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.912677544
Short name T886
Test name
Test status
Simulation time 347080184 ps
CPU time 4.5 seconds
Started Sep 01 08:45:09 PM UTC 24
Finished Sep 01 08:45:15 PM UTC 24
Peak memory 227764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912677544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.912677544
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.3737174450
Short name T881
Test name
Test status
Simulation time 21230207 ps
CPU time 1.08 seconds
Started Sep 01 08:45:08 PM UTC 24
Finished Sep 01 08:45:10 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3737174450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.3737174450
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.2400683699
Short name T889
Test name
Test status
Simulation time 412454128 ps
CPU time 7.45 seconds
Started Sep 01 08:45:11 PM UTC 24
Finished Sep 01 08:45:20 PM UTC 24
Peak memory 227820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400683699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2400683699
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.1229633711
Short name T883
Test name
Test status
Simulation time 56607933 ps
CPU time 1.34 seconds
Started Sep 01 08:45:10 PM UTC 24
Finished Sep 01 08:45:12 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229633711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1229633711
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.871995028
Short name T909
Test name
Test status
Simulation time 18035288810 ps
CPU time 31.37 seconds
Started Sep 01 08:45:14 PM UTC 24
Finished Sep 01 08:45:46 PM UTC 24
Peak memory 251808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871995028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.871995028
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/44.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.210045956
Short name T912
Test name
Test status
Simulation time 29000256 ps
CPU time 1.15 seconds
Started Sep 01 08:45:46 PM UTC 24
Finished Sep 01 08:45:48 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210045956 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.210045956
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.21260715
Short name T914
Test name
Test status
Simulation time 1117562107 ps
CPU time 15.54 seconds
Started Sep 01 08:45:33 PM UTC 24
Finished Sep 01 08:45:50 PM UTC 24
Peak memory 245584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21260715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.21260715
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.1845697132
Short name T896
Test name
Test status
Simulation time 18030038 ps
CPU time 1.19 seconds
Started Sep 01 08:45:25 PM UTC 24
Finished Sep 01 08:45:28 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845697132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1845697132
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.3389523954
Short name T365
Test name
Test status
Simulation time 48252710789 ps
CPU time 53.93 seconds
Started Sep 01 08:45:41 PM UTC 24
Finished Sep 01 08:46:36 PM UTC 24
Peak memory 249800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3389523954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3389523954
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.3972090714
Short name T979
Test name
Test status
Simulation time 21227797760 ps
CPU time 80.57 seconds
Started Sep 01 08:45:43 PM UTC 24
Finished Sep 01 08:47:06 PM UTC 24
Peak memory 264204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3972090714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.3972090714
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.4035445170
Short name T1020
Test name
Test status
Simulation time 95306775410 ps
CPU time 713.3 seconds
Started Sep 01 08:45:43 PM UTC 24
Finished Sep 01 08:57:46 PM UTC 24
Peak memory 278556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035445170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle.4035445170
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.1099773861
Short name T904
Test name
Test status
Simulation time 142592950 ps
CPU time 2.23 seconds
Started Sep 01 08:45:35 PM UTC 24
Finished Sep 01 08:45:39 PM UTC 24
Peak memory 245600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099773861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.1099773861
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.368503142
Short name T366
Test name
Test status
Simulation time 30265601302 ps
CPU time 124.34 seconds
Started Sep 01 08:45:38 PM UTC 24
Finished Sep 01 08:47:46 PM UTC 24
Peak memory 278464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=368503142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds.368503142
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.1898595946
Short name T919
Test name
Test status
Simulation time 4180787423 ps
CPU time 23.83 seconds
Started Sep 01 08:45:29 PM UTC 24
Finished Sep 01 08:45:54 PM UTC 24
Peak memory 235608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898595946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1898595946
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.4139261710
Short name T930
Test name
Test status
Simulation time 12614062664 ps
CPU time 37.66 seconds
Started Sep 01 08:45:31 PM UTC 24
Finished Sep 01 08:46:10 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139261710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4139261710
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.4259693576
Short name T915
Test name
Test status
Simulation time 3304402356 ps
CPU time 20.85 seconds
Started Sep 01 08:45:29 PM UTC 24
Finished Sep 01 08:45:51 PM UTC 24
Peak memory 245928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259693576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.4259693576
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.1773076027
Short name T907
Test name
Test status
Simulation time 1571411156 ps
CPU time 12.14 seconds
Started Sep 01 08:45:29 PM UTC 24
Finished Sep 01 08:45:42 PM UTC 24
Peak memory 251920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773076027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1773076027
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.3844571566
Short name T910
Test name
Test status
Simulation time 2468913944 ps
CPU time 5.6 seconds
Started Sep 01 08:45:39 PM UTC 24
Finished Sep 01 08:45:46 PM UTC 24
Peak memory 234528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844571566 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_direct.3844571566
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.3957515345
Short name T375
Test name
Test status
Simulation time 11804630632 ps
CPU time 220.14 seconds
Started Sep 01 08:45:45 PM UTC 24
Finished Sep 01 08:49:29 PM UTC 24
Peak memory 280612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957515345 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stress_all.3957515345
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.1152393338
Short name T922
Test name
Test status
Simulation time 1794059191 ps
CPU time 29.51 seconds
Started Sep 01 08:45:28 PM UTC 24
Finished Sep 01 08:45:59 PM UTC 24
Peak memory 227888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152393338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.1152393338
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.158271251
Short name T901
Test name
Test status
Simulation time 818265940 ps
CPU time 4.37 seconds
Started Sep 01 08:45:26 PM UTC 24
Finished Sep 01 08:45:32 PM UTC 24
Peak memory 217244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158271251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.158271251
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.597228958
Short name T902
Test name
Test status
Simulation time 181314389 ps
CPU time 4.3 seconds
Started Sep 01 08:45:29 PM UTC 24
Finished Sep 01 08:45:34 PM UTC 24
Peak memory 227692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=597228958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.597228958
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.2834131392
Short name T900
Test name
Test status
Simulation time 31561654 ps
CPU time 1.09 seconds
Started Sep 01 08:45:28 PM UTC 24
Finished Sep 01 08:45:30 PM UTC 24
Peak memory 215804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834131392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.2834131392
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.641803765
Short name T905
Test name
Test status
Simulation time 832702554 ps
CPU time 7.47 seconds
Started Sep 01 08:45:31 PM UTC 24
Finished Sep 01 08:45:40 PM UTC 24
Peak memory 245540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641803765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.641803765
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/45.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.1538798838
Short name T927
Test name
Test status
Simulation time 14626562 ps
CPU time 1.12 seconds
Started Sep 01 08:46:03 PM UTC 24
Finished Sep 01 08:46:06 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538798838 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.1538798838
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.663225748
Short name T923
Test name
Test status
Simulation time 82340057 ps
CPU time 3.12 seconds
Started Sep 01 08:45:55 PM UTC 24
Finished Sep 01 08:45:59 PM UTC 24
Peak memory 235328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663225748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.663225748
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.665589379
Short name T913
Test name
Test status
Simulation time 24901258 ps
CPU time 1.2 seconds
Started Sep 01 08:45:47 PM UTC 24
Finished Sep 01 08:45:49 PM UTC 24
Peak memory 215672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=665589379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.665589379
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.942473030
Short name T980
Test name
Test status
Simulation time 6720467465 ps
CPU time 64.13 seconds
Started Sep 01 08:46:00 PM UTC 24
Finished Sep 01 08:47:06 PM UTC 24
Peak memory 268260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942473030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.942473030
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.2815041383
Short name T388
Test name
Test status
Simulation time 31731709212 ps
CPU time 420.74 seconds
Started Sep 01 08:46:00 PM UTC 24
Finished Sep 01 08:53:06 PM UTC 24
Peak memory 276516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815041383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.2815041383
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.3210514756
Short name T1016
Test name
Test status
Simulation time 39499900045 ps
CPU time 464.84 seconds
Started Sep 01 08:46:00 PM UTC 24
Finished Sep 01 08:53:52 PM UTC 24
Peak memory 262144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3210514756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle.3210514756
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.3577138324
Short name T938
Test name
Test status
Simulation time 1831851658 ps
CPU time 25.58 seconds
Started Sep 01 08:45:55 PM UTC 24
Finished Sep 01 08:46:22 PM UTC 24
Peak memory 249668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577138324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3577138324
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.3334334010
Short name T936
Test name
Test status
Simulation time 2937536503 ps
CPU time 21.1 seconds
Started Sep 01 08:45:57 PM UTC 24
Finished Sep 01 08:46:19 PM UTC 24
Peak memory 235400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334334010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmds.3334334010
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.2353592349
Short name T937
Test name
Test status
Simulation time 2587637832 ps
CPU time 26.21 seconds
Started Sep 01 08:45:53 PM UTC 24
Finished Sep 01 08:46:20 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353592349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2353592349
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.2373810156
Short name T988
Test name
Test status
Simulation time 13264754080 ps
CPU time 92.66 seconds
Started Sep 01 08:45:54 PM UTC 24
Finished Sep 01 08:47:28 PM UTC 24
Peak memory 245636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2373810156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2373810156
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.880482539
Short name T946
Test name
Test status
Simulation time 7529013448 ps
CPU time 38.94 seconds
Started Sep 01 08:45:51 PM UTC 24
Finished Sep 01 08:46:32 PM UTC 24
Peak memory 245644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=880482539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swap.880482539
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.2400558569
Short name T926
Test name
Test status
Simulation time 8365160716 ps
CPU time 10.07 seconds
Started Sep 01 08:45:51 PM UTC 24
Finished Sep 01 08:46:03 PM UTC 24
Peak memory 235536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400558569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2400558569
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.284763006
Short name T931
Test name
Test status
Simulation time 2680402422 ps
CPU time 11.49 seconds
Started Sep 01 08:45:59 PM UTC 24
Finished Sep 01 08:46:12 PM UTC 24
Peak memory 233868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284763006 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_direct.284763006
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.2913202575
Short name T1018
Test name
Test status
Simulation time 55167563747 ps
CPU time 653.18 seconds
Started Sep 01 08:46:01 PM UTC 24
Finished Sep 01 08:57:03 PM UTC 24
Peak memory 268296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913202575 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stress_all.2913202575
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.3383746511
Short name T933
Test name
Test status
Simulation time 5729710354 ps
CPU time 24.55 seconds
Started Sep 01 08:45:49 PM UTC 24
Finished Sep 01 08:46:15 PM UTC 24
Peak memory 232112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383746511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3383746511
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.116851829
Short name T918
Test name
Test status
Simulation time 776034374 ps
CPU time 4.43 seconds
Started Sep 01 08:45:47 PM UTC 24
Finished Sep 01 08:45:53 PM UTC 24
Peak memory 227716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=116851829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_3
1/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.116851829
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.212854551
Short name T920
Test name
Test status
Simulation time 526620887 ps
CPU time 2.97 seconds
Started Sep 01 08:45:50 PM UTC 24
Finished Sep 01 08:45:54 PM UTC 24
Peak memory 227760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212854551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.212854551
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.2880379256
Short name T916
Test name
Test status
Simulation time 51104911 ps
CPU time 1.22 seconds
Started Sep 01 08:45:49 PM UTC 24
Finished Sep 01 08:45:51 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880379256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2880379256
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.1568018047
Short name T940
Test name
Test status
Simulation time 13359655477 ps
CPU time 28.53 seconds
Started Sep 01 08:45:54 PM UTC 24
Finished Sep 01 08:46:24 PM UTC 24
Peak memory 251780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568018047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1568018047
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/46.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.4177072753
Short name T944
Test name
Test status
Simulation time 34167526 ps
CPU time 1.09 seconds
Started Sep 01 08:46:28 PM UTC 24
Finished Sep 01 08:46:30 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177072753 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.4177072753
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.1195542410
Short name T941
Test name
Test status
Simulation time 243700144 ps
CPU time 3.51 seconds
Started Sep 01 08:46:20 PM UTC 24
Finished Sep 01 08:46:25 PM UTC 24
Peak memory 235336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195542410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1195542410
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.3376770056
Short name T929
Test name
Test status
Simulation time 44575670 ps
CPU time 1.12 seconds
Started Sep 01 08:46:07 PM UTC 24
Finished Sep 01 08:46:09 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376770056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.3376770056
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.1356739151
Short name T948
Test name
Test status
Simulation time 499266357 ps
CPU time 7.13 seconds
Started Sep 01 08:46:25 PM UTC 24
Finished Sep 01 08:46:33 PM UTC 24
Peak memory 251744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356739151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1356739151
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.80029364
Short name T991
Test name
Test status
Simulation time 2578743386 ps
CPU time 77.4 seconds
Started Sep 01 08:46:26 PM UTC 24
Finished Sep 01 08:47:45 PM UTC 24
Peak memory 246044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80029364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.80029364
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.2302898754
Short name T942
Test name
Test status
Simulation time 436251168 ps
CPU time 4.17 seconds
Started Sep 01 08:46:21 PM UTC 24
Finished Sep 01 08:46:26 PM UTC 24
Peak memory 235400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302898754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.2302898754
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.1595832364
Short name T1004
Test name
Test status
Simulation time 18632882872 ps
CPU time 149.46 seconds
Started Sep 01 08:46:23 PM UTC 24
Finished Sep 01 08:48:55 PM UTC 24
Peak memory 262368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595832364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds.1595832364
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.3139294917
Short name T952
Test name
Test status
Simulation time 1820610418 ps
CPU time 18.09 seconds
Started Sep 01 08:46:16 PM UTC 24
Finished Sep 01 08:46:35 PM UTC 24
Peak memory 235280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139294917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.3139294917
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.363916535
Short name T954
Test name
Test status
Simulation time 3071808538 ps
CPU time 19.36 seconds
Started Sep 01 08:46:16 PM UTC 24
Finished Sep 01 08:46:37 PM UTC 24
Peak memory 245588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363916535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.363916535
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.2646443847
Short name T953
Test name
Test status
Simulation time 4431666160 ps
CPU time 19.51 seconds
Started Sep 01 08:46:15 PM UTC 24
Finished Sep 01 08:46:36 PM UTC 24
Peak memory 235444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646443847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap.2646443847
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.1491028681
Short name T939
Test name
Test status
Simulation time 913557334 ps
CPU time 7.06 seconds
Started Sep 01 08:46:14 PM UTC 24
Finished Sep 01 08:46:22 PM UTC 24
Peak memory 235412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491028681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1491028681
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.208484643
Short name T947
Test name
Test status
Simulation time 834081268 ps
CPU time 8.65 seconds
Started Sep 01 08:46:23 PM UTC 24
Finished Sep 01 08:46:32 PM UTC 24
Peak memory 234100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208484643 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_direct.208484643
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.613378345
Short name T978
Test name
Test status
Simulation time 5445818805 ps
CPU time 36.95 seconds
Started Sep 01 08:46:27 PM UTC 24
Finished Sep 01 08:47:05 PM UTC 24
Peak memory 235652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=613378345 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stress_all.613378345
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.2190317732
Short name T935
Test name
Test status
Simulation time 228625403 ps
CPU time 5.4 seconds
Started Sep 01 08:46:10 PM UTC 24
Finished Sep 01 08:46:16 PM UTC 24
Peak memory 227956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190317732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2190317732
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.2721125590
Short name T951
Test name
Test status
Simulation time 14652261424 ps
CPU time 25.06 seconds
Started Sep 01 08:46:09 PM UTC 24
Finished Sep 01 08:46:35 PM UTC 24
Peak memory 227828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721125590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.2721125590
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.3346565467
Short name T934
Test name
Test status
Simulation time 16173162 ps
CPU time 1.1 seconds
Started Sep 01 08:46:13 PM UTC 24
Finished Sep 01 08:46:15 PM UTC 24
Peak memory 215796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346565467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3346565467
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.3232847468
Short name T932
Test name
Test status
Simulation time 180348148 ps
CPU time 1.44 seconds
Started Sep 01 08:46:11 PM UTC 24
Finished Sep 01 08:46:13 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232847468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.3232847468
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.815886158
Short name T943
Test name
Test status
Simulation time 3935587073 ps
CPU time 8.38 seconds
Started Sep 01 08:46:17 PM UTC 24
Finished Sep 01 08:46:27 PM UTC 24
Peak memory 235460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815886158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.815886158
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/47.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.290909264
Short name T960
Test name
Test status
Simulation time 40484107 ps
CPU time 1.15 seconds
Started Sep 01 08:46:41 PM UTC 24
Finished Sep 01 08:46:43 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=290909264 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.290909264
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.2976779805
Short name T967
Test name
Test status
Simulation time 1038748359 ps
CPU time 13.41 seconds
Started Sep 01 08:46:36 PM UTC 24
Finished Sep 01 08:46:51 PM UTC 24
Peak memory 235468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976779805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.2976779805
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.3063225411
Short name T945
Test name
Test status
Simulation time 37615316 ps
CPU time 1.15 seconds
Started Sep 01 08:46:29 PM UTC 24
Finished Sep 01 08:46:32 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063225411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3063225411
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.3899326272
Short name T1002
Test name
Test status
Simulation time 10582736442 ps
CPU time 118.09 seconds
Started Sep 01 08:46:37 PM UTC 24
Finished Sep 01 08:48:38 PM UTC 24
Peak memory 264136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899326272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3899326272
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.3943460967
Short name T1011
Test name
Test status
Simulation time 27497310548 ps
CPU time 287.5 seconds
Started Sep 01 08:46:38 PM UTC 24
Finished Sep 01 08:51:30 PM UTC 24
Peak memory 262184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943460967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3943460967
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.2716131922
Short name T993
Test name
Test status
Simulation time 8236513754 ps
CPU time 76.56 seconds
Started Sep 01 08:46:38 PM UTC 24
Finished Sep 01 08:47:57 PM UTC 24
Peak memory 262144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2716131922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idle.2716131922
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.2211217226
Short name T962
Test name
Test status
Simulation time 384168908 ps
CPU time 6.21 seconds
Started Sep 01 08:46:36 PM UTC 24
Finished Sep 01 08:46:43 PM UTC 24
Peak memory 245768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211217226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.2211217226
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.3088765139
Short name T374
Test name
Test status
Simulation time 80809636009 ps
CPU time 443.53 seconds
Started Sep 01 08:46:37 PM UTC 24
Finished Sep 01 08:54:07 PM UTC 24
Peak memory 262148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088765139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds.3088765139
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.2485341098
Short name T958
Test name
Test status
Simulation time 214033969 ps
CPU time 4.42 seconds
Started Sep 01 08:46:35 PM UTC 24
Finished Sep 01 08:46:40 PM UTC 24
Peak memory 245800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2485341098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2485341098
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.3536898853
Short name T989
Test name
Test status
Simulation time 4077395721 ps
CPU time 54.96 seconds
Started Sep 01 08:46:35 PM UTC 24
Finished Sep 01 08:47:31 PM UTC 24
Peak memory 245900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536898853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3536898853
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.2082172297
Short name T957
Test name
Test status
Simulation time 240595032 ps
CPU time 4.3 seconds
Started Sep 01 08:46:34 PM UTC 24
Finished Sep 01 08:46:39 PM UTC 24
Peak memory 245800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082172297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap.2082172297
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.108978261
Short name T956
Test name
Test status
Simulation time 57479273 ps
CPU time 3.16 seconds
Started Sep 01 08:46:34 PM UTC 24
Finished Sep 01 08:46:38 PM UTC 24
Peak memory 245488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=108978261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.108978261
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.4042955636
Short name T971
Test name
Test status
Simulation time 2469279090 ps
CPU time 21.81 seconds
Started Sep 01 08:46:37 PM UTC 24
Finished Sep 01 08:47:00 PM UTC 24
Peak memory 234032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042955636 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_direct.4042955636
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.2848405102
Short name T1005
Test name
Test status
Simulation time 37205166455 ps
CPU time 143.82 seconds
Started Sep 01 08:46:40 PM UTC 24
Finished Sep 01 08:49:06 PM UTC 24
Peak memory 262184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848405102 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stress_all.2848405102
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.227671094
Short name T959
Test name
Test status
Simulation time 5686180079 ps
CPU time 8.03 seconds
Started Sep 01 08:46:31 PM UTC 24
Finished Sep 01 08:46:41 PM UTC 24
Peak memory 228144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=227671094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.227671094
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.4176863756
Short name T949
Test name
Test status
Simulation time 29853949 ps
CPU time 1.12 seconds
Started Sep 01 08:46:31 PM UTC 24
Finished Sep 01 08:46:34 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176863756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4176863756
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.2809939446
Short name T955
Test name
Test status
Simulation time 77751745 ps
CPU time 4.2 seconds
Started Sep 01 08:46:32 PM UTC 24
Finished Sep 01 08:46:38 PM UTC 24
Peak memory 227884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809939446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.2809939446
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.2065206700
Short name T950
Test name
Test status
Simulation time 30536586 ps
CPU time 1.31 seconds
Started Sep 01 08:46:32 PM UTC 24
Finished Sep 01 08:46:35 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065206700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2065206700
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.3689213790
Short name T981
Test name
Test status
Simulation time 11393930130 ps
CPU time 31.84 seconds
Started Sep 01 08:46:36 PM UTC 24
Finished Sep 01 08:47:09 PM UTC 24
Peak memory 235712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689213790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.3689213790
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/48.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.3690148485
Short name T976
Test name
Test status
Simulation time 40531150 ps
CPU time 1.08 seconds
Started Sep 01 08:47:02 PM UTC 24
Finished Sep 01 08:47:04 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690148485 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.3690148485
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.2069024354
Short name T974
Test name
Test status
Simulation time 1603359815 ps
CPU time 6.24 seconds
Started Sep 01 08:46:53 PM UTC 24
Finished Sep 01 08:47:01 PM UTC 24
Peak memory 245604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069024354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.2069024354
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.3064925095
Short name T963
Test name
Test status
Simulation time 47211090 ps
CPU time 1.14 seconds
Started Sep 01 08:46:42 PM UTC 24
Finished Sep 01 08:46:44 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3064925095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.3064925095
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.3789449643
Short name T986
Test name
Test status
Simulation time 1157070513 ps
CPU time 23.97 seconds
Started Sep 01 08:46:57 PM UTC 24
Finished Sep 01 08:47:22 PM UTC 24
Peak memory 251940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789449643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3789449643
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.1197221127
Short name T1001
Test name
Test status
Simulation time 11352626044 ps
CPU time 90.38 seconds
Started Sep 01 08:47:01 PM UTC 24
Finished Sep 01 08:48:33 PM UTC 24
Peak memory 266264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197221127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.1197221127
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.1049070701
Short name T987
Test name
Test status
Simulation time 1922565787 ps
CPU time 32.91 seconds
Started Sep 01 08:46:53 PM UTC 24
Finished Sep 01 08:47:28 PM UTC 24
Peak memory 245544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049070701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.1049070701
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.3624178718
Short name T1012
Test name
Test status
Simulation time 125506857298 ps
CPU time 280.36 seconds
Started Sep 01 08:46:54 PM UTC 24
Finished Sep 01 08:51:39 PM UTC 24
Peak memory 266404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3624178718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds.3624178718
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.3636403908
Short name T982
Test name
Test status
Simulation time 6577512301 ps
CPU time 21.72 seconds
Started Sep 01 08:46:49 PM UTC 24
Finished Sep 01 08:47:13 PM UTC 24
Peak memory 235660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3636403908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.3636403908
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.3686364485
Short name T995
Test name
Test status
Simulation time 53031226187 ps
CPU time 68.6 seconds
Started Sep 01 08:46:50 PM UTC 24
Finished Sep 01 08:48:01 PM UTC 24
Peak memory 245644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686364485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3686364485
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.321794712
Short name T973
Test name
Test status
Simulation time 7982843200 ps
CPU time 10.56 seconds
Started Sep 01 08:46:48 PM UTC 24
Finished Sep 01 08:47:01 PM UTC 24
Peak memory 245704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=321794712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.321794712
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.152618926
Short name T972
Test name
Test status
Simulation time 3032799131 ps
CPU time 11.84 seconds
Started Sep 01 08:46:47 PM UTC 24
Finished Sep 01 08:47:00 PM UTC 24
Peak memory 245712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152618926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.152618926
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.2647070466
Short name T975
Test name
Test status
Simulation time 637215575 ps
CPU time 6.15 seconds
Started Sep 01 08:46:56 PM UTC 24
Finished Sep 01 08:47:03 PM UTC 24
Peak memory 233960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2647070466 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direct.2647070466
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.121978712
Short name T93
Test name
Test status
Simulation time 68953532686 ps
CPU time 418.85 seconds
Started Sep 01 08:47:01 PM UTC 24
Finished Sep 01 08:54:05 PM UTC 24
Peak memory 284672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121978712 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stress_all.121978712
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.4125982826
Short name T969
Test name
Test status
Simulation time 591213112 ps
CPU time 6.8 seconds
Started Sep 01 08:46:44 PM UTC 24
Finished Sep 01 08:46:52 PM UTC 24
Peak memory 227764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125982826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.4125982826
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.51742139
Short name T965
Test name
Test status
Simulation time 390412109 ps
CPU time 2.67 seconds
Started Sep 01 08:46:44 PM UTC 24
Finished Sep 01 08:46:48 PM UTC 24
Peak memory 217268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51742139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.51742139
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.344315185
Short name T966
Test name
Test status
Simulation time 94942700 ps
CPU time 1.83 seconds
Started Sep 01 08:46:45 PM UTC 24
Finished Sep 01 08:46:48 PM UTC 24
Peak memory 226732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344315185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.344315185
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2338143940
Short name T964
Test name
Test status
Simulation time 427567290 ps
CPU time 1.29 seconds
Started Sep 01 08:46:44 PM UTC 24
Finished Sep 01 08:46:46 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2338143940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.2338143940
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.640444435
Short name T983
Test name
Test status
Simulation time 8854584840 ps
CPU time 22.04 seconds
Started Sep 01 08:46:52 PM UTC 24
Finished Sep 01 08:47:15 PM UTC 24
Peak memory 245664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640444435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.640444435
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/49.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_alert_test.154458727
Short name T430
Test name
Test status
Simulation time 12945528 ps
CPU time 1.11 seconds
Started Sep 01 08:34:45 PM UTC 24
Finished Sep 01 08:34:47 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154458727 -assert nopostproc +UVM_TESTNA
ME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.154458727
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_cfg_cmd.2897535868
Short name T127
Test name
Test status
Simulation time 813089656 ps
CPU time 5.68 seconds
Started Sep 01 08:34:39 PM UTC 24
Finished Sep 01 08:34:46 PM UTC 24
Peak memory 245796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897535868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2897535868
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_csb_read.360680855
Short name T428
Test name
Test status
Simulation time 178667589 ps
CPU time 1.17 seconds
Started Sep 01 08:34:33 PM UTC 24
Finished Sep 01 08:34:36 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360680855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.360680855
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_all.248930883
Short name T71
Test name
Test status
Simulation time 3250933618 ps
CPU time 43.34 seconds
Started Sep 01 08:34:41 PM UTC 24
Finished Sep 01 08:35:26 PM UTC 24
Peak memory 245696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248930883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.248930883
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.1584322420
Short name T232
Test name
Test status
Simulation time 29383000891 ps
CPU time 304.62 seconds
Started Sep 01 08:34:42 PM UTC 24
Finished Sep 01 08:39:51 PM UTC 24
Peak memory 262344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584322420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1584322420
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm_min_idle.361004355
Short name T553
Test name
Test status
Simulation time 126637297965 ps
CPU time 256.04 seconds
Started Sep 01 08:34:43 PM UTC 24
Finished Sep 01 08:39:03 PM UTC 24
Peak memory 262352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361004355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.361004355
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode.3923970071
Short name T231
Test name
Test status
Simulation time 32046018988 ps
CPU time 29.27 seconds
Started Sep 01 08:34:40 PM UTC 24
Finished Sep 01 08:35:11 PM UTC 24
Peak memory 245708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923970071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3923970071
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.1983471031
Short name T114
Test name
Test status
Simulation time 3297627916 ps
CPU time 57.32 seconds
Started Sep 01 08:34:41 PM UTC 24
Finished Sep 01 08:35:40 PM UTC 24
Peak memory 262316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983471031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds.1983471031
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_intercept.4186105168
Short name T80
Test name
Test status
Simulation time 1159082756 ps
CPU time 3.13 seconds
Started Sep 01 08:34:37 PM UTC 24
Finished Sep 01 08:34:41 PM UTC 24
Peak memory 235264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186105168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.4186105168
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mailbox.895850865
Short name T132
Test name
Test status
Simulation time 645543880 ps
CPU time 14.61 seconds
Started Sep 01 08:34:38 PM UTC 24
Finished Sep 01 08:34:54 PM UTC 24
Peak memory 245736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895850865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.895850865
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_mem_parity.1853606481
Short name T429
Test name
Test status
Simulation time 28288936 ps
CPU time 1.56 seconds
Started Sep 01 08:34:34 PM UTC 24
Finished Sep 01 08:34:37 PM UTC 24
Peak memory 229204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853606481 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mem_parity.1853606481
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_addr_payload_swap.2980131424
Short name T72
Test name
Test status
Simulation time 45230143534 ps
CPU time 48.19 seconds
Started Sep 01 08:34:37 PM UTC 24
Finished Sep 01 08:35:27 PM UTC 24
Peak memory 245656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980131424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.2980131424
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_pass_cmd_filtering.2625711248
Short name T126
Test name
Test status
Simulation time 1440506440 ps
CPU time 6.51 seconds
Started Sep 01 08:34:37 PM UTC 24
Finished Sep 01 08:34:44 PM UTC 24
Peak memory 235524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625711248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2625711248
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_read_buffer_direct.1736432150
Short name T130
Test name
Test status
Simulation time 1498709946 ps
CPU time 8.36 seconds
Started Sep 01 08:34:41 PM UTC 24
Finished Sep 01 08:34:51 PM UTC 24
Peak memory 231796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736432150 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direct.1736432150
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_stress_all.3918007503
Short name T282
Test name
Test status
Simulation time 45539478293 ps
CPU time 361.35 seconds
Started Sep 01 08:34:44 PM UTC 24
Finished Sep 01 08:40:50 PM UTC 24
Peak memory 278600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918007503 -assert nopostproc +UVM_TE
STNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stress_all.3918007503
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_all.4204848500
Short name T124
Test name
Test status
Simulation time 479605764 ps
CPU time 11.16 seconds
Started Sep 01 08:34:36 PM UTC 24
Finished Sep 01 08:34:48 PM UTC 24
Peak memory 227992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204848500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.4204848500
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_read_hw_reg.2187202630
Short name T433
Test name
Test status
Simulation time 17944510260 ps
CPU time 18.1 seconds
Started Sep 01 08:34:34 PM UTC 24
Finished Sep 01 08:34:54 PM UTC 24
Peak memory 227832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187202630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2187202630
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_rw.286966440
Short name T77
Test name
Test status
Simulation time 118205217 ps
CPU time 1.37 seconds
Started Sep 01 08:34:37 PM UTC 24
Finished Sep 01 08:34:39 PM UTC 24
Peak memory 215924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286966440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_dev
ice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.286966440
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_tpm_sts_read.2987036877
Short name T76
Test name
Test status
Simulation time 158145377 ps
CPU time 1.27 seconds
Started Sep 01 08:34:36 PM UTC 24
Finished Sep 01 08:34:38 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987036877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.2987036877
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/5.spi_device_upload.1843652255
Short name T68
Test name
Test status
Simulation time 859282997 ps
CPU time 4.02 seconds
Started Sep 01 08:34:39 PM UTC 24
Finished Sep 01 08:34:44 PM UTC 24
Peak memory 235272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1843652255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.1843652255
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/5.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_alert_test.3497669764
Short name T435
Test name
Test status
Simulation time 32393749 ps
CPU time 1.07 seconds
Started Sep 01 08:34:59 PM UTC 24
Finished Sep 01 08:35:01 PM UTC 24
Peak memory 215732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497669764 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.3497669764
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_cfg_cmd.4015378881
Short name T434
Test name
Test status
Simulation time 328802653 ps
CPU time 6.7 seconds
Started Sep 01 08:34:51 PM UTC 24
Finished Sep 01 08:34:59 PM UTC 24
Peak memory 235336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015378881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.4015378881
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_csb_read.1138211247
Short name T431
Test name
Test status
Simulation time 20223938 ps
CPU time 1.23 seconds
Started Sep 01 08:34:45 PM UTC 24
Finished Sep 01 08:34:47 PM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138211247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.1138211247
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_all.2512254858
Short name T396
Test name
Test status
Simulation time 1335242654956 ps
CPU time 1095.58 seconds
Started Sep 01 08:34:55 PM UTC 24
Finished Sep 01 08:53:24 PM UTC 24
Peak memory 284644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512254858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2512254858
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2086893289
Short name T291
Test name
Test status
Simulation time 104825078531 ps
CPU time 213.18 seconds
Started Sep 01 08:34:56 PM UTC 24
Finished Sep 01 08:38:32 PM UTC 24
Peak memory 262084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086893289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.2086893289
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm_min_idle.2637296972
Short name T207
Test name
Test status
Simulation time 2475181104 ps
CPU time 28.53 seconds
Started Sep 01 08:34:57 PM UTC 24
Finished Sep 01 08:35:27 PM UTC 24
Peak memory 235664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637296972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.2637296972
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode.958190100
Short name T179
Test name
Test status
Simulation time 555769163 ps
CPU time 7.93 seconds
Started Sep 01 08:34:52 PM UTC 24
Finished Sep 01 08:35:02 PM UTC 24
Peak memory 245804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958190100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.958190100
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_mode_ignore_cmds.396730383
Short name T225
Test name
Test status
Simulation time 64888868547 ps
CPU time 182.39 seconds
Started Sep 01 08:34:55 PM UTC 24
Finished Sep 01 08:38:00 PM UTC 24
Peak memory 251856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396730383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.396730383
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_intercept.3776927062
Short name T280
Test name
Test status
Simulation time 286772052 ps
CPU time 5.46 seconds
Started Sep 01 08:34:49 PM UTC 24
Finished Sep 01 08:34:56 PM UTC 24
Peak memory 235624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776927062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3776927062
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mailbox.1199288429
Short name T213
Test name
Test status
Simulation time 2114259487 ps
CPU time 9.97 seconds
Started Sep 01 08:34:50 PM UTC 24
Finished Sep 01 08:35:01 PM UTC 24
Peak memory 245544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199288429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1199288429
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_mem_parity.1903052727
Short name T432
Test name
Test status
Simulation time 458090428 ps
CPU time 1.59 seconds
Started Sep 01 08:34:46 PM UTC 24
Finished Sep 01 08:34:48 PM UTC 24
Peak memory 229264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1903052727 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mem_parity.1903052727
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_addr_payload_swap.1443133221
Short name T211
Test name
Test status
Simulation time 668754371 ps
CPU time 3.85 seconds
Started Sep 01 08:34:49 PM UTC 24
Finished Sep 01 08:34:54 PM UTC 24
Peak memory 245588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1443133221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.1443133221
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_pass_cmd_filtering.2554317175
Short name T259
Test name
Test status
Simulation time 5990152985 ps
CPU time 41.36 seconds
Started Sep 01 08:34:48 PM UTC 24
Finished Sep 01 08:35:31 PM UTC 24
Peak memory 245736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554317175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.2554317175
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_read_buffer_direct.488993883
Short name T180
Test name
Test status
Simulation time 6469801151 ps
CPU time 18.38 seconds
Started Sep 01 08:34:55 PM UTC 24
Finished Sep 01 08:35:14 PM UTC 24
Peak memory 233996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488993883 -assert nopostproc +UVM_TESTNAME=spi_device_ba
se_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direct.488993883
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_all.690547977
Short name T405
Test name
Test status
Simulation time 1981388739 ps
CPU time 15.32 seconds
Started Sep 01 08:34:47 PM UTC 24
Finished Sep 01 08:35:03 PM UTC 24
Peak memory 227984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690547977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.690547977
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_read_hw_reg.2925176365
Short name T440
Test name
Test status
Simulation time 42114511773 ps
CPU time 17.05 seconds
Started Sep 01 08:34:47 PM UTC 24
Finished Sep 01 08:35:05 PM UTC 24
Peak memory 228024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925176365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.2925176365
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_rw.3491734937
Short name T413
Test name
Test status
Simulation time 273316837 ps
CPU time 9.93 seconds
Started Sep 01 08:34:48 PM UTC 24
Finished Sep 01 08:34:59 PM UTC 24
Peak memory 227800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491734937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3491734937
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_tpm_sts_read.495917304
Short name T129
Test name
Test status
Simulation time 18645101 ps
CPU time 1.12 seconds
Started Sep 01 08:34:48 PM UTC 24
Finished Sep 01 08:34:50 PM UTC 24
Peak memory 215920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495917304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.495917304
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/6.spi_device_upload.2737400569
Short name T276
Test name
Test status
Simulation time 9287411499 ps
CPU time 34.77 seconds
Started Sep 01 08:34:51 PM UTC 24
Finished Sep 01 08:35:28 PM UTC 24
Peak memory 245660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737400569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2737400569
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/6.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_alert_test.22006304
Short name T444
Test name
Test status
Simulation time 55159727 ps
CPU time 1.12 seconds
Started Sep 01 08:35:15 PM UTC 24
Finished Sep 01 08:35:18 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22006304 -assert nopostproc +UVM_TESTNAM
E=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.22006304
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_cfg_cmd.3897318649
Short name T328
Test name
Test status
Simulation time 743711816 ps
CPU time 8 seconds
Started Sep 01 08:35:06 PM UTC 24
Finished Sep 01 08:35:15 PM UTC 24
Peak memory 245724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897318649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.3897318649
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_csb_read.265840390
Short name T436
Test name
Test status
Simulation time 199069633 ps
CPU time 1.17 seconds
Started Sep 01 08:35:00 PM UTC 24
Finished Sep 01 08:35:02 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265840390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.265840390
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.2951775854
Short name T212
Test name
Test status
Simulation time 2371588549 ps
CPU time 13.68 seconds
Started Sep 01 08:35:11 PM UTC 24
Finished Sep 01 08:35:26 PM UTC 24
Peak memory 232188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951775854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.2951775854
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm.1285244077
Short name T209
Test name
Test status
Simulation time 7479474912 ps
CPU time 105.96 seconds
Started Sep 01 08:35:12 PM UTC 24
Finished Sep 01 08:37:00 PM UTC 24
Peak memory 264456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285244077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1285244077
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.2199531229
Short name T110
Test name
Test status
Simulation time 9215599706 ps
CPU time 52.58 seconds
Started Sep 01 08:35:12 PM UTC 24
Finished Sep 01 08:36:06 PM UTC 24
Peak memory 249872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2199531229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.2199531229
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_mode_ignore_cmds.280295568
Short name T203
Test name
Test status
Simulation time 20551034808 ps
CPU time 109.83 seconds
Started Sep 01 08:35:08 PM UTC 24
Finished Sep 01 08:37:00 PM UTC 24
Peak memory 282604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280295568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.280295568
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_intercept.1513993556
Short name T136
Test name
Test status
Simulation time 208914877 ps
CPU time 6.73 seconds
Started Sep 01 08:35:05 PM UTC 24
Finished Sep 01 08:35:12 PM UTC 24
Peak memory 245768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513993556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1513993556
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mailbox.2445777494
Short name T247
Test name
Test status
Simulation time 17229176834 ps
CPU time 107.95 seconds
Started Sep 01 08:35:05 PM UTC 24
Finished Sep 01 08:36:55 PM UTC 24
Peak memory 251812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445777494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.2445777494
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_mem_parity.1650833566
Short name T437
Test name
Test status
Simulation time 31650880 ps
CPU time 1.55 seconds
Started Sep 01 08:35:00 PM UTC 24
Finished Sep 01 08:35:03 PM UTC 24
Peak memory 229264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650833566 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mem_parity.1650833566
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_addr_payload_swap.526772280
Short name T441
Test name
Test status
Simulation time 74752447 ps
CPU time 2.63 seconds
Started Sep 01 08:35:03 PM UTC 24
Finished Sep 01 08:35:07 PM UTC 24
Peak memory 233928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526772280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap.526772280
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_pass_cmd_filtering.1000729020
Short name T198
Test name
Test status
Simulation time 3617106003 ps
CPU time 12.45 seconds
Started Sep 01 08:35:03 PM UTC 24
Finished Sep 01 08:35:17 PM UTC 24
Peak memory 245840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1000729020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.1000729020
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_read_buffer_direct.2888540016
Short name T171
Test name
Test status
Simulation time 7291323029 ps
CPU time 12.3 seconds
Started Sep 01 08:35:09 PM UTC 24
Finished Sep 01 08:35:22 PM UTC 24
Peak memory 233840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888540016 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direct.2888540016
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_all.854189835
Short name T438
Test name
Test status
Simulation time 26838880 ps
CPU time 1.15 seconds
Started Sep 01 08:35:02 PM UTC 24
Finished Sep 01 08:35:04 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854189835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.854189835
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_read_hw_reg.3199454628
Short name T442
Test name
Test status
Simulation time 2260221169 ps
CPU time 6.47 seconds
Started Sep 01 08:35:02 PM UTC 24
Finished Sep 01 08:35:10 PM UTC 24
Peak memory 228088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3199454628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3199454628
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_rw.2576550169
Short name T420
Test name
Test status
Simulation time 309497841 ps
CPU time 4.42 seconds
Started Sep 01 08:35:02 PM UTC 24
Finished Sep 01 08:35:08 PM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576550169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.2576550169
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_tpm_sts_read.3581211756
Short name T439
Test name
Test status
Simulation time 30504198 ps
CPU time 1.19 seconds
Started Sep 01 08:35:02 PM UTC 24
Finished Sep 01 08:35:04 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581211756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.3581211756
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/7.spi_device_upload.68901780
Short name T69
Test name
Test status
Simulation time 7667397370 ps
CPU time 18.72 seconds
Started Sep 01 08:35:06 PM UTC 24
Finished Sep 01 08:35:26 PM UTC 24
Peak memory 245668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68901780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_devi
ce_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.68901780
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/7.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_alert_test.2325779429
Short name T445
Test name
Test status
Simulation time 26021996 ps
CPU time 1.14 seconds
Started Sep 01 08:35:28 PM UTC 24
Finished Sep 01 08:35:30 PM UTC 24
Peak memory 215736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325779429 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2325779429
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_cfg_cmd.829573908
Short name T299
Test name
Test status
Simulation time 717501222 ps
CPU time 4.83 seconds
Started Sep 01 08:35:24 PM UTC 24
Finished Sep 01 08:35:30 PM UTC 24
Peak memory 245772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829573908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.829573908
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_csb_read.1809781303
Short name T443
Test name
Test status
Simulation time 83529106 ps
CPU time 0.94 seconds
Started Sep 01 08:35:15 PM UTC 24
Finished Sep 01 08:35:17 PM UTC 24
Peak memory 215680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809781303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1809781303
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_all.905644084
Short name T200
Test name
Test status
Simulation time 28819317875 ps
CPU time 178.95 seconds
Started Sep 01 08:35:26 PM UTC 24
Finished Sep 01 08:38:28 PM UTC 24
Peak memory 263832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905644084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.905644084
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.384325572
Short name T246
Test name
Test status
Simulation time 80643396024 ps
CPU time 355.92 seconds
Started Sep 01 08:35:27 PM UTC 24
Finished Sep 01 08:41:27 PM UTC 24
Peak memory 264396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384325572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.384325572
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.4191230465
Short name T204
Test name
Test status
Simulation time 30353088385 ps
CPU time 244.5 seconds
Started Sep 01 08:35:27 PM UTC 24
Finished Sep 01 08:39:35 PM UTC 24
Peak memory 280584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191230465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.4191230465
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode.934527142
Short name T279
Test name
Test status
Simulation time 1187625463 ps
CPU time 7.28 seconds
Started Sep 01 08:35:24 PM UTC 24
Finished Sep 01 08:35:33 PM UTC 24
Peak memory 235344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=934527142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.934527142
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.3709136483
Short name T382
Test name
Test status
Simulation time 143638140349 ps
CPU time 655.23 seconds
Started Sep 01 08:35:26 PM UTC 24
Finished Sep 01 08:46:30 PM UTC 24
Peak memory 266180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709136483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.3709136483
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_intercept.3931194457
Short name T173
Test name
Test status
Simulation time 393746128 ps
CPU time 3.38 seconds
Started Sep 01 08:35:21 PM UTC 24
Finished Sep 01 08:35:25 PM UTC 24
Peak memory 245548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931194457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3931194457
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mailbox.2783693546
Short name T289
Test name
Test status
Simulation time 509678021 ps
CPU time 14.17 seconds
Started Sep 01 08:35:22 PM UTC 24
Finished Sep 01 08:35:37 PM UTC 24
Peak memory 245576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783693546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2783693546
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_mem_parity.1107462832
Short name T168
Test name
Test status
Simulation time 284326251 ps
CPU time 1.48 seconds
Started Sep 01 08:35:17 PM UTC 24
Finished Sep 01 08:35:20 PM UTC 24
Peak memory 229260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107462832 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mem_parity.1107462832
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_addr_payload_swap.955355270
Short name T174
Test name
Test status
Simulation time 85080498 ps
CPU time 3.43 seconds
Started Sep 01 08:35:21 PM UTC 24
Finished Sep 01 08:35:25 PM UTC 24
Peak memory 245652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955355270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.955355270
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_pass_cmd_filtering.3610191201
Short name T201
Test name
Test status
Simulation time 556181283 ps
CPU time 4.76 seconds
Started Sep 01 08:35:20 PM UTC 24
Finished Sep 01 08:35:26 PM UTC 24
Peak memory 245772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610191201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.3610191201
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_read_buffer_direct.2648384341
Short name T452
Test name
Test status
Simulation time 3447006567 ps
CPU time 24.65 seconds
Started Sep 01 08:35:26 PM UTC 24
Finished Sep 01 08:35:52 PM UTC 24
Peak memory 233836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648384341 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direct.2648384341
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_all.2996227778
Short name T412
Test name
Test status
Simulation time 2136156556 ps
CPU time 20.67 seconds
Started Sep 01 08:35:19 PM UTC 24
Finished Sep 01 08:35:40 PM UTC 24
Peak memory 227764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996227778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.2996227778
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_read_hw_reg.1984647118
Short name T449
Test name
Test status
Simulation time 2752074900 ps
CPU time 17.56 seconds
Started Sep 01 08:35:19 PM UTC 24
Finished Sep 01 08:35:37 PM UTC 24
Peak memory 227852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984647118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1984647118
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_rw.2330470812
Short name T172
Test name
Test status
Simulation time 623758938 ps
CPU time 2.44 seconds
Started Sep 01 08:35:20 PM UTC 24
Finished Sep 01 08:35:23 PM UTC 24
Peak memory 227796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2330470812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2330470812
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_tpm_sts_read.274525795
Short name T170
Test name
Test status
Simulation time 116862911 ps
CPU time 1.31 seconds
Started Sep 01 08:35:19 PM UTC 24
Finished Sep 01 08:35:21 PM UTC 24
Peak memory 215920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274525795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/s
pi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.274525795
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/8.spi_device_upload.1017295379
Short name T199
Test name
Test status
Simulation time 7746516672 ps
CPU time 13.84 seconds
Started Sep 01 08:35:23 PM UTC 24
Finished Sep 01 08:35:38 PM UTC 24
Peak memory 245700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1017295379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1017295379
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/8.spi_device_upload/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_alert_test.3266384364
Short name T189
Test name
Test status
Simulation time 57828025 ps
CPU time 1.12 seconds
Started Sep 01 08:35:41 PM UTC 24
Finished Sep 01 08:35:43 PM UTC 24
Peak memory 215676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266384364 -assert nopostproc +UVM_TESTN
AME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3266384364
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_alert_test/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_cfg_cmd.3927552714
Short name T187
Test name
Test status
Simulation time 164031652 ps
CPU time 4.4 seconds
Started Sep 01 08:35:38 PM UTC 24
Finished Sep 01 08:35:43 PM UTC 24
Peak memory 235268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3927552714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.3927552714
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_cfg_cmd/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_csb_read.1804232347
Short name T446
Test name
Test status
Simulation time 60001491 ps
CPU time 1.11 seconds
Started Sep 01 08:35:28 PM UTC 24
Finished Sep 01 08:35:30 PM UTC 24
Peak memory 215800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804232347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_
device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1804232347
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_csb_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.3050622955
Short name T549
Test name
Test status
Simulation time 24358589828 ps
CPU time 197.67 seconds
Started Sep 01 08:35:40 PM UTC 24
Finished Sep 01 08:39:01 PM UTC 24
Peak memory 262088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3050622955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.3050622955
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_flash_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm.3209287378
Short name T206
Test name
Test status
Simulation time 12095939334 ps
CPU time 88.11 seconds
Started Sep 01 08:35:40 PM UTC 24
Finished Sep 01 08:37:10 PM UTC 24
Peak memory 262156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3209287378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31
/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.3209287378
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.61929712
Short name T205
Test name
Test status
Simulation time 2008760625 ps
CPU time 29.63 seconds
Started Sep 01 08:35:41 PM UTC 24
Finished Sep 01 08:36:12 PM UTC 24
Peak memory 235340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61929712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UV
M_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle.61929712
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_flash_and_tpm_min_idle/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode.2395578379
Short name T194
Test name
Test status
Simulation time 237552853 ps
CPU time 7.78 seconds
Started Sep 01 08:35:39 PM UTC 24
Finished Sep 01 08:35:48 PM UTC 24
Peak memory 245548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395578379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/sp
i_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2395578379
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_flash_mode/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_mode_ignore_cmds.1416191820
Short name T137
Test name
Test status
Simulation time 354328351 ps
CPU time 16.75 seconds
Started Sep 01 08:35:39 PM UTC 24
Finished Sep 01 08:35:57 PM UTC 24
Peak memory 262188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416191820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds.1416191820
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_flash_mode_ignore_cmds/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_intercept.3711218703
Short name T295
Test name
Test status
Simulation time 11949635474 ps
CPU time 29.14 seconds
Started Sep 01 08:35:32 PM UTC 24
Finished Sep 01 08:36:03 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711218703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi
_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.3711218703
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_intercept/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mailbox.985411570
Short name T321
Test name
Test status
Simulation time 7587502007 ps
CPU time 31.31 seconds
Started Sep 01 08:35:33 PM UTC 24
Finished Sep 01 08:36:06 PM UTC 24
Peak memory 245732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985411570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +U
VM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.985411570
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_mailbox/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_mem_parity.1697974919
Short name T447
Test name
Test status
Simulation time 29441191 ps
CPU time 1.45 seconds
Started Sep 01 08:35:29 PM UTC 24
Finished Sep 01 08:35:31 PM UTC 24
Peak memory 229264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +en_scb_tl_err_chk=0 +en_scb_mem_chk=0 +cdc_instrumenta
tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697974919 -asser
t nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mem_parity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mem_parity.1697974919
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_mem_parity/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_addr_payload_swap.1069301690
Short name T74
Test name
Test status
Simulation time 10232410095 ps
CPU time 18.57 seconds
Started Sep 01 08:35:32 PM UTC 24
Finished Sep 01 08:35:52 PM UTC 24
Peak memory 232004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069301690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.1069301690
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_pass_addr_payload_swap/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_pass_cmd_filtering.4261636052
Short name T190
Test name
Test status
Simulation time 7214903592 ps
CPU time 10.95 seconds
Started Sep 01 08:35:31 PM UTC 24
Finished Sep 01 08:35:43 PM UTC 24
Peak memory 251848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4261636052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.4261636052
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_pass_cmd_filtering/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_read_buffer_direct.3664549133
Short name T453
Test name
Test status
Simulation time 5243403899 ps
CPU time 15.56 seconds
Started Sep 01 08:35:39 PM UTC 24
Finished Sep 01 08:35:55 PM UTC 24
Peak memory 231724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE
RBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664549133 -assert nopostproc +UVM_TESTNAME=spi_device_b
ase_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_direct.3664549133
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_read_buffer_direct/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_stress_all.818575440
Short name T372
Test name
Test status
Simulation time 210119421339 ps
CPU time 563.56 seconds
Started Sep 01 08:35:41 PM UTC 24
Finished Sep 01 08:45:12 PM UTC 24
Peak memory 268244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_
NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818575440 -assert nopostproc +UVM_TES
TNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress_all.818575440
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_stress_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_all.4189280086
Short name T195
Test name
Test status
Simulation time 2323757480 ps
CPU time 16.8 seconds
Started Sep 01 08:35:31 PM UTC 24
Finished Sep 01 08:35:49 PM UTC 24
Peak memory 227912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189280086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_d
evice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.4189280086
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_tpm_all/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_read_hw_reg.2427031235
Short name T188
Test name
Test status
Simulation time 10664664275 ps
CPU time 13.14 seconds
Started Sep 01 08:35:29 PM UTC 24
Finished Sep 01 08:35:43 PM UTC 24
Peak memory 228124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2427031235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
31/spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.2427031235
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_tpm_read_hw_reg/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_rw.2249003463
Short name T415
Test name
Test status
Simulation time 220298633 ps
CPU time 4.1 seconds
Started Sep 01 08:35:31 PM UTC 24
Finished Sep 01 08:35:36 PM UTC 24
Peak memory 227952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249003463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2249003463
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_tpm_rw/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_tpm_sts_read.4029324858
Short name T448
Test name
Test status
Simulation time 11933690 ps
CPU time 1.08 seconds
Started Sep 01 08:35:31 PM UTC 24
Finished Sep 01 08:35:33 PM UTC 24
Peak memory 215928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4029324858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/
spi_device_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.4029324858
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_tpm_sts_read/latest


Test location /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/coverage/default/9.spi_device_upload.2971167420
Short name T296
Test name
Test status
Simulation time 5850000192 ps
CPU time 31.73 seconds
Started Sep 01 08:35:34 PM UTC 24
Finished Sep 01 08:36:08 PM UTC 24
Peak memory 251812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV
M_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971167420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +
UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_31/spi_de
vice_2p-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.2971167420
Directory /workspaces/repo/scratch/os_regression_2024_08_31/spi_device_2p-sim-vcs/9.spi_device_upload/latest
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