Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : spi_device
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.52 95.20 84.31 97.00 90.62 95.45

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/spi_device_2p-sim-vcs/default/sim-vcs/../src/lowrisc_ip_spi_device_0.1/rtl/spi_device.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 92.52 95.20 84.31 97.00 90.62 95.45


Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.52 95.20 84.31 97.00 90.62 95.45


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.54 98.44 94.08 98.62 89.36 97.28 95.43


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
spi_device_csr_assert 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_clk_csb_buf 100.00 100.00
u_clk_csb_mux 64.81 100.00 44.44 50.00
u_clk_spi 85.19 100.00 55.56 100.00
u_clk_spi_in_buf 100.00 100.00
u_clk_spi_in_mux 64.81 100.00 44.44 50.00
u_clk_spi_out_buf 100.00 100.00
u_clk_spi_out_mux 64.81 100.00 44.44 50.00
u_cmdparse 97.84 100.00 93.26 100.00 95.92 100.00
u_csb_buf 100.00 100.00
u_csb_rst_out_scan_mux 64.81 100.00 44.44 50.00
u_csb_rst_scan_mux 64.81 100.00 44.44 50.00
u_flash_readbuf_flip_pulse_sync 100.00 100.00 100.00 100.00 100.00
u_flash_readbuf_watermark_pulse_sync 100.00 100.00 100.00 100.00 100.00
u_intr_cmdfifo_not_empty 100.00 100.00 100.00 100.00 100.00
u_intr_payload_not_empty 100.00 100.00 100.00 100.00 100.00
u_intr_payload_overflow 100.00 100.00 100.00 100.00 100.00
u_intr_readbuf_flip 100.00 100.00 100.00 100.00 100.00
u_intr_readbuf_watermark 100.00 100.00 100.00 100.00 100.00
u_intr_tpm_cmdaddr_notempty 100.00 100.00 100.00 100.00 100.00
u_intr_tpm_rdfifo_cmd_end 100.00 100.00 100.00 100.00 100.00
u_intr_tpm_rdfifo_drop 97.92 100.00 91.67 100.00 100.00
u_intr_upload_edge 100.00 100.00 100.00
u_jedec 99.38 100.00 100.00 100.00 96.88 100.00
u_p2s 85.98 100.00 71.43 72.50 100.00
u_passthrough 90.54 94.95 89.22 75.00 93.52 100.00
u_read_en_pipe_stg1 100.00 100.00 100.00
u_read_en_pipe_stg2 100.00 100.00 100.00
u_read_intercept_pipe_stg1 100.00 100.00 100.00
u_read_intercept_pipe_stg2 100.00 100.00 100.00
u_read_pipe_stg1 100.00 100.00 100.00
u_read_pipe_stg2 100.00 100.00 100.00
u_readcmd 89.30 93.62 90.32 87.50 84.15 90.91
u_reg 99.64 99.53 99.33 100.00 99.35 100.00
u_rst_spi_out_sync 100.00 100.00 100.00
u_s2p 89.38 100.00 78.57 78.95 100.00
u_scanmode_sync 100.00 100.00
u_spi_tpm 92.81 99.28 85.25 91.67 95.68 92.16
u_spid_addr_4b 86.34 97.59 77.78 95.00 75.00
u_spid_csb_sync 96.97 100.00 100.00 90.91
u_spid_dpram 95.45 100.00 81.82 100.00 100.00
u_spid_status 92.61 100.00 88.46 98.63 83.33
u_sys_csb_syncd 100.00 100.00 100.00
u_sys_sram_arbiter 89.65 100.00 76.47 96.43 85.71
u_sys_tpm_csb_sync 100.00 100.00 100.00
u_tlul2sram_egress 71.47 82.11 59.19 63.33 81.25
u_tlul2sram_ingress 86.64 88.21 73.90 84.44 100.00
u_tpm_csb_buf 100.00 100.00
u_tpm_csb_rst_scan_mux 64.81 100.00 44.44 50.00
u_tpm_csb_rst_sync 70.83 88.89 44.44 100.00 50.00
u_tpm_rst_out_scan_mux 64.81 100.00 44.44 50.00
u_tpm_rst_out_sync 100.00 100.00 100.00
u_upload 90.79 98.60 71.95 100.00 94.12 89.29

Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : spi_device
Line No.TotalCoveredPercent
TOTAL22921895.20
CONT_ASSIGN17311100.00
CONT_ASSIGN30911100.00
CONT_ASSIGN37211100.00
CONT_ASSIGN37311100.00
CONT_ASSIGN37611100.00
CONT_ASSIGN37711100.00
CONT_ASSIGN37911100.00
CONT_ASSIGN39411100.00
CONT_ASSIGN52711100.00
CONT_ASSIGN53411100.00
CONT_ASSIGN53611100.00
ALWAYS53944100.00
CONT_ASSIGN54711100.00
CONT_ASSIGN55311100.00
CONT_ASSIGN55411100.00
CONT_ASSIGN55911100.00
CONT_ASSIGN56011100.00
CONT_ASSIGN56411100.00
ALWAYS56900
ALWAYS56922100.00
CONT_ASSIGN57411100.00
CONT_ASSIGN57511100.00
ALWAYS58300
ALWAYS5831212100.00
CONT_ASSIGN64711100.00
CONT_ASSIGN64811100.00
CONT_ASSIGN64911100.00
CONT_ASSIGN71011100.00
ALWAYS82833100.00
ALWAYS83488100.00
ALWAYS87299100.00
ALWAYS8962424100.00
CONT_ASSIGN96411100.00
CONT_ASSIGN96511100.00
ALWAYS102877100.00
ALWAYS10411313100.00
ALWAYS107833100.00
CONT_ASSIGN121711100.00
CONT_ASSIGN122011100.00
CONT_ASSIGN122411100.00
CONT_ASSIGN122511100.00
CONT_ASSIGN122611100.00
CONT_ASSIGN122811100.00
CONT_ASSIGN122911100.00
CONT_ASSIGN123211100.00
CONT_ASSIGN1282100.00
CONT_ASSIGN1313100.00
CONT_ASSIGN139611100.00
CONT_ASSIGN139711100.00
CONT_ASSIGN139811100.00
CONT_ASSIGN139911100.00
CONT_ASSIGN140011100.00
CONT_ASSIGN140211100.00
CONT_ASSIGN140611100.00
CONT_ASSIGN141311100.00
CONT_ASSIGN141411100.00
CONT_ASSIGN141611100.00
CONT_ASSIGN142011100.00
CONT_ASSIGN142311100.00
CONT_ASSIGN142611100.00
CONT_ASSIGN142911100.00
CONT_ASSIGN143211100.00
CONT_ASSIGN143511100.00
CONT_ASSIGN144211100.00
CONT_ASSIGN144311100.00
CONT_ASSIGN148211100.00
CONT_ASSIGN1585100.00
CONT_ASSIGN159311100.00
CONT_ASSIGN159411100.00
CONT_ASSIGN159511100.00
CONT_ASSIGN159611100.00
CONT_ASSIGN159711100.00
CONT_ASSIGN160011100.00
CONT_ASSIGN160711100.00
CONT_ASSIGN161411100.00
CONT_ASSIGN161411100.00
CONT_ASSIGN161411100.00
CONT_ASSIGN161411100.00
CONT_ASSIGN161411100.00
CONT_ASSIGN161711100.00
CONT_ASSIGN161811100.00
CONT_ASSIGN161911100.00
CONT_ASSIGN162011100.00
CONT_ASSIGN162111100.00
CONT_ASSIGN162211100.00
CONT_ASSIGN162411100.00
CONT_ASSIGN162811100.00
CONT_ASSIGN163011100.00
CONT_ASSIGN163111100.00
CONT_ASSIGN163811100.00
CONT_ASSIGN164011100.00
CONT_ASSIGN164111100.00
CONT_ASSIGN165011100.00
CONT_ASSIGN165111100.00
CONT_ASSIGN165211100.00
CONT_ASSIGN165311100.00
CONT_ASSIGN171611100.00
CONT_ASSIGN171811100.00
ALWAYS172344100.00
ALWAYS173200
ALWAYS173299100.00
CONT_ASSIGN174911100.00
CONT_ASSIGN174911100.00
CONT_ASSIGN174911100.00
CONT_ASSIGN174911100.00
CONT_ASSIGN174911100.00
CONT_ASSIGN175011100.00
CONT_ASSIGN175011100.00
CONT_ASSIGN1750100.00
CONT_ASSIGN1750100.00
CONT_ASSIGN1750100.00
CONT_ASSIGN175111100.00
CONT_ASSIGN175111100.00
CONT_ASSIGN1751100.00
CONT_ASSIGN1751100.00
CONT_ASSIGN175111100.00
CONT_ASSIGN175211100.00
CONT_ASSIGN175211100.00
CONT_ASSIGN1752100.00
CONT_ASSIGN1752100.00
CONT_ASSIGN1752100.00
CONT_ASSIGN175411100.00
CONT_ASSIGN175411100.00
CONT_ASSIGN175411100.00
CONT_ASSIGN175411100.00
CONT_ASSIGN175411100.00
CONT_ASSIGN175511100.00
CONT_ASSIGN175511100.00
CONT_ASSIGN175511100.00
CONT_ASSIGN175511100.00
CONT_ASSIGN175511100.00
CONT_ASSIGN175611100.00
CONT_ASSIGN175611100.00
CONT_ASSIGN175611100.00
CONT_ASSIGN175611100.00
CONT_ASSIGN175611100.00
CONT_ASSIGN179711100.00
CONT_ASSIGN179911100.00
CONT_ASSIGN180011100.00
CONT_ASSIGN180111100.00
CONT_ASSIGN180211100.00
CONT_ASSIGN180311100.00
CONT_ASSIGN180511100.00
CONT_ASSIGN180611100.00
CONT_ASSIGN180711100.00
CONT_ASSIGN186311100.00

Click here to see the source line report.
Cond Coverage for Module : spi_device
TotalCoveredPercent
Conditions514384.31
Logical514384.31
Non-Logical00
Event00

 LINE       173
 EXPRESSION (payload_depth != '0)
            ----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T43,T44 

 LINE       702
 EXPRESSION (rst_ni & ((~rst_csb_buf)))
             ---1--   --------2-------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T6,T7 

 LINE       736
 EXPRESSION (rst_ni & ((~rst_tpm_csb_buf)))
             ---1--   ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT1,T4,T5 

 LINE       858
 EXPRESSION (cmd_only_dp_sel == DpUpload)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT15,T43,T44 

 LINE       885
 EXPRESSION (((!sck_csb)) && ((spi_mode == FlashMode) || (spi_mode == PassThrough)))
             ------1-----    ---------------------------2--------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT1,T6,T7 

 LINE       885
 SUB-EXPRESSION ((spi_mode == FlashMode) || (spi_mode == PassThrough))
                 -----------1-----------    ------------2------------
-1--2-StatusTests
00Not Covered
01CoveredT6,T7,T8
10CoveredT1,T2,T3 

 LINE       885
 SUB-EXPRESSION (spi_mode == FlashMode)
                -----------1-----------
-1-StatusTests
0CoveredT6,T7,T8
1CoveredT1,T2,T3 

 LINE       885
 SUB-EXPRESSION (spi_mode == PassThrough)
                ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT6,T7,T8 

 LINE       1044
 EXPRESSION (cfg_tpm_en && ((!sck_tpm_csb_buf)))
             -----1----    ----------2---------
-1--2-StatusTests
01CoveredT1,T12,T28
10CoveredT4,T5,T9
11CoveredT4,T5,T9 

 LINE       1217
 EXPRESSION (reg2hw.flash_status.busy.qe && reg2hw.flash_status.wel.qe && reg2hw.flash_status.status.qe)
             -------------1-------------    -------------2------------    --------------3--------------
-1--2--3-StatusTests
011Not Covered
101Not Covered
110Not Covered
111CoveredT7,T8,T11 

 LINE       1228
 EXPRESSION (cmd_only_dp_sel == DpWrEn)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT43,T74,T73 

 LINE       1229
 EXPRESSION (cmd_only_dp_sel == DpWrDi)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T20,T44 

 LINE       1442
 EXPRESSION (cmd_only_dp_sel == DpEn4B)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT52,T48,T96 

 LINE       1443
 EXPRESSION (cmd_only_dp_sel == DpEx4B)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT18,T20,T43 

 LINE       1607
 EXPRESSION (reg2hw.tpm_status.wrfifo_pending.qe & ((~reg2hw.tpm_status.wrfifo_pending.q)))
             -----------------1-----------------   -------------------2-------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT5,T25,T27 

 LINE       1725
 EXPRESSION ((i != SysSramFwEgress) && (i != SysSramFwIngress))
             -----------1----------    -----------2-----------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T2,T3 

 LINE       1725
 SUB-EXPRESSION (i != SysSramFwEgress)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       1725
 SUB-EXPRESSION (i != SysSramFwIngress)
                -----------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       1797
 EXPRESSION (tpm_rst_in_n | rst_spi_in_n)
             ------1-----   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T6,T7
10CoveredT1,T4,T5 

 LINE       1863
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------
-1--2-StatusTests
01CoveredT24,T97,T98
10CoveredT1,T3,T4
11CoveredT24,T99,T97
Toggle Coverage for Module : spi_device
TotalCoveredPercent
Totals 63 58 92.06
Total Bits 466 452 97.00
Total Bits 0->1 233 226 97.00
Total Bits 1->0 233 226 97.00

Ports 63 58 92.06
Port Bits 466 452 97.00
Port Bits 0->1 233 226 97.00
Port Bits 1->0 233 226 97.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T10,T21,T22 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T3,T4 Yes T3,T4,T5 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T3,T7,T11 Yes T3,T7,T11 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T3,T5 Yes T3,T5,T6 INPUT
tl_i.a_address[31:0] Yes Yes T3,T5,T7 Yes T3,T5,T7 INPUT
tl_i.a_source[7:0] Yes Yes T1,T3,T5 Yes T1,T3,T5 INPUT
tl_i.a_size[1:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T3,T4,T5 Yes T3,T4,T5 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T3,T38,T42 Yes T3,T38,T42 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T5,T7 Yes T1,T5,T7 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,T3 Yes T1,T3,T4 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T3,T5,T6 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T3,T5 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T3,T4 Yes T1,T3,T4 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T3,*T4,*T5 Yes T3,T4,T5 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T10,T24,T21 Yes T10,T24,T21 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T10,T24,T21 Yes T10,T24,T21 OUTPUT
cio_sck_i Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cio_csb_i Yes Yes T1,T6,T7 Yes T1,T6,T7 INPUT
cio_sd_o[3:0] Yes Yes T6,T7,T8 Yes T6,T7,T8 OUTPUT
cio_sd_en_o[3:0] Yes Yes T7,T8,T11 Yes T7,T8,T11 OUTPUT
cio_sd_i[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
cio_tpm_csb_i Yes Yes T1,T4,T5 Yes T1,T4,T5 INPUT
passthrough_o.s_en[0] Yes Yes *T6,*T7,*T8 Yes T6,T7,T8 OUTPUT
passthrough_o.s_en[3:1] No No No OUTPUT
passthrough_o.s[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
passthrough_o.csb_en No No No OUTPUT
passthrough_o.csb Yes Yes T1,T6,T7 Yes T1,T6,T7 OUTPUT
passthrough_o.sck_en No No No OUTPUT
passthrough_o.sck Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
passthrough_o.passthrough_en Yes Yes T15,T59,T51 Yes T6,T7,T8 OUTPUT
passthrough_i.s[3:0] Yes Yes T4,T5,T6 Yes T4,T5,T6 INPUT
intr_upload_cmdfifo_not_empty_o Yes Yes T22,T34,T35 Yes T22,T34,T35 OUTPUT
intr_upload_payload_not_empty_o Yes Yes T22,T34,T35 Yes T22,T34,T35 OUTPUT
intr_upload_payload_overflow_o Yes Yes T22,T34,T35 Yes T22,T34,T35 OUTPUT
intr_readbuf_watermark_o Yes Yes T22,T34,T35 Yes T22,T34,T35 OUTPUT
intr_readbuf_flip_o Yes Yes T22,T34,T35 Yes T22,T34,T35 OUTPUT
intr_tpm_header_not_empty_o Yes Yes T22,T34,T35 Yes T22,T34,T35 OUTPUT
intr_tpm_rdfifo_cmd_end_o Yes Yes T22,T34,T35 Yes T22,T34,T35 OUTPUT
intr_tpm_rdfifo_drop_o Yes Yes T22,T34,T35 Yes T22,T34,T35 OUTPUT
ram_cfg_i.b_ram_lcfg.cfg[3:0] Yes Yes T2 Yes T2 INPUT
ram_cfg_i.b_ram_lcfg.cfg_en Yes Yes T2 Yes T2 INPUT
ram_cfg_i.b_ram_lcfg.test Yes Yes T2 Yes T2 INPUT
ram_cfg_i.a_ram_lcfg.cfg[3:0] Yes Yes T2 Yes T2 INPUT
ram_cfg_i.a_ram_lcfg.cfg_en Yes Yes T2 Yes T2 INPUT
ram_cfg_i.a_ram_lcfg.test Yes Yes T2 Yes T2 INPUT
ram_cfg_i.b_ram_fcfg.cfg[3:0] Yes Yes T2 Yes T2 INPUT
ram_cfg_i.b_ram_fcfg.cfg_en Yes Yes T2 Yes T2 INPUT
ram_cfg_i.b_ram_fcfg.test Yes Yes T2 Yes T2 INPUT
ram_cfg_i.a_ram_fcfg.cfg[3:0] Yes Yes T2 Yes T2 INPUT
ram_cfg_i.a_ram_fcfg.cfg_en Yes Yes T2 Yes T2 INPUT
ram_cfg_i.a_ram_fcfg.test Yes Yes T2 Yes T2 INPUT
sck_monitor_o Yes Yes T4,T5,T6 Yes T4,T5,T6 OUTPUT
mbist_en_i Unreachable Unreachable Unreachable INPUT
scan_clk_i No No No INPUT
scan_rst_ni No No No INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range
Branch Coverage for Module : spi_device
Line No.TotalCoveredPercent
Branches 32 29 90.62
IF 539 3 3 100.00
IF 828 2 2 100.00
CASE 844 4 4 100.00
IF 885 3 3 100.00
CASE 901 7 5 71.43
IF 1028 2 2 100.00
IF 1044 5 4 80.00
IF 1078 2 2 100.00
IF 1725 2 2 100.00
IF 1735 2 2 100.00 



539            if (!rst_ni) begin
               -1-  
540              readbuf_addr_busclk <= '0;
                 ==>
541            end else if (sys_csb_deasserted_pulse) begin
                        -2-  
542              readbuf_addr_busclk <= readbuf_addr_sck;
                 ==>
543            end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T6,T7,T8
0 0 Covered T1,T2,T3 



828            if (!rst_spi_out_n) io_mode_outclk <= SingleIO;
               -1-  
               ==>
829            else                io_mode_outclk <= io_mode;
               ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T6,T7,T8 



844            unique case (cmd_dp_sel)
                      -1-  
845              DpReadCmd, DpReadSFDP: begin
846                // SRAM:: Remember this has glitch
847                // switch should happen only when clock gate is disabled.
848                flash_sram_l2m = sub_sram_l2m[IoModeReadCmd];
                   ==>
849                sub_sram_m2l[IoModeReadCmd] = flash_sram_m2l;
850              end
851        
852              DpUpload: begin
853                flash_sram_l2m = sub_sram_l2m[IoModeUpload];
                   ==>
854                sub_sram_m2l[IoModeUpload] = flash_sram_m2l;
855              end
856        
857              default: begin
858                if (cmd_only_dp_sel == DpUpload) begin
                   -2-  
859                  // Be ready to upload commands on the 8th command bit, when directed
860                  flash_sram_l2m = sub_sram_l2m[IoModeUpload];
                     ==>
861                  sub_sram_m2l[IoModeUpload] = flash_sram_m2l;
862                end else begin
863                  // DpNone, DpReadStatus, DpReadJEDEC
864                  flash_sram_l2m = '{default: '0 };
                     ==>

Branches:
-1--2-StatusTests
DpReadCmd DpReadSFDP - Covered T7,T8,T11
DpUpload - Covered T15,T43,T44
default 1 Covered T15,T43,T44
default 0 Covered T1,T2,T3 



885            if (!sck_csb && ((spi_mode == FlashMode) || (spi_mode == PassThrough))) begin
               -1-  
886              mem_b_l2m = flash_sram_l2m;
                 ==>
887              flash_sram_m2l = mem_b_m2l;
888            end else if (cfg_tpm_en) begin
                        -2-  
889              mem_b_l2m = tpm_sram_l2m;
                 ==>
890              tpm_sram_m2l = mem_b_m2l;
891            end
               MISSING_ELSE
               ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T6,T7
0 1 Covered T4,T5,T9
0 0 Covered T1,T2,T3 



901            unique case (spi_mode)
                      -1-  
902              FlashMode, PassThrough: begin
903                unique case (cmd_dp_sel)
                          -2-  
904                  DpNone: begin
905                    io_mode = sub_iomode[IoModeCmdParse];
                       ==>
906        
907                    sub_p2s_sent[IoModeCmdParse] = p2s_sent;
908        
909                  end
910                  DpReadCmd, DpReadSFDP: begin
911                    io_mode = sub_iomode[IoModeReadCmd];
                       ==>
912        
913                    p2s_valid = sub_p2s_valid[IoModeReadCmd];
914                    p2s_data  = sub_p2s_data[IoModeReadCmd];
915                    sub_p2s_sent[IoModeReadCmd] = p2s_sent;
916                  end
917                  DpReadStatus: begin
918                    io_mode = sub_iomode[IoModeStatus];
                       ==>
919        
920                    p2s_valid = sub_p2s_valid[IoModeStatus];
921                    p2s_data  = sub_p2s_data[IoModeStatus];
922                    sub_p2s_sent[IoModeStatus] = p2s_sent;
923        
924                  end
925        
926                  DpReadJEDEC: begin
927                    io_mode = sub_iomode[IoModeJedec];
                       ==>
928        
929                    p2s_valid = sub_p2s_valid[IoModeJedec];
930                    p2s_data  = sub_p2s_data[IoModeJedec];
931                    sub_p2s_sent[IoModeJedec] = p2s_sent;
932                  end
933        
934                  DpUpload: begin
935                    io_mode = sub_iomode[IoModeUpload];
                       ==>
936        
937                    p2s_valid = sub_p2s_valid[IoModeUpload];
938                    p2s_data  = sub_p2s_data[IoModeUpload];
939                    sub_p2s_sent[IoModeUpload] = p2s_sent;
940                  end
941                  // DpUnknown:
942                  default: begin
943                    io_mode = sub_iomode[IoModeCmdParse];
                       ==>
944        
945                    sub_p2s_sent[IoModeCmdParse] = p2s_sent;
946                  end
947                endcase
948              end
949        
950              default: begin
951                io_mode = SingleIO;
                   ==>

Branches:
-1--2-StatusTests
FlashMode PassThrough DpNone Covered T1,T2,T3
FlashMode PassThrough DpReadCmd DpReadSFDP Covered T7,T8,T11
FlashMode PassThrough DpReadStatus Covered T15,T43,T44
FlashMode PassThrough DpReadJEDEC Covered T43,T44,T74
FlashMode PassThrough DpUpload Covered T15,T43,T44
FlashMode PassThrough default Not Covered
default - Not Covered 



1028           if (cmd_read_pipeline_sel) begin
               -1-  
1029             internal_sd_out = internal_sd_stg2_q;
                 ==>
1030             internal_sd_en_out = internal_sd_en_stg2;
1031             intercept_en_out = intercept_en_stg2;
1032           end else begin
1033             internal_sd_out = internal_sd;
                 ==>

Branches:
-1-StatusTests
1 Covered T7,T8,T11
0 Covered T1,T2,T3 



1044           if (cfg_tpm_en && !sck_tpm_csb_buf) begin : miso_tpm
               -1-  
1045             // TPM transaction is on-going. MOSI, MISO is being used by TPM
1046             cio_sd_o    = {2'b 00, tpm_miso,    1'b 0};
                 ==>
1047             cio_sd_en_o = {2'b 00, tpm_miso_en, 1'b 0};
1048       
1049           end else begin : spi_out_flash_passthrough
1050             // SPI Flash, Passthrough modes
1051             unique case (spi_mode)
                        -2-  
1052               FlashMode: begin
1053                 cio_sd_o    = internal_sd_out;
                     ==>
1054                 cio_sd_en_o = internal_sd_en_out;
1055               end
1056       
1057               PassThrough: begin
1058                 if (intercept_en_out) begin
                     -3-  
1059                   cio_sd_o    = internal_sd_out;
                       ==>
1060                   cio_sd_en_o = internal_sd_en_out;
1061                 end else begin
1062                   cio_sd_o    = passthrough_sd;
                       ==>
1063                   cio_sd_en_o = passthrough_sd_en;
1064                 end
1065               end
1066       
1067               default: begin
1068                 cio_sd_o    = internal_sd;
                     ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T4,T5,T9
0 FlashMode - Covered T1,T2,T3
0 PassThrough 1 Covered T7,T8,T15
0 PassThrough 0 Covered T6,T7,T8
0 default - Not Covered 



1078           if (!rst_spi_out_n) intercept_en <= 1'b 0;
               -1-  
               ==>
1079           else                intercept_en <= |intercept;
               ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T6,T7,T8 



1725             if ((i != SysSramFwEgress) && (i != SysSramFwIngress)) begin
                 -1-  
1726               sys_sram_hw_req |= sys_sram_l2m[i].req;
                   ==>
1727             end
                 MISSING_ELSE
                 ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



1735           if (sys_sram_hw_req) begin
               -1-  
1736             // Fixed low priority. (Discussed in #10065)
1737             // When HW requests the SRAM access, lower the SW requests (and grant)
1738             sys_sram_req[SysSramFwEgress] = 1'b0;
                 ==>
1739             sys_sram_fw_gnt[SPI_DEVICE_EGRESS_BUFFER_IDX] = 1'b0;
1740             sys_sram_req[SysSramFwIngress] = 1'b0;
1741             sys_sram_fw_gnt[SPI_DEVICE_INGRESS_BUFFER_IDX] = 1'b0;
1742           end else begin
1743             sys_sram_fw_gnt[SPI_DEVICE_EGRESS_BUFFER_IDX] = sys_sram_gnt[SysSramFwEgress];
                 ==>

Branches:
-1-StatusTests
1 Covered T5,T13,T15
0 Covered T1,T2,T3

Assert Coverage for Module : spi_device
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 22 22 100.00 21 95.45
Cover properties 0 0 0
Cover sequences 0 0 0
Total 22 22 100.00 21 95.45



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertKnownO_A 417361488 417272405 0 0
CioSdoEnOKnown 417361488 417272405 0 0
CioSdoEnOffWhenInactive 417361488 417272405 0 0
FpvSecCmRegWeOnehotCheck_A 417361488 120 0 0
InterceptLevel_M 147322891 0 0 0
IntrReadbufFlipOKnown 417361488 417272405 0 0
IntrReadbufWatermarkOKnown 417361488 417272405 0 0
IntrTpmHeaderNotEmptyOKnown 417361488 417272405 0 0
IntrTpmRdfifoCmdEndOKnown 417361488 417272405 0 0
IntrTpmRdfifoDropOKnown 417361488 417272405 0 0
IntrUploadCmdfifoNotEmptyOKnown 417361488 417272405 0 0
IntrUploadPayloadNotEmptyOKnown 417361488 417272405 0 0
IntrUploadPayloadOverflowOKnown 417361488 417272405 0 0
PayloadStartIdxWidthMatch_A 975 975 0 0
SpiModeKnown_A 417361488 417272405 0 0
TpmEnableWhenTpmCsbIdle_M 417361488 332 0 0
g_sram_connect[0].ReqAlwaysAccepted_A 417361488 1830416 0 0
g_sram_connect[1].ReqAlwaysAccepted_A 417361488 178561 0 0
g_sram_connect[2].ReqAlwaysAccepted_A 417361488 2240 0 0
g_sram_connect[3].ReqAlwaysAccepted_A 417361488 1669 0 0
g_sram_connect[4].ReqAlwaysAccepted_A 417361488 197504 0 0
scanmodeKnown 417361488 417361488 0 0


AlertKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 417272405 0 0
T1 1210 1156 0 0
T2 1007 910 0 0
T3 2604 2504 0 0
T4 2417 2361 0 0
T5 3001 2924 0 0
T6 9435 9385 0 0
T7 9250 9171 0 0
T8 14054 13986 0 0
T9 48313 48237 0 0
T10 8193 5809 0 0

CioSdoEnOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 417272405 0 0
T1 1210 1156 0 0
T2 1007 910 0 0
T3 2604 2504 0 0
T4 2417 2361 0 0
T5 3001 2924 0 0
T6 9435 9385 0 0
T7 9250 9171 0 0
T8 14054 13986 0 0
T9 48313 48237 0 0
T10 8193 5809 0 0

CioSdoEnOffWhenInactive
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 417272405 0 0
T1 1210 1156 0 0
T2 1007 910 0 0
T3 2604 2504 0 0
T4 2417 2361 0 0
T5 3001 2924 0 0
T6 9435 9385 0 0
T7 9250 9171 0 0
T8 14054 13986 0 0
T9 48313 48237 0 0
T10 8193 5809 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 120 0 0
T10 8193 30 0 0
T11 10853 0 0 0
T12 1455 0 0 0
T13 1841 0 0 0
T14 14376 0 0 0
T15 276559 0 0 0
T16 144375 0 0 0
T21 0 20 0 0
T23 0 10 0 0
T24 1225 0 0 0
T25 83508 0 0 0
T32 0 30 0 0
T33 0 30 0 0
T38 2853 0 0 0

InterceptLevel_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 147322891 0 0 0

IntrReadbufFlipOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 417272405 0 0
T1 1210 1156 0 0
T2 1007 910 0 0
T3 2604 2504 0 0
T4 2417 2361 0 0
T5 3001 2924 0 0
T6 9435 9385 0 0
T7 9250 9171 0 0
T8 14054 13986 0 0
T9 48313 48237 0 0
T10 8193 5809 0 0

IntrReadbufWatermarkOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 417272405 0 0
T1 1210 1156 0 0
T2 1007 910 0 0
T3 2604 2504 0 0
T4 2417 2361 0 0
T5 3001 2924 0 0
T6 9435 9385 0 0
T7 9250 9171 0 0
T8 14054 13986 0 0
T9 48313 48237 0 0
T10 8193 5809 0 0

IntrTpmHeaderNotEmptyOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 417272405 0 0
T1 1210 1156 0 0
T2 1007 910 0 0
T3 2604 2504 0 0
T4 2417 2361 0 0
T5 3001 2924 0 0
T6 9435 9385 0 0
T7 9250 9171 0 0
T8 14054 13986 0 0
T9 48313 48237 0 0
T10 8193 5809 0 0

IntrTpmRdfifoCmdEndOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 417272405 0 0
T1 1210 1156 0 0
T2 1007 910 0 0
T3 2604 2504 0 0
T4 2417 2361 0 0
T5 3001 2924 0 0
T6 9435 9385 0 0
T7 9250 9171 0 0
T8 14054 13986 0 0
T9 48313 48237 0 0
T10 8193 5809 0 0

IntrTpmRdfifoDropOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 417272405 0 0
T1 1210 1156 0 0
T2 1007 910 0 0
T3 2604 2504 0 0
T4 2417 2361 0 0
T5 3001 2924 0 0
T6 9435 9385 0 0
T7 9250 9171 0 0
T8 14054 13986 0 0
T9 48313 48237 0 0
T10 8193 5809 0 0

IntrUploadCmdfifoNotEmptyOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 417272405 0 0
T1 1210 1156 0 0
T2 1007 910 0 0
T3 2604 2504 0 0
T4 2417 2361 0 0
T5 3001 2924 0 0
T6 9435 9385 0 0
T7 9250 9171 0 0
T8 14054 13986 0 0
T9 48313 48237 0 0
T10 8193 5809 0 0

IntrUploadPayloadNotEmptyOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 417272405 0 0
T1 1210 1156 0 0
T2 1007 910 0 0
T3 2604 2504 0 0
T4 2417 2361 0 0
T5 3001 2924 0 0
T6 9435 9385 0 0
T7 9250 9171 0 0
T8 14054 13986 0 0
T9 48313 48237 0 0
T10 8193 5809 0 0

IntrUploadPayloadOverflowOKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 417272405 0 0
T1 1210 1156 0 0
T2 1007 910 0 0
T3 2604 2504 0 0
T4 2417 2361 0 0
T5 3001 2924 0 0
T6 9435 9385 0 0
T7 9250 9171 0 0
T8 14054 13986 0 0
T9 48313 48237 0 0
T10 8193 5809 0 0

PayloadStartIdxWidthMatch_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 975 975 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T5 1 1 0 0
T6 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T9 1 1 0 0
T10 1 1 0 0

SpiModeKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 417272405 0 0
T1 1210 1156 0 0
T2 1007 910 0 0
T3 2604 2504 0 0
T4 2417 2361 0 0
T5 3001 2924 0 0
T6 9435 9385 0 0
T7 9250 9171 0 0
T8 14054 13986 0 0
T9 48313 48237 0 0
T10 8193 5809 0 0

TpmEnableWhenTpmCsbIdle_M
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 332 0 0
T4 2417 1 0 0
T5 3001 1 0 0
T6 9435 0 0 0
T7 9250 0 0 0
T8 14054 0 0 0
T9 48313 1 0 0
T10 8193 0 0 0
T11 10853 0 0 0
T12 1455 0 0 0
T13 0 1 0 0
T14 0 1 0 0
T24 1225 0 0 0
T25 0 1 0 0
T26 0 1 0 0
T27 0 1 0 0
T29 0 1 0 0
T30 0 1 0 0

g_sram_connect[0].ReqAlwaysAccepted_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 1830416 0 0
T3 2604 100 0 0
T4 2417 0 0 0
T5 3001 0 0 0
T6 9435 832 0 0
T7 9250 832 0 0
T8 14054 832 0 0
T9 48313 0 0 0
T10 8193 0 0 0
T11 10853 832 0 0
T12 1455 0 0 0
T15 0 832 0 0
T16 0 832 0 0
T17 0 832 0 0
T18 0 832 0 0
T38 0 100 0 0

g_sram_connect[1].ReqAlwaysAccepted_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 178561 0 0
T3 2604 100 0 0
T4 2417 0 0 0
T5 3001 45 0 0
T6 9435 0 0 0
T7 9250 0 0 0
T8 14054 0 0 0
T9 48313 0 0 0
T10 8193 0 0 0
T11 10853 0 0 0
T12 1455 0 0 0
T15 0 256 0 0
T25 0 626 0 0
T27 0 258 0 0
T30 0 58 0 0
T38 0 100 0 0
T42 0 100 0 0
T43 0 79 0 0
T44 0 192 0 0

g_sram_connect[2].ReqAlwaysAccepted_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 2240 0 0
T15 276559 6 0 0
T16 144375 0 0 0
T17 63590 0 0 0
T18 109329 0 0 0
T19 62386 0 0 0
T20 18908 0 0 0
T25 83508 0 0 0
T26 37801 0 0 0
T27 70684 0 0 0
T43 0 2 0 0
T44 0 5 0 0
T48 0 2 0 0
T51 0 2 0 0
T59 0 8 0 0
T73 0 3 0 0
T74 0 3 0 0
T92 0 10 0 0
T93 0 26 0 0
T100 2831 0 0 0

g_sram_connect[3].ReqAlwaysAccepted_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 1669 0 0
T15 276559 6 0 0
T16 144375 0 0 0
T17 63590 0 0 0
T18 109329 0 0 0
T19 62386 0 0 0
T20 18908 0 0 0
T25 83508 0 0 0
T26 37801 0 0 0
T27 70684 0 0 0
T43 0 2 0 0
T44 0 4 0 0
T51 0 2 0 0
T59 0 6 0 0
T73 0 2 0 0
T74 0 1 0 0
T92 0 9 0 0
T93 0 23 0 0
T100 2831 0 0 0
T101 0 2 0 0

g_sram_connect[4].ReqAlwaysAccepted_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 197504 0 0
T5 3001 41 0 0
T6 9435 0 0 0
T7 9250 0 0 0
T8 14054 0 0 0
T9 48313 0 0 0
T10 8193 0 0 0
T11 10853 0 0 0
T12 1455 0 0 0
T13 0 5 0 0
T24 1225 0 0 0
T25 0 1038 0 0
T27 0 412 0 0
T30 0 48 0 0
T38 2853 0 0 0
T69 0 1474 0 0
T70 0 39 0 0
T71 0 578 0 0
T72 0 456 0 0
T73 0 537 0 0

scanmodeKnown
NameAttemptsReal SuccessesFailuresIncomplete
Total 417361488 417361488 0 0
T1 1210 1210 0 0
T2 1007 1007 0 0
T3 2604 2604 0 0
T4 2417 2417 0 0
T5 3001 3001 0 0
T6 9435 9435 0 0
T7 9250 9250 0 0
T8 14054 14054 0 0
T9 48313 48313 0 0
T10 8193 8193 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%