Assert Coverage for Module : 
spi_device_csr_assert_fpv
Assertion Details
TlulOOBAddrErr_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
3123 | 
0 | 
0 | 
| T119 | 
4272 | 
143 | 
0 | 
0 | 
| T120 | 
4575 | 
6 | 
0 | 
0 | 
| T121 | 
10624 | 
205 | 
0 | 
0 | 
| T122 | 
9674 | 
121 | 
0 | 
0 | 
| T123 | 
17776 | 
199 | 
0 | 
0 | 
| T124 | 
4303 | 
120 | 
0 | 
0 | 
| T125 | 
20434 | 
241 | 
0 | 
0 | 
| T136 | 
2332 | 
7 | 
0 | 
0 | 
| T137 | 
9219 | 
5 | 
0 | 
0 | 
| T138 | 
10037 | 
5 | 
0 | 
0 | 
addr_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
1893 | 
0 | 
0 | 
| T104 | 
2312 | 
1 | 
0 | 
0 | 
| T137 | 
9219 | 
5 | 
0 | 
0 | 
| T138 | 
10037 | 
4 | 
0 | 
0 | 
| T143 | 
7355 | 
11 | 
0 | 
0 | 
| T144 | 
5607 | 
1 | 
0 | 
0 | 
| T147 | 
79037 | 
543 | 
0 | 
0 | 
| T150 | 
10395 | 
4 | 
0 | 
0 | 
| T151 | 
156895 | 
227 | 
0 | 
0 | 
| T176 | 
13629 | 
28 | 
0 | 
0 | 
| T177 | 
9780 | 
8 | 
0 | 
0 | 
addr_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
1970 | 
0 | 
0 | 
| T104 | 
2312 | 
3 | 
0 | 
0 | 
| T138 | 
10037 | 
7 | 
0 | 
0 | 
| T143 | 
7355 | 
12 | 
0 | 
0 | 
| T147 | 
79037 | 
544 | 
0 | 
0 | 
| T150 | 
10395 | 
14 | 
0 | 
0 | 
| T151 | 
156895 | 
192 | 
0 | 
0 | 
| T176 | 
13629 | 
42 | 
0 | 
0 | 
| T177 | 
9780 | 
10 | 
0 | 
0 | 
| T178 | 
4864 | 
5 | 
0 | 
0 | 
| T179 | 
14987 | 
35 | 
0 | 
0 | 
cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2564 | 
0 | 
0 | 
| T104 | 
2312 | 
3 | 
0 | 
0 | 
| T137 | 
9219 | 
20 | 
0 | 
0 | 
| T138 | 
10037 | 
10 | 
0 | 
0 | 
| T143 | 
7355 | 
23 | 
0 | 
0 | 
| T144 | 
5607 | 
3 | 
0 | 
0 | 
| T147 | 
79037 | 
520 | 
0 | 
0 | 
| T150 | 
10395 | 
20 | 
0 | 
0 | 
| T151 | 
156895 | 
262 | 
0 | 
0 | 
| T176 | 
13629 | 
46 | 
0 | 
0 | 
| T178 | 
4864 | 
5 | 
0 | 
0 | 
cmd_filter_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
9633 | 
0 | 
0 | 
| T104 | 
2312 | 
4 | 
0 | 
0 | 
| T137 | 
9219 | 
103 | 
0 | 
0 | 
| T138 | 
10037 | 
66 | 
0 | 
0 | 
| T143 | 
7355 | 
123 | 
0 | 
0 | 
| T144 | 
5607 | 
134 | 
0 | 
0 | 
| T147 | 
79037 | 
416 | 
0 | 
0 | 
| T150 | 
10395 | 
133 | 
0 | 
0 | 
| T151 | 
156895 | 
279 | 
0 | 
0 | 
| T176 | 
13629 | 
79 | 
0 | 
0 | 
| T178 | 
4864 | 
91 | 
0 | 
0 | 
cmd_filter_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
10246 | 
0 | 
0 | 
| T104 | 
2312 | 
4 | 
0 | 
0 | 
| T137 | 
9219 | 
98 | 
0 | 
0 | 
| T138 | 
10037 | 
7 | 
0 | 
0 | 
| T143 | 
7355 | 
127 | 
0 | 
0 | 
| T144 | 
5607 | 
125 | 
0 | 
0 | 
| T147 | 
79037 | 
514 | 
0 | 
0 | 
| T150 | 
10395 | 
143 | 
0 | 
0 | 
| T151 | 
156895 | 
267 | 
0 | 
0 | 
| T176 | 
13629 | 
24 | 
0 | 
0 | 
| T178 | 
4864 | 
138 | 
0 | 
0 | 
cmd_filter_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
11531 | 
0 | 
0 | 
| T125 | 
20434 | 
4 | 
0 | 
0 | 
| T137 | 
9219 | 
107 | 
0 | 
0 | 
| T138 | 
10037 | 
59 | 
0 | 
0 | 
| T143 | 
7355 | 
6 | 
0 | 
0 | 
| T147 | 
79037 | 
502 | 
0 | 
0 | 
| T150 | 
10395 | 
155 | 
0 | 
0 | 
| T151 | 
156895 | 
291 | 
0 | 
0 | 
| T176 | 
13629 | 
37 | 
0 | 
0 | 
| T177 | 
9780 | 
84 | 
0 | 
0 | 
| T178 | 
4864 | 
116 | 
0 | 
0 | 
cmd_filter_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
10630 | 
0 | 
0 | 
| T104 | 
2312 | 
8 | 
0 | 
0 | 
| T137 | 
9219 | 
128 | 
0 | 
0 | 
| T138 | 
10037 | 
57 | 
0 | 
0 | 
| T143 | 
7355 | 
117 | 
0 | 
0 | 
| T144 | 
5607 | 
129 | 
0 | 
0 | 
| T147 | 
79037 | 
514 | 
0 | 
0 | 
| T150 | 
10395 | 
197 | 
0 | 
0 | 
| T151 | 
156895 | 
341 | 
0 | 
0 | 
| T176 | 
13629 | 
35 | 
0 | 
0 | 
| T178 | 
4864 | 
5 | 
0 | 
0 | 
cmd_filter_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
11328 | 
0 | 
0 | 
| T104 | 
2312 | 
7 | 
0 | 
0 | 
| T123 | 
17776 | 
6 | 
0 | 
0 | 
| T137 | 
9219 | 
10 | 
0 | 
0 | 
| T138 | 
10037 | 
163 | 
0 | 
0 | 
| T143 | 
7355 | 
126 | 
0 | 
0 | 
| T144 | 
5607 | 
102 | 
0 | 
0 | 
| T147 | 
79037 | 
525 | 
0 | 
0 | 
| T150 | 
10395 | 
13 | 
0 | 
0 | 
| T151 | 
156895 | 
300 | 
0 | 
0 | 
| T178 | 
4864 | 
127 | 
0 | 
0 | 
cmd_filter_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
8757 | 
0 | 
0 | 
| T104 | 
2312 | 
8 | 
0 | 
0 | 
| T137 | 
9219 | 
63 | 
0 | 
0 | 
| T138 | 
10037 | 
60 | 
0 | 
0 | 
| T143 | 
7355 | 
138 | 
0 | 
0 | 
| T147 | 
79037 | 
460 | 
0 | 
0 | 
| T150 | 
10395 | 
100 | 
0 | 
0 | 
| T151 | 
156895 | 
309 | 
0 | 
0 | 
| T176 | 
13629 | 
33 | 
0 | 
0 | 
| T177 | 
9780 | 
73 | 
0 | 
0 | 
| T178 | 
4864 | 
6 | 
0 | 
0 | 
cmd_filter_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
9423 | 
0 | 
0 | 
| T104 | 
2312 | 
1 | 
0 | 
0 | 
| T137 | 
9219 | 
7 | 
0 | 
0 | 
| T138 | 
10037 | 
69 | 
0 | 
0 | 
| T143 | 
7355 | 
3 | 
0 | 
0 | 
| T144 | 
5607 | 
114 | 
0 | 
0 | 
| T147 | 
79037 | 
501 | 
0 | 
0 | 
| T150 | 
10395 | 
113 | 
0 | 
0 | 
| T151 | 
156895 | 
343 | 
0 | 
0 | 
| T176 | 
13629 | 
82 | 
0 | 
0 | 
| T178 | 
4864 | 
130 | 
0 | 
0 | 
cmd_filter_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
11007 | 
0 | 
0 | 
| T104 | 
2312 | 
9 | 
0 | 
0 | 
| T137 | 
9219 | 
64 | 
0 | 
0 | 
| T138 | 
10037 | 
63 | 
0 | 
0 | 
| T143 | 
7355 | 
144 | 
0 | 
0 | 
| T144 | 
5607 | 
121 | 
0 | 
0 | 
| T147 | 
79037 | 
495 | 
0 | 
0 | 
| T150 | 
10395 | 
139 | 
0 | 
0 | 
| T151 | 
156895 | 
268 | 
0 | 
0 | 
| T176 | 
13629 | 
28 | 
0 | 
0 | 
| T178 | 
4864 | 
137 | 
0 | 
0 | 
cmd_info_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
4874 | 
0 | 
0 | 
| T104 | 
2312 | 
8 | 
0 | 
0 | 
| T123 | 
17776 | 
8 | 
0 | 
0 | 
| T137 | 
9219 | 
60 | 
0 | 
0 | 
| T138 | 
10037 | 
23 | 
0 | 
0 | 
| T143 | 
7355 | 
71 | 
0 | 
0 | 
| T144 | 
5607 | 
37 | 
0 | 
0 | 
| T147 | 
79037 | 
490 | 
0 | 
0 | 
| T150 | 
10395 | 
30 | 
0 | 
0 | 
| T151 | 
156895 | 
317 | 
0 | 
0 | 
| T176 | 
13629 | 
35 | 
0 | 
0 | 
cmd_info_10_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5053 | 
0 | 
0 | 
| T104 | 
2312 | 
6 | 
0 | 
0 | 
| T137 | 
9219 | 
38 | 
0 | 
0 | 
| T138 | 
10037 | 
59 | 
0 | 
0 | 
| T143 | 
7355 | 
45 | 
0 | 
0 | 
| T144 | 
5607 | 
47 | 
0 | 
0 | 
| T147 | 
79037 | 
516 | 
0 | 
0 | 
| T150 | 
10395 | 
67 | 
0 | 
0 | 
| T151 | 
156895 | 
286 | 
0 | 
0 | 
| T176 | 
13629 | 
27 | 
0 | 
0 | 
| T178 | 
4864 | 
2 | 
0 | 
0 | 
cmd_info_11_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
4961 | 
0 | 
0 | 
| T104 | 
2312 | 
6 | 
0 | 
0 | 
| T125 | 
20434 | 
6 | 
0 | 
0 | 
| T137 | 
9219 | 
46 | 
0 | 
0 | 
| T138 | 
10037 | 
48 | 
0 | 
0 | 
| T143 | 
7355 | 
45 | 
0 | 
0 | 
| T144 | 
5607 | 
7 | 
0 | 
0 | 
| T147 | 
79037 | 
504 | 
0 | 
0 | 
| T150 | 
10395 | 
55 | 
0 | 
0 | 
| T151 | 
156895 | 
224 | 
0 | 
0 | 
| T178 | 
4864 | 
2 | 
0 | 
0 | 
cmd_info_12_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5228 | 
0 | 
0 | 
| T104 | 
2312 | 
6 | 
0 | 
0 | 
| T137 | 
9219 | 
17 | 
0 | 
0 | 
| T138 | 
10037 | 
38 | 
0 | 
0 | 
| T143 | 
7355 | 
56 | 
0 | 
0 | 
| T144 | 
5607 | 
48 | 
0 | 
0 | 
| T147 | 
79037 | 
481 | 
0 | 
0 | 
| T150 | 
10395 | 
62 | 
0 | 
0 | 
| T151 | 
156895 | 
276 | 
0 | 
0 | 
| T176 | 
13629 | 
48 | 
0 | 
0 | 
| T178 | 
4864 | 
4 | 
0 | 
0 | 
cmd_info_13_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5360 | 
0 | 
0 | 
| T104 | 
2312 | 
8 | 
0 | 
0 | 
| T137 | 
9219 | 
47 | 
0 | 
0 | 
| T138 | 
10037 | 
53 | 
0 | 
0 | 
| T143 | 
7355 | 
80 | 
0 | 
0 | 
| T144 | 
5607 | 
33 | 
0 | 
0 | 
| T147 | 
79037 | 
525 | 
0 | 
0 | 
| T150 | 
10395 | 
41 | 
0 | 
0 | 
| T151 | 
156895 | 
296 | 
0 | 
0 | 
| T176 | 
13629 | 
87 | 
0 | 
0 | 
| T178 | 
4864 | 
9 | 
0 | 
0 | 
cmd_info_14_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5697 | 
0 | 
0 | 
| T104 | 
2312 | 
6 | 
0 | 
0 | 
| T137 | 
9219 | 
83 | 
0 | 
0 | 
| T138 | 
10037 | 
47 | 
0 | 
0 | 
| T143 | 
7355 | 
12 | 
0 | 
0 | 
| T144 | 
5607 | 
76 | 
0 | 
0 | 
| T147 | 
79037 | 
522 | 
0 | 
0 | 
| T150 | 
10395 | 
33 | 
0 | 
0 | 
| T151 | 
156895 | 
285 | 
0 | 
0 | 
| T176 | 
13629 | 
45 | 
0 | 
0 | 
| T178 | 
4864 | 
56 | 
0 | 
0 | 
cmd_info_15_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
4904 | 
0 | 
0 | 
| T104 | 
2312 | 
1 | 
0 | 
0 | 
| T137 | 
9219 | 
4 | 
0 | 
0 | 
| T138 | 
10037 | 
21 | 
0 | 
0 | 
| T143 | 
7355 | 
56 | 
0 | 
0 | 
| T144 | 
5607 | 
50 | 
0 | 
0 | 
| T147 | 
79037 | 
495 | 
0 | 
0 | 
| T150 | 
10395 | 
35 | 
0 | 
0 | 
| T151 | 
156895 | 
261 | 
0 | 
0 | 
| T176 | 
13629 | 
36 | 
0 | 
0 | 
| T178 | 
4864 | 
6 | 
0 | 
0 | 
cmd_info_16_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
4681 | 
0 | 
0 | 
| T104 | 
2312 | 
4 | 
0 | 
0 | 
| T137 | 
9219 | 
11 | 
0 | 
0 | 
| T138 | 
10037 | 
19 | 
0 | 
0 | 
| T143 | 
7355 | 
52 | 
0 | 
0 | 
| T147 | 
79037 | 
481 | 
0 | 
0 | 
| T150 | 
10395 | 
6 | 
0 | 
0 | 
| T151 | 
156895 | 
287 | 
0 | 
0 | 
| T176 | 
13629 | 
40 | 
0 | 
0 | 
| T177 | 
9780 | 
59 | 
0 | 
0 | 
| T178 | 
4864 | 
3 | 
0 | 
0 | 
cmd_info_17_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5212 | 
0 | 
0 | 
| T104 | 
2312 | 
1 | 
0 | 
0 | 
| T137 | 
9219 | 
4 | 
0 | 
0 | 
| T138 | 
10037 | 
36 | 
0 | 
0 | 
| T143 | 
7355 | 
59 | 
0 | 
0 | 
| T144 | 
5607 | 
40 | 
0 | 
0 | 
| T147 | 
79037 | 
520 | 
0 | 
0 | 
| T150 | 
10395 | 
33 | 
0 | 
0 | 
| T151 | 
156895 | 
317 | 
0 | 
0 | 
| T176 | 
13629 | 
62 | 
0 | 
0 | 
| T178 | 
4864 | 
43 | 
0 | 
0 | 
cmd_info_18_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5122 | 
0 | 
0 | 
| T104 | 
2312 | 
2 | 
0 | 
0 | 
| T137 | 
9219 | 
48 | 
0 | 
0 | 
| T138 | 
10037 | 
38 | 
0 | 
0 | 
| T143 | 
7355 | 
40 | 
0 | 
0 | 
| T144 | 
5607 | 
43 | 
0 | 
0 | 
| T147 | 
79037 | 
516 | 
0 | 
0 | 
| T150 | 
10395 | 
79 | 
0 | 
0 | 
| T151 | 
156895 | 
335 | 
0 | 
0 | 
| T176 | 
13629 | 
43 | 
0 | 
0 | 
| T178 | 
4864 | 
2 | 
0 | 
0 | 
cmd_info_19_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5030 | 
0 | 
0 | 
| T104 | 
2312 | 
4 | 
0 | 
0 | 
| T137 | 
9219 | 
12 | 
0 | 
0 | 
| T138 | 
10037 | 
33 | 
0 | 
0 | 
| T143 | 
7355 | 
85 | 
0 | 
0 | 
| T144 | 
5607 | 
46 | 
0 | 
0 | 
| T147 | 
79037 | 
525 | 
0 | 
0 | 
| T150 | 
10395 | 
107 | 
0 | 
0 | 
| T151 | 
156895 | 
226 | 
0 | 
0 | 
| T176 | 
13629 | 
30 | 
0 | 
0 | 
| T178 | 
4864 | 
56 | 
0 | 
0 | 
cmd_info_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
4982 | 
0 | 
0 | 
| T104 | 
2312 | 
5 | 
0 | 
0 | 
| T137 | 
9219 | 
54 | 
0 | 
0 | 
| T138 | 
10037 | 
73 | 
0 | 
0 | 
| T143 | 
7355 | 
5 | 
0 | 
0 | 
| T144 | 
5607 | 
6 | 
0 | 
0 | 
| T147 | 
79037 | 
455 | 
0 | 
0 | 
| T150 | 
10395 | 
48 | 
0 | 
0 | 
| T151 | 
156895 | 
275 | 
0 | 
0 | 
| T176 | 
13629 | 
50 | 
0 | 
0 | 
| T178 | 
4864 | 
53 | 
0 | 
0 | 
cmd_info_20_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5596 | 
0 | 
0 | 
| T137 | 
9219 | 
38 | 
0 | 
0 | 
| T138 | 
10037 | 
34 | 
0 | 
0 | 
| T143 | 
7355 | 
33 | 
0 | 
0 | 
| T144 | 
5607 | 
41 | 
0 | 
0 | 
| T147 | 
79037 | 
540 | 
0 | 
0 | 
| T150 | 
10395 | 
68 | 
0 | 
0 | 
| T151 | 
156895 | 
258 | 
0 | 
0 | 
| T176 | 
13629 | 
42 | 
0 | 
0 | 
| T177 | 
9780 | 
50 | 
0 | 
0 | 
| T178 | 
4864 | 
52 | 
0 | 
0 | 
cmd_info_21_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5081 | 
0 | 
0 | 
| T104 | 
2312 | 
5 | 
0 | 
0 | 
| T137 | 
9219 | 
85 | 
0 | 
0 | 
| T138 | 
10037 | 
2 | 
0 | 
0 | 
| T143 | 
7355 | 
69 | 
0 | 
0 | 
| T144 | 
5607 | 
6 | 
0 | 
0 | 
| T147 | 
79037 | 
506 | 
0 | 
0 | 
| T150 | 
10395 | 
24 | 
0 | 
0 | 
| T151 | 
156895 | 
274 | 
0 | 
0 | 
| T176 | 
13629 | 
6 | 
0 | 
0 | 
| T178 | 
4864 | 
52 | 
0 | 
0 | 
cmd_info_22_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5425 | 
0 | 
0 | 
| T104 | 
2312 | 
1 | 
0 | 
0 | 
| T137 | 
9219 | 
26 | 
0 | 
0 | 
| T138 | 
10037 | 
43 | 
0 | 
0 | 
| T143 | 
7355 | 
90 | 
0 | 
0 | 
| T144 | 
5607 | 
2 | 
0 | 
0 | 
| T147 | 
79037 | 
496 | 
0 | 
0 | 
| T150 | 
10395 | 
68 | 
0 | 
0 | 
| T151 | 
156895 | 
308 | 
0 | 
0 | 
| T176 | 
13629 | 
80 | 
0 | 
0 | 
| T178 | 
4864 | 
6 | 
0 | 
0 | 
cmd_info_23_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5459 | 
0 | 
0 | 
| T104 | 
2312 | 
5 | 
0 | 
0 | 
| T138 | 
10037 | 
39 | 
0 | 
0 | 
| T143 | 
7355 | 
97 | 
0 | 
0 | 
| T144 | 
5607 | 
7 | 
0 | 
0 | 
| T147 | 
79037 | 
525 | 
0 | 
0 | 
| T150 | 
10395 | 
60 | 
0 | 
0 | 
| T151 | 
156895 | 
278 | 
0 | 
0 | 
| T176 | 
13629 | 
70 | 
0 | 
0 | 
| T177 | 
9780 | 
22 | 
0 | 
0 | 
| T178 | 
4864 | 
50 | 
0 | 
0 | 
cmd_info_2_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5426 | 
0 | 
0 | 
| T104 | 
2312 | 
2 | 
0 | 
0 | 
| T137 | 
9219 | 
30 | 
0 | 
0 | 
| T138 | 
10037 | 
32 | 
0 | 
0 | 
| T143 | 
7355 | 
65 | 
0 | 
0 | 
| T144 | 
5607 | 
60 | 
0 | 
0 | 
| T147 | 
79037 | 
522 | 
0 | 
0 | 
| T150 | 
10395 | 
39 | 
0 | 
0 | 
| T151 | 
156895 | 
266 | 
0 | 
0 | 
| T176 | 
13629 | 
56 | 
0 | 
0 | 
| T178 | 
4864 | 
4 | 
0 | 
0 | 
cmd_info_3_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5131 | 
0 | 
0 | 
| T104 | 
2312 | 
7 | 
0 | 
0 | 
| T137 | 
9219 | 
38 | 
0 | 
0 | 
| T138 | 
10037 | 
59 | 
0 | 
0 | 
| T143 | 
7355 | 
44 | 
0 | 
0 | 
| T144 | 
5607 | 
57 | 
0 | 
0 | 
| T147 | 
79037 | 
496 | 
0 | 
0 | 
| T150 | 
10395 | 
47 | 
0 | 
0 | 
| T151 | 
156895 | 
300 | 
0 | 
0 | 
| T176 | 
13629 | 
59 | 
0 | 
0 | 
| T178 | 
4864 | 
55 | 
0 | 
0 | 
cmd_info_4_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5462 | 
0 | 
0 | 
| T104 | 
2312 | 
7 | 
0 | 
0 | 
| T137 | 
9219 | 
19 | 
0 | 
0 | 
| T138 | 
10037 | 
82 | 
0 | 
0 | 
| T143 | 
7355 | 
112 | 
0 | 
0 | 
| T144 | 
5607 | 
36 | 
0 | 
0 | 
| T147 | 
79037 | 
493 | 
0 | 
0 | 
| T150 | 
10395 | 
7 | 
0 | 
0 | 
| T151 | 
156895 | 
256 | 
0 | 
0 | 
| T176 | 
13629 | 
38 | 
0 | 
0 | 
| T177 | 
9780 | 
17 | 
0 | 
0 | 
cmd_info_5_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5482 | 
0 | 
0 | 
| T104 | 
2312 | 
3 | 
0 | 
0 | 
| T137 | 
9219 | 
30 | 
0 | 
0 | 
| T138 | 
10037 | 
60 | 
0 | 
0 | 
| T143 | 
7355 | 
59 | 
0 | 
0 | 
| T144 | 
5607 | 
55 | 
0 | 
0 | 
| T147 | 
79037 | 
476 | 
0 | 
0 | 
| T150 | 
10395 | 
63 | 
0 | 
0 | 
| T151 | 
156895 | 
244 | 
0 | 
0 | 
| T176 | 
13629 | 
59 | 
0 | 
0 | 
| T178 | 
4864 | 
3 | 
0 | 
0 | 
cmd_info_6_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5446 | 
0 | 
0 | 
| T133 | 
14828 | 
9 | 
0 | 
0 | 
| T137 | 
9219 | 
9 | 
0 | 
0 | 
| T138 | 
10037 | 
40 | 
0 | 
0 | 
| T143 | 
7355 | 
99 | 
0 | 
0 | 
| T144 | 
5607 | 
38 | 
0 | 
0 | 
| T147 | 
79037 | 
502 | 
0 | 
0 | 
| T150 | 
10395 | 
58 | 
0 | 
0 | 
| T151 | 
156895 | 
308 | 
0 | 
0 | 
| T176 | 
13629 | 
6 | 
0 | 
0 | 
| T178 | 
4864 | 
3 | 
0 | 
0 | 
cmd_info_7_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
4920 | 
0 | 
0 | 
| T104 | 
2312 | 
8 | 
0 | 
0 | 
| T137 | 
9219 | 
35 | 
0 | 
0 | 
| T138 | 
10037 | 
75 | 
0 | 
0 | 
| T143 | 
7355 | 
78 | 
0 | 
0 | 
| T144 | 
5607 | 
3 | 
0 | 
0 | 
| T147 | 
79037 | 
445 | 
0 | 
0 | 
| T150 | 
10395 | 
55 | 
0 | 
0 | 
| T151 | 
156895 | 
314 | 
0 | 
0 | 
| T176 | 
13629 | 
11 | 
0 | 
0 | 
| T178 | 
4864 | 
6 | 
0 | 
0 | 
cmd_info_8_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5433 | 
0 | 
0 | 
| T104 | 
2312 | 
6 | 
0 | 
0 | 
| T137 | 
9219 | 
35 | 
0 | 
0 | 
| T138 | 
10037 | 
22 | 
0 | 
0 | 
| T143 | 
7355 | 
7 | 
0 | 
0 | 
| T144 | 
5607 | 
41 | 
0 | 
0 | 
| T147 | 
79037 | 
514 | 
0 | 
0 | 
| T150 | 
10395 | 
11 | 
0 | 
0 | 
| T151 | 
156895 | 
301 | 
0 | 
0 | 
| T176 | 
13629 | 
50 | 
0 | 
0 | 
| T178 | 
4864 | 
34 | 
0 | 
0 | 
cmd_info_9_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
5087 | 
0 | 
0 | 
| T104 | 
2312 | 
4 | 
0 | 
0 | 
| T137 | 
9219 | 
37 | 
0 | 
0 | 
| T138 | 
10037 | 
39 | 
0 | 
0 | 
| T143 | 
7355 | 
57 | 
0 | 
0 | 
| T144 | 
5607 | 
48 | 
0 | 
0 | 
| T147 | 
79037 | 
488 | 
0 | 
0 | 
| T150 | 
10395 | 
35 | 
0 | 
0 | 
| T151 | 
156895 | 
284 | 
0 | 
0 | 
| T176 | 
13629 | 
43 | 
0 | 
0 | 
| T178 | 
4864 | 
3 | 
0 | 
0 | 
cmd_info_en4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2121 | 
0 | 
0 | 
| T104 | 
2312 | 
3 | 
0 | 
0 | 
| T137 | 
9219 | 
4 | 
0 | 
0 | 
| T138 | 
10037 | 
9 | 
0 | 
0 | 
| T143 | 
7355 | 
7 | 
0 | 
0 | 
| T144 | 
5607 | 
2 | 
0 | 
0 | 
| T147 | 
79037 | 
444 | 
0 | 
0 | 
| T150 | 
10395 | 
3 | 
0 | 
0 | 
| T151 | 
156895 | 
237 | 
0 | 
0 | 
| T176 | 
13629 | 
93 | 
0 | 
0 | 
| T178 | 
4864 | 
5 | 
0 | 
0 | 
cmd_info_ex4b_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2222 | 
0 | 
0 | 
| T104 | 
2312 | 
3 | 
0 | 
0 | 
| T137 | 
9219 | 
6 | 
0 | 
0 | 
| T138 | 
10037 | 
20 | 
0 | 
0 | 
| T143 | 
7355 | 
21 | 
0 | 
0 | 
| T144 | 
5607 | 
1 | 
0 | 
0 | 
| T147 | 
79037 | 
450 | 
0 | 
0 | 
| T150 | 
10395 | 
12 | 
0 | 
0 | 
| T151 | 
156895 | 
292 | 
0 | 
0 | 
| T176 | 
13629 | 
37 | 
0 | 
0 | 
| T178 | 
4864 | 
3 | 
0 | 
0 | 
cmd_info_wrdi_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2271 | 
0 | 
0 | 
| T104 | 
2312 | 
6 | 
0 | 
0 | 
| T137 | 
9219 | 
6 | 
0 | 
0 | 
| T138 | 
10037 | 
9 | 
0 | 
0 | 
| T143 | 
7355 | 
20 | 
0 | 
0 | 
| T144 | 
5607 | 
1 | 
0 | 
0 | 
| T147 | 
79037 | 
509 | 
0 | 
0 | 
| T150 | 
10395 | 
13 | 
0 | 
0 | 
| T151 | 
156895 | 
238 | 
0 | 
0 | 
| T176 | 
13629 | 
85 | 
0 | 
0 | 
| T178 | 
4864 | 
5 | 
0 | 
0 | 
cmd_info_wren_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2237 | 
0 | 
0 | 
| T104 | 
2312 | 
6 | 
0 | 
0 | 
| T137 | 
9219 | 
6 | 
0 | 
0 | 
| T138 | 
10037 | 
13 | 
0 | 
0 | 
| T143 | 
7355 | 
15 | 
0 | 
0 | 
| T144 | 
5607 | 
9 | 
0 | 
0 | 
| T147 | 
79037 | 
483 | 
0 | 
0 | 
| T150 | 
10395 | 
11 | 
0 | 
0 | 
| T151 | 
156895 | 
299 | 
0 | 
0 | 
| T176 | 
13629 | 
26 | 
0 | 
0 | 
| T178 | 
4864 | 
7 | 
0 | 
0 | 
intercept_en_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2763 | 
0 | 
0 | 
| T104 | 
2312 | 
5 | 
0 | 
0 | 
| T137 | 
9219 | 
15 | 
0 | 
0 | 
| T138 | 
10037 | 
9 | 
0 | 
0 | 
| T143 | 
7355 | 
30 | 
0 | 
0 | 
| T144 | 
5607 | 
23 | 
0 | 
0 | 
| T147 | 
79037 | 
516 | 
0 | 
0 | 
| T150 | 
10395 | 
13 | 
0 | 
0 | 
| T151 | 
156895 | 
284 | 
0 | 
0 | 
| T176 | 
13629 | 
33 | 
0 | 
0 | 
| T178 | 
4864 | 
12 | 
0 | 
0 | 
intr_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
4906 | 
0 | 
0 | 
| T22 | 
5123 | 
21 | 
0 | 
0 | 
| T23 | 
3944 | 
0 | 
0 | 
0 | 
| T37 | 
0 | 
20 | 
0 | 
0 | 
| T46 | 
135606 | 
0 | 
0 | 
0 | 
| T55 | 
32958 | 
0 | 
0 | 
0 | 
| T70 | 
20170 | 
0 | 
0 | 
0 | 
| T97 | 
959 | 
0 | 
0 | 
0 | 
| T107 | 
4307 | 
0 | 
0 | 
0 | 
| T129 | 
2790 | 
0 | 
0 | 
0 | 
| T180 | 
0 | 
13 | 
0 | 
0 | 
| T181 | 
0 | 
7 | 
0 | 
0 | 
| T182 | 
0 | 
91 | 
0 | 
0 | 
| T183 | 
0 | 
58 | 
0 | 
0 | 
| T184 | 
0 | 
21 | 
0 | 
0 | 
| T185 | 
0 | 
47 | 
0 | 
0 | 
| T186 | 
0 | 
5 | 
0 | 
0 | 
| T187 | 
0 | 
25 | 
0 | 
0 | 
| T188 | 
980 | 
0 | 
0 | 
0 | 
| T189 | 
2437 | 
0 | 
0 | 
0 | 
jedec_cc_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2298 | 
0 | 
0 | 
| T104 | 
2312 | 
3 | 
0 | 
0 | 
| T137 | 
9219 | 
7 | 
0 | 
0 | 
| T138 | 
10037 | 
9 | 
0 | 
0 | 
| T143 | 
7355 | 
3 | 
0 | 
0 | 
| T144 | 
5607 | 
8 | 
0 | 
0 | 
| T147 | 
79037 | 
523 | 
0 | 
0 | 
| T150 | 
10395 | 
6 | 
0 | 
0 | 
| T151 | 
156895 | 
304 | 
0 | 
0 | 
| T176 | 
13629 | 
81 | 
0 | 
0 | 
| T178 | 
4864 | 
6 | 
0 | 
0 | 
jedec_id_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2290 | 
0 | 
0 | 
| T104 | 
2312 | 
1 | 
0 | 
0 | 
| T138 | 
10037 | 
6 | 
0 | 
0 | 
| T143 | 
7355 | 
1 | 
0 | 
0 | 
| T144 | 
5607 | 
12 | 
0 | 
0 | 
| T147 | 
79037 | 
501 | 
0 | 
0 | 
| T150 | 
10395 | 
10 | 
0 | 
0 | 
| T151 | 
156895 | 
260 | 
0 | 
0 | 
| T176 | 
13629 | 
53 | 
0 | 
0 | 
| T177 | 
9780 | 
19 | 
0 | 
0 | 
| T178 | 
4864 | 
4 | 
0 | 
0 | 
mailbox_addr_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2083 | 
0 | 
0 | 
| T104 | 
2312 | 
2 | 
0 | 
0 | 
| T137 | 
9219 | 
1 | 
0 | 
0 | 
| T138 | 
10037 | 
12 | 
0 | 
0 | 
| T143 | 
7355 | 
9 | 
0 | 
0 | 
| T144 | 
5607 | 
3 | 
0 | 
0 | 
| T147 | 
79037 | 
491 | 
0 | 
0 | 
| T150 | 
10395 | 
6 | 
0 | 
0 | 
| T151 | 
156895 | 
307 | 
0 | 
0 | 
| T176 | 
13629 | 
12 | 
0 | 
0 | 
| T179 | 
14987 | 
23 | 
0 | 
0 | 
payload_swap_data_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
1957 | 
0 | 
0 | 
| T104 | 
2312 | 
7 | 
0 | 
0 | 
| T137 | 
9219 | 
12 | 
0 | 
0 | 
| T138 | 
10037 | 
4 | 
0 | 
0 | 
| T143 | 
7355 | 
11 | 
0 | 
0 | 
| T144 | 
5607 | 
9 | 
0 | 
0 | 
| T147 | 
79037 | 
476 | 
0 | 
0 | 
| T150 | 
10395 | 
4 | 
0 | 
0 | 
| T151 | 
156895 | 
261 | 
0 | 
0 | 
| T176 | 
13629 | 
66 | 
0 | 
0 | 
| T178 | 
4864 | 
4 | 
0 | 
0 | 
payload_swap_mask_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2143 | 
0 | 
0 | 
| T104 | 
2312 | 
8 | 
0 | 
0 | 
| T125 | 
20434 | 
6 | 
0 | 
0 | 
| T137 | 
9219 | 
9 | 
0 | 
0 | 
| T138 | 
10037 | 
9 | 
0 | 
0 | 
| T143 | 
7355 | 
4 | 
0 | 
0 | 
| T144 | 
5607 | 
4 | 
0 | 
0 | 
| T147 | 
79037 | 
514 | 
0 | 
0 | 
| T150 | 
10395 | 
18 | 
0 | 
0 | 
| T151 | 
156895 | 
315 | 
0 | 
0 | 
| T178 | 
4864 | 
6 | 
0 | 
0 | 
read_threshold_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2160 | 
0 | 
0 | 
| T104 | 
2312 | 
2 | 
0 | 
0 | 
| T137 | 
9219 | 
6 | 
0 | 
0 | 
| T138 | 
10037 | 
13 | 
0 | 
0 | 
| T143 | 
7355 | 
15 | 
0 | 
0 | 
| T147 | 
79037 | 
505 | 
0 | 
0 | 
| T150 | 
10395 | 
7 | 
0 | 
0 | 
| T151 | 
156895 | 
335 | 
0 | 
0 | 
| T176 | 
13629 | 
63 | 
0 | 
0 | 
| T177 | 
9780 | 
13 | 
0 | 
0 | 
| T179 | 
14987 | 
21 | 
0 | 
0 | 
tpm_access_0_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2663 | 
0 | 
0 | 
| T137 | 
9219 | 
15 | 
0 | 
0 | 
| T138 | 
10037 | 
7 | 
0 | 
0 | 
| T143 | 
7355 | 
33 | 
0 | 
0 | 
| T144 | 
5607 | 
2 | 
0 | 
0 | 
| T147 | 
79037 | 
435 | 
0 | 
0 | 
| T150 | 
10395 | 
28 | 
0 | 
0 | 
| T151 | 
156895 | 
248 | 
0 | 
0 | 
| T176 | 
13629 | 
50 | 
0 | 
0 | 
| T177 | 
9780 | 
9 | 
0 | 
0 | 
| T178 | 
4864 | 
10 | 
0 | 
0 | 
tpm_access_1_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
1998 | 
0 | 
0 | 
| T104 | 
2312 | 
6 | 
0 | 
0 | 
| T137 | 
9219 | 
14 | 
0 | 
0 | 
| T138 | 
10037 | 
9 | 
0 | 
0 | 
| T143 | 
7355 | 
7 | 
0 | 
0 | 
| T147 | 
79037 | 
483 | 
0 | 
0 | 
| T150 | 
10395 | 
4 | 
0 | 
0 | 
| T151 | 
156895 | 
282 | 
0 | 
0 | 
| T176 | 
13629 | 
53 | 
0 | 
0 | 
| T177 | 
9780 | 
7 | 
0 | 
0 | 
| T178 | 
4864 | 
5 | 
0 | 
0 | 
tpm_cfg_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2915 | 
0 | 
0 | 
| T104 | 
2312 | 
1 | 
0 | 
0 | 
| T137 | 
9219 | 
12 | 
0 | 
0 | 
| T138 | 
10037 | 
5 | 
0 | 
0 | 
| T143 | 
7355 | 
25 | 
0 | 
0 | 
| T144 | 
5607 | 
19 | 
0 | 
0 | 
| T147 | 
79037 | 
514 | 
0 | 
0 | 
| T150 | 
10395 | 
44 | 
0 | 
0 | 
| T151 | 
156895 | 
248 | 
0 | 
0 | 
| T176 | 
13629 | 
46 | 
0 | 
0 | 
| T178 | 
4864 | 
11 | 
0 | 
0 | 
tpm_did_vid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2246 | 
0 | 
0 | 
| T137 | 
9219 | 
12 | 
0 | 
0 | 
| T138 | 
10037 | 
11 | 
0 | 
0 | 
| T143 | 
7355 | 
10 | 
0 | 
0 | 
| T144 | 
5607 | 
13 | 
0 | 
0 | 
| T147 | 
79037 | 
491 | 
0 | 
0 | 
| T150 | 
10395 | 
4 | 
0 | 
0 | 
| T151 | 
156895 | 
277 | 
0 | 
0 | 
| T176 | 
13629 | 
14 | 
0 | 
0 | 
| T177 | 
9780 | 
8 | 
0 | 
0 | 
| T178 | 
4864 | 
7 | 
0 | 
0 | 
tpm_int_enable_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
1975 | 
0 | 
0 | 
| T104 | 
2312 | 
3 | 
0 | 
0 | 
| T125 | 
20434 | 
3 | 
0 | 
0 | 
| T137 | 
9219 | 
6 | 
0 | 
0 | 
| T138 | 
10037 | 
5 | 
0 | 
0 | 
| T143 | 
7355 | 
10 | 
0 | 
0 | 
| T144 | 
5607 | 
1 | 
0 | 
0 | 
| T147 | 
79037 | 
435 | 
0 | 
0 | 
| T150 | 
10395 | 
4 | 
0 | 
0 | 
| T151 | 
156895 | 
275 | 
0 | 
0 | 
| T178 | 
4864 | 
1 | 
0 | 
0 | 
tpm_int_status_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2038 | 
0 | 
0 | 
| T104 | 
2312 | 
3 | 
0 | 
0 | 
| T137 | 
9219 | 
5 | 
0 | 
0 | 
| T138 | 
10037 | 
2 | 
0 | 
0 | 
| T143 | 
7355 | 
4 | 
0 | 
0 | 
| T144 | 
5607 | 
2 | 
0 | 
0 | 
| T147 | 
79037 | 
538 | 
0 | 
0 | 
| T151 | 
156895 | 
308 | 
0 | 
0 | 
| T176 | 
13629 | 
66 | 
0 | 
0 | 
| T177 | 
9780 | 
1 | 
0 | 
0 | 
| T178 | 
4864 | 
8 | 
0 | 
0 | 
tpm_int_vector_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2167 | 
0 | 
0 | 
| T104 | 
2312 | 
4 | 
0 | 
0 | 
| T137 | 
9219 | 
4 | 
0 | 
0 | 
| T138 | 
10037 | 
12 | 
0 | 
0 | 
| T143 | 
7355 | 
8 | 
0 | 
0 | 
| T144 | 
5607 | 
6 | 
0 | 
0 | 
| T147 | 
79037 | 
495 | 
0 | 
0 | 
| T150 | 
10395 | 
6 | 
0 | 
0 | 
| T151 | 
156895 | 
322 | 
0 | 
0 | 
| T176 | 
13629 | 
94 | 
0 | 
0 | 
| T177 | 
9780 | 
13 | 
0 | 
0 | 
tpm_intf_capability_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2007 | 
0 | 
0 | 
| T104 | 
2312 | 
1 | 
0 | 
0 | 
| T137 | 
9219 | 
6 | 
0 | 
0 | 
| T138 | 
10037 | 
10 | 
0 | 
0 | 
| T143 | 
7355 | 
3 | 
0 | 
0 | 
| T144 | 
5607 | 
2 | 
0 | 
0 | 
| T147 | 
79037 | 
498 | 
0 | 
0 | 
| T150 | 
10395 | 
4 | 
0 | 
0 | 
| T151 | 
156895 | 
242 | 
0 | 
0 | 
| T176 | 
13629 | 
53 | 
0 | 
0 | 
| T178 | 
4864 | 
2 | 
0 | 
0 | 
tpm_rid_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
2019 | 
0 | 
0 | 
| T104 | 
2312 | 
3 | 
0 | 
0 | 
| T137 | 
9219 | 
7 | 
0 | 
0 | 
| T138 | 
10037 | 
5 | 
0 | 
0 | 
| T143 | 
7355 | 
7 | 
0 | 
0 | 
| T144 | 
5607 | 
5 | 
0 | 
0 | 
| T147 | 
79037 | 
512 | 
0 | 
0 | 
| T150 | 
10395 | 
9 | 
0 | 
0 | 
| T151 | 
156895 | 
270 | 
0 | 
0 | 
| T176 | 
13629 | 
22 | 
0 | 
0 | 
| T177 | 
9780 | 
13 | 
0 | 
0 | 
tpm_sts_rd_A
| Name | Attempts | Real Successes | Failures | Incomplete | 
| Total | 
419546845 | 
1854 | 
0 | 
0 | 
| T137 | 
9219 | 
1 | 
0 | 
0 | 
| T138 | 
10037 | 
3 | 
0 | 
0 | 
| T143 | 
7355 | 
5 | 
0 | 
0 | 
| T144 | 
5607 | 
2 | 
0 | 
0 | 
| T147 | 
79037 | 
493 | 
0 | 
0 | 
| T150 | 
10395 | 
3 | 
0 | 
0 | 
| T151 | 
156895 | 
210 | 
0 | 
0 | 
| T176 | 
13629 | 
9 | 
0 | 
0 | 
| T177 | 
9780 | 
8 | 
0 | 
0 | 
| T178 | 
4864 | 
1 | 
0 | 
0 |