T499 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_cfg_cmd.642124344 |
|
|
Sep 09 11:10:19 AM UTC 24 |
Sep 09 11:10:23 AM UTC 24 |
27969468 ps |
T113 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_and_tpm.677629791 |
|
|
Sep 09 11:08:52 AM UTC 24 |
Sep 09 11:10:24 AM UTC 24 |
6466183629 ps |
T244 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_mailbox.3607831691 |
|
|
Sep 09 11:10:07 AM UTC 24 |
Sep 09 11:10:27 AM UTC 24 |
4751188695 ps |
T500 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_alert_test.1886284048 |
|
|
Sep 09 11:10:25 AM UTC 24 |
Sep 09 11:10:27 AM UTC 24 |
34494431 ps |
T320 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_cmd_filtering.2818277096 |
|
|
Sep 09 11:10:15 AM UTC 24 |
Sep 09 11:10:27 AM UTC 24 |
850998237 ps |
T312 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_upload.3693753785 |
|
|
Sep 09 11:10:08 AM UTC 24 |
Sep 09 11:10:28 AM UTC 24 |
16501447058 ps |
T501 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_csb_read.1161148808 |
|
|
Sep 09 11:10:28 AM UTC 24 |
Sep 09 11:10:30 AM UTC 24 |
24374459 ps |
T313 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_upload.1519184636 |
|
|
Sep 09 11:10:19 AM UTC 24 |
Sep 09 11:10:31 AM UTC 24 |
633952570 ps |
T502 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mem_parity.1490419516 |
|
|
Sep 09 11:10:28 AM UTC 24 |
Sep 09 11:10:31 AM UTC 24 |
98688397 ps |
T503 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_read_buffer_direct.797691018 |
|
|
Sep 09 11:10:21 AM UTC 24 |
Sep 09 11:10:32 AM UTC 24 |
1637442686 ps |
T504 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_sts_read.3143334646 |
|
|
Sep 09 11:10:31 AM UTC 24 |
Sep 09 11:10:34 AM UTC 24 |
17085873 ps |
T401 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_tpm_all.577834564 |
|
|
Sep 09 11:09:52 AM UTC 24 |
Sep 09 11:10:36 AM UTC 24 |
8058992940 ps |
T505 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_rw.3546661457 |
|
|
Sep 09 11:10:31 AM UTC 24 |
Sep 09 11:10:39 AM UTC 24 |
126395165 ps |
T73 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_cmd_filtering.2089213485 |
|
|
Sep 09 11:10:32 AM UTC 24 |
Sep 09 11:10:40 AM UTC 24 |
1011726041 ps |
T506 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_read_hw_reg.731803097 |
|
|
Sep 09 11:10:28 AM UTC 24 |
Sep 09 11:10:40 AM UTC 24 |
775006387 ps |
T245 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_all.3014179057 |
|
|
Sep 09 11:10:10 AM UTC 24 |
Sep 09 11:10:41 AM UTC 24 |
10655853826 ps |
T218 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/5.spi_device_flash_mode_ignore_cmds.9999444 |
|
|
Sep 09 11:08:50 AM UTC 24 |
Sep 09 11:10:41 AM UTC 24 |
20834524861 ps |
T412 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_tpm_all.2980804879 |
|
|
Sep 09 11:10:29 AM UTC 24 |
Sep 09 11:10:43 AM UTC 24 |
1352948939 ps |
T334 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_upload.3241050769 |
|
|
Sep 09 11:10:50 AM UTC 24 |
Sep 09 11:11:17 AM UTC 24 |
26428343848 ps |
T212 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm.141892387 |
|
|
Sep 09 11:10:00 AM UTC 24 |
Sep 09 11:10:43 AM UTC 24 |
7239932687 ps |
T326 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/0.spi_device_mailbox.889861478 |
|
|
Sep 09 11:08:27 AM UTC 24 |
Sep 09 11:10:44 AM UTC 24 |
44030786085 ps |
T213 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_flash_all.2644424486 |
|
|
Sep 09 11:08:37 AM UTC 24 |
Sep 09 11:10:44 AM UTC 24 |
11700658073 ps |
T293 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_and_tpm_min_idle.1808936801 |
|
|
Sep 09 11:10:00 AM UTC 24 |
Sep 09 11:10:45 AM UTC 24 |
2577507527 ps |
T347 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_pass_addr_payload_swap.301805085 |
|
|
Sep 09 11:10:33 AM UTC 24 |
Sep 09 11:10:45 AM UTC 24 |
1861133016 ps |
T317 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_cfg_cmd.3246280119 |
|
|
Sep 09 11:10:41 AM UTC 24 |
Sep 09 11:10:46 AM UTC 24 |
166622006 ps |
T281 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_mailbox.2630695688 |
|
|
Sep 09 11:10:18 AM UTC 24 |
Sep 09 11:10:46 AM UTC 24 |
2424817426 ps |
T303 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_mailbox.2597147537 |
|
|
Sep 09 11:09:49 AM UTC 24 |
Sep 09 11:10:47 AM UTC 24 |
29231522671 ps |
T507 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_alert_test.3364309573 |
|
|
Sep 09 11:10:45 AM UTC 24 |
Sep 09 11:10:47 AM UTC 24 |
46849187 ps |
T508 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_csb_read.2616423820 |
|
|
Sep 09 11:10:46 AM UTC 24 |
Sep 09 11:10:48 AM UTC 24 |
284514910 ps |
T509 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mem_parity.2647868325 |
|
|
Sep 09 11:10:46 AM UTC 24 |
Sep 09 11:10:48 AM UTC 24 |
110222018 ps |
T292 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_upload.1161527953 |
|
|
Sep 09 11:10:40 AM UTC 24 |
Sep 09 11:10:48 AM UTC 24 |
649915489 ps |
T283 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_intercept.495386572 |
|
|
Sep 09 11:10:35 AM UTC 24 |
Sep 09 11:10:49 AM UTC 24 |
3985321304 ps |
T89 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_stress_all.1640042436 |
|
|
Sep 09 11:08:32 AM UTC 24 |
Sep 09 11:10:50 AM UTC 24 |
64041775139 ps |
T96 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_mailbox.1645131834 |
|
|
Sep 09 11:10:37 AM UTC 24 |
Sep 09 11:10:50 AM UTC 24 |
979649555 ps |
T97 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_sts_read.2387152862 |
|
|
Sep 09 11:10:48 AM UTC 24 |
Sep 09 11:10:50 AM UTC 24 |
74076301 ps |
T98 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_rw.3075540066 |
|
|
Sep 09 11:10:48 AM UTC 24 |
Sep 09 11:10:50 AM UTC 24 |
17196114 ps |
T99 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_pass_addr_payload_swap.3672797385 |
|
|
Sep 09 11:10:15 AM UTC 24 |
Sep 09 11:10:52 AM UTC 24 |
15781283047 ps |
T100 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_read_buffer_direct.3803459404 |
|
|
Sep 09 11:10:42 AM UTC 24 |
Sep 09 11:10:52 AM UTC 24 |
1422291851 ps |
T101 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/2.spi_device_flash_and_tpm_min_idle.1438317041 |
|
|
Sep 09 11:08:31 AM UTC 24 |
Sep 09 11:10:52 AM UTC 24 |
10496743615 ps |
T102 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_mode_ignore_cmds.3067116056 |
|
|
Sep 09 11:10:08 AM UTC 24 |
Sep 09 11:10:52 AM UTC 24 |
4167429100 ps |
T103 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_mode.1835164010 |
|
|
Sep 09 11:10:41 AM UTC 24 |
Sep 09 11:10:53 AM UTC 24 |
374648827 ps |
T90 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_and_tpm_min_idle.4175374021 |
|
|
Sep 09 11:08:43 AM UTC 24 |
Sep 09 11:10:54 AM UTC 24 |
42619417437 ps |
T510 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_intercept.4287652937 |
|
|
Sep 09 11:10:49 AM UTC 24 |
Sep 09 11:10:55 AM UTC 24 |
980570766 ps |
T327 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_cfg_cmd.3655827471 |
|
|
Sep 09 11:10:50 AM UTC 24 |
Sep 09 11:10:56 AM UTC 24 |
486722558 ps |
T511 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_alert_test.1760926715 |
|
|
Sep 09 11:10:55 AM UTC 24 |
Sep 09 11:10:57 AM UTC 24 |
14384429 ps |
T512 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_csb_read.1003046134 |
|
|
Sep 09 11:10:56 AM UTC 24 |
Sep 09 11:10:58 AM UTC 24 |
74873349 ps |
T513 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mem_parity.693721605 |
|
|
Sep 09 11:10:58 AM UTC 24 |
Sep 09 11:11:01 AM UTC 24 |
24761679 ps |
T410 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_tpm_all.382526180 |
|
|
Sep 09 11:10:14 AM UTC 24 |
Sep 09 11:11:01 AM UTC 24 |
4225950055 ps |
T342 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_addr_payload_swap.1751010260 |
|
|
Sep 09 11:10:49 AM UTC 24 |
Sep 09 11:11:01 AM UTC 24 |
1689795215 ps |
T246 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm_min_idle.2727614240 |
|
|
Sep 09 11:10:10 AM UTC 24 |
Sep 09 11:11:02 AM UTC 24 |
12637632544 ps |
T514 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_read_hw_reg.3170274072 |
|
|
Sep 09 11:10:47 AM UTC 24 |
Sep 09 11:11:02 AM UTC 24 |
4025146267 ps |
T340 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm_min_idle.986687356 |
|
|
Sep 09 11:10:53 AM UTC 24 |
Sep 09 11:11:04 AM UTC 24 |
1542969385 ps |
T515 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_sts_read.1445743782 |
|
|
Sep 09 11:11:02 AM UTC 24 |
Sep 09 11:11:04 AM UTC 24 |
93065627 ps |
T516 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_tpm_all.3959237186 |
|
|
Sep 09 11:10:47 AM UTC 24 |
Sep 09 11:11:05 AM UTC 24 |
2557633581 ps |
T333 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_cmd_filtering.363793408 |
|
|
Sep 09 11:11:02 AM UTC 24 |
Sep 09 11:11:06 AM UTC 24 |
99686838 ps |
T282 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/6.spi_device_flash_and_tpm.2878281069 |
|
|
Sep 09 11:08:58 AM UTC 24 |
Sep 09 11:11:07 AM UTC 24 |
12958354968 ps |
T517 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_read_buffer_direct.884810956 |
|
|
Sep 09 11:10:53 AM UTC 24 |
Sep 09 11:11:08 AM UTC 24 |
1102859778 ps |
T518 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_rw.2546377614 |
|
|
Sep 09 11:11:02 AM UTC 24 |
Sep 09 11:11:08 AM UTC 24 |
170369960 ps |
T398 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode.2033208410 |
|
|
Sep 09 11:10:20 AM UTC 24 |
Sep 09 11:11:09 AM UTC 24 |
2729832943 ps |
T268 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_pass_cmd_filtering.1922690805 |
|
|
Sep 09 11:10:49 AM UTC 24 |
Sep 09 11:11:12 AM UTC 24 |
42539830656 ps |
T191 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_stress_all.4086017723 |
|
|
Sep 09 11:09:33 AM UTC 24 |
Sep 09 11:11:17 AM UTC 24 |
13193127358 ps |
T519 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_read_buffer_direct.492390714 |
|
|
Sep 09 11:11:11 AM UTC 24 |
Sep 09 11:11:17 AM UTC 24 |
90567216 ps |
T318 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_upload.3664160243 |
|
|
Sep 09 11:11:06 AM UTC 24 |
Sep 09 11:11:18 AM UTC 24 |
2541093746 ps |
T520 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_alert_test.2488757105 |
|
|
Sep 09 11:11:18 AM UTC 24 |
Sep 09 11:11:20 AM UTC 24 |
30094803 ps |
T521 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_csb_read.3912439865 |
|
|
Sep 09 11:11:18 AM UTC 24 |
Sep 09 11:11:20 AM UTC 24 |
15272044 ps |
T404 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm.487337980 |
|
|
Sep 09 11:10:43 AM UTC 24 |
Sep 09 11:11:22 AM UTC 24 |
3662344370 ps |
T522 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mem_parity.2354906330 |
|
|
Sep 09 11:11:20 AM UTC 24 |
Sep 09 11:11:23 AM UTC 24 |
25292539 ps |
T523 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_read_hw_reg.1302607660 |
|
|
Sep 09 11:10:58 AM UTC 24 |
Sep 09 11:11:24 AM UTC 24 |
6419999211 ps |
T114 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_all.1824761392 |
|
|
Sep 09 11:09:22 AM UTC 24 |
Sep 09 11:11:24 AM UTC 24 |
20247307919 ps |
T216 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_mode_ignore_cmds.2528824881 |
|
|
Sep 09 11:09:13 AM UTC 24 |
Sep 09 11:11:25 AM UTC 24 |
47958066636 ps |
T351 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_pass_addr_payload_swap.1598555536 |
|
|
Sep 09 11:11:04 AM UTC 24 |
Sep 09 11:11:26 AM UTC 24 |
29002049125 ps |
T524 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_sts_read.1850390485 |
|
|
Sep 09 11:11:24 AM UTC 24 |
Sep 09 11:11:27 AM UTC 24 |
342516451 ps |
T525 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_rw.2641883924 |
|
|
Sep 09 11:11:24 AM UTC 24 |
Sep 09 11:11:28 AM UTC 24 |
364937720 ps |
T262 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/12.spi_device_flash_all.1772921663 |
|
|
Sep 09 11:09:59 AM UTC 24 |
Sep 09 11:11:28 AM UTC 24 |
68053550636 ps |
T526 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_tpm_all.3146254607 |
|
|
Sep 09 11:11:00 AM UTC 24 |
Sep 09 11:11:29 AM UTC 24 |
14982474255 ps |
T406 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_all.2353053528 |
|
|
Sep 09 11:11:22 AM UTC 24 |
Sep 09 11:11:29 AM UTC 24 |
1183220975 ps |
T219 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/10.spi_device_flash_and_tpm_min_idle.3210062794 |
|
|
Sep 09 11:09:33 AM UTC 24 |
Sep 09 11:11:31 AM UTC 24 |
9901948718 ps |
T527 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_mailbox.2444358359 |
|
|
Sep 09 11:11:28 AM UTC 24 |
Sep 09 11:11:32 AM UTC 24 |
34317227 ps |
T528 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_tpm_read_hw_reg.2343455645 |
|
|
Sep 09 11:11:22 AM UTC 24 |
Sep 09 11:11:33 AM UTC 24 |
1610353156 ps |
T296 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_intercept.1025102678 |
|
|
Sep 09 11:11:04 AM UTC 24 |
Sep 09 11:11:34 AM UTC 24 |
2094259313 ps |
T288 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_intercept.1678817941 |
|
|
Sep 09 11:11:26 AM UTC 24 |
Sep 09 11:11:34 AM UTC 24 |
585537277 ps |
T529 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_cfg_cmd.2551140653 |
|
|
Sep 09 11:11:28 AM UTC 24 |
Sep 09 11:11:34 AM UTC 24 |
407197014 ps |
T361 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_upload.1513126520 |
|
|
Sep 09 11:11:28 AM UTC 24 |
Sep 09 11:11:35 AM UTC 24 |
966035803 ps |
T314 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_cfg_cmd.1558627663 |
|
|
Sep 09 11:11:06 AM UTC 24 |
Sep 09 11:11:36 AM UTC 24 |
1950639972 ps |
T530 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_alert_test.1682980900 |
|
|
Sep 09 11:11:34 AM UTC 24 |
Sep 09 11:11:37 AM UTC 24 |
22206775 ps |
T531 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_csb_read.4048756885 |
|
|
Sep 09 11:11:34 AM UTC 24 |
Sep 09 11:11:37 AM UTC 24 |
50193831 ps |
T367 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_cmd_filtering.1720599113 |
|
|
Sep 09 11:11:26 AM UTC 24 |
Sep 09 11:11:38 AM UTC 24 |
1215424448 ps |
T532 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mem_parity.3413438080 |
|
|
Sep 09 11:11:36 AM UTC 24 |
Sep 09 11:11:38 AM UTC 24 |
33436097 ps |
T533 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode.208142893 |
|
|
Sep 09 11:11:08 AM UTC 24 |
Sep 09 11:11:38 AM UTC 24 |
4307829314 ps |
T207 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_stress_all.2473824131 |
|
|
Sep 09 11:10:24 AM UTC 24 |
Sep 09 11:11:39 AM UTC 24 |
3367095396 ps |
T534 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_sts_read.4234770245 |
|
|
Sep 09 11:11:37 AM UTC 24 |
Sep 09 11:11:39 AM UTC 24 |
31100501 ps |
T535 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode.604923013 |
|
|
Sep 09 11:11:29 AM UTC 24 |
Sep 09 11:11:41 AM UTC 24 |
584754822 ps |
T344 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_pass_addr_payload_swap.1427264312 |
|
|
Sep 09 11:11:26 AM UTC 24 |
Sep 09 11:11:41 AM UTC 24 |
5129102778 ps |
T536 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_addr_payload_swap.1076529189 |
|
|
Sep 09 11:11:39 AM UTC 24 |
Sep 09 11:11:43 AM UTC 24 |
100342044 ps |
T537 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_read_buffer_direct.2994345182 |
|
|
Sep 09 11:11:30 AM UTC 24 |
Sep 09 11:11:44 AM UTC 24 |
4863245115 ps |
T235 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_cfg_cmd.3939996552 |
|
|
Sep 09 11:11:40 AM UTC 24 |
Sep 09 11:11:45 AM UTC 24 |
182359443 ps |
T538 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_rw.588432026 |
|
|
Sep 09 11:11:38 AM UTC 24 |
Sep 09 11:11:46 AM UTC 24 |
268593578 ps |
T192 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_stress_all.3737227908 |
|
|
Sep 09 11:09:15 AM UTC 24 |
Sep 09 11:11:48 AM UTC 24 |
18107750843 ps |
T325 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_mailbox.1223804196 |
|
|
Sep 09 11:11:39 AM UTC 24 |
Sep 09 11:11:49 AM UTC 24 |
1287668136 ps |
T539 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_mode.1604604525 |
|
|
Sep 09 11:11:41 AM UTC 24 |
Sep 09 11:11:49 AM UTC 24 |
1243945121 ps |
T540 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_pass_cmd_filtering.1449681812 |
|
|
Sep 09 11:11:38 AM UTC 24 |
Sep 09 11:11:51 AM UTC 24 |
9608441055 ps |
T541 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_alert_test.2311977900 |
|
|
Sep 09 11:11:49 AM UTC 24 |
Sep 09 11:11:51 AM UTC 24 |
15767302 ps |
T542 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_all.2403351989 |
|
|
Sep 09 11:11:37 AM UTC 24 |
Sep 09 11:11:53 AM UTC 24 |
3114699747 ps |
T543 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_read_buffer_direct.2285555244 |
|
|
Sep 09 11:11:45 AM UTC 24 |
Sep 09 11:11:54 AM UTC 24 |
1353191583 ps |
T544 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_csb_read.475075502 |
|
|
Sep 09 11:11:52 AM UTC 24 |
Sep 09 11:11:54 AM UTC 24 |
17292712 ps |
T193 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_stress_all.2584335381 |
|
|
Sep 09 11:09:51 AM UTC 24 |
Sep 09 11:11:55 AM UTC 24 |
23088687332 ps |
T545 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_sts_read.34895168 |
|
|
Sep 09 11:11:54 AM UTC 24 |
Sep 09 11:11:56 AM UTC 24 |
30227946 ps |
T276 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_intercept.2803116431 |
|
|
Sep 09 11:11:39 AM UTC 24 |
Sep 09 11:11:56 AM UTC 24 |
5686993142 ps |
T546 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_tpm_read_hw_reg.3319091254 |
|
|
Sep 09 11:11:36 AM UTC 24 |
Sep 09 11:11:56 AM UTC 24 |
13645818520 ps |
T547 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_read_hw_reg.1938282421 |
|
|
Sep 09 11:11:52 AM UTC 24 |
Sep 09 11:11:59 AM UTC 24 |
1234054487 ps |
T355 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_upload.3933402014 |
|
|
Sep 09 11:11:40 AM UTC 24 |
Sep 09 11:12:00 AM UTC 24 |
995895721 ps |
T548 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_rw.3151079008 |
|
|
Sep 09 11:11:56 AM UTC 24 |
Sep 09 11:12:01 AM UTC 24 |
320579804 ps |
T350 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_all.3696485610 |
|
|
Sep 09 11:10:23 AM UTC 24 |
Sep 09 11:12:01 AM UTC 24 |
28865039845 ps |
T549 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_tpm_all.1169921399 |
|
|
Sep 09 11:11:54 AM UTC 24 |
Sep 09 11:12:02 AM UTC 24 |
2818183119 ps |
T295 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm_min_idle.191839033 |
|
|
Sep 09 11:11:14 AM UTC 24 |
Sep 09 11:12:03 AM UTC 24 |
7355073475 ps |
T550 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_cfg_cmd.1646765662 |
|
|
Sep 09 11:12:00 AM UTC 24 |
Sep 09 11:12:06 AM UTC 24 |
79784533 ps |
T399 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_mode.3757170133 |
|
|
Sep 09 11:10:51 AM UTC 24 |
Sep 09 11:12:06 AM UTC 24 |
8387678724 ps |
T396 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_mode.3413814303 |
|
|
Sep 09 11:12:00 AM UTC 24 |
Sep 09 11:12:08 AM UTC 24 |
757944188 ps |
T551 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_read_buffer_direct.1060247478 |
|
|
Sep 09 11:12:04 AM UTC 24 |
Sep 09 11:12:09 AM UTC 24 |
116981889 ps |
T194 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_stress_all.2895170881 |
|
|
Sep 09 11:12:07 AM UTC 24 |
Sep 09 11:12:09 AM UTC 24 |
110474610 ps |
T552 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_mode_ignore_cmds.152855604 |
|
|
Sep 09 11:11:29 AM UTC 24 |
Sep 09 11:12:09 AM UTC 24 |
3050640948 ps |
T553 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_alert_test.3203041251 |
|
|
Sep 09 11:12:08 AM UTC 24 |
Sep 09 11:12:10 AM UTC 24 |
27165718 ps |
T256 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm_min_idle.1840446782 |
|
|
Sep 09 11:09:51 AM UTC 24 |
Sep 09 11:12:10 AM UTC 24 |
23708195507 ps |
T554 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_csb_read.1471675891 |
|
|
Sep 09 11:12:09 AM UTC 24 |
Sep 09 11:12:11 AM UTC 24 |
20006963 ps |
T254 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_addr_payload_swap.1566707835 |
|
|
Sep 09 11:11:56 AM UTC 24 |
Sep 09 11:12:12 AM UTC 24 |
2293876827 ps |
T555 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_sts_read.2358349982 |
|
|
Sep 09 11:12:10 AM UTC 24 |
Sep 09 11:12:12 AM UTC 24 |
16009133 ps |
T556 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_all.1192275671 |
|
|
Sep 09 11:12:04 AM UTC 24 |
Sep 09 11:12:12 AM UTC 24 |
2902298928 ps |
T557 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_mailbox.1723723019 |
|
|
Sep 09 11:11:58 AM UTC 24 |
Sep 09 11:12:14 AM UTC 24 |
812443495 ps |
T558 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_rw.2959033260 |
|
|
Sep 09 11:12:11 AM UTC 24 |
Sep 09 11:12:14 AM UTC 24 |
61158528 ps |
T559 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_upload.2596731303 |
|
|
Sep 09 11:11:58 AM UTC 24 |
Sep 09 11:12:14 AM UTC 24 |
7058197932 ps |
T323 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_mailbox.3853252378 |
|
|
Sep 09 11:11:06 AM UTC 24 |
Sep 09 11:12:15 AM UTC 24 |
48268170583 ps |
T560 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm_min_idle.503988430 |
|
|
Sep 09 11:08:28 AM UTC 24 |
Sep 09 11:12:16 AM UTC 24 |
20600586838 ps |
T279 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_pass_cmd_filtering.1775693752 |
|
|
Sep 09 11:11:56 AM UTC 24 |
Sep 09 11:12:17 AM UTC 24 |
50024718967 ps |
T561 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_mode_ignore_cmds.745913381 |
|
|
Sep 09 11:11:08 AM UTC 24 |
Sep 09 11:12:20 AM UTC 24 |
30523222075 ps |
T341 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_intercept.3696463935 |
|
|
Sep 09 11:12:14 AM UTC 24 |
Sep 09 11:12:20 AM UTC 24 |
734846215 ps |
T562 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_all.251261131 |
|
|
Sep 09 11:10:53 AM UTC 24 |
Sep 09 11:12:21 AM UTC 24 |
36149507433 ps |
T358 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_upload.1693866176 |
|
|
Sep 09 11:12:14 AM UTC 24 |
Sep 09 11:12:22 AM UTC 24 |
778046866 ps |
T563 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode.2434124716 |
|
|
Sep 09 11:12:15 AM UTC 24 |
Sep 09 11:12:23 AM UTC 24 |
136263785 ps |
T564 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_all.3861254197 |
|
|
Sep 09 11:12:10 AM UTC 24 |
Sep 09 11:12:24 AM UTC 24 |
1822799829 ps |
T565 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_alert_test.548020611 |
|
|
Sep 09 11:12:22 AM UTC 24 |
Sep 09 11:12:24 AM UTC 24 |
23702007 ps |
T566 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_csb_read.1807944267 |
|
|
Sep 09 11:12:22 AM UTC 24 |
Sep 09 11:12:24 AM UTC 24 |
87294486 ps |
T338 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_cmd_filtering.1405276751 |
|
|
Sep 09 11:12:11 AM UTC 24 |
Sep 09 11:12:26 AM UTC 24 |
9260003989 ps |
T567 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_cfg_cmd.983926426 |
|
|
Sep 09 11:12:15 AM UTC 24 |
Sep 09 11:12:26 AM UTC 24 |
861475670 ps |
T568 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_read_hw_reg.358518886 |
|
|
Sep 09 11:12:24 AM UTC 24 |
Sep 09 11:12:27 AM UTC 24 |
13995227 ps |
T569 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_tpm_read_hw_reg.3951920929 |
|
|
Sep 09 11:12:10 AM UTC 24 |
Sep 09 11:12:27 AM UTC 24 |
2373573752 ps |
T570 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_sts_read.846804782 |
|
|
Sep 09 11:12:26 AM UTC 24 |
Sep 09 11:12:28 AM UTC 24 |
215477869 ps |
T571 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_rw.3072837016 |
|
|
Sep 09 11:12:26 AM UTC 24 |
Sep 09 11:12:28 AM UTC 24 |
31531008 ps |
T365 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_pass_addr_payload_swap.256008525 |
|
|
Sep 09 11:12:12 AM UTC 24 |
Sep 09 11:12:29 AM UTC 24 |
1260847567 ps |
T572 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_read_buffer_direct.4174311549 |
|
|
Sep 09 11:12:16 AM UTC 24 |
Sep 09 11:12:32 AM UTC 24 |
2704645541 ps |
T573 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_intercept.2339993135 |
|
|
Sep 09 11:12:28 AM UTC 24 |
Sep 09 11:12:32 AM UTC 24 |
146512093 ps |
T250 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_intercept.1141289079 |
|
|
Sep 09 11:11:58 AM UTC 24 |
Sep 09 11:12:33 AM UTC 24 |
8214575278 ps |
T574 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/19.spi_device_flash_all.2362871255 |
|
|
Sep 09 11:11:45 AM UTC 24 |
Sep 09 11:12:34 AM UTC 24 |
6841188217 ps |
T348 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_stress_all.1060175783 |
|
|
Sep 09 11:11:18 AM UTC 24 |
Sep 09 11:12:34 AM UTC 24 |
27880334611 ps |
T575 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/9.spi_device_flash_and_tpm_min_idle.555514549 |
|
|
Sep 09 11:09:23 AM UTC 24 |
Sep 09 11:12:34 AM UTC 24 |
40206550749 ps |
T576 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode.4260088341 |
|
|
Sep 09 11:12:30 AM UTC 24 |
Sep 09 11:12:35 AM UTC 24 |
92061460 ps |
T285 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_upload.1780728856 |
|
|
Sep 09 11:12:29 AM UTC 24 |
Sep 09 11:12:35 AM UTC 24 |
134694032 ps |
T332 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_cfg_cmd.852362898 |
|
|
Sep 09 11:12:29 AM UTC 24 |
Sep 09 11:12:36 AM UTC 24 |
372047256 ps |
T352 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_addr_payload_swap.4055932705 |
|
|
Sep 09 11:12:27 AM UTC 24 |
Sep 09 11:12:36 AM UTC 24 |
2112324683 ps |
T247 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_and_tpm_min_idle.1193582917 |
|
|
Sep 09 11:09:09 AM UTC 24 |
Sep 09 11:12:37 AM UTC 24 |
17175278477 ps |
T577 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_alert_test.4256093720 |
|
|
Sep 09 11:12:36 AM UTC 24 |
Sep 09 11:12:38 AM UTC 24 |
20205445 ps |
T578 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_csb_read.1533337288 |
|
|
Sep 09 11:12:36 AM UTC 24 |
Sep 09 11:12:38 AM UTC 24 |
15609619 ps |
T579 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_mailbox.4135294556 |
|
|
Sep 09 11:12:14 AM UTC 24 |
Sep 09 11:12:39 AM UTC 24 |
1399826462 ps |
T580 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_sts_read.1384082834 |
|
|
Sep 09 11:12:38 AM UTC 24 |
Sep 09 11:12:40 AM UTC 24 |
43167524 ps |
T115 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_and_tpm_min_idle.1096677391 |
|
|
Sep 09 11:10:23 AM UTC 24 |
Sep 09 11:12:41 AM UTC 24 |
8654753656 ps |
T581 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm.918204852 |
|
|
Sep 09 11:12:04 AM UTC 24 |
Sep 09 11:12:42 AM UTC 24 |
16139061526 ps |
T582 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_all.1224781162 |
|
|
Sep 09 11:12:37 AM UTC 24 |
Sep 09 11:12:43 AM UTC 24 |
632342954 ps |
T583 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_alert_test.1618020861 |
|
|
Sep 09 11:13:32 AM UTC 24 |
Sep 09 11:13:34 AM UTC 24 |
73665903 ps |
T584 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_addr_payload_swap.725814282 |
|
|
Sep 09 11:12:39 AM UTC 24 |
Sep 09 11:12:43 AM UTC 24 |
35805941 ps |
T585 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_read_hw_reg.2235692128 |
|
|
Sep 09 11:12:37 AM UTC 24 |
Sep 09 11:12:44 AM UTC 24 |
1734639864 ps |
T586 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_read_buffer_direct.1403400204 |
|
|
Sep 09 11:12:33 AM UTC 24 |
Sep 09 11:12:45 AM UTC 24 |
3077480480 ps |
T587 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_flash_mode_ignore_cmds.784349529 |
|
|
Sep 09 11:12:32 AM UTC 24 |
Sep 09 11:12:46 AM UTC 24 |
2264655816 ps |
T588 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_tpm_rw.4195415336 |
|
|
Sep 09 11:12:39 AM UTC 24 |
Sep 09 11:12:46 AM UTC 24 |
99750092 ps |
T589 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_intercept.914098126 |
|
|
Sep 09 11:12:41 AM UTC 24 |
Sep 09 11:12:46 AM UTC 24 |
101920607 ps |
T356 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_pass_cmd_filtering.4145765680 |
|
|
Sep 09 11:12:27 AM UTC 24 |
Sep 09 11:12:47 AM UTC 24 |
17399679980 ps |
T590 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_cfg_cmd.1313343043 |
|
|
Sep 09 11:12:44 AM UTC 24 |
Sep 09 11:12:48 AM UTC 24 |
59038506 ps |
T591 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_pass_cmd_filtering.3076992750 |
|
|
Sep 09 11:12:39 AM UTC 24 |
Sep 09 11:12:49 AM UTC 24 |
3024510893 ps |
T592 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_read_buffer_direct.1597948514 |
|
|
Sep 09 11:13:22 AM UTC 24 |
Sep 09 11:13:34 AM UTC 24 |
3434123090 ps |
T304 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_flash_and_tpm.3432003832 |
|
|
Sep 09 11:10:53 AM UTC 24 |
Sep 09 11:12:49 AM UTC 24 |
7989851405 ps |
T593 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_alert_test.493600841 |
|
|
Sep 09 11:12:48 AM UTC 24 |
Sep 09 11:12:50 AM UTC 24 |
14303376 ps |
T594 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_csb_read.1571440210 |
|
|
Sep 09 11:12:49 AM UTC 24 |
Sep 09 11:12:51 AM UTC 24 |
15837589 ps |
T595 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_read_buffer_direct.3162998405 |
|
|
Sep 09 11:12:46 AM UTC 24 |
Sep 09 11:12:52 AM UTC 24 |
423086838 ps |
T596 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_read_hw_reg.226264697 |
|
|
Sep 09 11:12:50 AM UTC 24 |
Sep 09 11:12:55 AM UTC 24 |
546863211 ps |
T597 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_sts_read.4233794872 |
|
|
Sep 09 11:12:52 AM UTC 24 |
Sep 09 11:12:55 AM UTC 24 |
12884150 ps |
T363 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_upload.2791221852 |
|
|
Sep 09 11:12:42 AM UTC 24 |
Sep 09 11:12:57 AM UTC 24 |
9844757013 ps |
T598 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_rw.1820595892 |
|
|
Sep 09 11:12:53 AM UTC 24 |
Sep 09 11:12:57 AM UTC 24 |
701016940 ps |
T362 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_stress_all.2810026590 |
|
|
Sep 09 11:10:45 AM UTC 24 |
Sep 09 11:12:58 AM UTC 24 |
47925272275 ps |
T599 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_tpm_all.4111115407 |
|
|
Sep 09 11:12:25 AM UTC 24 |
Sep 09 11:12:59 AM UTC 24 |
3443807166 ps |
T328 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_mailbox.1655244258 |
|
|
Sep 09 11:12:28 AM UTC 24 |
Sep 09 11:13:00 AM UTC 24 |
3537050254 ps |
T330 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_mailbox.2479608522 |
|
|
Sep 09 11:12:41 AM UTC 24 |
Sep 09 11:13:03 AM UTC 24 |
1236701633 ps |
T600 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_cfg_cmd.1195815464 |
|
|
Sep 09 11:13:00 AM UTC 24 |
Sep 09 11:13:04 AM UTC 24 |
496805900 ps |
T260 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_addr_payload_swap.832453762 |
|
|
Sep 09 11:12:56 AM UTC 24 |
Sep 09 11:13:05 AM UTC 24 |
353334590 ps |
T601 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode.1210306185 |
|
|
Sep 09 11:12:45 AM UTC 24 |
Sep 09 11:13:07 AM UTC 24 |
1227199417 ps |
T274 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_mailbox.2687960236 |
|
|
Sep 09 11:10:49 AM UTC 24 |
Sep 09 11:13:07 AM UTC 24 |
83119693022 ps |
T360 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_mailbox.991315064 |
|
|
Sep 09 11:12:58 AM UTC 24 |
Sep 09 11:13:07 AM UTC 24 |
1659283132 ps |
T602 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/14.spi_device_flash_mode_ignore_cmds.3106953466 |
|
|
Sep 09 11:10:20 AM UTC 24 |
Sep 09 11:13:10 AM UTC 24 |
20559299000 ps |
T603 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_upload.2391656009 |
|
|
Sep 09 11:12:59 AM UTC 24 |
Sep 09 11:13:12 AM UTC 24 |
1964673297 ps |
T604 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_read_buffer_direct.3782836075 |
|
|
Sep 09 11:13:05 AM UTC 24 |
Sep 09 11:13:12 AM UTC 24 |
229000990 ps |
T605 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_alert_test.653538585 |
|
|
Sep 09 11:13:11 AM UTC 24 |
Sep 09 11:13:13 AM UTC 24 |
11799402 ps |
T606 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode.2607632679 |
|
|
Sep 09 11:13:01 AM UTC 24 |
Sep 09 11:13:15 AM UTC 24 |
1119157069 ps |
T607 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_csb_read.4048458320 |
|
|
Sep 09 11:13:13 AM UTC 24 |
Sep 09 11:13:15 AM UTC 24 |
52533121 ps |
T335 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_intercept.555619655 |
|
|
Sep 09 11:12:58 AM UTC 24 |
Sep 09 11:13:15 AM UTC 24 |
852683261 ps |
T608 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_tpm_all.745665668 |
|
|
Sep 09 11:12:51 AM UTC 24 |
Sep 09 11:13:15 AM UTC 24 |
2628127217 ps |
T609 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_all.2672493810 |
|
|
Sep 09 11:13:14 AM UTC 24 |
Sep 09 11:13:16 AM UTC 24 |
34470286 ps |
T610 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_sts_read.1998103835 |
|
|
Sep 09 11:13:14 AM UTC 24 |
Sep 09 11:13:16 AM UTC 24 |
312481633 ps |
T611 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/15.spi_device_flash_and_tpm_min_idle.2594684077 |
|
|
Sep 09 11:10:43 AM UTC 24 |
Sep 09 11:13:20 AM UTC 24 |
19594276416 ps |
T612 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_rw.3825302289 |
|
|
Sep 09 11:13:15 AM UTC 24 |
Sep 09 11:13:21 AM UTC 24 |
941341429 ps |
T613 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_all.558481113 |
|
|
Sep 09 11:13:06 AM UTC 24 |
Sep 09 11:13:21 AM UTC 24 |
566923518 ps |
T263 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm.4193096590 |
|
|
Sep 09 11:09:13 AM UTC 24 |
Sep 09 11:13:21 AM UTC 24 |
49357627381 ps |
T309 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_pass_cmd_filtering.2972728117 |
|
|
Sep 09 11:12:56 AM UTC 24 |
Sep 09 11:13:22 AM UTC 24 |
55856538265 ps |
T614 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_addr_payload_swap.1149414803 |
|
|
Sep 09 11:13:16 AM UTC 24 |
Sep 09 11:13:26 AM UTC 24 |
7308741316 ps |
T615 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_intercept.647026790 |
|
|
Sep 09 11:13:16 AM UTC 24 |
Sep 09 11:13:28 AM UTC 24 |
560523169 ps |
T616 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_cfg_cmd.3498205394 |
|
|
Sep 09 11:13:21 AM UTC 24 |
Sep 09 11:13:30 AM UTC 24 |
1698384577 ps |
T617 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/7.spi_device_flash_all.103613081 |
|
|
Sep 09 11:09:08 AM UTC 24 |
Sep 09 11:13:31 AM UTC 24 |
295392334224 ps |
T618 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_mode.28048550 |
|
|
Sep 09 11:13:22 AM UTC 24 |
Sep 09 11:13:33 AM UTC 24 |
2446148974 ps |
T619 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_upload.2946515774 |
|
|
Sep 09 11:13:17 AM UTC 24 |
Sep 09 11:13:36 AM UTC 24 |
3782382482 ps |
T620 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_pass_cmd_filtering.46549049 |
|
|
Sep 09 11:13:16 AM UTC 24 |
Sep 09 11:13:35 AM UTC 24 |
6606953776 ps |
T621 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_csb_read.3990626514 |
|
|
Sep 09 11:13:34 AM UTC 24 |
Sep 09 11:13:36 AM UTC 24 |
15325261 ps |
T239 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_mode_ignore_cmds.2382858119 |
|
|
Sep 09 11:08:28 AM UTC 24 |
Sep 09 11:13:37 AM UTC 24 |
39251573320 ps |
T622 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_all.948871681 |
|
|
Sep 09 11:13:35 AM UTC 24 |
Sep 09 11:13:37 AM UTC 24 |
34853704 ps |
T623 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_rw.3383670392 |
|
|
Sep 09 11:13:37 AM UTC 24 |
Sep 09 11:13:39 AM UTC 24 |
26397563 ps |
T624 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_sts_read.4037402931 |
|
|
Sep 09 11:13:36 AM UTC 24 |
Sep 09 11:13:39 AM UTC 24 |
92374536 ps |
T300 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/17.spi_device_flash_and_tpm.1403310302 |
|
|
Sep 09 11:11:11 AM UTC 24 |
Sep 09 11:13:39 AM UTC 24 |
8889516304 ps |
T234 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/23.spi_device_flash_mode_ignore_cmds.1149029113 |
|
|
Sep 09 11:12:45 AM UTC 24 |
Sep 09 11:13:40 AM UTC 24 |
12595734572 ps |
T266 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm.4267950728 |
|
|
Sep 09 11:12:18 AM UTC 24 |
Sep 09 11:13:43 AM UTC 24 |
98268142089 ps |
T625 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_pass_cmd_filtering.621493941 |
|
|
Sep 09 11:13:38 AM UTC 24 |
Sep 09 11:13:43 AM UTC 24 |
230077112 ps |
T626 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_tpm_read_hw_reg.3054961350 |
|
|
Sep 09 11:13:13 AM UTC 24 |
Sep 09 11:13:43 AM UTC 24 |
24542915973 ps |
T267 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/11.spi_device_flash_and_tpm.4068691469 |
|
|
Sep 09 11:09:51 AM UTC 24 |
Sep 09 11:13:45 AM UTC 24 |
17263119296 ps |
T627 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode.3644345014 |
|
|
Sep 09 11:13:41 AM UTC 24 |
Sep 09 11:13:46 AM UTC 24 |
146645687 ps |
T91 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/8.spi_device_flash_and_tpm_min_idle.3870864452 |
|
|
Sep 09 11:09:13 AM UTC 24 |
Sep 09 11:13:48 AM UTC 24 |
28721447207 ps |
T628 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_read_buffer_direct.874515294 |
|
|
Sep 09 11:13:43 AM UTC 24 |
Sep 09 11:13:49 AM UTC 24 |
263329975 ps |
T629 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/20.spi_device_flash_and_tpm_min_idle.1736513397 |
|
|
Sep 09 11:12:07 AM UTC 24 |
Sep 09 11:13:50 AM UTC 24 |
10608160145 ps |
T130 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_mode_ignore_cmds.19901247 |
|
|
Sep 09 11:12:15 AM UTC 24 |
Sep 09 11:13:51 AM UTC 24 |
3826276467 ps |
T364 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_intercept.3912191802 |
|
|
Sep 09 11:13:39 AM UTC 24 |
Sep 09 11:13:51 AM UTC 24 |
1228712281 ps |
T630 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_alert_test.3351355924 |
|
|
Sep 09 11:13:50 AM UTC 24 |
Sep 09 11:13:52 AM UTC 24 |
163098399 ps |
T631 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_csb_read.2491922811 |
|
|
Sep 09 11:13:51 AM UTC 24 |
Sep 09 11:13:53 AM UTC 24 |
24833459 ps |
T632 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/24.spi_device_flash_mode_ignore_cmds.1574124148 |
|
|
Sep 09 11:13:04 AM UTC 24 |
Sep 09 11:13:54 AM UTC 24 |
3222942212 ps |
T633 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_cfg_cmd.3157677782 |
|
|
Sep 09 11:13:41 AM UTC 24 |
Sep 09 11:13:55 AM UTC 24 |
5314061989 ps |
T634 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_sts_read.2592894515 |
|
|
Sep 09 11:13:53 AM UTC 24 |
Sep 09 11:13:55 AM UTC 24 |
119188430 ps |
T264 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/1.spi_device_flash_and_tpm.2905735989 |
|
|
Sep 09 11:08:28 AM UTC 24 |
Sep 09 11:13:56 AM UTC 24 |
32263466440 ps |
T635 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_read_hw_reg.2865846117 |
|
|
Sep 09 11:13:52 AM UTC 24 |
Sep 09 11:13:57 AM UTC 24 |
901424602 ps |
T636 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_tpm_rw.3079621698 |
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Sep 09 11:13:54 AM UTC 24 |
Sep 09 11:13:58 AM UTC 24 |
350093299 ps |
T637 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_addr_payload_swap.230971581 |
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Sep 09 11:13:56 AM UTC 24 |
Sep 09 11:14:01 AM UTC 24 |
505067172 ps |
T638 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_upload.339685475 |
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Sep 09 11:13:40 AM UTC 24 |
Sep 09 11:14:01 AM UTC 24 |
13207089453 ps |
T639 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_mailbox.1352277148 |
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Sep 09 11:13:17 AM UTC 24 |
Sep 09 11:14:03 AM UTC 24 |
13154165507 ps |
T640 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_tpm_read_hw_reg.1062597890 |
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Sep 09 11:13:35 AM UTC 24 |
Sep 09 11:14:03 AM UTC 24 |
18345002089 ps |
T641 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_flash_and_tpm_min_idle.2855764854 |
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Sep 09 11:12:20 AM UTC 24 |
Sep 09 11:14:04 AM UTC 24 |
13493861639 ps |
T642 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_cfg_cmd.3907686717 |
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Sep 09 11:13:58 AM UTC 24 |
Sep 09 11:14:04 AM UTC 24 |
264429439 ps |
T241 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_all.4086538622 |
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Sep 09 11:13:24 AM UTC 24 |
Sep 09 11:14:05 AM UTC 24 |
7560807742 ps |
T643 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_flash_mode_ignore_cmds.2475260372 |
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Sep 09 11:13:43 AM UTC 24 |
Sep 09 11:14:06 AM UTC 24 |
19516029430 ps |
T366 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/27.spi_device_pass_cmd_filtering.209147222 |
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Sep 09 11:13:54 AM UTC 24 |
Sep 09 11:14:07 AM UTC 24 |
20520552269 ps |