| T834 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_read_hw_reg.1799586030 |
|
|
Sep 09 11:17:21 AM UTC 24 |
Sep 09 11:17:43 AM UTC 24 |
37179288020 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_alert_test.3589915515 |
|
|
Sep 09 11:17:41 AM UTC 24 |
Sep 09 11:17:44 AM UTC 24 |
22488385 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_csb_read.3525617899 |
|
|
Sep 09 11:17:41 AM UTC 24 |
Sep 09 11:17:44 AM UTC 24 |
45267580 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_tpm_all.2217393526 |
|
|
Sep 09 11:17:23 AM UTC 24 |
Sep 09 11:17:44 AM UTC 24 |
4292043697 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_mailbox.2332643826 |
|
|
Sep 09 11:17:10 AM UTC 24 |
Sep 09 11:17:44 AM UTC 24 |
6170110416 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_sts_read.2899580629 |
|
|
Sep 09 11:17:43 AM UTC 24 |
Sep 09 11:17:45 AM UTC 24 |
29621966 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_rw.2870007681 |
|
|
Sep 09 11:17:44 AM UTC 24 |
Sep 09 11:17:46 AM UTC 24 |
45453508 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/22.spi_device_stress_all.2780871523 |
|
|
Sep 09 11:12:36 AM UTC 24 |
Sep 09 11:17:46 AM UTC 24 |
29046460928 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_all.181554747 |
|
|
Sep 09 11:15:41 AM UTC 24 |
Sep 09 11:17:47 AM UTC 24 |
22465577429 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_read_hw_reg.869739639 |
|
|
Sep 09 11:17:43 AM UTC 24 |
Sep 09 11:17:49 AM UTC 24 |
767842539 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_mailbox.771481594 |
|
|
Sep 09 11:17:29 AM UTC 24 |
Sep 09 11:17:50 AM UTC 24 |
1035438820 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_intercept.386134747 |
|
|
Sep 09 11:17:45 AM UTC 24 |
Sep 09 11:17:50 AM UTC 24 |
749621071 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode.1840662256 |
|
|
Sep 09 11:17:47 AM UTC 24 |
Sep 09 11:17:53 AM UTC 24 |
159275369 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/21.spi_device_stress_all.3875258538 |
|
|
Sep 09 11:12:21 AM UTC 24 |
Sep 09 11:17:54 AM UTC 24 |
99970493607 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_addr_payload_swap.3317183161 |
|
|
Sep 09 11:17:26 AM UTC 24 |
Sep 09 11:17:55 AM UTC 24 |
11944636667 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_pass_cmd_filtering.2441829568 |
|
|
Sep 09 11:17:26 AM UTC 24 |
Sep 09 11:17:55 AM UTC 24 |
25386580298 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_mailbox.1778294678 |
|
|
Sep 09 11:17:45 AM UTC 24 |
Sep 09 11:17:55 AM UTC 24 |
343171959 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_cfg_cmd.1440117312 |
|
|
Sep 09 11:17:47 AM UTC 24 |
Sep 09 11:17:56 AM UTC 24 |
2038133170 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_upload.872880269 |
|
|
Sep 09 11:17:46 AM UTC 24 |
Sep 09 11:17:56 AM UTC 24 |
1285291796 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_cmd_filtering.4076874258 |
|
|
Sep 09 11:17:45 AM UTC 24 |
Sep 09 11:17:57 AM UTC 24 |
1159595367 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_read_buffer_direct.520483219 |
|
|
Sep 09 11:17:49 AM UTC 24 |
Sep 09 11:17:58 AM UTC 24 |
1661866296 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_csb_read.648711056 |
|
|
Sep 09 11:18:51 AM UTC 24 |
Sep 09 11:18:53 AM UTC 24 |
18541559 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_alert_test.3578792093 |
|
|
Sep 09 11:17:56 AM UTC 24 |
Sep 09 11:17:58 AM UTC 24 |
11853162 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_csb_read.2779356390 |
|
|
Sep 09 11:17:56 AM UTC 24 |
Sep 09 11:17:58 AM UTC 24 |
25120788 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_and_tpm_min_idle.3134373850 |
|
|
Sep 09 11:16:34 AM UTC 24 |
Sep 09 11:17:59 AM UTC 24 |
35928946643 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_stress_all.2469756640 |
|
|
Sep 09 11:17:40 AM UTC 24 |
Sep 09 11:17:59 AM UTC 24 |
7935960578 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_sts_read.2573791582 |
|
|
Sep 09 11:17:57 AM UTC 24 |
Sep 09 11:17:59 AM UTC 24 |
54160404 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_all.3831175023 |
|
|
Sep 09 11:17:57 AM UTC 24 |
Sep 09 11:17:59 AM UTC 24 |
32988255 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_rw.4133570227 |
|
|
Sep 09 11:17:58 AM UTC 24 |
Sep 09 11:18:01 AM UTC 24 |
35187808 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm_min_idle.48755690 |
|
|
Sep 09 11:15:57 AM UTC 24 |
Sep 09 11:18:03 AM UTC 24 |
15730151568 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode.2392923533 |
|
|
Sep 09 11:17:33 AM UTC 24 |
Sep 09 11:18:03 AM UTC 24 |
10511591643 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_intercept.1052404563 |
|
|
Sep 09 11:17:59 AM UTC 24 |
Sep 09 11:18:03 AM UTC 24 |
109499176 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm.3949277877 |
|
|
Sep 09 11:15:43 AM UTC 24 |
Sep 09 11:18:04 AM UTC 24 |
6991367297 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_mode_ignore_cmds.582618001 |
|
|
Sep 09 11:17:47 AM UTC 24 |
Sep 09 11:18:05 AM UTC 24 |
2386974307 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_upload.1833689876 |
|
|
Sep 09 11:18:00 AM UTC 24 |
Sep 09 11:18:05 AM UTC 24 |
119363612 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm.869921910 |
|
|
Sep 09 11:16:48 AM UTC 24 |
Sep 09 11:18:07 AM UTC 24 |
18510897302 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_alert_test.2814110876 |
|
|
Sep 09 11:18:06 AM UTC 24 |
Sep 09 11:18:08 AM UTC 24 |
65480989 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_stress_all.1089547376 |
|
|
Sep 09 11:18:06 AM UTC 24 |
Sep 09 11:18:09 AM UTC 24 |
38145583 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_mailbox.2876050004 |
|
|
Sep 09 11:17:59 AM UTC 24 |
Sep 09 11:18:09 AM UTC 24 |
626649685 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_addr_payload_swap.644933136 |
|
|
Sep 09 11:17:59 AM UTC 24 |
Sep 09 11:18:10 AM UTC 24 |
1908099895 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_csb_read.3420488523 |
|
|
Sep 09 11:18:08 AM UTC 24 |
Sep 09 11:18:11 AM UTC 24 |
22121112 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_sts_read.2078801411 |
|
|
Sep 09 11:18:09 AM UTC 24 |
Sep 09 11:18:12 AM UTC 24 |
66781391 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_cfg_cmd.388128045 |
|
|
Sep 09 11:18:01 AM UTC 24 |
Sep 09 11:18:12 AM UTC 24 |
1818243854 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_rw.3156231337 |
|
|
Sep 09 11:18:11 AM UTC 24 |
Sep 09 11:18:14 AM UTC 24 |
88901798 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_tpm_read_hw_reg.3002058695 |
|
|
Sep 09 11:17:56 AM UTC 24 |
Sep 09 11:18:15 AM UTC 24 |
47919298398 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_tpm_all.2462390068 |
|
|
Sep 09 11:17:43 AM UTC 24 |
Sep 09 11:18:15 AM UTC 24 |
50464664285 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_all.1430999536 |
|
|
Sep 09 11:18:09 AM UTC 24 |
Sep 09 11:18:15 AM UTC 24 |
384377136 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/34.spi_device_flash_and_tpm.3787663502 |
|
|
Sep 09 11:15:57 AM UTC 24 |
Sep 09 11:18:16 AM UTC 24 |
22947013527 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_stress_all.3190587828 |
|
|
Sep 09 11:17:19 AM UTC 24 |
Sep 09 11:18:17 AM UTC 24 |
2220779836 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_pass_addr_payload_swap.2601473286 |
|
|
Sep 09 11:17:45 AM UTC 24 |
Sep 09 11:18:18 AM UTC 24 |
43832375578 ps |
| T45 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_flash_and_tpm.1182262953 |
|
|
Sep 09 11:11:32 AM UTC 24 |
Sep 09 11:18:19 AM UTC 24 |
72695379305 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm_min_idle.3836966064 |
|
|
Sep 09 11:17:40 AM UTC 24 |
Sep 09 11:18:19 AM UTC 24 |
9351961543 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_read_buffer_direct.2540636298 |
|
|
Sep 09 11:18:04 AM UTC 24 |
Sep 09 11:18:19 AM UTC 24 |
2011106098 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/25.spi_device_flash_and_tpm.3160911517 |
|
|
Sep 09 11:13:27 AM UTC 24 |
Sep 09 11:18:21 AM UTC 24 |
22341157239 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_cmd_filtering.604826829 |
|
|
Sep 09 11:18:12 AM UTC 24 |
Sep 09 11:18:21 AM UTC 24 |
1474467745 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_intercept.3804973465 |
|
|
Sep 09 11:18:13 AM UTC 24 |
Sep 09 11:18:21 AM UTC 24 |
1923786261 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_tpm_read_hw_reg.2283387212 |
|
|
Sep 09 11:18:09 AM UTC 24 |
Sep 09 11:18:23 AM UTC 24 |
16584698499 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_stress_all.1792965117 |
|
|
Sep 09 11:10:12 AM UTC 24 |
Sep 09 11:18:24 AM UTC 24 |
191718757480 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_alert_test.1754123191 |
|
|
Sep 09 11:18:22 AM UTC 24 |
Sep 09 11:18:24 AM UTC 24 |
22360509 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_csb_read.882124916 |
|
|
Sep 09 11:18:22 AM UTC 24 |
Sep 09 11:18:24 AM UTC 24 |
17384024 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_mailbox.217742579 |
|
|
Sep 09 11:18:15 AM UTC 24 |
Sep 09 11:18:24 AM UTC 24 |
278252288 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_read_buffer_direct.1348338790 |
|
|
Sep 09 11:18:18 AM UTC 24 |
Sep 09 11:18:24 AM UTC 24 |
212338541 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode.3402681988 |
|
|
Sep 09 11:18:16 AM UTC 24 |
Sep 09 11:18:25 AM UTC 24 |
462409164 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_cfg_cmd.2612554775 |
|
|
Sep 09 11:18:16 AM UTC 24 |
Sep 09 11:18:25 AM UTC 24 |
1378007300 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_mode_ignore_cmds.749046034 |
|
|
Sep 09 11:14:52 AM UTC 24 |
Sep 09 11:18:25 AM UTC 24 |
214414979349 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_all.815457219 |
|
|
Sep 09 11:16:59 AM UTC 24 |
Sep 09 11:18:27 AM UTC 24 |
6444809126 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_upload.1543786949 |
|
|
Sep 09 11:18:16 AM UTC 24 |
Sep 09 11:18:27 AM UTC 24 |
11169448702 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_rw.3596414338 |
|
|
Sep 09 11:18:25 AM UTC 24 |
Sep 09 11:18:27 AM UTC 24 |
15486823 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_sts_read.3212335887 |
|
|
Sep 09 11:18:25 AM UTC 24 |
Sep 09 11:18:28 AM UTC 24 |
435877693 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_pass_cmd_filtering.1252886847 |
|
|
Sep 09 11:17:58 AM UTC 24 |
Sep 09 11:18:29 AM UTC 24 |
4805059249 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_intercept.2206589819 |
|
|
Sep 09 11:18:41 AM UTC 24 |
Sep 09 11:18:51 AM UTC 24 |
624152746 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_intercept.2112751245 |
|
|
Sep 09 11:18:25 AM UTC 24 |
Sep 09 11:18:29 AM UTC 24 |
473766151 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_cfg_cmd.3875548124 |
|
|
Sep 09 11:18:26 AM UTC 24 |
Sep 09 11:18:31 AM UTC 24 |
94581490 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_addr_payload_swap.3444756579 |
|
|
Sep 09 11:18:25 AM UTC 24 |
Sep 09 11:18:32 AM UTC 24 |
3126118282 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_mode.261565464 |
|
|
Sep 09 11:17:14 AM UTC 24 |
Sep 09 11:18:34 AM UTC 24 |
5400971805 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_read_buffer_direct.3313877573 |
|
|
Sep 09 11:18:29 AM UTC 24 |
Sep 09 11:18:34 AM UTC 24 |
175228904 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_upload.1220632932 |
|
|
Sep 09 11:18:26 AM UTC 24 |
Sep 09 11:18:35 AM UTC 24 |
2606076597 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_alert_test.3911827993 |
|
|
Sep 09 11:18:33 AM UTC 24 |
Sep 09 11:18:35 AM UTC 24 |
21565953 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_csb_read.4060273153 |
|
|
Sep 09 11:18:35 AM UTC 24 |
Sep 09 11:18:37 AM UTC 24 |
18473655 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_read_hw_reg.1437881050 |
|
|
Sep 09 11:18:22 AM UTC 24 |
Sep 09 11:18:38 AM UTC 24 |
30004401004 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_sts_read.3315430063 |
|
|
Sep 09 11:18:36 AM UTC 24 |
Sep 09 11:18:39 AM UTC 24 |
81217730 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_all.2037477504 |
|
|
Sep 09 11:17:39 AM UTC 24 |
Sep 09 11:18:40 AM UTC 24 |
4411377933 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/13.spi_device_flash_and_tpm.1254531949 |
|
|
Sep 09 11:10:10 AM UTC 24 |
Sep 09 11:18:41 AM UTC 24 |
351031541000 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_mailbox.2704291421 |
|
|
Sep 09 11:18:25 AM UTC 24 |
Sep 09 11:18:41 AM UTC 24 |
2433783315 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode.1120907040 |
|
|
Sep 09 11:18:01 AM UTC 24 |
Sep 09 11:18:42 AM UTC 24 |
1914288475 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_rw.2402628935 |
|
|
Sep 09 11:18:38 AM UTC 24 |
Sep 09 11:18:42 AM UTC 24 |
145663743 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_addr_payload_swap.3656243173 |
|
|
Sep 09 11:18:40 AM UTC 24 |
Sep 09 11:18:44 AM UTC 24 |
97085449 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_pass_cmd_filtering.1790471267 |
|
|
Sep 09 11:18:25 AM UTC 24 |
Sep 09 11:18:44 AM UTC 24 |
10772706780 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_cfg_cmd.3082537332 |
|
|
Sep 09 11:18:42 AM UTC 24 |
Sep 09 11:18:46 AM UTC 24 |
75452998 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_and_tpm_min_idle.3377137474 |
|
|
Sep 09 11:16:48 AM UTC 24 |
Sep 09 11:18:46 AM UTC 24 |
116368457094 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_all.2452593077 |
|
|
Sep 09 11:18:18 AM UTC 24 |
Sep 09 11:18:47 AM UTC 24 |
3088719576 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_mode_ignore_cmds.369132160 |
|
|
Sep 09 11:18:17 AM UTC 24 |
Sep 09 11:18:47 AM UTC 24 |
2836609681 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_read_hw_reg.3059679318 |
|
|
Sep 09 11:18:35 AM UTC 24 |
Sep 09 11:18:49 AM UTC 24 |
13817341689 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode.2247543391 |
|
|
Sep 09 11:18:42 AM UTC 24 |
Sep 09 11:18:50 AM UTC 24 |
505186797 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_alert_test.3192660115 |
|
|
Sep 09 11:18:49 AM UTC 24 |
Sep 09 11:18:51 AM UTC 24 |
13780062 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode.1504927791 |
|
|
Sep 09 11:18:28 AM UTC 24 |
Sep 09 11:18:52 AM UTC 24 |
1648629105 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm.1382862951 |
|
|
Sep 09 11:17:17 AM UTC 24 |
Sep 09 11:18:53 AM UTC 24 |
22813072284 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_read_hw_reg.1297793933 |
|
|
Sep 09 11:18:51 AM UTC 24 |
Sep 09 11:18:54 AM UTC 24 |
173288841 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_sts_read.1351721229 |
|
|
Sep 09 11:18:52 AM UTC 24 |
Sep 09 11:18:54 AM UTC 24 |
87333746 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_stress_all.4105896706 |
|
|
Sep 09 11:17:56 AM UTC 24 |
Sep 09 11:18:55 AM UTC 24 |
10460931149 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_pass_cmd_filtering.3129432876 |
|
|
Sep 09 11:18:38 AM UTC 24 |
Sep 09 11:18:59 AM UTC 24 |
4376664734 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_upload.310786041 |
|
|
Sep 09 11:18:55 AM UTC 24 |
Sep 09 11:19:00 AM UTC 24 |
813173713 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_rw.1435395253 |
|
|
Sep 09 11:18:53 AM UTC 24 |
Sep 09 11:19:02 AM UTC 24 |
217741149 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_tpm_all.1485669332 |
|
|
Sep 09 11:18:52 AM UTC 24 |
Sep 09 11:19:02 AM UTC 24 |
1781010762 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_intercept.1109854875 |
|
|
Sep 09 11:18:55 AM UTC 24 |
Sep 09 11:19:03 AM UTC 24 |
1511814994 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_upload.4071405726 |
|
|
Sep 09 11:18:42 AM UTC 24 |
Sep 09 11:19:03 AM UTC 24 |
11469011309 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_cmd_filtering.3293386503 |
|
|
Sep 09 11:18:54 AM UTC 24 |
Sep 09 11:19:04 AM UTC 24 |
1206851575 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_read_buffer_direct.2081447310 |
|
|
Sep 09 11:18:44 AM UTC 24 |
Sep 09 11:19:05 AM UTC 24 |
1843350625 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode_ignore_cmds.1836559040 |
|
|
Sep 09 11:19:03 AM UTC 24 |
Sep 09 11:19:05 AM UTC 24 |
88780877 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_tpm_all.3249002536 |
|
|
Sep 09 11:18:36 AM UTC 24 |
Sep 09 11:19:05 AM UTC 24 |
18788716484 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_and_tpm.2497774899 |
|
|
Sep 09 11:17:40 AM UTC 24 |
Sep 09 11:19:05 AM UTC 24 |
18653303129 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_pass_addr_payload_swap.980729770 |
|
|
Sep 09 11:18:13 AM UTC 24 |
Sep 09 11:19:06 AM UTC 24 |
14062068266 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_cfg_cmd.2552424496 |
|
|
Sep 09 11:19:00 AM UTC 24 |
Sep 09 11:19:06 AM UTC 24 |
312740393 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/29.spi_device_stress_all.2496328764 |
|
|
Sep 09 11:14:42 AM UTC 24 |
Sep 09 11:19:06 AM UTC 24 |
76699004466 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_alert_test.2907648193 |
|
|
Sep 09 11:19:06 AM UTC 24 |
Sep 09 11:19:08 AM UTC 24 |
33349046 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_mode.3890745375 |
|
|
Sep 09 11:19:02 AM UTC 24 |
Sep 09 11:19:08 AM UTC 24 |
307615475 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_csb_read.4264298519 |
|
|
Sep 09 11:19:06 AM UTC 24 |
Sep 09 11:19:08 AM UTC 24 |
19241624 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_stress_all.187383172 |
|
|
Sep 09 11:19:06 AM UTC 24 |
Sep 09 11:19:09 AM UTC 24 |
134445332 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_all.269957243 |
|
|
Sep 09 11:19:07 AM UTC 24 |
Sep 09 11:19:09 AM UTC 24 |
26823077 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_rw.1969873462 |
|
|
Sep 09 11:19:07 AM UTC 24 |
Sep 09 11:19:10 AM UTC 24 |
21182884 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_sts_read.54046481 |
|
|
Sep 09 11:19:07 AM UTC 24 |
Sep 09 11:19:10 AM UTC 24 |
366592517 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_tpm_all.1043601700 |
|
|
Sep 09 11:18:24 AM UTC 24 |
Sep 09 11:19:10 AM UTC 24 |
12344360595 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/40.spi_device_flash_mode_ignore_cmds.2704942490 |
|
|
Sep 09 11:17:34 AM UTC 24 |
Sep 09 11:19:10 AM UTC 24 |
16972562078 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_mode_ignore_cmds.3822963658 |
|
|
Sep 09 11:18:02 AM UTC 24 |
Sep 09 11:19:15 AM UTC 24 |
22148613623 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_read_buffer_direct.2682710416 |
|
|
Sep 09 11:19:11 AM UTC 24 |
Sep 09 11:19:18 AM UTC 24 |
552175790 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_mailbox.3900282293 |
|
|
Sep 09 11:18:55 AM UTC 24 |
Sep 09 11:19:18 AM UTC 24 |
2344024804 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_cfg_cmd.3976998007 |
|
|
Sep 09 11:19:11 AM UTC 24 |
Sep 09 11:19:18 AM UTC 24 |
1258159882 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_flash_mode_ignore_cmds.1051441570 |
|
|
Sep 09 11:16:30 AM UTC 24 |
Sep 09 11:19:19 AM UTC 24 |
15246081236 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_read_buffer_direct.1157253842 |
|
|
Sep 09 11:19:03 AM UTC 24 |
Sep 09 11:19:19 AM UTC 24 |
5716243332 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/30.spi_device_flash_and_tpm.1513021382 |
|
|
Sep 09 11:14:54 AM UTC 24 |
Sep 09 11:19:19 AM UTC 24 |
227113259322 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_intercept.2430427349 |
|
|
Sep 09 11:19:10 AM UTC 24 |
Sep 09 11:19:20 AM UTC 24 |
522265446 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode.4020819953 |
|
|
Sep 09 11:19:11 AM UTC 24 |
Sep 09 11:19:21 AM UTC 24 |
152018425 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_addr_payload_swap.262436611 |
|
|
Sep 09 11:19:10 AM UTC 24 |
Sep 09 11:19:21 AM UTC 24 |
1591850213 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_alert_test.2755961402 |
|
|
Sep 09 11:19:20 AM UTC 24 |
Sep 09 11:19:22 AM UTC 24 |
15039899 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_all.768991183 |
|
|
Sep 09 11:18:04 AM UTC 24 |
Sep 09 11:19:23 AM UTC 24 |
26905891659 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_csb_read.3974949821 |
|
|
Sep 09 11:19:21 AM UTC 24 |
Sep 09 11:19:23 AM UTC 24 |
19469666 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_sts_read.486013728 |
|
|
Sep 09 11:19:22 AM UTC 24 |
Sep 09 11:19:25 AM UTC 24 |
32182382 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_upload.3529782724 |
|
|
Sep 09 11:19:11 AM UTC 24 |
Sep 09 11:19:25 AM UTC 24 |
1563581886 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_all.3618346148 |
|
|
Sep 09 11:19:22 AM UTC 24 |
Sep 09 11:19:47 AM UTC 24 |
8147388885 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_rw.4025411119 |
|
|
Sep 09 11:19:22 AM UTC 24 |
Sep 09 11:19:25 AM UTC 24 |
33672717 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm.1218223333 |
|
|
Sep 09 11:18:46 AM UTC 24 |
Sep 09 11:19:25 AM UTC 24 |
10023208298 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_tpm_read_hw_reg.1897725158 |
|
|
Sep 09 11:19:06 AM UTC 24 |
Sep 09 11:19:26 AM UTC 24 |
13278323466 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_intercept.1727642433 |
|
|
Sep 09 11:19:24 AM UTC 24 |
Sep 09 11:19:28 AM UTC 24 |
380593804 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_mailbox.393298059 |
|
|
Sep 09 11:19:10 AM UTC 24 |
Sep 09 11:19:31 AM UTC 24 |
4588560912 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm_min_idle.3614300043 |
|
|
Sep 09 11:18:19 AM UTC 24 |
Sep 09 11:19:32 AM UTC 24 |
3188159348 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_stress_all.4170057135 |
|
|
Sep 09 11:17:00 AM UTC 24 |
Sep 09 11:19:33 AM UTC 24 |
30997240841 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_stress_all.3945624376 |
|
|
Sep 09 11:18:32 AM UTC 24 |
Sep 09 11:19:33 AM UTC 24 |
5693713538 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_cfg_cmd.540306918 |
|
|
Sep 09 11:19:26 AM UTC 24 |
Sep 09 11:19:34 AM UTC 24 |
350456662 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode.1475608074 |
|
|
Sep 09 11:19:26 AM UTC 24 |
Sep 09 11:19:34 AM UTC 24 |
230103856 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_all.4037722523 |
|
|
Sep 09 11:16:47 AM UTC 24 |
Sep 09 11:19:34 AM UTC 24 |
21199027131 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_read_buffer_direct.452828826 |
|
|
Sep 09 11:19:30 AM UTC 24 |
Sep 09 11:19:35 AM UTC 24 |
114805883 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_tpm_read_hw_reg.602914873 |
|
|
Sep 09 11:19:21 AM UTC 24 |
Sep 09 11:19:36 AM UTC 24 |
8045062684 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_all.1485204578 |
|
|
Sep 09 11:19:15 AM UTC 24 |
Sep 09 11:19:37 AM UTC 24 |
2937715703 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_csb_read.1670863655 |
|
|
Sep 09 11:19:35 AM UTC 24 |
Sep 09 11:19:37 AM UTC 24 |
34117435 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_alert_test.2226028699 |
|
|
Sep 09 11:19:35 AM UTC 24 |
Sep 09 11:19:37 AM UTC 24 |
69565685 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_upload.2063014088 |
|
|
Sep 09 11:19:25 AM UTC 24 |
Sep 09 11:19:39 AM UTC 24 |
1202781065 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_sts_read.2295963995 |
|
|
Sep 09 11:19:37 AM UTC 24 |
Sep 09 11:19:40 AM UTC 24 |
203580049 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_all.1424203072 |
|
|
Sep 09 11:15:26 AM UTC 24 |
Sep 09 11:19:40 AM UTC 24 |
542186474878 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_rw.169644394 |
|
|
Sep 09 11:19:37 AM UTC 24 |
Sep 09 11:19:41 AM UTC 24 |
458856147 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_pass_addr_payload_swap.3025372692 |
|
|
Sep 09 11:18:54 AM UTC 24 |
Sep 09 11:19:42 AM UTC 24 |
52227186123 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_mailbox.282739362 |
|
|
Sep 09 11:18:41 AM UTC 24 |
Sep 09 11:19:42 AM UTC 24 |
24169686645 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_cmd_filtering.3657436731 |
|
|
Sep 09 11:19:38 AM UTC 24 |
Sep 09 11:19:43 AM UTC 24 |
157425226 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/4.spi_device_flash_all.4103340499 |
|
|
Sep 09 11:08:43 AM UTC 24 |
Sep 09 11:19:43 AM UTC 24 |
82465625384 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm_min_idle.3414443041 |
|
|
Sep 09 11:19:18 AM UTC 24 |
Sep 09 11:19:43 AM UTC 24 |
3323053061 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_mode_ignore_cmds.2368376782 |
|
|
Sep 09 11:18:43 AM UTC 24 |
Sep 09 11:19:44 AM UTC 24 |
13250440922 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_all.2806167609 |
|
|
Sep 09 11:17:17 AM UTC 24 |
Sep 09 11:19:45 AM UTC 24 |
72036146013 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_mailbox.897735133 |
|
|
Sep 09 11:19:25 AM UTC 24 |
Sep 09 11:19:45 AM UTC 24 |
3664346042 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_read_hw_reg.3064164165 |
|
|
Sep 09 11:19:35 AM UTC 24 |
Sep 09 11:19:45 AM UTC 24 |
10113270378 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm.1208371715 |
|
|
Sep 09 11:17:52 AM UTC 24 |
Sep 09 11:19:45 AM UTC 24 |
17393541829 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_pass_cmd_filtering.4294963633 |
|
|
Sep 09 11:19:09 AM UTC 24 |
Sep 09 11:19:46 AM UTC 24 |
6243934504 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_cfg_cmd.2458576281 |
|
|
Sep 09 11:19:42 AM UTC 24 |
Sep 09 11:19:47 AM UTC 24 |
755730958 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_tpm_all.3991814612 |
|
|
Sep 09 11:19:36 AM UTC 24 |
Sep 09 11:19:47 AM UTC 24 |
1005558695 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_alert_test.2719917304 |
|
|
Sep 09 11:19:45 AM UTC 24 |
Sep 09 11:19:48 AM UTC 24 |
22674181 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_intercept.3140838243 |
|
|
Sep 09 11:19:41 AM UTC 24 |
Sep 09 11:19:48 AM UTC 24 |
730211662 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_upload.1502537864 |
|
|
Sep 09 11:19:41 AM UTC 24 |
Sep 09 11:19:48 AM UTC 24 |
217809385 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_addr_payload_swap.3853113731 |
|
|
Sep 09 11:19:23 AM UTC 24 |
Sep 09 11:19:48 AM UTC 24 |
21692666873 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode.2741083043 |
|
|
Sep 09 11:19:43 AM UTC 24 |
Sep 09 11:19:49 AM UTC 24 |
107622248 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_pass_cmd_filtering.2976495883 |
|
|
Sep 09 11:19:23 AM UTC 24 |
Sep 09 11:19:50 AM UTC 24 |
6730893612 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_read_buffer_direct.2670920189 |
|
|
Sep 09 11:19:44 AM UTC 24 |
Sep 09 11:19:51 AM UTC 24 |
120001010 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_pass_addr_payload_swap.2176359067 |
|
|
Sep 09 11:19:39 AM UTC 24 |
Sep 09 11:19:51 AM UTC 24 |
2265544962 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_flash_and_tpm.1211975040 |
|
|
Sep 09 11:18:19 AM UTC 24 |
Sep 09 11:19:56 AM UTC 24 |
18648483432 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm_min_idle.752283135 |
|
|
Sep 09 11:19:05 AM UTC 24 |
Sep 09 11:20:05 AM UTC 24 |
8131390456 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_all.2019610136 |
|
|
Sep 09 11:18:44 AM UTC 24 |
Sep 09 11:20:12 AM UTC 24 |
42411534146 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_mode_ignore_cmds.469104780 |
|
|
Sep 09 11:16:58 AM UTC 24 |
Sep 09 11:20:25 AM UTC 24 |
112326163618 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_mode_ignore_cmds.1509056190 |
|
|
Sep 09 11:18:28 AM UTC 24 |
Sep 09 11:20:29 AM UTC 24 |
14025728148 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm_min_idle.892809442 |
|
|
Sep 09 11:16:16 AM UTC 24 |
Sep 09 11:20:31 AM UTC 24 |
315925229683 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm_min_idle.1005056676 |
|
|
Sep 09 11:19:45 AM UTC 24 |
Sep 09 11:20:36 AM UTC 24 |
5767527794 ps |
| T1003 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_flash_mode_ignore_cmds.3331735192 |
|
|
Sep 09 11:16:47 AM UTC 24 |
Sep 09 11:20:38 AM UTC 24 |
28179041799 ps |
| T1004 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_and_tpm.380299097 |
|
|
Sep 09 11:19:18 AM UTC 24 |
Sep 09 11:20:56 AM UTC 24 |
27241910614 ps |
| T1005 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm_min_idle.683885201 |
|
|
Sep 09 11:18:05 AM UTC 24 |
Sep 09 11:20:56 AM UTC 24 |
58976396888 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm_min_idle.4152693351 |
|
|
Sep 09 11:18:30 AM UTC 24 |
Sep 09 11:20:57 AM UTC 24 |
13073001750 ps |
| T1006 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_all.2091375797 |
|
|
Sep 09 11:17:51 AM UTC 24 |
Sep 09 11:21:14 AM UTC 24 |
101315337360 ps |
| T1007 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_stress_all.2164080739 |
|
|
Sep 09 11:19:45 AM UTC 24 |
Sep 09 11:21:19 AM UTC 24 |
11752377967 ps |
| T1008 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/33.spi_device_flash_and_tpm_min_idle.1666335385 |
|
|
Sep 09 11:15:43 AM UTC 24 |
Sep 09 11:21:20 AM UTC 24 |
85302611502 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_and_tpm.927349489 |
|
|
Sep 09 11:18:30 AM UTC 24 |
Sep 09 11:21:31 AM UTC 24 |
123367251192 ps |
| T1009 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_flash_and_tpm_min_idle.90339179 |
|
|
Sep 09 11:18:46 AM UTC 24 |
Sep 09 11:21:32 AM UTC 24 |
211581327976 ps |
| T1010 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/44.spi_device_flash_all.1084943065 |
|
|
Sep 09 11:18:29 AM UTC 24 |
Sep 09 11:21:44 AM UTC 24 |
27640399362 ps |
| T1011 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/37.spi_device_stress_all.2801606050 |
|
|
Sep 09 11:16:48 AM UTC 24 |
Sep 09 11:21:52 AM UTC 24 |
118530723941 ps |
| T1012 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_mode_ignore_cmds.1056872926 |
|
|
Sep 09 11:15:24 AM UTC 24 |
Sep 09 11:21:53 AM UTC 24 |
42357039433 ps |
| T1013 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_and_tpm.595818063 |
|
|
Sep 09 11:19:04 AM UTC 24 |
Sep 09 11:22:01 AM UTC 24 |
13821860692 ps |
| T1014 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/32.spi_device_flash_and_tpm_min_idle.3233903909 |
|
|
Sep 09 11:15:28 AM UTC 24 |
Sep 09 11:22:04 AM UTC 24 |
41140185735 ps |
| T1015 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_mode_ignore_cmds.4286837209 |
|
|
Sep 09 11:19:43 AM UTC 24 |
Sep 09 11:22:13 AM UTC 24 |
40822847725 ps |
| T1016 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm_min_idle.692602475 |
|
|
Sep 09 11:17:00 AM UTC 24 |
Sep 09 11:22:13 AM UTC 24 |
357882865039 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm_min_idle.3773939079 |
|
|
Sep 09 11:19:34 AM UTC 24 |
Sep 09 11:22:22 AM UTC 24 |
21560830724 ps |
| T1017 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/36.spi_device_stress_all.880691516 |
|
|
Sep 09 11:16:36 AM UTC 24 |
Sep 09 11:22:25 AM UTC 24 |
132405977238 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/16.spi_device_stress_all.2586371148 |
|
|
Sep 09 11:10:54 AM UTC 24 |
Sep 09 11:22:30 AM UTC 24 |
275739753792 ps |
| T1018 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/41.spi_device_flash_and_tpm_min_idle.4062638180 |
|
|
Sep 09 11:17:55 AM UTC 24 |
Sep 09 11:22:40 AM UTC 24 |
31927982423 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_and_tpm.3243675298 |
|
|
Sep 09 11:19:44 AM UTC 24 |
Sep 09 11:22:43 AM UTC 24 |
43499333896 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/26.spi_device_stress_all.3662739165 |
|
|
Sep 09 11:13:49 AM UTC 24 |
Sep 09 11:22:54 AM UTC 24 |
50304786176 ps |
| T1019 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/35.spi_device_flash_and_tpm.2403521316 |
|
|
Sep 09 11:16:15 AM UTC 24 |
Sep 09 11:22:59 AM UTC 24 |
154097296028 ps |
| T1020 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_mailbox.514203664 |
|
|
Sep 09 11:19:41 AM UTC 24 |
Sep 09 11:23:06 AM UTC 24 |
39572819196 ps |
| T1021 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_all.899510943 |
|
|
Sep 09 11:19:32 AM UTC 24 |
Sep 09 11:23:16 AM UTC 24 |
106702164073 ps |
| T1022 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/49.spi_device_flash_all.1746119413 |
|
|
Sep 09 11:19:44 AM UTC 24 |
Sep 09 11:23:27 AM UTC 24 |
121296140220 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/38.spi_device_flash_and_tpm.1397445414 |
|
|
Sep 09 11:16:59 AM UTC 24 |
Sep 09 11:23:30 AM UTC 24 |
39382463116 ps |
| T1023 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/43.spi_device_stress_all.224994027 |
|
|
Sep 09 11:18:21 AM UTC 24 |
Sep 09 11:23:43 AM UTC 24 |
31881555703 ps |
| T1024 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/46.spi_device_flash_all.2539196996 |
|
|
Sep 09 11:19:04 AM UTC 24 |
Sep 09 11:23:57 AM UTC 24 |
39274388484 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_flash_mode_ignore_cmds.3410569153 |
|
|
Sep 09 11:19:11 AM UTC 24 |
Sep 09 11:24:27 AM UTC 24 |
37916211841 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/3.spi_device_stress_all.1540885115 |
|
|
Sep 09 11:08:39 AM UTC 24 |
Sep 09 11:24:45 AM UTC 24 |
91504533319 ps |
| T1025 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/42.spi_device_flash_and_tpm.921322730 |
|
|
Sep 09 11:18:04 AM UTC 24 |
Sep 09 11:25:13 AM UTC 24 |
43553132585 ps |
| T1026 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_mode_ignore_cmds.3379909204 |
|
|
Sep 09 11:19:27 AM UTC 24 |
Sep 09 11:25:57 AM UTC 24 |
171707458497 ps |
| T1027 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/18.spi_device_stress_all.146586763 |
|
|
Sep 09 11:11:34 AM UTC 24 |
Sep 09 11:26:06 AM UTC 24 |
996012251345 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/39.spi_device_flash_and_tpm_min_idle.1891542445 |
|
|
Sep 09 11:17:18 AM UTC 24 |
Sep 09 11:26:54 AM UTC 24 |
109186943273 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_flash_and_tpm.430785880 |
|
|
Sep 09 11:19:33 AM UTC 24 |
Sep 09 11:27:41 AM UTC 24 |
197072118214 ps |
| T1028 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/48.spi_device_stress_all.2434528569 |
|
|
Sep 09 11:19:34 AM UTC 24 |
Sep 09 11:28:18 AM UTC 24 |
104886373319 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/47.spi_device_stress_all.1434926057 |
|
|
Sep 09 11:19:18 AM UTC 24 |
Sep 09 11:28:33 AM UTC 24 |
61667460283 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/default/45.spi_device_stress_all.996299202 |
|
|
Sep 09 11:18:47 AM UTC 24 |
Sep 09 11:32:35 AM UTC 24 |
449660137438 ps |
| T1029 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_intr_test.1670490131 |
|
|
Sep 09 11:19:47 AM UTC 24 |
Sep 09 11:19:49 AM UTC 24 |
11950208 ps |
| T1030 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_walk.905414097 |
|
|
Sep 09 11:19:48 AM UTC 24 |
Sep 09 11:19:50 AM UTC 24 |
39193120 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_mem_partial_access.824042848 |
|
|
Sep 09 11:19:48 AM UTC 24 |
Sep 09 11:19:51 AM UTC 24 |
159547017 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_rw.1376290329 |
|
|
Sep 09 11:19:49 AM UTC 24 |
Sep 09 11:19:52 AM UTC 24 |
18907318 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2483430174 |
|
|
Sep 09 11:19:49 AM UTC 24 |
Sep 09 11:19:52 AM UTC 24 |
211959840 ps |
| T1031 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_intr_test.3104819550 |
|
|
Sep 09 11:19:50 AM UTC 24 |
Sep 09 11:19:53 AM UTC 24 |
24465372 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.4047659712 |
|
|
Sep 09 11:19:49 AM UTC 24 |
Sep 09 11:19:53 AM UTC 24 |
49669038 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_tl_errors.2583984369 |
|
|
Sep 09 11:19:45 AM UTC 24 |
Sep 09 11:19:54 AM UTC 24 |
4495334570 ps |
| T1032 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_walk.3958243815 |
|
|
Sep 09 11:19:53 AM UTC 24 |
Sep 09 11:19:55 AM UTC 24 |
17869330 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1979425199 |
|
|
Sep 09 11:19:50 AM UTC 24 |
Sep 09 11:19:55 AM UTC 24 |
163007166 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_mem_partial_access.1826274186 |
|
|
Sep 09 11:19:53 AM UTC 24 |
Sep 09 11:19:55 AM UTC 24 |
17076917 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_hw_reset.3053251324 |
|
|
Sep 09 11:19:53 AM UTC 24 |
Sep 09 11:19:56 AM UTC 24 |
104965803 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_rw.2637099554 |
|
|
Sep 09 11:19:53 AM UTC 24 |
Sep 09 11:19:56 AM UTC 24 |
138780066 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_tl_errors.440686002 |
|
|
Sep 09 11:19:50 AM UTC 24 |
Sep 09 11:19:56 AM UTC 24 |
243029737 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.128425230 |
|
|
Sep 09 11:19:54 AM UTC 24 |
Sep 09 11:19:58 AM UTC 24 |
113033808 ps |
| T1033 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_walk.1072901270 |
|
|
Sep 09 11:19:56 AM UTC 24 |
Sep 09 11:19:58 AM UTC 24 |
11614651 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3690098572 |
|
|
Sep 09 11:19:55 AM UTC 24 |
Sep 09 11:19:58 AM UTC 24 |
89021044 ps |
| T1034 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_intr_test.2718560636 |
|
|
Sep 09 11:19:56 AM UTC 24 |
Sep 09 11:19:58 AM UTC 24 |
69384038 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_hw_reset.2801689878 |
|
|
Sep 09 11:19:57 AM UTC 24 |
Sep 09 11:20:00 AM UTC 24 |
23473154 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_mem_partial_access.1232135513 |
|
|
Sep 09 11:19:57 AM UTC 24 |
Sep 09 11:20:02 AM UTC 24 |
130823105 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_rw.3800875161 |
|
|
Sep 09 11:19:58 AM UTC 24 |
Sep 09 11:20:02 AM UTC 24 |
125199854 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_tl_errors.1900007903 |
|
|
Sep 09 11:19:55 AM UTC 24 |
Sep 09 11:20:02 AM UTC 24 |
71301420 ps |
| T1035 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/0.spi_device_csr_bit_bash.4039495910 |
|
|
Sep 09 11:19:49 AM UTC 24 |
Sep 09 11:20:04 AM UTC 24 |
2361756646 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_09_08/spi_device_2p-sim-vcs/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.1248741343 |
|
|
Sep 09 11:20:00 AM UTC 24 |
Sep 09 11:20:04 AM UTC 24 |
39390651 ps |